1 /*
2 * Copyright 2002 Momentum Computer
3 * Author: mdharm@momenco.com
4 *
5 * arch/mips/momentum/ocelot_c/uart-irq.c
6 * Interrupt routines for UARTs. Interrupt numbers are assigned from
7 * 80 to 81 (2 interrupt sources).
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
18 #include <linux/kernel.h>
19 #include <asm/ptrace.h>
20 #include <linux/config.h>
21 #include <linux/sched.h>
22 #include <linux/kernel_stat.h>
23 #include <asm/io.h>
24 #include <asm/irq.h>
25 #include "ocelot_c_fpga.h"
26
ls1bit8(unsigned int x)27 static inline int ls1bit8(unsigned int x)
28 {
29 int b = 7, s;
30
31 s = 4; if (((unsigned char)(x << 4)) == 0) s = 0; b -= s; x <<= s;
32 s = 2; if (((unsigned char)(x << 2)) == 0) s = 0; b -= s; x <<= s;
33 s = 1; if (((unsigned char)(x << 1)) == 0) s = 0; b -= s;
34
35 return b;
36 }
37
38 /* mask off an interrupt -- 0 is enable, 1 is disable */
mask_uart_irq(unsigned int irq)39 static inline void mask_uart_irq(unsigned int irq)
40 {
41 uint8_t value;
42
43 value = OCELOT_FPGA_READ(UART_INTMASK);
44 value |= 1 << (irq - 74);
45 OCELOT_FPGA_WRITE(value, UART_INTMASK);
46
47 /* read the value back to assure that it's really been written */
48 value = OCELOT_FPGA_READ(UART_INTMASK);
49 }
50
51 /* unmask an interrupt -- 0 is enable, 1 is disable */
unmask_uart_irq(unsigned int irq)52 static inline void unmask_uart_irq(unsigned int irq)
53 {
54 uint8_t value;
55
56 value = OCELOT_FPGA_READ(UART_INTMASK);
57 value &= ~(1 << (irq - 74));
58 OCELOT_FPGA_WRITE(value, UART_INTMASK);
59
60 /* read the value back to assure that it's really been written */
61 value = OCELOT_FPGA_READ(UART_INTMASK);
62 }
63
64 /*
65 * Enables the IRQ in the FPGA
66 */
enable_uart_irq(unsigned int irq)67 static void enable_uart_irq(unsigned int irq)
68 {
69 unmask_uart_irq(irq);
70 }
71
72 /*
73 * Initialize the IRQ in the FPGA
74 */
startup_uart_irq(unsigned int irq)75 static unsigned int startup_uart_irq(unsigned int irq)
76 {
77 unmask_uart_irq(irq);
78 return 0;
79 }
80
81 /*
82 * Disables the IRQ in the FPGA
83 */
disable_uart_irq(unsigned int irq)84 static void disable_uart_irq(unsigned int irq)
85 {
86 mask_uart_irq(irq);
87 }
88
89 /*
90 * Masks and ACKs an IRQ
91 */
mask_and_ack_uart_irq(unsigned int irq)92 static void mask_and_ack_uart_irq(unsigned int irq)
93 {
94 mask_uart_irq(irq);
95 }
96
97 /*
98 * End IRQ processing
99 */
end_uart_irq(unsigned int irq)100 static void end_uart_irq(unsigned int irq)
101 {
102 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
103 unmask_uart_irq(irq);
104 }
105
106 /*
107 * Interrupt handler for interrupts coming from the FPGA chip.
108 */
ll_uart_irq(struct pt_regs * regs)109 void ll_uart_irq(struct pt_regs *regs)
110 {
111 unsigned int irq_src, irq_mask;
112
113 /* read the interrupt status registers */
114 irq_src = OCELOT_FPGA_READ(UART_INTSTAT);
115 irq_mask = OCELOT_FPGA_READ(UART_INTMASK);
116
117 /* mask for just the interrupts we want */
118 irq_src &= ~irq_mask;
119
120 do_IRQ(ls1bit8(irq_src) + 74, regs);
121 }
122
123 #define shutdown_uart_irq disable_uart_irq
124
125 struct hw_interrupt_type uart_irq_type = {
126 "UART/FPGA",
127 startup_uart_irq,
128 shutdown_uart_irq,
129 enable_uart_irq,
130 disable_uart_irq,
131 mask_and_ack_uart_irq,
132 end_uart_irq,
133 NULL
134 };
135
uart_irq_init(void)136 void uart_irq_init(void)
137 {
138 /* Reset irq handlers pointers to NULL */
139 irq_desc[80].status = IRQ_DISABLED;
140 irq_desc[80].action = 0;
141 irq_desc[80].depth = 2;
142 irq_desc[80].handler = &uart_irq_type;
143
144 irq_desc[81].status = IRQ_DISABLED;
145 irq_desc[81].action = 0;
146 irq_desc[81].depth = 2;
147 irq_desc[81].handler = &uart_irq_type;
148 }
149