1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2 /*
3  * Based on arch/arm/include/asm/ptrace.h
4  *
5  * Copyright (C) 1996-2003 Russell King
6  * Copyright (C) 2012 ARM Ltd.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
19  */
20 #ifndef _UAPI__ASM_PTRACE_H
21 #define _UAPI__ASM_PTRACE_H
22 
23 #include <linux/types.h>
24 
25 #include <asm/hwcap.h>
26 #include <asm/sve_context.h>
27 
28 
29 /*
30  * PSR bits
31  */
32 #define PSR_MODE_EL0t	0x00000000
33 #define PSR_MODE_EL1t	0x00000004
34 #define PSR_MODE_EL1h	0x00000005
35 #define PSR_MODE_EL2t	0x00000008
36 #define PSR_MODE_EL2h	0x00000009
37 #define PSR_MODE_EL3t	0x0000000c
38 #define PSR_MODE_EL3h	0x0000000d
39 #define PSR_MODE_MASK	0x0000000f
40 
41 /* AArch32 CPSR bits */
42 #define PSR_MODE32_BIT		0x00000010
43 
44 /* AArch64 SPSR bits */
45 #define PSR_F_BIT	0x00000040
46 #define PSR_I_BIT	0x00000080
47 #define PSR_A_BIT	0x00000100
48 #define PSR_D_BIT	0x00000200
49 #define PSR_BTYPE_MASK	0x00000c00
50 #define PSR_SSBS_BIT	0x00001000
51 #define PSR_PAN_BIT	0x00400000
52 #define PSR_UAO_BIT	0x00800000
53 #define PSR_DIT_BIT	0x01000000
54 #define PSR_TCO_BIT	0x02000000
55 #define PSR_V_BIT	0x10000000
56 #define PSR_C_BIT	0x20000000
57 #define PSR_Z_BIT	0x40000000
58 #define PSR_N_BIT	0x80000000
59 
60 #define PSR_BTYPE_SHIFT		10
61 
62 /*
63  * Groups of PSR bits
64  */
65 #define PSR_f		0xff000000	/* Flags		*/
66 #define PSR_s		0x00ff0000	/* Status		*/
67 #define PSR_x		0x0000ff00	/* Extension		*/
68 #define PSR_c		0x000000ff	/* Control		*/
69 
70 /* Convenience names for the values of PSTATE.BTYPE */
71 #define PSR_BTYPE_NONE		(0b00 << PSR_BTYPE_SHIFT)
72 #define PSR_BTYPE_JC		(0b01 << PSR_BTYPE_SHIFT)
73 #define PSR_BTYPE_C		(0b10 << PSR_BTYPE_SHIFT)
74 #define PSR_BTYPE_J		(0b11 << PSR_BTYPE_SHIFT)
75 
76 /* syscall emulation path in ptrace */
77 #define PTRACE_SYSEMU		  31
78 #define PTRACE_SYSEMU_SINGLESTEP  32
79 /* MTE allocation tag access */
80 #define PTRACE_PEEKMTETAGS	  33
81 #define PTRACE_POKEMTETAGS	  34
82 
83 #ifndef __ASSEMBLY__
84 
85 /*
86  * User structures for general purpose, floating point and debug registers.
87  */
88 struct user_pt_regs {
89 	__u64		regs[31];
90 	__u64		sp;
91 	__u64		pc;
92 	__u64		pstate;
93 };
94 
95 struct user_fpsimd_state {
96 	__uint128_t	vregs[32];
97 	__u32		fpsr;
98 	__u32		fpcr;
99 	__u32		__reserved[2];
100 };
101 
102 struct user_hwdebug_state {
103 	__u32		dbg_info;
104 	__u32		pad;
105 	struct {
106 		__u64	addr;
107 		__u32	ctrl;
108 		__u32	pad;
109 	}		dbg_regs[16];
110 };
111 
112 /* SVE/FP/SIMD state (NT_ARM_SVE & NT_ARM_SSVE) */
113 
114 struct user_sve_header {
115 	__u32 size; /* total meaningful regset content in bytes */
116 	__u32 max_size; /* maxmium possible size for this thread */
117 	__u16 vl; /* current vector length */
118 	__u16 max_vl; /* maximum possible vector length */
119 	__u16 flags;
120 	__u16 __reserved;
121 };
122 
123 /* Definitions for user_sve_header.flags: */
124 #define SVE_PT_REGS_MASK		(1 << 0)
125 
126 #define SVE_PT_REGS_FPSIMD		0
127 #define SVE_PT_REGS_SVE			SVE_PT_REGS_MASK
128 
129 /*
130  * Common SVE_PT_* flags:
131  * These must be kept in sync with prctl interface in <linux/prctl.h>
132  */
133 #define SVE_PT_VL_INHERIT		((1 << 17) /* PR_SVE_VL_INHERIT */ >> 16)
134 #define SVE_PT_VL_ONEXEC		((1 << 18) /* PR_SVE_SET_VL_ONEXEC */ >> 16)
135 
136 
137 /*
138  * The remainder of the SVE state follows struct user_sve_header.  The
139  * total size of the SVE state (including header) depends on the
140  * metadata in the header:  SVE_PT_SIZE(vq, flags) gives the total size
141  * of the state in bytes, including the header.
142  *
143  * Refer to <asm/sigcontext.h> for details of how to pass the correct
144  * "vq" argument to these macros.
145  */
146 
147 /* Offset from the start of struct user_sve_header to the register data */
148 #define SVE_PT_REGS_OFFSET						\
149 	((sizeof(struct user_sve_header) + (__SVE_VQ_BYTES - 1))	\
150 		/ __SVE_VQ_BYTES * __SVE_VQ_BYTES)
151 
152 /*
153  * The register data content and layout depends on the value of the
154  * flags field.
155  */
156 
157 /*
158  * (flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_FPSIMD case:
159  *
160  * The payload starts at offset SVE_PT_FPSIMD_OFFSET, and is of type
161  * struct user_fpsimd_state.  Additional data might be appended in the
162  * future: use SVE_PT_FPSIMD_SIZE(vq, flags) to compute the total size.
163  * SVE_PT_FPSIMD_SIZE(vq, flags) will never be less than
164  * sizeof(struct user_fpsimd_state).
165  */
166 
167 #define SVE_PT_FPSIMD_OFFSET		SVE_PT_REGS_OFFSET
168 
169 #define SVE_PT_FPSIMD_SIZE(vq, flags)	(sizeof(struct user_fpsimd_state))
170 
171 /*
172  * (flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_SVE case:
173  *
174  * The payload starts at offset SVE_PT_SVE_OFFSET, and is of size
175  * SVE_PT_SVE_SIZE(vq, flags).
176  *
177  * Additional macros describe the contents and layout of the payload.
178  * For each, SVE_PT_SVE_x_OFFSET(args) is the start offset relative to
179  * the start of struct user_sve_header, and SVE_PT_SVE_x_SIZE(args) is
180  * the size in bytes:
181  *
182  *	x	type				description
183  *	-	----				-----------
184  *	ZREGS		\
185  *	ZREG		|
186  *	PREGS		| refer to <asm/sigcontext.h>
187  *	PREG		|
188  *	FFR		/
189  *
190  *	FPSR	uint32_t			FPSR
191  *	FPCR	uint32_t			FPCR
192  *
193  * Additional data might be appended in the future.
194  *
195  * The Z-, P- and FFR registers are represented in memory in an endianness-
196  * invariant layout which differs from the layout used for the FPSIMD
197  * V-registers on big-endian systems: see sigcontext.h for more explanation.
198  */
199 
200 #define SVE_PT_SVE_ZREG_SIZE(vq)	__SVE_ZREG_SIZE(vq)
201 #define SVE_PT_SVE_PREG_SIZE(vq)	__SVE_PREG_SIZE(vq)
202 #define SVE_PT_SVE_FFR_SIZE(vq)		__SVE_FFR_SIZE(vq)
203 #define SVE_PT_SVE_FPSR_SIZE		sizeof(__u32)
204 #define SVE_PT_SVE_FPCR_SIZE		sizeof(__u32)
205 
206 #define SVE_PT_SVE_OFFSET		SVE_PT_REGS_OFFSET
207 
208 #define SVE_PT_SVE_ZREGS_OFFSET \
209 	(SVE_PT_REGS_OFFSET + __SVE_ZREGS_OFFSET)
210 #define SVE_PT_SVE_ZREG_OFFSET(vq, n) \
211 	(SVE_PT_REGS_OFFSET + __SVE_ZREG_OFFSET(vq, n))
212 #define SVE_PT_SVE_ZREGS_SIZE(vq) \
213 	(SVE_PT_SVE_ZREG_OFFSET(vq, __SVE_NUM_ZREGS) - SVE_PT_SVE_ZREGS_OFFSET)
214 
215 #define SVE_PT_SVE_PREGS_OFFSET(vq) \
216 	(SVE_PT_REGS_OFFSET + __SVE_PREGS_OFFSET(vq))
217 #define SVE_PT_SVE_PREG_OFFSET(vq, n) \
218 	(SVE_PT_REGS_OFFSET + __SVE_PREG_OFFSET(vq, n))
219 #define SVE_PT_SVE_PREGS_SIZE(vq) \
220 	(SVE_PT_SVE_PREG_OFFSET(vq, __SVE_NUM_PREGS) - \
221 		SVE_PT_SVE_PREGS_OFFSET(vq))
222 
223 /* For streaming mode SVE (SSVE) FFR must be read and written as zero */
224 #define SVE_PT_SVE_FFR_OFFSET(vq) \
225 	(SVE_PT_REGS_OFFSET + __SVE_FFR_OFFSET(vq))
226 
227 #define SVE_PT_SVE_FPSR_OFFSET(vq)				\
228 	((SVE_PT_SVE_FFR_OFFSET(vq) + SVE_PT_SVE_FFR_SIZE(vq) +	\
229 			(__SVE_VQ_BYTES - 1))			\
230 		/ __SVE_VQ_BYTES * __SVE_VQ_BYTES)
231 #define SVE_PT_SVE_FPCR_OFFSET(vq) \
232 	(SVE_PT_SVE_FPSR_OFFSET(vq) + SVE_PT_SVE_FPSR_SIZE)
233 
234 /*
235  * Any future extension appended after FPCR must be aligned to the next
236  * 128-bit boundary.
237  */
238 
239 #define SVE_PT_SVE_SIZE(vq, flags)					\
240 	((SVE_PT_SVE_FPCR_OFFSET(vq) + SVE_PT_SVE_FPCR_SIZE		\
241 			- SVE_PT_SVE_OFFSET + (__SVE_VQ_BYTES - 1))	\
242 		/ __SVE_VQ_BYTES * __SVE_VQ_BYTES)
243 
244 #define SVE_PT_SIZE(vq, flags)						  \
245 	 (((flags) & SVE_PT_REGS_MASK) == SVE_PT_REGS_SVE ?		  \
246 		  SVE_PT_SVE_OFFSET + SVE_PT_SVE_SIZE(vq, flags)	  \
247 		: ((((flags) & SVE_PT_REGS_MASK) == SVE_PT_REGS_FPSIMD ?  \
248 		    SVE_PT_FPSIMD_OFFSET + SVE_PT_FPSIMD_SIZE(vq, flags) \
249 		  : SVE_PT_REGS_OFFSET)))
250 
251 /* pointer authentication masks (NT_ARM_PAC_MASK) */
252 
253 struct user_pac_mask {
254 	__u64		data_mask;
255 	__u64		insn_mask;
256 };
257 
258 /* pointer authentication keys (NT_ARM_PACA_KEYS, NT_ARM_PACG_KEYS) */
259 
260 struct user_pac_address_keys {
261 	__uint128_t	apiakey;
262 	__uint128_t	apibkey;
263 	__uint128_t	apdakey;
264 	__uint128_t	apdbkey;
265 };
266 
267 struct user_pac_generic_keys {
268 	__uint128_t	apgakey;
269 };
270 
271 /* ZA state (NT_ARM_ZA) */
272 
273 struct user_za_header {
274 	__u32 size; /* total meaningful regset content in bytes */
275 	__u32 max_size; /* maxmium possible size for this thread */
276 	__u16 vl; /* current vector length */
277 	__u16 max_vl; /* maximum possible vector length */
278 	__u16 flags;
279 	__u16 __reserved;
280 };
281 
282 /*
283  * Common ZA_PT_* flags:
284  * These must be kept in sync with prctl interface in <linux/prctl.h>
285  */
286 #define ZA_PT_VL_INHERIT		((1 << 17) /* PR_SME_VL_INHERIT */ >> 16)
287 #define ZA_PT_VL_ONEXEC			((1 << 18) /* PR_SME_SET_VL_ONEXEC */ >> 16)
288 
289 
290 /*
291  * The remainder of the ZA state follows struct user_za_header.  The
292  * total size of the ZA state (including header) depends on the
293  * metadata in the header:  ZA_PT_SIZE(vq, flags) gives the total size
294  * of the state in bytes, including the header.
295  *
296  * Refer to <asm/sigcontext.h> for details of how to pass the correct
297  * "vq" argument to these macros.
298  */
299 
300 /* Offset from the start of struct user_za_header to the register data */
301 #define ZA_PT_ZA_OFFSET						\
302 	((sizeof(struct user_za_header) + (__SVE_VQ_BYTES - 1))	\
303 		/ __SVE_VQ_BYTES * __SVE_VQ_BYTES)
304 
305 /*
306  * The payload starts at offset ZA_PT_ZA_OFFSET, and is of size
307  * ZA_PT_ZA_SIZE(vq, flags).
308  *
309  * The ZA array is stored as a sequence of horizontal vectors ZAV of SVL/8
310  * bytes each, starting from vector 0.
311  *
312  * Additional data might be appended in the future.
313  *
314  * The ZA matrix is represented in memory in an endianness-invariant layout
315  * which differs from the layout used for the FPSIMD V-registers on big-endian
316  * systems: see sigcontext.h for more explanation.
317  */
318 
319 #define ZA_PT_ZAV_OFFSET(vq, n) \
320 	(ZA_PT_ZA_OFFSET + ((vq * __SVE_VQ_BYTES) * n))
321 
322 #define ZA_PT_ZA_SIZE(vq) ((vq * __SVE_VQ_BYTES) * (vq * __SVE_VQ_BYTES))
323 
324 #define ZA_PT_SIZE(vq)						\
325 	(ZA_PT_ZA_OFFSET + ZA_PT_ZA_SIZE(vq))
326 
327 #endif /* __ASSEMBLY__ */
328 
329 #endif /* _UAPI__ASM_PTRACE_H */
330