1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Copyright 2007 Simtec Electronics
4 // Ben Dooks <ben@simtec.co.uk>
5 //
6 // http://armlinux.simtec.co.uk/
7
8 #include <linux/kernel.h>
9 #include <linux/types.h>
10 #include <linux/interrupt.h>
11 #include <linux/list.h>
12 #include <linux/timer.h>
13 #include <linux/init.h>
14 #include <linux/gpio.h>
15 #include <linux/gpio/machine.h>
16 #include <linux/syscore_ops.h>
17 #include <linux/serial_core.h>
18 #include <linux/serial_s3c.h>
19 #include <linux/platform_device.h>
20 #include <linux/i2c.h>
21
22 #include <video/ili9320.h>
23
24 #include <linux/spi/spi.h>
25 #include <linux/spi/spi_gpio.h>
26
27 #include <asm/mach/arch.h>
28 #include <asm/mach/map.h>
29 #include <asm/mach/irq.h>
30
31 #include <linux/platform_data/mtd-nand-s3c2410.h>
32 #include <linux/platform_data/i2c-s3c2410.h>
33
34 #include "hardware-s3c24xx.h"
35 #include "regs-gpio.h"
36 #include <linux/platform_data/fb-s3c2410.h>
37 #include "gpio-samsung.h"
38
39 #include <asm/mach-types.h>
40
41 #include <linux/mtd/mtd.h>
42 #include <linux/mtd/rawnand.h>
43 #include <linux/mtd/nand-ecc-sw-hamming.h>
44 #include <linux/mtd/partitions.h>
45
46 #include "gpio-cfg.h"
47 #include "devs.h"
48 #include "cpu.h"
49 #include "pm.h"
50 #include <linux/platform_data/usb-s3c2410_udc.h>
51
52 #include "s3c24xx.h"
53 #include "s3c2412-power.h"
54
55 static struct map_desc jive_iodesc[] __initdata = {
56 };
57
58 #define UCON S3C2410_UCON_DEFAULT
59 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE
60 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
61
62 static struct s3c2410_uartcfg jive_uartcfgs[] = {
63 [0] = {
64 .hwport = 0,
65 .flags = 0,
66 .ucon = UCON,
67 .ulcon = ULCON,
68 .ufcon = UFCON,
69 },
70 [1] = {
71 .hwport = 1,
72 .flags = 0,
73 .ucon = UCON,
74 .ulcon = ULCON,
75 .ufcon = UFCON,
76 },
77 [2] = {
78 .hwport = 2,
79 .flags = 0,
80 .ucon = UCON,
81 .ulcon = ULCON,
82 .ufcon = UFCON,
83 }
84 };
85
86 /* Jive flash assignment
87 *
88 * 0x00000000-0x00028000 : uboot
89 * 0x00028000-0x0002c000 : uboot env
90 * 0x0002c000-0x00030000 : spare
91 * 0x00030000-0x00200000 : zimage A
92 * 0x00200000-0x01600000 : cramfs A
93 * 0x01600000-0x017d0000 : zimage B
94 * 0x017d0000-0x02bd0000 : cramfs B
95 * 0x02bd0000-0x03fd0000 : yaffs
96 */
97 static struct mtd_partition __initdata jive_imageA_nand_part[] = {
98
99 #ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
100 /* Don't allow access to the bootloader from linux */
101 {
102 .name = "uboot",
103 .offset = 0,
104 .size = (160 * SZ_1K),
105 .mask_flags = MTD_WRITEABLE, /* force read-only */
106 },
107
108 /* spare */
109 {
110 .name = "spare",
111 .offset = (176 * SZ_1K),
112 .size = (16 * SZ_1K),
113 },
114 #endif
115
116 /* booted images */
117 {
118 .name = "kernel (ro)",
119 .offset = (192 * SZ_1K),
120 .size = (SZ_2M) - (192 * SZ_1K),
121 .mask_flags = MTD_WRITEABLE, /* force read-only */
122 }, {
123 .name = "root (ro)",
124 .offset = (SZ_2M),
125 .size = (20 * SZ_1M),
126 .mask_flags = MTD_WRITEABLE, /* force read-only */
127 },
128
129 /* yaffs */
130 {
131 .name = "yaffs",
132 .offset = (44 * SZ_1M),
133 .size = (20 * SZ_1M),
134 },
135
136 /* bootloader environment */
137 {
138 .name = "env",
139 .offset = (160 * SZ_1K),
140 .size = (16 * SZ_1K),
141 },
142
143 /* upgrade images */
144 {
145 .name = "zimage",
146 .offset = (22 * SZ_1M),
147 .size = (2 * SZ_1M) - (192 * SZ_1K),
148 }, {
149 .name = "cramfs",
150 .offset = (24 * SZ_1M) - (192*SZ_1K),
151 .size = (20 * SZ_1M),
152 },
153 };
154
155 static struct mtd_partition __initdata jive_imageB_nand_part[] = {
156
157 #ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
158 /* Don't allow access to the bootloader from linux */
159 {
160 .name = "uboot",
161 .offset = 0,
162 .size = (160 * SZ_1K),
163 .mask_flags = MTD_WRITEABLE, /* force read-only */
164 },
165
166 /* spare */
167 {
168 .name = "spare",
169 .offset = (176 * SZ_1K),
170 .size = (16 * SZ_1K),
171 },
172 #endif
173
174 /* booted images */
175 {
176 .name = "kernel (ro)",
177 .offset = (22 * SZ_1M),
178 .size = (2 * SZ_1M) - (192 * SZ_1K),
179 .mask_flags = MTD_WRITEABLE, /* force read-only */
180 },
181 {
182 .name = "root (ro)",
183 .offset = (24 * SZ_1M) - (192 * SZ_1K),
184 .size = (20 * SZ_1M),
185 .mask_flags = MTD_WRITEABLE, /* force read-only */
186 },
187
188 /* yaffs */
189 {
190 .name = "yaffs",
191 .offset = (44 * SZ_1M),
192 .size = (20 * SZ_1M),
193 },
194
195 /* bootloader environment */
196 {
197 .name = "env",
198 .offset = (160 * SZ_1K),
199 .size = (16 * SZ_1K),
200 },
201
202 /* upgrade images */
203 {
204 .name = "zimage",
205 .offset = (192 * SZ_1K),
206 .size = (2 * SZ_1M) - (192 * SZ_1K),
207 }, {
208 .name = "cramfs",
209 .offset = (2 * SZ_1M),
210 .size = (20 * SZ_1M),
211 },
212 };
213
214 static struct s3c2410_nand_set __initdata jive_nand_sets[] = {
215 [0] = {
216 .name = "flash",
217 .nr_chips = 1,
218 .nr_partitions = ARRAY_SIZE(jive_imageA_nand_part),
219 .partitions = jive_imageA_nand_part,
220 },
221 };
222
223 static struct s3c2410_platform_nand __initdata jive_nand_info = {
224 /* set taken from osiris nand timings, possibly still conservative */
225 .tacls = 30,
226 .twrph0 = 55,
227 .twrph1 = 40,
228 .sets = jive_nand_sets,
229 .nr_sets = ARRAY_SIZE(jive_nand_sets),
230 .engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
231 };
232
jive_mtdset(char * options)233 static int __init jive_mtdset(char *options)
234 {
235 struct s3c2410_nand_set *nand = &jive_nand_sets[0];
236 unsigned long set;
237
238 if (options == NULL || options[0] == '\0')
239 return 1;
240
241 if (kstrtoul(options, 10, &set)) {
242 printk(KERN_ERR "failed to parse mtdset=%s\n", options);
243 return 1;
244 }
245
246 switch (set) {
247 case 1:
248 nand->nr_partitions = ARRAY_SIZE(jive_imageB_nand_part);
249 nand->partitions = jive_imageB_nand_part;
250 break;
251 case 0:
252 /* this is already setup in the nand info */
253 break;
254 default:
255 printk(KERN_ERR "Unknown mtd set %ld specified,"
256 "using default.", set);
257 }
258
259 return 1;
260 }
261
262 /* parse the mtdset= option given to the kernel command line */
263 __setup("mtdset=", jive_mtdset);
264
265 /* LCD timing and setup */
266
267 #define LCD_XRES (240)
268 #define LCD_YRES (320)
269 #define LCD_LEFT_MARGIN (12)
270 #define LCD_RIGHT_MARGIN (12)
271 #define LCD_LOWER_MARGIN (12)
272 #define LCD_UPPER_MARGIN (12)
273 #define LCD_VSYNC (2)
274 #define LCD_HSYNC (2)
275
276 #define LCD_REFRESH (60)
277
278 #define LCD_HTOT (LCD_HSYNC + LCD_LEFT_MARGIN + LCD_XRES + LCD_RIGHT_MARGIN)
279 #define LCD_VTOT (LCD_VSYNC + LCD_LOWER_MARGIN + LCD_YRES + LCD_UPPER_MARGIN)
280
281 static struct s3c2410fb_display jive_vgg2432a4_display[] = {
282 [0] = {
283 .width = LCD_XRES,
284 .height = LCD_YRES,
285 .xres = LCD_XRES,
286 .yres = LCD_YRES,
287 .left_margin = LCD_LEFT_MARGIN,
288 .right_margin = LCD_RIGHT_MARGIN,
289 .upper_margin = LCD_UPPER_MARGIN,
290 .lower_margin = LCD_LOWER_MARGIN,
291 .hsync_len = LCD_HSYNC,
292 .vsync_len = LCD_VSYNC,
293
294 .pixclock = (1000000000000LL /
295 (LCD_REFRESH * LCD_HTOT * LCD_VTOT)),
296
297 .bpp = 16,
298 .type = (S3C2410_LCDCON1_TFT16BPP |
299 S3C2410_LCDCON1_TFT),
300
301 .lcdcon5 = (S3C2410_LCDCON5_FRM565 |
302 S3C2410_LCDCON5_INVVLINE |
303 S3C2410_LCDCON5_INVVFRAME |
304 S3C2410_LCDCON5_INVVDEN |
305 S3C2410_LCDCON5_PWREN),
306 },
307 };
308
309 /* todo - put into gpio header */
310
311 #define S3C2410_GPCCON_MASK(x) (3 << ((x) * 2))
312 #define S3C2410_GPDCON_MASK(x) (3 << ((x) * 2))
313
314 static struct s3c2410fb_mach_info jive_lcd_config = {
315 .displays = jive_vgg2432a4_display,
316 .num_displays = ARRAY_SIZE(jive_vgg2432a4_display),
317 .default_display = 0,
318
319 /* Enable VD[2..7], VD[10..15], VD[18..23] and VCLK, syncs, VDEN
320 * and disable the pull down resistors on pins we are using for LCD
321 * data. */
322
323 .gpcup = (0xf << 1) | (0x3f << 10),
324 .gpcup_reg = S3C2410_GPCUP,
325
326 .gpccon = (S3C2410_GPC1_VCLK | S3C2410_GPC2_VLINE |
327 S3C2410_GPC3_VFRAME | S3C2410_GPC4_VM |
328 S3C2410_GPC10_VD2 | S3C2410_GPC11_VD3 |
329 S3C2410_GPC12_VD4 | S3C2410_GPC13_VD5 |
330 S3C2410_GPC14_VD6 | S3C2410_GPC15_VD7),
331
332 .gpccon_mask = (S3C2410_GPCCON_MASK(1) | S3C2410_GPCCON_MASK(2) |
333 S3C2410_GPCCON_MASK(3) | S3C2410_GPCCON_MASK(4) |
334 S3C2410_GPCCON_MASK(10) | S3C2410_GPCCON_MASK(11) |
335 S3C2410_GPCCON_MASK(12) | S3C2410_GPCCON_MASK(13) |
336 S3C2410_GPCCON_MASK(14) | S3C2410_GPCCON_MASK(15)),
337
338 .gpccon_reg = S3C2410_GPCCON,
339
340 .gpdup = (0x3f << 2) | (0x3f << 10),
341
342 .gpdup_reg = S3C2410_GPDUP,
343
344 .gpdcon = (S3C2410_GPD2_VD10 | S3C2410_GPD3_VD11 |
345 S3C2410_GPD4_VD12 | S3C2410_GPD5_VD13 |
346 S3C2410_GPD6_VD14 | S3C2410_GPD7_VD15 |
347 S3C2410_GPD10_VD18 | S3C2410_GPD11_VD19 |
348 S3C2410_GPD12_VD20 | S3C2410_GPD13_VD21 |
349 S3C2410_GPD14_VD22 | S3C2410_GPD15_VD23),
350
351 .gpdcon_mask = (S3C2410_GPDCON_MASK(2) | S3C2410_GPDCON_MASK(3) |
352 S3C2410_GPDCON_MASK(4) | S3C2410_GPDCON_MASK(5) |
353 S3C2410_GPDCON_MASK(6) | S3C2410_GPDCON_MASK(7) |
354 S3C2410_GPDCON_MASK(10) | S3C2410_GPDCON_MASK(11)|
355 S3C2410_GPDCON_MASK(12) | S3C2410_GPDCON_MASK(13)|
356 S3C2410_GPDCON_MASK(14) | S3C2410_GPDCON_MASK(15)),
357
358 .gpdcon_reg = S3C2410_GPDCON,
359 };
360
361 /* ILI9320 support. */
362
jive_lcm_reset(unsigned int set)363 static void jive_lcm_reset(unsigned int set)
364 {
365 printk(KERN_DEBUG "%s(%d)\n", __func__, set);
366
367 gpio_set_value(S3C2410_GPG(13), set);
368 }
369
370 #undef LCD_UPPER_MARGIN
371 #define LCD_UPPER_MARGIN 2
372
373 static struct ili9320_platdata jive_lcm_config = {
374 .hsize = LCD_XRES,
375 .vsize = LCD_YRES,
376
377 .reset = jive_lcm_reset,
378 .suspend = ILI9320_SUSPEND_DEEP,
379
380 .entry_mode = ILI9320_ENTRYMODE_ID(3) | ILI9320_ENTRYMODE_BGR,
381 .display2 = (ILI9320_DISPLAY2_FP(LCD_UPPER_MARGIN) |
382 ILI9320_DISPLAY2_BP(LCD_LOWER_MARGIN)),
383 .display3 = 0x0,
384 .display4 = 0x0,
385 .rgb_if1 = (ILI9320_RGBIF1_RIM_RGB18 |
386 ILI9320_RGBIF1_RM | ILI9320_RGBIF1_CLK_RGBIF),
387 .rgb_if2 = ILI9320_RGBIF2_DPL,
388 .interface2 = 0x0,
389 .interface3 = 0x3,
390 .interface4 = (ILI9320_INTERFACE4_RTNE(16) |
391 ILI9320_INTERFACE4_DIVE(1)),
392 .interface5 = 0x0,
393 .interface6 = 0x0,
394 };
395
396 /* LCD SPI support */
397
398 static struct spi_gpio_platform_data jive_lcd_spi = {
399 .num_chipselect = 1,
400 };
401
402 static struct platform_device jive_device_lcdspi = {
403 .name = "spi_gpio",
404 .id = 1,
405 .dev.platform_data = &jive_lcd_spi,
406 };
407
408 static struct gpiod_lookup_table jive_lcdspi_gpiod_table = {
409 .dev_id = "spi_gpio",
410 .table = {
411 GPIO_LOOKUP("GPIOG", 8,
412 "sck", GPIO_ACTIVE_HIGH),
413 GPIO_LOOKUP("GPIOB", 8,
414 "mosi", GPIO_ACTIVE_HIGH),
415 GPIO_LOOKUP("GPIOB", 7,
416 "cs", GPIO_ACTIVE_HIGH),
417 { },
418 },
419 };
420
421 /* WM8750 audio code SPI definition */
422
423 static struct spi_gpio_platform_data jive_wm8750_spi = {
424 .num_chipselect = 1,
425 };
426
427 static struct platform_device jive_device_wm8750 = {
428 .name = "spi_gpio",
429 .id = 2,
430 .dev.platform_data = &jive_wm8750_spi,
431 };
432
433 static struct gpiod_lookup_table jive_wm8750_gpiod_table = {
434 .dev_id = "spi_gpio",
435 .table = {
436 GPIO_LOOKUP("GPIOB", 4,
437 "sck", GPIO_ACTIVE_HIGH),
438 GPIO_LOOKUP("GPIOB", 9,
439 "mosi", GPIO_ACTIVE_HIGH),
440 GPIO_LOOKUP("GPIOH", 10,
441 "cs", GPIO_ACTIVE_HIGH),
442 { },
443 },
444 };
445
446 /* JIVE SPI devices. */
447
448 static struct spi_board_info __initdata jive_spi_devs[] = {
449 [0] = {
450 .modalias = "VGG2432A4",
451 .bus_num = 1,
452 .chip_select = 0,
453 .mode = SPI_MODE_3, /* CPOL=1, CPHA=1 */
454 .max_speed_hz = 100000,
455 .platform_data = &jive_lcm_config,
456 }, {
457 .modalias = "WM8750",
458 .bus_num = 2,
459 .chip_select = 0,
460 .mode = SPI_MODE_0, /* CPOL=0, CPHA=0 */
461 .max_speed_hz = 100000,
462 },
463 };
464
465 /* I2C bus and device configuration. */
466
467 static struct s3c2410_platform_i2c jive_i2c_cfg __initdata = {
468 .frequency = 80 * 1000,
469 .flags = S3C_IICFLG_FILTER,
470 .sda_delay = 2,
471 };
472
473 static struct i2c_board_info jive_i2c_devs[] __initdata = {
474 [0] = {
475 I2C_BOARD_INFO("lis302dl", 0x1c),
476 .irq = IRQ_EINT14,
477 },
478 };
479
480 /* The platform devices being used. */
481
482 static struct platform_device *jive_devices[] __initdata = {
483 &s3c_device_ohci,
484 &s3c_device_rtc,
485 &s3c_device_wdt,
486 &s3c_device_i2c0,
487 &s3c_device_lcd,
488 &jive_device_lcdspi,
489 &jive_device_wm8750,
490 &s3c_device_nand,
491 &s3c_device_usbgadget,
492 &s3c2412_device_dma,
493 };
494
495 static struct s3c2410_udc_mach_info jive_udc_cfg __initdata = {
496 };
497
498 static struct gpiod_lookup_table jive_udc_gpio_table = {
499 .dev_id = "s3c2410-usbgadget",
500 .table = {
501 GPIO_LOOKUP("GPIOG", 1, "vbus", GPIO_ACTIVE_HIGH),
502 { },
503 },
504 };
505
506 /* Jive power management device */
507
508 #ifdef CONFIG_PM
jive_pm_suspend(void)509 static int jive_pm_suspend(void)
510 {
511 /* Write the magic value u-boot uses to check for resume into
512 * the INFORM0 register, and ensure INFORM1 is set to the
513 * correct address to resume from. */
514
515 __raw_writel(0x2BED, S3C2412_INFORM0);
516 __raw_writel(__pa_symbol(s3c_cpu_resume), S3C2412_INFORM1);
517
518 return 0;
519 }
520
jive_pm_resume(void)521 static void jive_pm_resume(void)
522 {
523 __raw_writel(0x0, S3C2412_INFORM0);
524 }
525
526 #else
527 #define jive_pm_suspend NULL
528 #define jive_pm_resume NULL
529 #endif
530
531 static struct syscore_ops jive_pm_syscore_ops = {
532 .suspend = jive_pm_suspend,
533 .resume = jive_pm_resume,
534 };
535
jive_map_io(void)536 static void __init jive_map_io(void)
537 {
538 s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc));
539 s3c24xx_init_uarts(jive_uartcfgs, ARRAY_SIZE(jive_uartcfgs));
540 s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
541 }
542
jive_init_time(void)543 static void __init jive_init_time(void)
544 {
545 s3c2412_init_clocks(12000000);
546 s3c24xx_timer_init();
547 }
548
jive_power_off(void)549 static void jive_power_off(void)
550 {
551 printk(KERN_INFO "powering system down...\n");
552
553 gpio_request_one(S3C2410_GPC(5), GPIOF_OUT_INIT_HIGH, NULL);
554 gpio_free(S3C2410_GPC(5));
555 }
556
jive_machine_init(void)557 static void __init jive_machine_init(void)
558 {
559 /* register system core operations for managing low level suspend */
560
561 register_syscore_ops(&jive_pm_syscore_ops);
562
563 /* write our sleep configurations for the IO. Pull down all unused
564 * IO, ensure that we have turned off all peripherals we do not
565 * need, and configure the ones we do need. */
566
567 /* Port B sleep */
568
569 __raw_writel(S3C2412_SLPCON_IN(0) |
570 S3C2412_SLPCON_PULL(1) |
571 S3C2412_SLPCON_HIGH(2) |
572 S3C2412_SLPCON_PULL(3) |
573 S3C2412_SLPCON_PULL(4) |
574 S3C2412_SLPCON_PULL(5) |
575 S3C2412_SLPCON_PULL(6) |
576 S3C2412_SLPCON_HIGH(7) |
577 S3C2412_SLPCON_PULL(8) |
578 S3C2412_SLPCON_PULL(9) |
579 S3C2412_SLPCON_PULL(10), S3C2412_GPBSLPCON);
580
581 /* Port C sleep */
582
583 __raw_writel(S3C2412_SLPCON_PULL(0) |
584 S3C2412_SLPCON_PULL(1) |
585 S3C2412_SLPCON_PULL(2) |
586 S3C2412_SLPCON_PULL(3) |
587 S3C2412_SLPCON_PULL(4) |
588 S3C2412_SLPCON_PULL(5) |
589 S3C2412_SLPCON_LOW(6) |
590 S3C2412_SLPCON_PULL(6) |
591 S3C2412_SLPCON_PULL(7) |
592 S3C2412_SLPCON_PULL(8) |
593 S3C2412_SLPCON_PULL(9) |
594 S3C2412_SLPCON_PULL(10) |
595 S3C2412_SLPCON_PULL(11) |
596 S3C2412_SLPCON_PULL(12) |
597 S3C2412_SLPCON_PULL(13) |
598 S3C2412_SLPCON_PULL(14) |
599 S3C2412_SLPCON_PULL(15), S3C2412_GPCSLPCON);
600
601 /* Port D sleep */
602
603 __raw_writel(S3C2412_SLPCON_ALL_PULL, S3C2412_GPDSLPCON);
604
605 /* Port F sleep */
606
607 __raw_writel(S3C2412_SLPCON_LOW(0) |
608 S3C2412_SLPCON_LOW(1) |
609 S3C2412_SLPCON_LOW(2) |
610 S3C2412_SLPCON_EINT(3) |
611 S3C2412_SLPCON_EINT(4) |
612 S3C2412_SLPCON_EINT(5) |
613 S3C2412_SLPCON_EINT(6) |
614 S3C2412_SLPCON_EINT(7), S3C2412_GPFSLPCON);
615
616 /* Port G sleep */
617
618 __raw_writel(S3C2412_SLPCON_IN(0) |
619 S3C2412_SLPCON_IN(1) |
620 S3C2412_SLPCON_IN(2) |
621 S3C2412_SLPCON_IN(3) |
622 S3C2412_SLPCON_IN(4) |
623 S3C2412_SLPCON_IN(5) |
624 S3C2412_SLPCON_IN(6) |
625 S3C2412_SLPCON_IN(7) |
626 S3C2412_SLPCON_PULL(8) |
627 S3C2412_SLPCON_PULL(9) |
628 S3C2412_SLPCON_IN(10) |
629 S3C2412_SLPCON_PULL(11) |
630 S3C2412_SLPCON_PULL(12) |
631 S3C2412_SLPCON_PULL(13) |
632 S3C2412_SLPCON_IN(14) |
633 S3C2412_SLPCON_PULL(15), S3C2412_GPGSLPCON);
634
635 /* Port H sleep */
636
637 __raw_writel(S3C2412_SLPCON_PULL(0) |
638 S3C2412_SLPCON_PULL(1) |
639 S3C2412_SLPCON_PULL(2) |
640 S3C2412_SLPCON_PULL(3) |
641 S3C2412_SLPCON_PULL(4) |
642 S3C2412_SLPCON_PULL(5) |
643 S3C2412_SLPCON_PULL(6) |
644 S3C2412_SLPCON_IN(7) |
645 S3C2412_SLPCON_IN(8) |
646 S3C2412_SLPCON_PULL(9) |
647 S3C2412_SLPCON_IN(10), S3C2412_GPHSLPCON);
648
649 /* initialise the power management now we've setup everything. */
650
651 s3c_pm_init();
652
653 /** TODO - check that this is after the cmdline option! */
654 s3c_nand_set_platdata(&jive_nand_info);
655
656 gpio_request(S3C2410_GPG(13), "lcm reset");
657 gpio_direction_output(S3C2410_GPG(13), 0);
658
659 gpio_request_one(S3C2410_GPB(6), GPIOF_OUT_INIT_LOW, NULL);
660 gpio_free(S3C2410_GPB(6));
661
662 /* Turn off suspend on both USB ports, and switch the
663 * selectable USB port to USB device mode. */
664
665 s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
666 S3C2410_MISCCR_USBSUSPND0 |
667 S3C2410_MISCCR_USBSUSPND1, 0x0);
668
669 s3c24xx_udc_set_platdata(&jive_udc_cfg);
670 s3c24xx_fb_set_platdata(&jive_lcd_config);
671
672 spi_register_board_info(jive_spi_devs, ARRAY_SIZE(jive_spi_devs));
673
674 s3c_i2c0_set_platdata(&jive_i2c_cfg);
675 i2c_register_board_info(0, jive_i2c_devs, ARRAY_SIZE(jive_i2c_devs));
676
677 pm_power_off = jive_power_off;
678
679 gpiod_add_lookup_table(&jive_udc_gpio_table);
680 gpiod_add_lookup_table(&jive_lcdspi_gpiod_table);
681 gpiod_add_lookup_table(&jive_wm8750_gpiod_table);
682 platform_add_devices(jive_devices, ARRAY_SIZE(jive_devices));
683 }
684
685 MACHINE_START(JIVE, "JIVE")
686 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
687 .atag_offset = 0x100,
688 .nr_irqs = NR_IRQS_S3C2412,
689 .init_irq = s3c2412_init_irq,
690 .map_io = jive_map_io,
691 .init_machine = jive_machine_init,
692 .init_time = jive_init_time,
693 MACHINE_END
694