1 /*
2 * arch/arm/mach-dove/pcie.c
3 *
4 * PCIe functions for Marvell Dove 88AP510 SoC
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/pci.h>
13 #include <linux/clk.h>
14 #include <video/vga.h>
15 #include <asm/mach/pci.h>
16 #include <asm/mach/arch.h>
17 #include <asm/setup.h>
18 #include <asm/delay.h>
19 #include <plat/pcie.h>
20 #include <plat/addr-map.h>
21 #include "irqs.h"
22 #include "bridge-regs.h"
23 #include "common.h"
24
25 struct pcie_port {
26 u8 index;
27 u8 root_bus_nr;
28 void __iomem *base;
29 spinlock_t conf_lock;
30 char mem_space_name[16];
31 struct resource res;
32 };
33
34 static struct pcie_port pcie_port[2];
35 static int num_pcie_ports;
36
37
dove_pcie_setup(int nr,struct pci_sys_data * sys)38 static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
39 {
40 struct pcie_port *pp;
41 struct resource realio;
42
43 if (nr >= num_pcie_ports)
44 return 0;
45
46 pp = &pcie_port[nr];
47 sys->private_data = pp;
48 pp->root_bus_nr = sys->busnr;
49
50 /*
51 * Generic PCIe unit setup.
52 */
53 orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
54
55 orion_pcie_setup(pp->base);
56
57 realio.start = sys->busnr * SZ_64K;
58 realio.end = realio.start + SZ_64K - 1;
59 pci_remap_iospace(&realio, pp->index == 0 ? DOVE_PCIE0_IO_PHYS_BASE :
60 DOVE_PCIE1_IO_PHYS_BASE);
61
62 /*
63 * IORESOURCE_MEM
64 */
65 snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
66 "PCIe %d MEM", pp->index);
67 pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
68 pp->res.name = pp->mem_space_name;
69 if (pp->index == 0) {
70 pp->res.start = DOVE_PCIE0_MEM_PHYS_BASE;
71 pp->res.end = pp->res.start + DOVE_PCIE0_MEM_SIZE - 1;
72 } else {
73 pp->res.start = DOVE_PCIE1_MEM_PHYS_BASE;
74 pp->res.end = pp->res.start + DOVE_PCIE1_MEM_SIZE - 1;
75 }
76 pp->res.flags = IORESOURCE_MEM;
77 if (request_resource(&iomem_resource, &pp->res))
78 panic("Request PCIe Memory resource failed\n");
79 pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
80
81 return 1;
82 }
83
pcie_valid_config(struct pcie_port * pp,int bus,int dev)84 static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
85 {
86 /*
87 * Don't go out when trying to access nonexisting devices
88 * on the local bus.
89 */
90 if (bus == pp->root_bus_nr && dev > 1)
91 return 0;
92
93 return 1;
94 }
95
pcie_rd_conf(struct pci_bus * bus,u32 devfn,int where,int size,u32 * val)96 static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
97 int size, u32 *val)
98 {
99 struct pci_sys_data *sys = bus->sysdata;
100 struct pcie_port *pp = sys->private_data;
101 unsigned long flags;
102 int ret;
103
104 if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
105 *val = 0xffffffff;
106 return PCIBIOS_DEVICE_NOT_FOUND;
107 }
108
109 spin_lock_irqsave(&pp->conf_lock, flags);
110 ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
111 spin_unlock_irqrestore(&pp->conf_lock, flags);
112
113 return ret;
114 }
115
pcie_wr_conf(struct pci_bus * bus,u32 devfn,int where,int size,u32 val)116 static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
117 int where, int size, u32 val)
118 {
119 struct pci_sys_data *sys = bus->sysdata;
120 struct pcie_port *pp = sys->private_data;
121 unsigned long flags;
122 int ret;
123
124 if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
125 return PCIBIOS_DEVICE_NOT_FOUND;
126
127 spin_lock_irqsave(&pp->conf_lock, flags);
128 ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
129 spin_unlock_irqrestore(&pp->conf_lock, flags);
130
131 return ret;
132 }
133
134 static struct pci_ops pcie_ops = {
135 .read = pcie_rd_conf,
136 .write = pcie_wr_conf,
137 };
138
139 /*
140 * The root complex has a hardwired class of PCI_CLASS_MEMORY_OTHER, when it
141 * is operating as a root complex this needs to be switched to
142 * PCI_CLASS_BRIDGE_HOST or Linux will errantly try to process the BAR's on
143 * the device. Decoding setup is handled by the orion code.
144 */
rc_pci_fixup(struct pci_dev * dev)145 static void rc_pci_fixup(struct pci_dev *dev)
146 {
147 if (dev->bus->parent == NULL && dev->devfn == 0) {
148 int i;
149
150 dev->class &= 0xff;
151 dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
152 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
153 dev->resource[i].start = 0;
154 dev->resource[i].end = 0;
155 dev->resource[i].flags = 0;
156 }
157 }
158 }
159 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
160
161 static int __init
dove_pcie_scan_bus(int nr,struct pci_host_bridge * bridge)162 dove_pcie_scan_bus(int nr, struct pci_host_bridge *bridge)
163 {
164 struct pci_sys_data *sys = pci_host_bridge_priv(bridge);
165
166 if (nr >= num_pcie_ports) {
167 BUG();
168 return -EINVAL;
169 }
170
171 list_splice_init(&sys->resources, &bridge->windows);
172 bridge->dev.parent = NULL;
173 bridge->sysdata = sys;
174 bridge->busnr = sys->busnr;
175 bridge->ops = &pcie_ops;
176
177 return pci_scan_root_bus_bridge(bridge);
178 }
179
dove_pcie_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)180 static int __init dove_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
181 {
182 struct pci_sys_data *sys = dev->sysdata;
183 struct pcie_port *pp = sys->private_data;
184
185 return pp->index ? IRQ_DOVE_PCIE1 : IRQ_DOVE_PCIE0;
186 }
187
188 static struct hw_pci dove_pci __initdata = {
189 .nr_controllers = 2,
190 .setup = dove_pcie_setup,
191 .scan = dove_pcie_scan_bus,
192 .map_irq = dove_pcie_map_irq,
193 };
194
add_pcie_port(int index,void __iomem * base)195 static void __init add_pcie_port(int index, void __iomem *base)
196 {
197 printk(KERN_INFO "Dove PCIe port %d: ", index);
198
199 if (orion_pcie_link_up(base)) {
200 struct pcie_port *pp = &pcie_port[num_pcie_ports++];
201 struct clk *clk = clk_get_sys("pcie", (index ? "1" : "0"));
202
203 if (!IS_ERR(clk))
204 clk_prepare_enable(clk);
205
206 printk(KERN_INFO "link up\n");
207
208 pp->index = index;
209 pp->root_bus_nr = -1;
210 pp->base = base;
211 spin_lock_init(&pp->conf_lock);
212 memset(&pp->res, 0, sizeof(pp->res));
213 } else {
214 printk(KERN_INFO "link down, ignoring\n");
215 }
216 }
217
dove_pcie_init(int init_port0,int init_port1)218 void __init dove_pcie_init(int init_port0, int init_port1)
219 {
220 vga_base = DOVE_PCIE0_MEM_PHYS_BASE;
221
222 if (init_port0)
223 add_pcie_port(0, DOVE_PCIE0_VIRT_BASE);
224
225 if (init_port1)
226 add_pcie_port(1, DOVE_PCIE1_VIRT_BASE);
227
228 pci_common_init(&dove_pci);
229 }
230