1/*
2 *  linux/arch/arm/kernel/head.S
3 *
4 *  Copyright (C) 1994-2002 Russell King
5 *  Copyright (c) 2003 ARM Limited
6 *  All Rights Reserved
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 *  Kernel startup code for all 32-bit CPUs
13 */
14#include <linux/linkage.h>
15#include <linux/init.h>
16
17#include <asm/assembler.h>
18#include <asm/cp15.h>
19#include <asm/domain.h>
20#include <asm/ptrace.h>
21#include <asm/asm-offsets.h>
22#include <asm/memory.h>
23#include <asm/thread_info.h>
24#include <asm/pgtable.h>
25
26#ifdef CONFIG_DEBUG_LL
27#include <mach/debug-macro.S>
28#endif
29
30/*
31 * swapper_pg_dir is the virtual address of the initial page table.
32 * We place the page tables 16K below KERNEL_RAM_VADDR.  Therefore, we must
33 * make sure that KERNEL_RAM_VADDR is correctly set.  Currently, we expect
34 * the least significant 16 bits to be 0x8000, but we could probably
35 * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000.
36 */
37#define KERNEL_RAM_VADDR	(PAGE_OFFSET + TEXT_OFFSET)
38#if (KERNEL_RAM_VADDR & 0xffff) != 0x8000
39#error KERNEL_RAM_VADDR must start at 0xXXXX8000
40#endif
41
42#ifdef CONFIG_ARM_LPAE
43	/* LPAE requires an additional page for the PGD */
44#define PG_DIR_SIZE	0x5000
45#define PMD_ORDER	3
46#else
47#define PG_DIR_SIZE	0x4000
48#define PMD_ORDER	2
49#endif
50
51	.globl	swapper_pg_dir
52	.equ	swapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE
53
54	.macro	pgtbl, rd, phys
55	add	\rd, \phys, #TEXT_OFFSET - PG_DIR_SIZE
56	.endm
57
58#ifdef CONFIG_XIP_KERNEL
59#define KERNEL_START	XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR)
60#define KERNEL_END	_edata_loc
61#else
62#define KERNEL_START	KERNEL_RAM_VADDR
63#define KERNEL_END	_end
64#endif
65
66/*
67 * Kernel startup entry point.
68 * ---------------------------
69 *
70 * This is normally called from the decompressor code.  The requirements
71 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
72 * r1 = machine nr, r2 = atags or dtb pointer.
73 *
74 * This code is mostly position independent, so if you link the kernel at
75 * 0xc0008000, you call this at __pa(0xc0008000).
76 *
77 * See linux/arch/arm/tools/mach-types for the complete list of machine
78 * numbers for r1.
79 *
80 * We're trying to keep crap to a minimum; DO NOT add any machine specific
81 * crap here - that's what the boot loader (or in extreme, well justified
82 * circumstances, zImage) is for.
83 */
84	.arm
85
86	__HEAD
87ENTRY(stext)
88
89 THUMB(	adr	r9, BSYM(1f)	)	@ Kernel is always entered in ARM.
90 THUMB(	bx	r9		)	@ If this is a Thumb-2 kernel,
91 THUMB(	.thumb			)	@ switch to Thumb now.
92 THUMB(1:			)
93
94	setmode	PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
95						@ and irqs disabled
96	mrc	p15, 0, r9, c0, c0		@ get processor id
97	bl	__lookup_processor_type		@ r5=procinfo r9=cpuid
98	movs	r10, r5				@ invalid processor (r5=0)?
99 THUMB( it	eq )		@ force fixup-able long branch encoding
100	beq	__error_p			@ yes, error 'p'
101
102#ifdef CONFIG_ARM_LPAE
103	mrc	p15, 0, r3, c0, c1, 4		@ read ID_MMFR0
104	and	r3, r3, #0xf			@ extract VMSA support
105	cmp	r3, #5				@ long-descriptor translation table format?
106 THUMB( it	lo )				@ force fixup-able long branch encoding
107	blo	__error_p			@ only classic page table format
108#endif
109
110#ifndef CONFIG_XIP_KERNEL
111	adr	r3, 2f
112	ldmia	r3, {r4, r8}
113	sub	r4, r3, r4			@ (PHYS_OFFSET - PAGE_OFFSET)
114	add	r8, r8, r4			@ PHYS_OFFSET
115#else
116	ldr	r8, =PHYS_OFFSET		@ always constant in this case
117#endif
118
119	/*
120	 * r1 = machine no, r2 = atags or dtb,
121	 * r8 = phys_offset, r9 = cpuid, r10 = procinfo
122	 */
123	bl	__vet_atags
124#ifdef CONFIG_SMP_ON_UP
125	bl	__fixup_smp
126#endif
127#ifdef CONFIG_ARM_PATCH_PHYS_VIRT
128	bl	__fixup_pv_table
129#endif
130	bl	__create_page_tables
131
132	/*
133	 * The following calls CPU specific code in a position independent
134	 * manner.  See arch/arm/mm/proc-*.S for details.  r10 = base of
135	 * xxx_proc_info structure selected by __lookup_processor_type
136	 * above.  On return, the CPU will be ready for the MMU to be
137	 * turned on, and r0 will hold the CPU control register value.
138	 */
139	ldr	r13, =__mmap_switched		@ address to jump to after
140						@ mmu has been enabled
141	adr	lr, BSYM(1f)			@ return (PIC) address
142	mov	r8, r4				@ set TTBR1 to swapper_pg_dir
143 ARM(	add	pc, r10, #PROCINFO_INITFUNC	)
144 THUMB(	add	r12, r10, #PROCINFO_INITFUNC	)
145 THUMB(	mov	pc, r12				)
1461:	b	__enable_mmu
147ENDPROC(stext)
148	.ltorg
149#ifndef CONFIG_XIP_KERNEL
1502:	.long	.
151	.long	PAGE_OFFSET
152#endif
153
154/*
155 * Setup the initial page tables.  We only setup the barest
156 * amount which are required to get the kernel running, which
157 * generally means mapping in the kernel code.
158 *
159 * r8 = phys_offset, r9 = cpuid, r10 = procinfo
160 *
161 * Returns:
162 *  r0, r3, r5-r7 corrupted
163 *  r4 = physical page table address
164 */
165__create_page_tables:
166	pgtbl	r4, r8				@ page table address
167
168	/*
169	 * Clear the swapper page table
170	 */
171	mov	r0, r4
172	mov	r3, #0
173	add	r6, r0, #PG_DIR_SIZE
1741:	str	r3, [r0], #4
175	str	r3, [r0], #4
176	str	r3, [r0], #4
177	str	r3, [r0], #4
178	teq	r0, r6
179	bne	1b
180
181#ifdef CONFIG_ARM_LPAE
182	/*
183	 * Build the PGD table (first level) to point to the PMD table. A PGD
184	 * entry is 64-bit wide.
185	 */
186	mov	r0, r4
187	add	r3, r4, #0x1000			@ first PMD table address
188	orr	r3, r3, #3			@ PGD block type
189	mov	r6, #4				@ PTRS_PER_PGD
190	mov	r7, #1 << (55 - 32)		@ L_PGD_SWAPPER
1911:	str	r3, [r0], #4			@ set bottom PGD entry bits
192	str	r7, [r0], #4			@ set top PGD entry bits
193	add	r3, r3, #0x1000			@ next PMD table
194	subs	r6, r6, #1
195	bne	1b
196
197	add	r4, r4, #0x1000			@ point to the PMD tables
198#endif
199
200	ldr	r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags
201
202	/*
203	 * Create identity mapping to cater for __enable_mmu.
204	 * This identity mapping will be removed by paging_init().
205	 */
206	adr	r0, __turn_mmu_on_loc
207	ldmia	r0, {r3, r5, r6}
208	sub	r0, r0, r3			@ virt->phys offset
209	add	r5, r5, r0			@ phys __turn_mmu_on
210	add	r6, r6, r0			@ phys __turn_mmu_on_end
211	mov	r5, r5, lsr #SECTION_SHIFT
212	mov	r6, r6, lsr #SECTION_SHIFT
213
2141:	orr	r3, r7, r5, lsl #SECTION_SHIFT	@ flags + kernel base
215	str	r3, [r4, r5, lsl #PMD_ORDER]	@ identity mapping
216	cmp	r5, r6
217	addlo	r5, r5, #1			@ next section
218	blo	1b
219
220	/*
221	 * Now setup the pagetables for our kernel direct
222	 * mapped region.
223	 */
224	mov	r3, pc
225	mov	r3, r3, lsr #SECTION_SHIFT
226	orr	r3, r7, r3, lsl #SECTION_SHIFT
227	add	r0, r4,  #(KERNEL_START & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER)
228	str	r3, [r0, #((KERNEL_START & 0x00f00000) >> SECTION_SHIFT) << PMD_ORDER]!
229	ldr	r6, =(KERNEL_END - 1)
230	add	r0, r0, #1 << PMD_ORDER
231	add	r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
2321:	cmp	r0, r6
233	add	r3, r3, #1 << SECTION_SHIFT
234	strls	r3, [r0], #1 << PMD_ORDER
235	bls	1b
236
237#ifdef CONFIG_XIP_KERNEL
238	/*
239	 * Map some ram to cover our .data and .bss areas.
240	 */
241	add	r3, r8, #TEXT_OFFSET
242	orr	r3, r3, r7
243	add	r0, r4,  #(KERNEL_RAM_VADDR & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER)
244	str	r3, [r0, #(KERNEL_RAM_VADDR & 0x00f00000) >> (SECTION_SHIFT - PMD_ORDER)]!
245	ldr	r6, =(_end - 1)
246	add	r0, r0, #4
247	add	r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
2481:	cmp	r0, r6
249	add	r3, r3, #1 << 20
250	strls	r3, [r0], #4
251	bls	1b
252#endif
253
254	/*
255	 * Then map boot params address in r2 or the first 1MB (2MB with LPAE)
256	 * of ram if boot params address is not specified.
257	 * We map 2 sections in case the ATAGs/DTB crosses a section boundary.
258	 */
259	mov	r0, r2, lsr #SECTION_SHIFT
260	movs	r0, r0, lsl #SECTION_SHIFT
261	moveq	r0, r8
262	sub	r3, r0, r8
263	add	r3, r3, #PAGE_OFFSET
264	add	r3, r4, r3, lsr #(SECTION_SHIFT - PMD_ORDER)
265	orr	r6, r7, r0
266	str	r6, [r3], #1 << PMD_ORDER
267	add	r6, r6, #1 << SECTION_SHIFT
268	str	r6, [r3]
269
270#ifdef CONFIG_DEBUG_LL
271#if !defined(CONFIG_DEBUG_ICEDCC) && !defined(CONFIG_DEBUG_SEMIHOSTING)
272	/*
273	 * Map in IO space for serial debugging.
274	 * This allows debug messages to be output
275	 * via a serial console before paging_init.
276	 */
277	addruart r7, r3, r0
278
279	mov	r3, r3, lsr #SECTION_SHIFT
280	mov	r3, r3, lsl #PMD_ORDER
281
282	add	r0, r4, r3
283	rsb	r3, r3, #0x4000			@ PTRS_PER_PGD*sizeof(long)
284	cmp	r3, #0x0800			@ limit to 512MB
285	movhi	r3, #0x0800
286	add	r6, r0, r3
287	mov	r3, r7, lsr #SECTION_SHIFT
288	ldr	r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
289	orr	r3, r7, r3, lsl #SECTION_SHIFT
290#ifdef CONFIG_ARM_LPAE
291	mov	r7, #1 << (54 - 32)		@ XN
292#else
293	orr	r3, r3, #PMD_SECT_XN
294#endif
2951:	str	r3, [r0], #4
296#ifdef CONFIG_ARM_LPAE
297	str	r7, [r0], #4
298#endif
299	add	r3, r3, #1 << SECTION_SHIFT
300	cmp	r0, r6
301	blo	1b
302
303#else /* CONFIG_DEBUG_ICEDCC || CONFIG_DEBUG_SEMIHOSTING */
304	/* we don't need any serial debugging mappings */
305	ldr	r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
306#endif
307
308#if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS)
309	/*
310	 * If we're using the NetWinder or CATS, we also need to map
311	 * in the 16550-type serial port for the debug messages
312	 */
313	add	r0, r4, #0xff000000 >> (SECTION_SHIFT - PMD_ORDER)
314	orr	r3, r7, #0x7c000000
315	str	r3, [r0]
316#endif
317#ifdef CONFIG_ARCH_RPC
318	/*
319	 * Map in screen at 0x02000000 & SCREEN2_BASE
320	 * Similar reasons here - for debug.  This is
321	 * only for Acorn RiscPC architectures.
322	 */
323	add	r0, r4, #0x02000000 >> (SECTION_SHIFT - PMD_ORDER)
324	orr	r3, r7, #0x02000000
325	str	r3, [r0]
326	add	r0, r4, #0xd8000000 >> (SECTION_SHIFT - PMD_ORDER)
327	str	r3, [r0]
328#endif
329#endif
330#ifdef CONFIG_ARM_LPAE
331	sub	r4, r4, #0x1000		@ point to the PGD table
332#endif
333	mov	pc, lr
334ENDPROC(__create_page_tables)
335	.ltorg
336	.align
337__turn_mmu_on_loc:
338	.long	.
339	.long	__turn_mmu_on
340	.long	__turn_mmu_on_end
341
342#if defined(CONFIG_SMP)
343	__CPUINIT
344ENTRY(secondary_startup)
345	/*
346	 * Common entry point for secondary CPUs.
347	 *
348	 * Ensure that we're in SVC mode, and IRQs are disabled.  Lookup
349	 * the processor type - there is no need to check the machine type
350	 * as it has already been validated by the primary processor.
351	 */
352	setmode	PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9
353	mrc	p15, 0, r9, c0, c0		@ get processor id
354	bl	__lookup_processor_type
355	movs	r10, r5				@ invalid processor?
356	moveq	r0, #'p'			@ yes, error 'p'
357 THUMB( it	eq )		@ force fixup-able long branch encoding
358	beq	__error_p
359
360	/*
361	 * Use the page tables supplied from  __cpu_up.
362	 */
363	adr	r4, __secondary_data
364	ldmia	r4, {r5, r7, r12}		@ address to jump to after
365	sub	lr, r4, r5			@ mmu has been enabled
366	ldr	r4, [r7, lr]			@ get secondary_data.pgdir
367	add	r7, r7, #4
368	ldr	r8, [r7, lr]			@ get secondary_data.swapper_pg_dir
369	adr	lr, BSYM(__enable_mmu)		@ return address
370	mov	r13, r12			@ __secondary_switched address
371 ARM(	add	pc, r10, #PROCINFO_INITFUNC	) @ initialise processor
372						  @ (return control reg)
373 THUMB(	add	r12, r10, #PROCINFO_INITFUNC	)
374 THUMB(	mov	pc, r12				)
375ENDPROC(secondary_startup)
376
377	/*
378	 * r6  = &secondary_data
379	 */
380ENTRY(__secondary_switched)
381	ldr	sp, [r7, #4]			@ get secondary_data.stack
382	mov	fp, #0
383	b	secondary_start_kernel
384ENDPROC(__secondary_switched)
385
386	.align
387
388	.type	__secondary_data, %object
389__secondary_data:
390	.long	.
391	.long	secondary_data
392	.long	__secondary_switched
393#endif /* defined(CONFIG_SMP) */
394
395
396
397/*
398 * Setup common bits before finally enabling the MMU.  Essentially
399 * this is just loading the page table pointer and domain access
400 * registers.
401 *
402 *  r0  = cp#15 control register
403 *  r1  = machine ID
404 *  r2  = atags or dtb pointer
405 *  r4  = page table pointer
406 *  r9  = processor ID
407 *  r13 = *virtual* address to jump to upon completion
408 */
409__enable_mmu:
410#if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6
411	orr	r0, r0, #CR_A
412#else
413	bic	r0, r0, #CR_A
414#endif
415#ifdef CONFIG_CPU_DCACHE_DISABLE
416	bic	r0, r0, #CR_C
417#endif
418#ifdef CONFIG_CPU_BPREDICT_DISABLE
419	bic	r0, r0, #CR_Z
420#endif
421#ifdef CONFIG_CPU_ICACHE_DISABLE
422	bic	r0, r0, #CR_I
423#endif
424#ifdef CONFIG_ARM_LPAE
425	mov	r5, #0
426	mcrr	p15, 0, r4, r5, c2		@ load TTBR0
427#else
428	mov	r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
429		      domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
430		      domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
431		      domain_val(DOMAIN_IO, DOMAIN_CLIENT))
432	mcr	p15, 0, r5, c3, c0, 0		@ load domain access register
433	mcr	p15, 0, r4, c2, c0, 0		@ load page table pointer
434#endif
435	b	__turn_mmu_on
436ENDPROC(__enable_mmu)
437
438/*
439 * Enable the MMU.  This completely changes the structure of the visible
440 * memory space.  You will not be able to trace execution through this.
441 * If you have an enquiry about this, *please* check the linux-arm-kernel
442 * mailing list archives BEFORE sending another post to the list.
443 *
444 *  r0  = cp#15 control register
445 *  r1  = machine ID
446 *  r2  = atags or dtb pointer
447 *  r9  = processor ID
448 *  r13 = *virtual* address to jump to upon completion
449 *
450 * other registers depend on the function called upon completion
451 */
452	.align	5
453	.pushsection	.idmap.text, "ax"
454ENTRY(__turn_mmu_on)
455	mov	r0, r0
456	instr_sync
457	mcr	p15, 0, r0, c1, c0, 0		@ write control reg
458	mrc	p15, 0, r3, c0, c0, 0		@ read id reg
459	instr_sync
460	mov	r3, r3
461	mov	r3, r13
462	mov	pc, r3
463__turn_mmu_on_end:
464ENDPROC(__turn_mmu_on)
465	.popsection
466
467
468#ifdef CONFIG_SMP_ON_UP
469	__INIT
470__fixup_smp:
471	and	r3, r9, #0x000f0000	@ architecture version
472	teq	r3, #0x000f0000		@ CPU ID supported?
473	bne	__fixup_smp_on_up	@ no, assume UP
474
475	bic	r3, r9, #0x00ff0000
476	bic	r3, r3, #0x0000000f	@ mask 0xff00fff0
477	mov	r4, #0x41000000
478	orr	r4, r4, #0x0000b000
479	orr	r4, r4, #0x00000020	@ val 0x4100b020
480	teq	r3, r4			@ ARM 11MPCore?
481	moveq	pc, lr			@ yes, assume SMP
482
483	mrc	p15, 0, r0, c0, c0, 5	@ read MPIDR
484	and	r0, r0, #0xc0000000	@ multiprocessing extensions and
485	teq	r0, #0x80000000		@ not part of a uniprocessor system?
486	moveq	pc, lr			@ yes, assume SMP
487
488__fixup_smp_on_up:
489	adr	r0, 1f
490	ldmia	r0, {r3 - r5}
491	sub	r3, r0, r3
492	add	r4, r4, r3
493	add	r5, r5, r3
494	b	__do_fixup_smp_on_up
495ENDPROC(__fixup_smp)
496
497	.align
4981:	.word	.
499	.word	__smpalt_begin
500	.word	__smpalt_end
501
502	.pushsection .data
503	.globl	smp_on_up
504smp_on_up:
505	ALT_SMP(.long	1)
506	ALT_UP(.long	0)
507	.popsection
508#endif
509
510	.text
511__do_fixup_smp_on_up:
512	cmp	r4, r5
513	movhs	pc, lr
514	ldmia	r4!, {r0, r6}
515 ARM(	str	r6, [r0, r3]	)
516 THUMB(	add	r0, r0, r3	)
517#ifdef __ARMEB__
518 THUMB(	mov	r6, r6, ror #16	)	@ Convert word order for big-endian.
519#endif
520 THUMB(	strh	r6, [r0], #2	)	@ For Thumb-2, store as two halfwords
521 THUMB(	mov	r6, r6, lsr #16	)	@ to be robust against misaligned r3.
522 THUMB(	strh	r6, [r0]	)
523	b	__do_fixup_smp_on_up
524ENDPROC(__do_fixup_smp_on_up)
525
526ENTRY(fixup_smp)
527	stmfd	sp!, {r4 - r6, lr}
528	mov	r4, r0
529	add	r5, r0, r1
530	mov	r3, #0
531	bl	__do_fixup_smp_on_up
532	ldmfd	sp!, {r4 - r6, pc}
533ENDPROC(fixup_smp)
534
535#ifdef CONFIG_ARM_PATCH_PHYS_VIRT
536
537/* __fixup_pv_table - patch the stub instructions with the delta between
538 * PHYS_OFFSET and PAGE_OFFSET, which is assumed to be 16MiB aligned and
539 * can be expressed by an immediate shifter operand. The stub instruction
540 * has a form of '(add|sub) rd, rn, #imm'.
541 */
542	__HEAD
543__fixup_pv_table:
544	adr	r0, 1f
545	ldmia	r0, {r3-r5, r7}
546	sub	r3, r0, r3	@ PHYS_OFFSET - PAGE_OFFSET
547	add	r4, r4, r3	@ adjust table start address
548	add	r5, r5, r3	@ adjust table end address
549	add	r7, r7, r3	@ adjust __pv_phys_offset address
550	str	r8, [r7]	@ save computed PHYS_OFFSET to __pv_phys_offset
551	mov	r6, r3, lsr #24	@ constant for add/sub instructions
552	teq	r3, r6, lsl #24 @ must be 16MiB aligned
553THUMB(	it	ne		@ cross section branch )
554	bne	__error
555	str	r6, [r7, #4]	@ save to __pv_offset
556	b	__fixup_a_pv_table
557ENDPROC(__fixup_pv_table)
558
559	.align
5601:	.long	.
561	.long	__pv_table_begin
562	.long	__pv_table_end
5632:	.long	__pv_phys_offset
564
565	.text
566__fixup_a_pv_table:
567#ifdef CONFIG_THUMB2_KERNEL
568	lsls	r6, #24
569	beq	2f
570	clz	r7, r6
571	lsr	r6, #24
572	lsl	r6, r7
573	bic	r6, #0x0080
574	lsrs	r7, #1
575	orrcs	r6, #0x0080
576	orr	r6, r6, r7, lsl #12
577	orr	r6, #0x4000
578	b	2f
5791:	add     r7, r3
580	ldrh	ip, [r7, #2]
581	and	ip, 0x8f00
582	orr	ip, r6	@ mask in offset bits 31-24
583	strh	ip, [r7, #2]
5842:	cmp	r4, r5
585	ldrcc	r7, [r4], #4	@ use branch for delay slot
586	bcc	1b
587	bx	lr
588#else
589	b	2f
5901:	ldr	ip, [r7, r3]
591	bic	ip, ip, #0x000000ff
592	orr	ip, ip, r6	@ mask in offset bits 31-24
593	str	ip, [r7, r3]
5942:	cmp	r4, r5
595	ldrcc	r7, [r4], #4	@ use branch for delay slot
596	bcc	1b
597	mov	pc, lr
598#endif
599ENDPROC(__fixup_a_pv_table)
600
601ENTRY(fixup_pv_table)
602	stmfd	sp!, {r4 - r7, lr}
603	ldr	r2, 2f			@ get address of __pv_phys_offset
604	mov	r3, #0			@ no offset
605	mov	r4, r0			@ r0 = table start
606	add	r5, r0, r1		@ r1 = table size
607	ldr	r6, [r2, #4]		@ get __pv_offset
608	bl	__fixup_a_pv_table
609	ldmfd	sp!, {r4 - r7, pc}
610ENDPROC(fixup_pv_table)
611
612	.align
6132:	.long	__pv_phys_offset
614
615	.data
616	.globl	__pv_phys_offset
617	.type	__pv_phys_offset, %object
618__pv_phys_offset:
619	.long	0
620	.size	__pv_phys_offset, . - __pv_phys_offset
621__pv_offset:
622	.long	0
623#endif
624
625#include "head-common.S"
626