1 /*
2 * arch/arch/mach-ixp4xx/vulcan-pci.c
3 *
4 * Vulcan board-level PCI initialization
5 *
6 * Copyright (C) 2010 Marc Zyngier <maz@misterjones.org>
7 *
8 * based on ixdp425-pci.c:
9 * Copyright (C) 2002 Intel Corporation.
10 * Copyright (C) 2003-2004 MontaVista Software, Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 */
17
18 #include <linux/pci.h>
19 #include <linux/init.h>
20 #include <linux/irq.h>
21 #include <asm/mach/pci.h>
22 #include <asm/mach-types.h>
23
24 /* PCI controller GPIO to IRQ pin mappings */
25 #define INTA 2
26 #define INTB 3
27
vulcan_pci_preinit(void)28 void __init vulcan_pci_preinit(void)
29 {
30 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
31 /*
32 * Cardbus bridge wants way more than the SoC can actually offer,
33 * and leaves the whole PCI bus in a mess. Artificially limit it
34 * to 8MB per region. Of course indirect mode doesn't have this
35 * limitation...
36 */
37 pci_cardbus_mem_size = SZ_8M;
38 pr_info("Vulcan PCI: limiting CardBus memory size to %dMB\n",
39 (int)(pci_cardbus_mem_size >> 20));
40 #endif
41 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
42 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
43 ixp4xx_pci_preinit();
44 }
45
vulcan_map_irq(struct pci_dev * dev,u8 slot,u8 pin)46 static int __init vulcan_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
47 {
48 if (slot == 1)
49 return IXP4XX_GPIO_IRQ(INTA);
50
51 if (slot == 2)
52 return IXP4XX_GPIO_IRQ(INTB);
53
54 return -1;
55 }
56
57 struct hw_pci vulcan_pci __initdata = {
58 .nr_controllers = 1,
59 .preinit = vulcan_pci_preinit,
60 .swizzle = pci_std_swizzle,
61 .setup = ixp4xx_setup,
62 .scan = ixp4xx_scan_bus,
63 .map_irq = vulcan_map_irq,
64 };
65
vulcan_pci_init(void)66 int __init vulcan_pci_init(void)
67 {
68 if (machine_is_arcom_vulcan())
69 pci_common_init(&vulcan_pci);
70 return 0;
71 }
72
73 subsys_initcall(vulcan_pci_init);
74