1/* 2 * Device Tree Source for AM33XX SoC 3 * 4 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ 5 * 6 * This file is licensed under the terms of the GNU General Public License 7 * version 2. This program is licensed "as is" without any warranty of any 8 * kind, whether express or implied. 9 */ 10 11#include <dt-bindings/bus/ti-sysc.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/pinctrl/am33xx.h> 14#include <dt-bindings/clock/am3.h> 15 16/ { 17 compatible = "ti,am33xx"; 18 interrupt-parent = <&intc>; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 chosen { }; 22 23 aliases { 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 serial0 = &uart0; 28 serial1 = &uart1; 29 serial2 = &uart2; 30 serial3 = &uart3; 31 serial4 = &uart4; 32 serial5 = &uart5; 33 d-can0 = &dcan0; 34 d-can1 = &dcan1; 35 usb0 = &usb0; 36 usb1 = &usb1; 37 phy0 = &usb0_phy; 38 phy1 = &usb1_phy; 39 ethernet0 = &cpsw_port1; 40 ethernet1 = &cpsw_port2; 41 spi0 = &spi0; 42 spi1 = &spi1; 43 mmc0 = &mmc1; 44 mmc1 = &mmc2; 45 mmc2 = &mmc3; 46 }; 47 48 cpus { 49 #address-cells = <1>; 50 #size-cells = <0>; 51 cpu@0 { 52 compatible = "arm,cortex-a8"; 53 enable-method = "ti,am3352"; 54 device_type = "cpu"; 55 reg = <0>; 56 57 operating-points-v2 = <&cpu0_opp_table>; 58 59 clocks = <&dpll_mpu_ck>; 60 clock-names = "cpu"; 61 62 clock-latency = <300000>; /* From omap-cpufreq driver */ 63 cpu-idle-states = <&mpu_gate>; 64 }; 65 66 idle-states { 67 mpu_gate: mpu_gate { 68 compatible = "arm,idle-state"; 69 entry-latency-us = <40>; 70 exit-latency-us = <90>; 71 min-residency-us = <300>; 72 ti,idle-wkup-m3; 73 }; 74 }; 75 }; 76 77 cpu0_opp_table: opp-table { 78 compatible = "operating-points-v2-ti-cpu"; 79 syscon = <&scm_conf>; 80 81 /* 82 * The three following nodes are marked with opp-suspend 83 * because the can not be enabled simultaneously on a 84 * single SoC. 85 */ 86 opp50-300000000 { 87 opp-hz = /bits/ 64 <300000000>; 88 opp-microvolt = <950000 931000 969000>; 89 opp-supported-hw = <0x06 0x0010>; 90 opp-suspend; 91 }; 92 93 opp100-275000000 { 94 opp-hz = /bits/ 64 <275000000>; 95 opp-microvolt = <1100000 1078000 1122000>; 96 opp-supported-hw = <0x01 0x00FF>; 97 opp-suspend; 98 }; 99 100 opp100-300000000 { 101 opp-hz = /bits/ 64 <300000000>; 102 opp-microvolt = <1100000 1078000 1122000>; 103 opp-supported-hw = <0x06 0x0020>; 104 opp-suspend; 105 }; 106 107 opp100-500000000 { 108 opp-hz = /bits/ 64 <500000000>; 109 opp-microvolt = <1100000 1078000 1122000>; 110 opp-supported-hw = <0x01 0xFFFF>; 111 }; 112 113 opp100-600000000 { 114 opp-hz = /bits/ 64 <600000000>; 115 opp-microvolt = <1100000 1078000 1122000>; 116 opp-supported-hw = <0x06 0x0040>; 117 }; 118 119 opp120-600000000 { 120 opp-hz = /bits/ 64 <600000000>; 121 opp-microvolt = <1200000 1176000 1224000>; 122 opp-supported-hw = <0x01 0xFFFF>; 123 }; 124 125 opp120-720000000 { 126 opp-hz = /bits/ 64 <720000000>; 127 opp-microvolt = <1200000 1176000 1224000>; 128 opp-supported-hw = <0x06 0x0080>; 129 }; 130 131 oppturbo-720000000 { 132 opp-hz = /bits/ 64 <720000000>; 133 opp-microvolt = <1260000 1234800 1285200>; 134 opp-supported-hw = <0x01 0xFFFF>; 135 }; 136 137 oppturbo-800000000 { 138 opp-hz = /bits/ 64 <800000000>; 139 opp-microvolt = <1260000 1234800 1285200>; 140 opp-supported-hw = <0x06 0x0100>; 141 }; 142 143 oppnitro-1000000000 { 144 opp-hz = /bits/ 64 <1000000000>; 145 opp-microvolt = <1325000 1298500 1351500>; 146 opp-supported-hw = <0x04 0x0200>; 147 }; 148 }; 149 150 target-module@4b000000 { 151 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 152 clocks = <&l3_clkctrl AM3_L3_L3_INSTR_CLKCTRL 0>; 153 clock-names = "fck"; 154 ti,no-idle; 155 #address-cells = <1>; 156 #size-cells = <1>; 157 ranges = <0x0 0x4b000000 0x1000000>; 158 159 target-module@140000 { 160 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 161 clocks = <&l3_aon_clkctrl AM3_L3_AON_DEBUGSS_CLKCTRL 0>; 162 clock-names = "fck"; 163 #address-cells = <1>; 164 #size-cells = <1>; 165 ranges = <0x0 0x140000 0xec0000>; 166 167 pmu@0 { 168 compatible = "arm,cortex-a8-pmu"; 169 interrupts = <3>; 170 }; 171 }; 172 }; 173 174 /* 175 * The soc node represents the soc top level view. It is used for IPs 176 * that are not memory mapped in the MPU view or for the MPU itself. 177 */ 178 soc { 179 compatible = "ti,omap-infra"; 180 }; 181 182 /* 183 * XXX: Use a flat representation of the AM33XX interconnect. 184 * The real AM33XX interconnect network is quite complex. Since 185 * it will not bring real advantage to represent that in DT 186 * for the moment, just use a fake OCP bus entry to represent 187 * the whole bus hierarchy. 188 */ 189 ocp: ocp { 190 compatible = "simple-pm-bus"; 191 power-domains = <&prm_per>; 192 clocks = <&l3_clkctrl AM3_L3_L3_MAIN_CLKCTRL 0>; 193 clock-names = "fck"; 194 #address-cells = <1>; 195 #size-cells = <1>; 196 ranges; 197 198 l4_wkup: interconnect@44c00000 { 199 }; 200 l4_per: interconnect@48000000 { 201 }; 202 l4_fw: interconnect@47c00000 { 203 }; 204 l4_fast: interconnect@4a000000 { 205 }; 206 l4_mpuss: interconnect@4b140000 { 207 }; 208 209 intc: interrupt-controller@48200000 { 210 compatible = "ti,am33xx-intc"; 211 interrupt-controller; 212 #interrupt-cells = <1>; 213 reg = <0x48200000 0x1000>; 214 }; 215 216 target-module@49000000 { 217 compatible = "ti,sysc-omap4", "ti,sysc"; 218 reg = <0x49000000 0x4>; 219 reg-names = "rev"; 220 clocks = <&l3_clkctrl AM3_L3_TPCC_CLKCTRL 0>; 221 clock-names = "fck"; 222 #address-cells = <1>; 223 #size-cells = <1>; 224 ranges = <0x0 0x49000000 0x10000>; 225 226 edma: dma@0 { 227 compatible = "ti,edma3-tpcc"; 228 reg = <0 0x10000>; 229 reg-names = "edma3_cc"; 230 interrupts = <12 13 14>; 231 interrupt-names = "edma3_ccint", "edma3_mperr", 232 "edma3_ccerrint"; 233 dma-requests = <64>; 234 #dma-cells = <2>; 235 236 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, 237 <&edma_tptc2 0>; 238 239 ti,edma-memcpy-channels = <20 21>; 240 }; 241 }; 242 243 target-module@49800000 { 244 compatible = "ti,sysc-omap4", "ti,sysc"; 245 reg = <0x49800000 0x4>, 246 <0x49800010 0x4>; 247 reg-names = "rev", "sysc"; 248 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 249 ti,sysc-midle = <SYSC_IDLE_FORCE>; 250 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 251 <SYSC_IDLE_SMART>; 252 clocks = <&l3_clkctrl AM3_L3_TPTC0_CLKCTRL 0>; 253 clock-names = "fck"; 254 #address-cells = <1>; 255 #size-cells = <1>; 256 ranges = <0x0 0x49800000 0x100000>; 257 258 edma_tptc0: dma@0 { 259 compatible = "ti,edma3-tptc"; 260 reg = <0 0x100000>; 261 interrupts = <112>; 262 interrupt-names = "edma3_tcerrint"; 263 }; 264 }; 265 266 target-module@49900000 { 267 compatible = "ti,sysc-omap4", "ti,sysc"; 268 reg = <0x49900000 0x4>, 269 <0x49900010 0x4>; 270 reg-names = "rev", "sysc"; 271 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 272 ti,sysc-midle = <SYSC_IDLE_FORCE>; 273 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 274 <SYSC_IDLE_SMART>; 275 clocks = <&l3_clkctrl AM3_L3_TPTC1_CLKCTRL 0>; 276 clock-names = "fck"; 277 #address-cells = <1>; 278 #size-cells = <1>; 279 ranges = <0x0 0x49900000 0x100000>; 280 281 edma_tptc1: dma@0 { 282 compatible = "ti,edma3-tptc"; 283 reg = <0 0x100000>; 284 interrupts = <113>; 285 interrupt-names = "edma3_tcerrint"; 286 }; 287 }; 288 289 target-module@49a00000 { 290 compatible = "ti,sysc-omap4", "ti,sysc"; 291 reg = <0x49a00000 0x4>, 292 <0x49a00010 0x4>; 293 reg-names = "rev", "sysc"; 294 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 295 ti,sysc-midle = <SYSC_IDLE_FORCE>; 296 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 297 <SYSC_IDLE_SMART>; 298 clocks = <&l3_clkctrl AM3_L3_TPTC2_CLKCTRL 0>; 299 clock-names = "fck"; 300 #address-cells = <1>; 301 #size-cells = <1>; 302 ranges = <0x0 0x49a00000 0x100000>; 303 304 edma_tptc2: dma@0 { 305 compatible = "ti,edma3-tptc"; 306 reg = <0 0x100000>; 307 interrupts = <114>; 308 interrupt-names = "edma3_tcerrint"; 309 }; 310 }; 311 312 target-module@47810000 { 313 compatible = "ti,sysc-omap2", "ti,sysc"; 314 reg = <0x478102fc 0x4>, 315 <0x47810110 0x4>, 316 <0x47810114 0x4>; 317 reg-names = "rev", "sysc", "syss"; 318 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 319 SYSC_OMAP2_ENAWAKEUP | 320 SYSC_OMAP2_SOFTRESET | 321 SYSC_OMAP2_AUTOIDLE)>; 322 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 323 <SYSC_IDLE_NO>, 324 <SYSC_IDLE_SMART>; 325 ti,syss-mask = <1>; 326 clocks = <&l3s_clkctrl AM3_L3S_MMC3_CLKCTRL 0>; 327 clock-names = "fck"; 328 #address-cells = <1>; 329 #size-cells = <1>; 330 ranges = <0x0 0x47810000 0x1000>; 331 332 mmc3: mmc@0 { 333 compatible = "ti,am335-sdhci"; 334 ti,needs-special-reset; 335 interrupts = <29>; 336 reg = <0x0 0x1000>; 337 status = "disabled"; 338 }; 339 }; 340 341 usb: target-module@47400000 { 342 compatible = "ti,sysc-omap4", "ti,sysc"; 343 reg = <0x47400000 0x4>, 344 <0x47400010 0x4>; 345 reg-names = "rev", "sysc"; 346 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 347 SYSC_OMAP4_SOFTRESET)>; 348 ti,sysc-midle = <SYSC_IDLE_FORCE>, 349 <SYSC_IDLE_NO>, 350 <SYSC_IDLE_SMART>; 351 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 352 <SYSC_IDLE_NO>, 353 <SYSC_IDLE_SMART>, 354 <SYSC_IDLE_SMART_WKUP>; 355 clocks = <&l3s_clkctrl AM3_L3S_USB_OTG_HS_CLKCTRL 0>; 356 clock-names = "fck"; 357 #address-cells = <1>; 358 #size-cells = <1>; 359 ranges = <0x0 0x47400000 0x8000>; 360 361 usb0_phy: usb-phy@1300 { 362 compatible = "ti,am335x-usb-phy"; 363 reg = <0x1300 0x100>; 364 reg-names = "phy"; 365 ti,ctrl_mod = <&usb_ctrl_mod>; 366 #phy-cells = <0>; 367 }; 368 369 usb0: usb@1400 { 370 compatible = "ti,musb-am33xx"; 371 reg = <0x1400 0x400>, 372 <0x1000 0x200>; 373 reg-names = "mc", "control"; 374 375 interrupts = <18>; 376 interrupt-names = "mc"; 377 dr_mode = "otg"; 378 mentor,multipoint = <1>; 379 mentor,num-eps = <16>; 380 mentor,ram-bits = <12>; 381 mentor,power = <500>; 382 phys = <&usb0_phy>; 383 384 dmas = <&cppi41dma 0 0 &cppi41dma 1 0 385 &cppi41dma 2 0 &cppi41dma 3 0 386 &cppi41dma 4 0 &cppi41dma 5 0 387 &cppi41dma 6 0 &cppi41dma 7 0 388 &cppi41dma 8 0 &cppi41dma 9 0 389 &cppi41dma 10 0 &cppi41dma 11 0 390 &cppi41dma 12 0 &cppi41dma 13 0 391 &cppi41dma 14 0 &cppi41dma 0 1 392 &cppi41dma 1 1 &cppi41dma 2 1 393 &cppi41dma 3 1 &cppi41dma 4 1 394 &cppi41dma 5 1 &cppi41dma 6 1 395 &cppi41dma 7 1 &cppi41dma 8 1 396 &cppi41dma 9 1 &cppi41dma 10 1 397 &cppi41dma 11 1 &cppi41dma 12 1 398 &cppi41dma 13 1 &cppi41dma 14 1>; 399 dma-names = 400 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", 401 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", 402 "rx14", "rx15", 403 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", 404 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", 405 "tx14", "tx15"; 406 }; 407 408 usb1_phy: usb-phy@1b00 { 409 compatible = "ti,am335x-usb-phy"; 410 reg = <0x1b00 0x100>; 411 reg-names = "phy"; 412 ti,ctrl_mod = <&usb_ctrl_mod>; 413 #phy-cells = <0>; 414 }; 415 416 usb1: usb@1800 { 417 compatible = "ti,musb-am33xx"; 418 reg = <0x1c00 0x400>, 419 <0x1800 0x200>; 420 reg-names = "mc", "control"; 421 interrupts = <19>; 422 interrupt-names = "mc"; 423 dr_mode = "otg"; 424 mentor,multipoint = <1>; 425 mentor,num-eps = <16>; 426 mentor,ram-bits = <12>; 427 mentor,power = <500>; 428 phys = <&usb1_phy>; 429 430 dmas = <&cppi41dma 15 0 &cppi41dma 16 0 431 &cppi41dma 17 0 &cppi41dma 18 0 432 &cppi41dma 19 0 &cppi41dma 20 0 433 &cppi41dma 21 0 &cppi41dma 22 0 434 &cppi41dma 23 0 &cppi41dma 24 0 435 &cppi41dma 25 0 &cppi41dma 26 0 436 &cppi41dma 27 0 &cppi41dma 28 0 437 &cppi41dma 29 0 &cppi41dma 15 1 438 &cppi41dma 16 1 &cppi41dma 17 1 439 &cppi41dma 18 1 &cppi41dma 19 1 440 &cppi41dma 20 1 &cppi41dma 21 1 441 &cppi41dma 22 1 &cppi41dma 23 1 442 &cppi41dma 24 1 &cppi41dma 25 1 443 &cppi41dma 26 1 &cppi41dma 27 1 444 &cppi41dma 28 1 &cppi41dma 29 1>; 445 dma-names = 446 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", 447 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", 448 "rx14", "rx15", 449 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", 450 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", 451 "tx14", "tx15"; 452 }; 453 454 cppi41dma: dma-controller@2000 { 455 compatible = "ti,am3359-cppi41"; 456 reg = <0x0000 0x1000>, 457 <0x2000 0x1000>, 458 <0x3000 0x1000>, 459 <0x4000 0x4000>; 460 reg-names = "glue", "controller", "scheduler", "queuemgr"; 461 interrupts = <17>; 462 interrupt-names = "glue"; 463 #dma-cells = <2>; 464 /* For backwards compatibility: */ 465 #dma-channels = <30>; 466 dma-channels = <30>; 467 #dma-requests = <256>; 468 dma-requests = <256>; 469 }; 470 }; 471 472 target-module@40300000 { 473 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 474 clocks = <&l3_clkctrl AM3_L3_OCMCRAM_CLKCTRL 0>; 475 clock-names = "fck"; 476 ti,no-idle; 477 #address-cells = <1>; 478 #size-cells = <1>; 479 ranges = <0 0x40300000 0x10000>; 480 481 ocmcram: sram@0 { 482 compatible = "mmio-sram"; 483 reg = <0 0x10000>; /* 64k */ 484 ranges = <0 0 0x10000>; 485 #address-cells = <1>; 486 #size-cells = <1>; 487 488 pm_sram_code: pm-code-sram@0 { 489 compatible = "ti,sram"; 490 reg = <0x0 0x1000>; 491 protect-exec; 492 }; 493 494 pm_sram_data: pm-data-sram@1000 { 495 compatible = "ti,sram"; 496 reg = <0x1000 0x1000>; 497 pool; 498 }; 499 }; 500 }; 501 502 target-module@4c000000 { 503 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 504 reg = <0x4c000000 0x4>; 505 reg-names = "rev"; 506 clocks = <&l3_clkctrl AM3_L3_EMIF_CLKCTRL 0>; 507 clock-names = "fck"; 508 ti,no-idle; 509 #address-cells = <1>; 510 #size-cells = <1>; 511 ranges = <0x0 0x4c000000 0x1000000>; 512 513 emif: emif@0 { 514 compatible = "ti,emif-am3352"; 515 reg = <0 0x1000000>; 516 interrupts = <101>; 517 sram = <&pm_sram_code 518 &pm_sram_data>; 519 }; 520 }; 521 522 target-module@50000000 { 523 compatible = "ti,sysc-omap2", "ti,sysc"; 524 reg = <0x50000000 4>, 525 <0x50000010 4>, 526 <0x50000014 4>; 527 reg-names = "rev", "sysc", "syss"; 528 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 529 <SYSC_IDLE_NO>, 530 <SYSC_IDLE_SMART>; 531 ti,syss-mask = <1>; 532 clocks = <&l3s_clkctrl AM3_L3S_GPMC_CLKCTRL 0>; 533 clock-names = "fck"; 534 #address-cells = <1>; 535 #size-cells = <1>; 536 ranges = <0x50000000 0x50000000 0x00001000>, /* regs */ 537 <0x00000000 0x00000000 0x40000000>; /* data */ 538 539 gpmc: gpmc@50000000 { 540 compatible = "ti,am3352-gpmc"; 541 reg = <0x50000000 0x2000>; 542 interrupts = <100>; 543 dmas = <&edma 52 0>; 544 dma-names = "rxtx"; 545 gpmc,num-cs = <7>; 546 gpmc,num-waitpins = <2>; 547 #address-cells = <2>; 548 #size-cells = <1>; 549 interrupt-controller; 550 #interrupt-cells = <2>; 551 gpio-controller; 552 #gpio-cells = <2>; 553 status = "disabled"; 554 }; 555 }; 556 557 sham_target: target-module@53100000 { 558 compatible = "ti,sysc-omap3-sham", "ti,sysc"; 559 reg = <0x53100100 0x4>, 560 <0x53100110 0x4>, 561 <0x53100114 0x4>; 562 reg-names = "rev", "sysc", "syss"; 563 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 564 SYSC_OMAP2_AUTOIDLE)>; 565 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 566 <SYSC_IDLE_NO>, 567 <SYSC_IDLE_SMART>; 568 ti,syss-mask = <1>; 569 /* Domains (P, C): per_pwrdm, l3_clkdm */ 570 clocks = <&l3_clkctrl AM3_L3_SHAM_CLKCTRL 0>; 571 clock-names = "fck"; 572 #address-cells = <1>; 573 #size-cells = <1>; 574 ranges = <0x0 0x53100000 0x1000>; 575 576 sham: sham@0 { 577 compatible = "ti,omap4-sham"; 578 reg = <0 0x200>; 579 interrupts = <109>; 580 dmas = <&edma 36 0>; 581 dma-names = "rx"; 582 }; 583 }; 584 585 aes_target: target-module@53500000 { 586 compatible = "ti,sysc-omap2", "ti,sysc"; 587 reg = <0x53500080 0x4>, 588 <0x53500084 0x4>, 589 <0x53500088 0x4>; 590 reg-names = "rev", "sysc", "syss"; 591 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 592 SYSC_OMAP2_AUTOIDLE)>; 593 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 594 <SYSC_IDLE_NO>, 595 <SYSC_IDLE_SMART>, 596 <SYSC_IDLE_SMART_WKUP>; 597 ti,syss-mask = <1>; 598 /* Domains (P, C): per_pwrdm, l3_clkdm */ 599 clocks = <&l3_clkctrl AM3_L3_AES_CLKCTRL 0>; 600 clock-names = "fck"; 601 #address-cells = <1>; 602 #size-cells = <1>; 603 ranges = <0x0 0x53500000 0x1000>; 604 605 aes: aes@0 { 606 compatible = "ti,omap4-aes"; 607 reg = <0 0xa0>; 608 interrupts = <103>; 609 dmas = <&edma 6 0>, 610 <&edma 5 0>; 611 dma-names = "tx", "rx"; 612 }; 613 }; 614 615 target-module@56000000 { 616 compatible = "ti,sysc-omap4", "ti,sysc"; 617 reg = <0x5600fe00 0x4>, 618 <0x5600fe10 0x4>; 619 reg-names = "rev", "sysc"; 620 ti,sysc-midle = <SYSC_IDLE_FORCE>, 621 <SYSC_IDLE_NO>, 622 <SYSC_IDLE_SMART>; 623 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 624 <SYSC_IDLE_NO>, 625 <SYSC_IDLE_SMART>; 626 clocks = <&gfx_l3_clkctrl AM3_GFX_L3_GFX_CLKCTRL 0>; 627 clock-names = "fck"; 628 power-domains = <&prm_gfx>; 629 resets = <&prm_gfx 0>; 630 reset-names = "rstctrl"; 631 #address-cells = <1>; 632 #size-cells = <1>; 633 ranges = <0 0x56000000 0x1000000>; 634 635 /* 636 * Closed source PowerVR driver, no child device 637 * binding or driver in mainline 638 */ 639 }; 640 }; 641}; 642 643#include "am33xx-l4.dtsi" 644#include "am33xx-clocks.dtsi" 645 646&prcm { 647 prm_per: prm@c00 { 648 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; 649 reg = <0xc00 0x100>; 650 #reset-cells = <1>; 651 #power-domain-cells = <0>; 652 }; 653 654 prm_wkup: prm@d00 { 655 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; 656 reg = <0xd00 0x100>; 657 #reset-cells = <1>; 658 #power-domain-cells = <0>; 659 }; 660 661 prm_mpu: prm@e00 { 662 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; 663 reg = <0xe00 0x100>; 664 #power-domain-cells = <0>; 665 }; 666 667 prm_device: prm@f00 { 668 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; 669 reg = <0xf00 0x100>; 670 #reset-cells = <1>; 671 }; 672 673 prm_rtc: prm@1000 { 674 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; 675 reg = <0x1000 0x100>; 676 #power-domain-cells = <0>; 677 }; 678 679 prm_gfx: prm@1100 { 680 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; 681 reg = <0x1100 0x100>; 682 #power-domain-cells = <0>; 683 #reset-cells = <1>; 684 }; 685 686 prm_cefuse: prm@1200 { 687 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; 688 reg = <0x1200 0x100>; 689 #power-domain-cells = <0>; 690 }; 691}; 692 693/* Preferred always-on timer for clocksource */ 694&timer1_target { 695 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_TIMER1_CLKCTRL 0>, 696 <&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>; 697 clock-names = "fck", "ick"; 698 ti,no-reset-on-init; 699 ti,no-idle; 700 timer@0 { 701 assigned-clocks = <&timer1_fck>; 702 assigned-clock-parents = <&sys_clkin_ck>; 703 }; 704}; 705 706/* Preferred timer for clockevent */ 707&timer2_target { 708 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER2_CLKCTRL 0>, 709 <&l4ls_clkctrl AM3_L4LS_L4_LS_CLKCTRL 0>; 710 clock-names = "fck", "ick"; 711 ti,no-reset-on-init; 712 ti,no-idle; 713 timer@0 { 714 assigned-clocks = <&timer2_fck>; 715 assigned-clock-parents = <&sys_clkin_ck>; 716 }; 717}; 718