1/*
2 * SA11x0 Assembler Sleep/WakeUp Management Routines
3 *
4 * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License.
8 *
9 * History:
10 *
11 * 2001-02-06: Cliff Brake         Initial code
12 *
13 * 2001-08-29:	Nicolas Pitre	Simplified.
14 *
15 * 2002-05-27:	Nicolas Pitre	Revisited, more cleanup and simplification.
16 *				Storage is on the stack now.
17 */
18
19#include <linux/linkage.h>
20#include <asm/assembler.h>
21#include <asm/hardware.h>
22
23
24		.text
25
26/*
27 * sa1100_cpu_suspend()
28 *
29 * Causes sa11x0 to enter sleep state
30 *
31 */
32
33ENTRY(sa1100_cpu_suspend)
34
35	stmfd	sp!, {r4 - r12, lr}		@ save registers on stack
36
37	@ get coprocessor registers
38	mrc 	p15, 0, r4, c3, c0, 0		@ domain ID
39	mrc 	p15, 0, r5, c2, c0, 0		@ translation table base addr
40	mrc	p15, 0, r6, c13, c0, 0		@ PID
41	mrc 	p15, 0, r7, c1, c0, 0		@ control reg
42
43	@ store them plus current virtual stack ptr on stack
44	mov	r8, sp
45	stmfd	sp!, {r4 - r8}
46
47	@ preserve phys address of stack
48	mov	r0, sp
49	bl	sleep_phys_sp
50	ldr	r1, =sleep_save_sp
51	str	r0, [r1]
52
53	@ clean data cache and invalidate WB
54	bl	cpu_sa1100_cache_clean_invalidate_all
55
56	@ disable clock switching
57	mcr	p15, 0, r1, c15, c2, 2
58
59        @ Adjust memory timing before lowering CPU clock
60	@ Clock speed adjustment without changing memory timing makes
61	@ CPU hang in some cases
62        ldr     r0, =MDREFR
63        ldr     r1, [r0]
64        orr     r1, r1, #MDREFR_K1DB2
65        str     r1, [r0]
66
67	@ delay 90us and set CPU PLL to lowest speed
68	@ fixes resume problem on high speed SA1110
69	mov	r0, #90
70	bl	SYMBOL_NAME(__udelay)
71	ldr	r0, =PPCR
72	mov	r1, #0
73	str	r1, [r0]
74	mov	r0, #90
75	bl	SYMBOL_NAME(__udelay)
76
77	/*
78	 * SA1110 SDRAM controller workaround.  register values:
79	 *
80	 * r0  = &MSC0
81	 * r1  = &MSC1
82	 * r2  = &MSC2
83	 * r3  = MSC0 value
84	 * r4  = MSC1 value
85	 * r5  = MSC2 value
86	 * r6  = &MDREFR
87	 * r7  = first MDREFR value
88	 * r8  = second MDREFR value
89	 * r9  = &MDCNFG
90	 * r10 = MDCNFG value
91	 * r11 = third MDREFR value
92	 * r12 = &PMCR
93	 * r13 = PMCR value (1)
94	 */
95
96	ldr	r0, =MSC0
97	ldr	r1, =MSC1
98	ldr	r2, =MSC2
99
100        ldr     r3, [r0]
101        bic     r3, r3, #FMsk(MSC_RT)
102        bic     r3, r3, #FMsk(MSC_RT)<<16
103
104        ldr     r4, [r1]
105        bic     r4, r4, #FMsk(MSC_RT)
106        bic     r4, r4, #FMsk(MSC_RT)<<16
107
108        ldr     r5, [r2]
109        bic     r5, r5, #FMsk(MSC_RT)
110        bic     r5, r5, #FMsk(MSC_RT)<<16
111
112        ldr     r6, =MDREFR
113
114        ldr     r7, [r6]
115        bic     r7, r7, #0x0000FF00
116        bic     r7, r7, #0x000000F0
117        orr     r8, r7, #MDREFR_SLFRSH
118
119        ldr     r9, =MDCNFG
120        ldr     r10, [r9]
121        bic     r10, r10, #(MDCNFG_DE0+MDCNFG_DE1)
122        bic     r10, r10, #(MDCNFG_DE2+MDCNFG_DE3)
123
124        bic     r11, r8, #MDREFR_SLFRSH
125        bic     r11, r11, #MDREFR_E1PIN
126
127        ldr     r12, =PMCR
128
129        mov     r13, #PMCR_SF
130
131	b	sa1110_sdram_controller_fix
132
133	.align 5
134sa1110_sdram_controller_fix:
135
136	@ Step 1 clear RT field of all MSCx registers
137	str 	r3, [r0]
138	str	r4, [r1]
139	str	r5, [r2]
140
141	@ Step 2 clear DRI field in MDREFR
142	str	r7, [r6]
143
144	@ Step 3 set SLFRSH bit in MDREFR
145	str	r8, [r6]
146
147	@ Step 4 clear DE bis in MDCNFG
148	str	r10, [r9]
149
150	@ Step 5 clear DRAM refresh control register
151	str	r11, [r6]
152
153	@ Wow, now the hardware suspend request pins can be used, that makes them functional for
154	@ about 7 ns out of the	entire time that the CPU is running!
155
156	@ Step 6 set force sleep bit in PMCR
157
158	str	r13, [r12]
159
16020:	b	20b			@ loop waiting for sleep
161
162/*
163 * cpu_sa1100_resume()
164 *
165 * entry point from bootloader into kernel during resume
166 *
167 * Note: Yes, part of the following code is located into the .data section.
168 *       This is to allow sleep_save_sp to be accessed with a relative load
169 *       while we can't rely on any MMU translation.  We could have put
170 *       sleep_save_sp in the .text section as well, but some setups might
171 *       insist on .text to be truely read-only.
172 */
173
174	.data
175	.align 5
176ENTRY(sa1100_cpu_resume)
177	mov	r0, #I_BIT | F_BIT | MODE_SVC	@ set SVC, irqs off
178	msr	cpsr_c, r0
179
180	ldr	r0, sleep_save_sp		@ stack phys addr
181	ldr	r2, =resume_after_mmu		@ its absolute virtual address
182	ldmfd	r0, {r4 - r7, sp}		@ CP regs + virt stack ptr
183
184	mov	r1, #0
185	mcr	p15, 0, r1, c8, c7, 0   	@ flush I+D TLBs
186	mcr	p15, 0, r1, c7, c7, 0		@ flush I&D cache
187	mcr	p15, 0, r1, c9, c0, 0		@ invalidate RB
188	mcr     p15, 0, r1, c9, c0, 5		@ allow user space to use RB
189
190	mcr 	p15, 0, r4, c3, c0, 0		@ domain ID
191	mcr 	p15, 0, r5, c2, c0, 0		@ translation table base addr
192	mcr	p15, 0, r6, c13, c0, 0		@ PID
193	b	resume_turn_on_mmu		@ cache align execution
194
195	.align 5
196resume_turn_on_mmu:
197	mcr 	p15, 0, r7, c1, c0, 0		@ turn on MMU, caches, etc.
198	nop
199	mov	pc, r2				@ jump to virtual addr
200	nop
201	nop
202	nop
203
204sleep_save_sp:
205	.word	0				@ preserve stack phys ptr here
206
207	.text
208resume_after_mmu:
209	mcr     p15, 0, r1, c15, c1, 2		@ enable clock switching
210	ldmfd	sp!, {r4 - r12, pc}		@ return to caller
211
212
213