1 /*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24 #include <linux/firmware.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
27 #include <linux/module.h>
28 #include "drmP.h"
29 #include "radeon.h"
30 #include "radeon_asic.h"
31 #include "radeon_drm.h"
32 #include "sid.h"
33 #include "atom.h"
34 #include "si_blit_shaders.h"
35
36 #define SI_PFP_UCODE_SIZE 2144
37 #define SI_PM4_UCODE_SIZE 2144
38 #define SI_CE_UCODE_SIZE 2144
39 #define SI_RLC_UCODE_SIZE 2048
40 #define SI_MC_UCODE_SIZE 7769
41
42 MODULE_FIRMWARE("radeon/TAHITI_pfp.bin");
43 MODULE_FIRMWARE("radeon/TAHITI_me.bin");
44 MODULE_FIRMWARE("radeon/TAHITI_ce.bin");
45 MODULE_FIRMWARE("radeon/TAHITI_mc.bin");
46 MODULE_FIRMWARE("radeon/TAHITI_rlc.bin");
47 MODULE_FIRMWARE("radeon/PITCAIRN_pfp.bin");
48 MODULE_FIRMWARE("radeon/PITCAIRN_me.bin");
49 MODULE_FIRMWARE("radeon/PITCAIRN_ce.bin");
50 MODULE_FIRMWARE("radeon/PITCAIRN_mc.bin");
51 MODULE_FIRMWARE("radeon/PITCAIRN_rlc.bin");
52 MODULE_FIRMWARE("radeon/VERDE_pfp.bin");
53 MODULE_FIRMWARE("radeon/VERDE_me.bin");
54 MODULE_FIRMWARE("radeon/VERDE_ce.bin");
55 MODULE_FIRMWARE("radeon/VERDE_mc.bin");
56 MODULE_FIRMWARE("radeon/VERDE_rlc.bin");
57
58 extern int r600_ih_ring_alloc(struct radeon_device *rdev);
59 extern void r600_ih_ring_fini(struct radeon_device *rdev);
60 extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
61 extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
62 extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
63 extern u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev);
64
65 /* get temperature in millidegrees */
si_get_temp(struct radeon_device * rdev)66 int si_get_temp(struct radeon_device *rdev)
67 {
68 u32 temp;
69 int actual_temp = 0;
70
71 temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
72 CTF_TEMP_SHIFT;
73
74 if (temp & 0x200)
75 actual_temp = 255;
76 else
77 actual_temp = temp & 0x1ff;
78
79 actual_temp = (actual_temp * 1000);
80
81 return actual_temp;
82 }
83
84 #define TAHITI_IO_MC_REGS_SIZE 36
85
86 static const u32 tahiti_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
87 {0x0000006f, 0x03044000},
88 {0x00000070, 0x0480c018},
89 {0x00000071, 0x00000040},
90 {0x00000072, 0x01000000},
91 {0x00000074, 0x000000ff},
92 {0x00000075, 0x00143400},
93 {0x00000076, 0x08ec0800},
94 {0x00000077, 0x040000cc},
95 {0x00000079, 0x00000000},
96 {0x0000007a, 0x21000409},
97 {0x0000007c, 0x00000000},
98 {0x0000007d, 0xe8000000},
99 {0x0000007e, 0x044408a8},
100 {0x0000007f, 0x00000003},
101 {0x00000080, 0x00000000},
102 {0x00000081, 0x01000000},
103 {0x00000082, 0x02000000},
104 {0x00000083, 0x00000000},
105 {0x00000084, 0xe3f3e4f4},
106 {0x00000085, 0x00052024},
107 {0x00000087, 0x00000000},
108 {0x00000088, 0x66036603},
109 {0x00000089, 0x01000000},
110 {0x0000008b, 0x1c0a0000},
111 {0x0000008c, 0xff010000},
112 {0x0000008e, 0xffffefff},
113 {0x0000008f, 0xfff3efff},
114 {0x00000090, 0xfff3efbf},
115 {0x00000094, 0x00101101},
116 {0x00000095, 0x00000fff},
117 {0x00000096, 0x00116fff},
118 {0x00000097, 0x60010000},
119 {0x00000098, 0x10010000},
120 {0x00000099, 0x00006000},
121 {0x0000009a, 0x00001000},
122 {0x0000009f, 0x00a77400}
123 };
124
125 static const u32 pitcairn_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
126 {0x0000006f, 0x03044000},
127 {0x00000070, 0x0480c018},
128 {0x00000071, 0x00000040},
129 {0x00000072, 0x01000000},
130 {0x00000074, 0x000000ff},
131 {0x00000075, 0x00143400},
132 {0x00000076, 0x08ec0800},
133 {0x00000077, 0x040000cc},
134 {0x00000079, 0x00000000},
135 {0x0000007a, 0x21000409},
136 {0x0000007c, 0x00000000},
137 {0x0000007d, 0xe8000000},
138 {0x0000007e, 0x044408a8},
139 {0x0000007f, 0x00000003},
140 {0x00000080, 0x00000000},
141 {0x00000081, 0x01000000},
142 {0x00000082, 0x02000000},
143 {0x00000083, 0x00000000},
144 {0x00000084, 0xe3f3e4f4},
145 {0x00000085, 0x00052024},
146 {0x00000087, 0x00000000},
147 {0x00000088, 0x66036603},
148 {0x00000089, 0x01000000},
149 {0x0000008b, 0x1c0a0000},
150 {0x0000008c, 0xff010000},
151 {0x0000008e, 0xffffefff},
152 {0x0000008f, 0xfff3efff},
153 {0x00000090, 0xfff3efbf},
154 {0x00000094, 0x00101101},
155 {0x00000095, 0x00000fff},
156 {0x00000096, 0x00116fff},
157 {0x00000097, 0x60010000},
158 {0x00000098, 0x10010000},
159 {0x00000099, 0x00006000},
160 {0x0000009a, 0x00001000},
161 {0x0000009f, 0x00a47400}
162 };
163
164 static const u32 verde_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
165 {0x0000006f, 0x03044000},
166 {0x00000070, 0x0480c018},
167 {0x00000071, 0x00000040},
168 {0x00000072, 0x01000000},
169 {0x00000074, 0x000000ff},
170 {0x00000075, 0x00143400},
171 {0x00000076, 0x08ec0800},
172 {0x00000077, 0x040000cc},
173 {0x00000079, 0x00000000},
174 {0x0000007a, 0x21000409},
175 {0x0000007c, 0x00000000},
176 {0x0000007d, 0xe8000000},
177 {0x0000007e, 0x044408a8},
178 {0x0000007f, 0x00000003},
179 {0x00000080, 0x00000000},
180 {0x00000081, 0x01000000},
181 {0x00000082, 0x02000000},
182 {0x00000083, 0x00000000},
183 {0x00000084, 0xe3f3e4f4},
184 {0x00000085, 0x00052024},
185 {0x00000087, 0x00000000},
186 {0x00000088, 0x66036603},
187 {0x00000089, 0x01000000},
188 {0x0000008b, 0x1c0a0000},
189 {0x0000008c, 0xff010000},
190 {0x0000008e, 0xffffefff},
191 {0x0000008f, 0xfff3efff},
192 {0x00000090, 0xfff3efbf},
193 {0x00000094, 0x00101101},
194 {0x00000095, 0x00000fff},
195 {0x00000096, 0x00116fff},
196 {0x00000097, 0x60010000},
197 {0x00000098, 0x10010000},
198 {0x00000099, 0x00006000},
199 {0x0000009a, 0x00001000},
200 {0x0000009f, 0x00a37400}
201 };
202
203 /* ucode loading */
si_mc_load_microcode(struct radeon_device * rdev)204 static int si_mc_load_microcode(struct radeon_device *rdev)
205 {
206 const __be32 *fw_data;
207 u32 running, blackout = 0;
208 u32 *io_mc_regs;
209 int i, ucode_size, regs_size;
210
211 if (!rdev->mc_fw)
212 return -EINVAL;
213
214 switch (rdev->family) {
215 case CHIP_TAHITI:
216 io_mc_regs = (u32 *)&tahiti_io_mc_regs;
217 ucode_size = SI_MC_UCODE_SIZE;
218 regs_size = TAHITI_IO_MC_REGS_SIZE;
219 break;
220 case CHIP_PITCAIRN:
221 io_mc_regs = (u32 *)&pitcairn_io_mc_regs;
222 ucode_size = SI_MC_UCODE_SIZE;
223 regs_size = TAHITI_IO_MC_REGS_SIZE;
224 break;
225 case CHIP_VERDE:
226 default:
227 io_mc_regs = (u32 *)&verde_io_mc_regs;
228 ucode_size = SI_MC_UCODE_SIZE;
229 regs_size = TAHITI_IO_MC_REGS_SIZE;
230 break;
231 }
232
233 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
234
235 if (running == 0) {
236 if (running) {
237 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
238 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
239 }
240
241 /* reset the engine and set to writable */
242 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
243 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
244
245 /* load mc io regs */
246 for (i = 0; i < regs_size; i++) {
247 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
248 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
249 }
250 /* load the MC ucode */
251 fw_data = (const __be32 *)rdev->mc_fw->data;
252 for (i = 0; i < ucode_size; i++)
253 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
254
255 /* put the engine back into the active state */
256 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
257 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
258 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
259
260 /* wait for training to complete */
261 for (i = 0; i < rdev->usec_timeout; i++) {
262 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0)
263 break;
264 udelay(1);
265 }
266 for (i = 0; i < rdev->usec_timeout; i++) {
267 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1)
268 break;
269 udelay(1);
270 }
271
272 if (running)
273 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
274 }
275
276 return 0;
277 }
278
si_init_microcode(struct radeon_device * rdev)279 static int si_init_microcode(struct radeon_device *rdev)
280 {
281 struct platform_device *pdev;
282 const char *chip_name;
283 const char *rlc_chip_name;
284 size_t pfp_req_size, me_req_size, ce_req_size, rlc_req_size, mc_req_size;
285 char fw_name[30];
286 int err;
287
288 DRM_DEBUG("\n");
289
290 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
291 err = IS_ERR(pdev);
292 if (err) {
293 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
294 return -EINVAL;
295 }
296
297 switch (rdev->family) {
298 case CHIP_TAHITI:
299 chip_name = "TAHITI";
300 rlc_chip_name = "TAHITI";
301 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
302 me_req_size = SI_PM4_UCODE_SIZE * 4;
303 ce_req_size = SI_CE_UCODE_SIZE * 4;
304 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
305 mc_req_size = SI_MC_UCODE_SIZE * 4;
306 break;
307 case CHIP_PITCAIRN:
308 chip_name = "PITCAIRN";
309 rlc_chip_name = "PITCAIRN";
310 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
311 me_req_size = SI_PM4_UCODE_SIZE * 4;
312 ce_req_size = SI_CE_UCODE_SIZE * 4;
313 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
314 mc_req_size = SI_MC_UCODE_SIZE * 4;
315 break;
316 case CHIP_VERDE:
317 chip_name = "VERDE";
318 rlc_chip_name = "VERDE";
319 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
320 me_req_size = SI_PM4_UCODE_SIZE * 4;
321 ce_req_size = SI_CE_UCODE_SIZE * 4;
322 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
323 mc_req_size = SI_MC_UCODE_SIZE * 4;
324 break;
325 default: BUG();
326 }
327
328 DRM_INFO("Loading %s Microcode\n", chip_name);
329
330 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
331 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
332 if (err)
333 goto out;
334 if (rdev->pfp_fw->size != pfp_req_size) {
335 printk(KERN_ERR
336 "si_cp: Bogus length %zu in firmware \"%s\"\n",
337 rdev->pfp_fw->size, fw_name);
338 err = -EINVAL;
339 goto out;
340 }
341
342 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
343 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
344 if (err)
345 goto out;
346 if (rdev->me_fw->size != me_req_size) {
347 printk(KERN_ERR
348 "si_cp: Bogus length %zu in firmware \"%s\"\n",
349 rdev->me_fw->size, fw_name);
350 err = -EINVAL;
351 }
352
353 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
354 err = request_firmware(&rdev->ce_fw, fw_name, &pdev->dev);
355 if (err)
356 goto out;
357 if (rdev->ce_fw->size != ce_req_size) {
358 printk(KERN_ERR
359 "si_cp: Bogus length %zu in firmware \"%s\"\n",
360 rdev->ce_fw->size, fw_name);
361 err = -EINVAL;
362 }
363
364 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
365 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
366 if (err)
367 goto out;
368 if (rdev->rlc_fw->size != rlc_req_size) {
369 printk(KERN_ERR
370 "si_rlc: Bogus length %zu in firmware \"%s\"\n",
371 rdev->rlc_fw->size, fw_name);
372 err = -EINVAL;
373 }
374
375 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
376 err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev);
377 if (err)
378 goto out;
379 if (rdev->mc_fw->size != mc_req_size) {
380 printk(KERN_ERR
381 "si_mc: Bogus length %zu in firmware \"%s\"\n",
382 rdev->mc_fw->size, fw_name);
383 err = -EINVAL;
384 }
385
386 out:
387 platform_device_unregister(pdev);
388
389 if (err) {
390 if (err != -EINVAL)
391 printk(KERN_ERR
392 "si_cp: Failed to load firmware \"%s\"\n",
393 fw_name);
394 release_firmware(rdev->pfp_fw);
395 rdev->pfp_fw = NULL;
396 release_firmware(rdev->me_fw);
397 rdev->me_fw = NULL;
398 release_firmware(rdev->ce_fw);
399 rdev->ce_fw = NULL;
400 release_firmware(rdev->rlc_fw);
401 rdev->rlc_fw = NULL;
402 release_firmware(rdev->mc_fw);
403 rdev->mc_fw = NULL;
404 }
405 return err;
406 }
407
408 /* watermark setup */
dce6_line_buffer_adjust(struct radeon_device * rdev,struct radeon_crtc * radeon_crtc,struct drm_display_mode * mode,struct drm_display_mode * other_mode)409 static u32 dce6_line_buffer_adjust(struct radeon_device *rdev,
410 struct radeon_crtc *radeon_crtc,
411 struct drm_display_mode *mode,
412 struct drm_display_mode *other_mode)
413 {
414 u32 tmp, buffer_alloc, i;
415 u32 pipe_offset = radeon_crtc->crtc_id * 0x20;
416 /*
417 * Line Buffer Setup
418 * There are 3 line buffers, each one shared by 2 display controllers.
419 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
420 * the display controllers. The paritioning is done via one of four
421 * preset allocations specified in bits 21:20:
422 * 0 - half lb
423 * 2 - whole lb, other crtc must be disabled
424 */
425 /* this can get tricky if we have two large displays on a paired group
426 * of crtcs. Ideally for multiple large displays we'd assign them to
427 * non-linked crtcs for maximum line buffer allocation.
428 */
429 if (radeon_crtc->base.enabled && mode) {
430 if (other_mode) {
431 tmp = 0; /* 1/2 */
432 buffer_alloc = 1;
433 } else {
434 tmp = 2; /* whole */
435 buffer_alloc = 2;
436 }
437 } else {
438 tmp = 0;
439 buffer_alloc = 0;
440 }
441
442 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset,
443 DC_LB_MEMORY_CONFIG(tmp));
444
445 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
446 DMIF_BUFFERS_ALLOCATED(buffer_alloc));
447 for (i = 0; i < rdev->usec_timeout; i++) {
448 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
449 DMIF_BUFFERS_ALLOCATED_COMPLETED)
450 break;
451 udelay(1);
452 }
453
454 if (radeon_crtc->base.enabled && mode) {
455 switch (tmp) {
456 case 0:
457 default:
458 return 4096 * 2;
459 case 2:
460 return 8192 * 2;
461 }
462 }
463
464 /* controller not enabled, so no lb used */
465 return 0;
466 }
467
si_get_number_of_dram_channels(struct radeon_device * rdev)468 static u32 si_get_number_of_dram_channels(struct radeon_device *rdev)
469 {
470 u32 tmp = RREG32(MC_SHARED_CHMAP);
471
472 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
473 case 0:
474 default:
475 return 1;
476 case 1:
477 return 2;
478 case 2:
479 return 4;
480 case 3:
481 return 8;
482 case 4:
483 return 3;
484 case 5:
485 return 6;
486 case 6:
487 return 10;
488 case 7:
489 return 12;
490 case 8:
491 return 16;
492 }
493 }
494
495 struct dce6_wm_params {
496 u32 dram_channels; /* number of dram channels */
497 u32 yclk; /* bandwidth per dram data pin in kHz */
498 u32 sclk; /* engine clock in kHz */
499 u32 disp_clk; /* display clock in kHz */
500 u32 src_width; /* viewport width */
501 u32 active_time; /* active display time in ns */
502 u32 blank_time; /* blank time in ns */
503 bool interlaced; /* mode is interlaced */
504 fixed20_12 vsc; /* vertical scale ratio */
505 u32 num_heads; /* number of active crtcs */
506 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
507 u32 lb_size; /* line buffer allocated to pipe */
508 u32 vtaps; /* vertical scaler taps */
509 };
510
dce6_dram_bandwidth(struct dce6_wm_params * wm)511 static u32 dce6_dram_bandwidth(struct dce6_wm_params *wm)
512 {
513 /* Calculate raw DRAM Bandwidth */
514 fixed20_12 dram_efficiency; /* 0.7 */
515 fixed20_12 yclk, dram_channels, bandwidth;
516 fixed20_12 a;
517
518 a.full = dfixed_const(1000);
519 yclk.full = dfixed_const(wm->yclk);
520 yclk.full = dfixed_div(yclk, a);
521 dram_channels.full = dfixed_const(wm->dram_channels * 4);
522 a.full = dfixed_const(10);
523 dram_efficiency.full = dfixed_const(7);
524 dram_efficiency.full = dfixed_div(dram_efficiency, a);
525 bandwidth.full = dfixed_mul(dram_channels, yclk);
526 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
527
528 return dfixed_trunc(bandwidth);
529 }
530
dce6_dram_bandwidth_for_display(struct dce6_wm_params * wm)531 static u32 dce6_dram_bandwidth_for_display(struct dce6_wm_params *wm)
532 {
533 /* Calculate DRAM Bandwidth and the part allocated to display. */
534 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
535 fixed20_12 yclk, dram_channels, bandwidth;
536 fixed20_12 a;
537
538 a.full = dfixed_const(1000);
539 yclk.full = dfixed_const(wm->yclk);
540 yclk.full = dfixed_div(yclk, a);
541 dram_channels.full = dfixed_const(wm->dram_channels * 4);
542 a.full = dfixed_const(10);
543 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
544 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
545 bandwidth.full = dfixed_mul(dram_channels, yclk);
546 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
547
548 return dfixed_trunc(bandwidth);
549 }
550
dce6_data_return_bandwidth(struct dce6_wm_params * wm)551 static u32 dce6_data_return_bandwidth(struct dce6_wm_params *wm)
552 {
553 /* Calculate the display Data return Bandwidth */
554 fixed20_12 return_efficiency; /* 0.8 */
555 fixed20_12 sclk, bandwidth;
556 fixed20_12 a;
557
558 a.full = dfixed_const(1000);
559 sclk.full = dfixed_const(wm->sclk);
560 sclk.full = dfixed_div(sclk, a);
561 a.full = dfixed_const(10);
562 return_efficiency.full = dfixed_const(8);
563 return_efficiency.full = dfixed_div(return_efficiency, a);
564 a.full = dfixed_const(32);
565 bandwidth.full = dfixed_mul(a, sclk);
566 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
567
568 return dfixed_trunc(bandwidth);
569 }
570
dce6_get_dmif_bytes_per_request(struct dce6_wm_params * wm)571 static u32 dce6_get_dmif_bytes_per_request(struct dce6_wm_params *wm)
572 {
573 return 32;
574 }
575
dce6_dmif_request_bandwidth(struct dce6_wm_params * wm)576 static u32 dce6_dmif_request_bandwidth(struct dce6_wm_params *wm)
577 {
578 /* Calculate the DMIF Request Bandwidth */
579 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
580 fixed20_12 disp_clk, sclk, bandwidth;
581 fixed20_12 a, b1, b2;
582 u32 min_bandwidth;
583
584 a.full = dfixed_const(1000);
585 disp_clk.full = dfixed_const(wm->disp_clk);
586 disp_clk.full = dfixed_div(disp_clk, a);
587 a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm) / 2);
588 b1.full = dfixed_mul(a, disp_clk);
589
590 a.full = dfixed_const(1000);
591 sclk.full = dfixed_const(wm->sclk);
592 sclk.full = dfixed_div(sclk, a);
593 a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm));
594 b2.full = dfixed_mul(a, sclk);
595
596 a.full = dfixed_const(10);
597 disp_clk_request_efficiency.full = dfixed_const(8);
598 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
599
600 min_bandwidth = min(dfixed_trunc(b1), dfixed_trunc(b2));
601
602 a.full = dfixed_const(min_bandwidth);
603 bandwidth.full = dfixed_mul(a, disp_clk_request_efficiency);
604
605 return dfixed_trunc(bandwidth);
606 }
607
dce6_available_bandwidth(struct dce6_wm_params * wm)608 static u32 dce6_available_bandwidth(struct dce6_wm_params *wm)
609 {
610 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
611 u32 dram_bandwidth = dce6_dram_bandwidth(wm);
612 u32 data_return_bandwidth = dce6_data_return_bandwidth(wm);
613 u32 dmif_req_bandwidth = dce6_dmif_request_bandwidth(wm);
614
615 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
616 }
617
dce6_average_bandwidth(struct dce6_wm_params * wm)618 static u32 dce6_average_bandwidth(struct dce6_wm_params *wm)
619 {
620 /* Calculate the display mode Average Bandwidth
621 * DisplayMode should contain the source and destination dimensions,
622 * timing, etc.
623 */
624 fixed20_12 bpp;
625 fixed20_12 line_time;
626 fixed20_12 src_width;
627 fixed20_12 bandwidth;
628 fixed20_12 a;
629
630 a.full = dfixed_const(1000);
631 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
632 line_time.full = dfixed_div(line_time, a);
633 bpp.full = dfixed_const(wm->bytes_per_pixel);
634 src_width.full = dfixed_const(wm->src_width);
635 bandwidth.full = dfixed_mul(src_width, bpp);
636 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
637 bandwidth.full = dfixed_div(bandwidth, line_time);
638
639 return dfixed_trunc(bandwidth);
640 }
641
dce6_latency_watermark(struct dce6_wm_params * wm)642 static u32 dce6_latency_watermark(struct dce6_wm_params *wm)
643 {
644 /* First calcualte the latency in ns */
645 u32 mc_latency = 2000; /* 2000 ns. */
646 u32 available_bandwidth = dce6_available_bandwidth(wm);
647 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
648 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
649 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
650 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
651 (wm->num_heads * cursor_line_pair_return_time);
652 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
653 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
654 u32 tmp, dmif_size = 12288;
655 fixed20_12 a, b, c;
656
657 if (wm->num_heads == 0)
658 return 0;
659
660 a.full = dfixed_const(2);
661 b.full = dfixed_const(1);
662 if ((wm->vsc.full > a.full) ||
663 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
664 (wm->vtaps >= 5) ||
665 ((wm->vsc.full >= a.full) && wm->interlaced))
666 max_src_lines_per_dst_line = 4;
667 else
668 max_src_lines_per_dst_line = 2;
669
670 a.full = dfixed_const(available_bandwidth);
671 b.full = dfixed_const(wm->num_heads);
672 a.full = dfixed_div(a, b);
673
674 b.full = dfixed_const(mc_latency + 512);
675 c.full = dfixed_const(wm->disp_clk);
676 b.full = dfixed_div(b, c);
677
678 c.full = dfixed_const(dmif_size);
679 b.full = dfixed_div(c, b);
680
681 tmp = min(dfixed_trunc(a), dfixed_trunc(b));
682
683 b.full = dfixed_const(1000);
684 c.full = dfixed_const(wm->disp_clk);
685 b.full = dfixed_div(c, b);
686 c.full = dfixed_const(wm->bytes_per_pixel);
687 b.full = dfixed_mul(b, c);
688
689 lb_fill_bw = min(tmp, dfixed_trunc(b));
690
691 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
692 b.full = dfixed_const(1000);
693 c.full = dfixed_const(lb_fill_bw);
694 b.full = dfixed_div(c, b);
695 a.full = dfixed_div(a, b);
696 line_fill_time = dfixed_trunc(a);
697
698 if (line_fill_time < wm->active_time)
699 return latency;
700 else
701 return latency + (line_fill_time - wm->active_time);
702
703 }
704
dce6_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params * wm)705 static bool dce6_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm)
706 {
707 if (dce6_average_bandwidth(wm) <=
708 (dce6_dram_bandwidth_for_display(wm) / wm->num_heads))
709 return true;
710 else
711 return false;
712 };
713
dce6_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params * wm)714 static bool dce6_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm)
715 {
716 if (dce6_average_bandwidth(wm) <=
717 (dce6_available_bandwidth(wm) / wm->num_heads))
718 return true;
719 else
720 return false;
721 };
722
dce6_check_latency_hiding(struct dce6_wm_params * wm)723 static bool dce6_check_latency_hiding(struct dce6_wm_params *wm)
724 {
725 u32 lb_partitions = wm->lb_size / wm->src_width;
726 u32 line_time = wm->active_time + wm->blank_time;
727 u32 latency_tolerant_lines;
728 u32 latency_hiding;
729 fixed20_12 a;
730
731 a.full = dfixed_const(1);
732 if (wm->vsc.full > a.full)
733 latency_tolerant_lines = 1;
734 else {
735 if (lb_partitions <= (wm->vtaps + 1))
736 latency_tolerant_lines = 1;
737 else
738 latency_tolerant_lines = 2;
739 }
740
741 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
742
743 if (dce6_latency_watermark(wm) <= latency_hiding)
744 return true;
745 else
746 return false;
747 }
748
dce6_program_watermarks(struct radeon_device * rdev,struct radeon_crtc * radeon_crtc,u32 lb_size,u32 num_heads)749 static void dce6_program_watermarks(struct radeon_device *rdev,
750 struct radeon_crtc *radeon_crtc,
751 u32 lb_size, u32 num_heads)
752 {
753 struct drm_display_mode *mode = &radeon_crtc->base.mode;
754 struct dce6_wm_params wm;
755 u32 pixel_period;
756 u32 line_time = 0;
757 u32 latency_watermark_a = 0, latency_watermark_b = 0;
758 u32 priority_a_mark = 0, priority_b_mark = 0;
759 u32 priority_a_cnt = PRIORITY_OFF;
760 u32 priority_b_cnt = PRIORITY_OFF;
761 u32 tmp, arb_control3;
762 fixed20_12 a, b, c;
763
764 if (radeon_crtc->base.enabled && num_heads && mode) {
765 pixel_period = 1000000 / (u32)mode->clock;
766 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
767 priority_a_cnt = 0;
768 priority_b_cnt = 0;
769
770 wm.yclk = rdev->pm.current_mclk * 10;
771 wm.sclk = rdev->pm.current_sclk * 10;
772 wm.disp_clk = mode->clock;
773 wm.src_width = mode->crtc_hdisplay;
774 wm.active_time = mode->crtc_hdisplay * pixel_period;
775 wm.blank_time = line_time - wm.active_time;
776 wm.interlaced = false;
777 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
778 wm.interlaced = true;
779 wm.vsc = radeon_crtc->vsc;
780 wm.vtaps = 1;
781 if (radeon_crtc->rmx_type != RMX_OFF)
782 wm.vtaps = 2;
783 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
784 wm.lb_size = lb_size;
785 if (rdev->family == CHIP_ARUBA)
786 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
787 else
788 wm.dram_channels = si_get_number_of_dram_channels(rdev);
789 wm.num_heads = num_heads;
790
791 /* set for high clocks */
792 latency_watermark_a = min(dce6_latency_watermark(&wm), (u32)65535);
793 /* set for low clocks */
794 /* wm.yclk = low clk; wm.sclk = low clk */
795 latency_watermark_b = min(dce6_latency_watermark(&wm), (u32)65535);
796
797 /* possibly force display priority to high */
798 /* should really do this at mode validation time... */
799 if (!dce6_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
800 !dce6_average_bandwidth_vs_available_bandwidth(&wm) ||
801 !dce6_check_latency_hiding(&wm) ||
802 (rdev->disp_priority == 2)) {
803 DRM_DEBUG_KMS("force priority to high\n");
804 priority_a_cnt |= PRIORITY_ALWAYS_ON;
805 priority_b_cnt |= PRIORITY_ALWAYS_ON;
806 }
807
808 a.full = dfixed_const(1000);
809 b.full = dfixed_const(mode->clock);
810 b.full = dfixed_div(b, a);
811 c.full = dfixed_const(latency_watermark_a);
812 c.full = dfixed_mul(c, b);
813 c.full = dfixed_mul(c, radeon_crtc->hsc);
814 c.full = dfixed_div(c, a);
815 a.full = dfixed_const(16);
816 c.full = dfixed_div(c, a);
817 priority_a_mark = dfixed_trunc(c);
818 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
819
820 a.full = dfixed_const(1000);
821 b.full = dfixed_const(mode->clock);
822 b.full = dfixed_div(b, a);
823 c.full = dfixed_const(latency_watermark_b);
824 c.full = dfixed_mul(c, b);
825 c.full = dfixed_mul(c, radeon_crtc->hsc);
826 c.full = dfixed_div(c, a);
827 a.full = dfixed_const(16);
828 c.full = dfixed_div(c, a);
829 priority_b_mark = dfixed_trunc(c);
830 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
831 }
832
833 /* select wm A */
834 arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
835 tmp = arb_control3;
836 tmp &= ~LATENCY_WATERMARK_MASK(3);
837 tmp |= LATENCY_WATERMARK_MASK(1);
838 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
839 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
840 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
841 LATENCY_HIGH_WATERMARK(line_time)));
842 /* select wm B */
843 tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
844 tmp &= ~LATENCY_WATERMARK_MASK(3);
845 tmp |= LATENCY_WATERMARK_MASK(2);
846 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
847 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
848 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
849 LATENCY_HIGH_WATERMARK(line_time)));
850 /* restore original selection */
851 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3);
852
853 /* write the priority marks */
854 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
855 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
856
857 }
858
dce6_bandwidth_update(struct radeon_device * rdev)859 void dce6_bandwidth_update(struct radeon_device *rdev)
860 {
861 struct drm_display_mode *mode0 = NULL;
862 struct drm_display_mode *mode1 = NULL;
863 u32 num_heads = 0, lb_size;
864 int i;
865
866 radeon_update_display_priority(rdev);
867
868 for (i = 0; i < rdev->num_crtc; i++) {
869 if (rdev->mode_info.crtcs[i]->base.enabled)
870 num_heads++;
871 }
872 for (i = 0; i < rdev->num_crtc; i += 2) {
873 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
874 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
875 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
876 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
877 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
878 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
879 }
880 }
881
882 /*
883 * Core functions
884 */
si_get_tile_pipe_to_backend_map(struct radeon_device * rdev,u32 num_tile_pipes,u32 num_backends_per_asic,u32 * backend_disable_mask_per_asic,u32 num_shader_engines)885 static u32 si_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
886 u32 num_tile_pipes,
887 u32 num_backends_per_asic,
888 u32 *backend_disable_mask_per_asic,
889 u32 num_shader_engines)
890 {
891 u32 backend_map = 0;
892 u32 enabled_backends_mask = 0;
893 u32 enabled_backends_count = 0;
894 u32 num_backends_per_se;
895 u32 cur_pipe;
896 u32 swizzle_pipe[SI_MAX_PIPES];
897 u32 cur_backend = 0;
898 u32 i;
899 bool force_no_swizzle;
900
901 /* force legal values */
902 if (num_tile_pipes < 1)
903 num_tile_pipes = 1;
904 if (num_tile_pipes > rdev->config.si.max_tile_pipes)
905 num_tile_pipes = rdev->config.si.max_tile_pipes;
906 if (num_shader_engines < 1)
907 num_shader_engines = 1;
908 if (num_shader_engines > rdev->config.si.max_shader_engines)
909 num_shader_engines = rdev->config.si.max_shader_engines;
910 if (num_backends_per_asic < num_shader_engines)
911 num_backends_per_asic = num_shader_engines;
912 if (num_backends_per_asic > (rdev->config.si.max_backends_per_se * num_shader_engines))
913 num_backends_per_asic = rdev->config.si.max_backends_per_se * num_shader_engines;
914
915 /* make sure we have the same number of backends per se */
916 num_backends_per_asic = ALIGN(num_backends_per_asic, num_shader_engines);
917 /* set up the number of backends per se */
918 num_backends_per_se = num_backends_per_asic / num_shader_engines;
919 if (num_backends_per_se > rdev->config.si.max_backends_per_se) {
920 num_backends_per_se = rdev->config.si.max_backends_per_se;
921 num_backends_per_asic = num_backends_per_se * num_shader_engines;
922 }
923
924 /* create enable mask and count for enabled backends */
925 for (i = 0; i < SI_MAX_BACKENDS; ++i) {
926 if (((*backend_disable_mask_per_asic >> i) & 1) == 0) {
927 enabled_backends_mask |= (1 << i);
928 ++enabled_backends_count;
929 }
930 if (enabled_backends_count == num_backends_per_asic)
931 break;
932 }
933
934 /* force the backends mask to match the current number of backends */
935 if (enabled_backends_count != num_backends_per_asic) {
936 u32 this_backend_enabled;
937 u32 shader_engine;
938 u32 backend_per_se;
939
940 enabled_backends_mask = 0;
941 enabled_backends_count = 0;
942 *backend_disable_mask_per_asic = SI_MAX_BACKENDS_MASK;
943 for (i = 0; i < SI_MAX_BACKENDS; ++i) {
944 /* calc the current se */
945 shader_engine = i / rdev->config.si.max_backends_per_se;
946 /* calc the backend per se */
947 backend_per_se = i % rdev->config.si.max_backends_per_se;
948 /* default to not enabled */
949 this_backend_enabled = 0;
950 if ((shader_engine < num_shader_engines) &&
951 (backend_per_se < num_backends_per_se))
952 this_backend_enabled = 1;
953 if (this_backend_enabled) {
954 enabled_backends_mask |= (1 << i);
955 *backend_disable_mask_per_asic &= ~(1 << i);
956 ++enabled_backends_count;
957 }
958 }
959 }
960
961
962 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * SI_MAX_PIPES);
963 switch (rdev->family) {
964 case CHIP_TAHITI:
965 case CHIP_PITCAIRN:
966 case CHIP_VERDE:
967 force_no_swizzle = true;
968 break;
969 default:
970 force_no_swizzle = false;
971 break;
972 }
973 if (force_no_swizzle) {
974 bool last_backend_enabled = false;
975
976 force_no_swizzle = false;
977 for (i = 0; i < SI_MAX_BACKENDS; ++i) {
978 if (((enabled_backends_mask >> i) & 1) == 1) {
979 if (last_backend_enabled)
980 force_no_swizzle = true;
981 last_backend_enabled = true;
982 } else
983 last_backend_enabled = false;
984 }
985 }
986
987 switch (num_tile_pipes) {
988 case 1:
989 case 3:
990 case 5:
991 case 7:
992 DRM_ERROR("odd number of pipes!\n");
993 break;
994 case 2:
995 swizzle_pipe[0] = 0;
996 swizzle_pipe[1] = 1;
997 break;
998 case 4:
999 if (force_no_swizzle) {
1000 swizzle_pipe[0] = 0;
1001 swizzle_pipe[1] = 1;
1002 swizzle_pipe[2] = 2;
1003 swizzle_pipe[3] = 3;
1004 } else {
1005 swizzle_pipe[0] = 0;
1006 swizzle_pipe[1] = 2;
1007 swizzle_pipe[2] = 1;
1008 swizzle_pipe[3] = 3;
1009 }
1010 break;
1011 case 6:
1012 if (force_no_swizzle) {
1013 swizzle_pipe[0] = 0;
1014 swizzle_pipe[1] = 1;
1015 swizzle_pipe[2] = 2;
1016 swizzle_pipe[3] = 3;
1017 swizzle_pipe[4] = 4;
1018 swizzle_pipe[5] = 5;
1019 } else {
1020 swizzle_pipe[0] = 0;
1021 swizzle_pipe[1] = 2;
1022 swizzle_pipe[2] = 4;
1023 swizzle_pipe[3] = 1;
1024 swizzle_pipe[4] = 3;
1025 swizzle_pipe[5] = 5;
1026 }
1027 break;
1028 case 8:
1029 if (force_no_swizzle) {
1030 swizzle_pipe[0] = 0;
1031 swizzle_pipe[1] = 1;
1032 swizzle_pipe[2] = 2;
1033 swizzle_pipe[3] = 3;
1034 swizzle_pipe[4] = 4;
1035 swizzle_pipe[5] = 5;
1036 swizzle_pipe[6] = 6;
1037 swizzle_pipe[7] = 7;
1038 } else {
1039 swizzle_pipe[0] = 0;
1040 swizzle_pipe[1] = 2;
1041 swizzle_pipe[2] = 4;
1042 swizzle_pipe[3] = 6;
1043 swizzle_pipe[4] = 1;
1044 swizzle_pipe[5] = 3;
1045 swizzle_pipe[6] = 5;
1046 swizzle_pipe[7] = 7;
1047 }
1048 break;
1049 }
1050
1051 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1052 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1053 cur_backend = (cur_backend + 1) % SI_MAX_BACKENDS;
1054
1055 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
1056
1057 cur_backend = (cur_backend + 1) % SI_MAX_BACKENDS;
1058 }
1059
1060 return backend_map;
1061 }
1062
si_get_disable_mask_per_asic(struct radeon_device * rdev,u32 disable_mask_per_se,u32 max_disable_mask_per_se,u32 num_shader_engines)1063 static u32 si_get_disable_mask_per_asic(struct radeon_device *rdev,
1064 u32 disable_mask_per_se,
1065 u32 max_disable_mask_per_se,
1066 u32 num_shader_engines)
1067 {
1068 u32 disable_field_width_per_se = r600_count_pipe_bits(disable_mask_per_se);
1069 u32 disable_mask_per_asic = disable_mask_per_se & max_disable_mask_per_se;
1070
1071 if (num_shader_engines == 1)
1072 return disable_mask_per_asic;
1073 else if (num_shader_engines == 2)
1074 return disable_mask_per_asic | (disable_mask_per_asic << disable_field_width_per_se);
1075 else
1076 return 0xffffffff;
1077 }
1078
si_tiling_mode_table_init(struct radeon_device * rdev)1079 static void si_tiling_mode_table_init(struct radeon_device *rdev)
1080 {
1081 const u32 num_tile_mode_states = 32;
1082 u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
1083
1084 switch (rdev->config.si.mem_row_size_in_kb) {
1085 case 1:
1086 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
1087 break;
1088 case 2:
1089 default:
1090 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
1091 break;
1092 case 4:
1093 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
1094 break;
1095 }
1096
1097 if ((rdev->family == CHIP_TAHITI) ||
1098 (rdev->family == CHIP_PITCAIRN)) {
1099 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1100 switch (reg_offset) {
1101 case 0: /* non-AA compressed depth or any compressed stencil */
1102 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1103 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1104 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1105 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1106 NUM_BANKS(ADDR_SURF_16_BANK) |
1107 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1108 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1109 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1110 break;
1111 case 1: /* 2xAA/4xAA compressed depth only */
1112 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1113 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1114 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1115 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1116 NUM_BANKS(ADDR_SURF_16_BANK) |
1117 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1118 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1119 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1120 break;
1121 case 2: /* 8xAA compressed depth only */
1122 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1123 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1124 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1125 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1126 NUM_BANKS(ADDR_SURF_16_BANK) |
1127 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1128 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1129 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1130 break;
1131 case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
1132 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1133 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1134 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1135 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1136 NUM_BANKS(ADDR_SURF_16_BANK) |
1137 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1138 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1139 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1140 break;
1141 case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
1142 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1143 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1144 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1145 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1146 NUM_BANKS(ADDR_SURF_16_BANK) |
1147 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1148 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1149 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1150 break;
1151 case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
1152 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1153 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1154 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1155 TILE_SPLIT(split_equal_to_row_size) |
1156 NUM_BANKS(ADDR_SURF_16_BANK) |
1157 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1158 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1159 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1160 break;
1161 case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
1162 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1163 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1164 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1165 TILE_SPLIT(split_equal_to_row_size) |
1166 NUM_BANKS(ADDR_SURF_16_BANK) |
1167 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1168 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1169 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1170 break;
1171 case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
1172 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1173 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1174 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1175 TILE_SPLIT(split_equal_to_row_size) |
1176 NUM_BANKS(ADDR_SURF_16_BANK) |
1177 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1178 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1179 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1180 break;
1181 case 8: /* 1D and 1D Array Surfaces */
1182 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1183 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1184 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1185 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1186 NUM_BANKS(ADDR_SURF_16_BANK) |
1187 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1188 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1189 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1190 break;
1191 case 9: /* Displayable maps. */
1192 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1193 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1194 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1195 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1196 NUM_BANKS(ADDR_SURF_16_BANK) |
1197 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1198 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1199 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1200 break;
1201 case 10: /* Display 8bpp. */
1202 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1203 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1204 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1205 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1206 NUM_BANKS(ADDR_SURF_16_BANK) |
1207 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1208 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1209 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1210 break;
1211 case 11: /* Display 16bpp. */
1212 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1213 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1214 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1215 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1216 NUM_BANKS(ADDR_SURF_16_BANK) |
1217 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1218 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1219 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1220 break;
1221 case 12: /* Display 32bpp. */
1222 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1223 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1224 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1225 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1226 NUM_BANKS(ADDR_SURF_16_BANK) |
1227 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1228 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1229 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1230 break;
1231 case 13: /* Thin. */
1232 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1233 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1234 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1235 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1236 NUM_BANKS(ADDR_SURF_16_BANK) |
1237 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1238 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1239 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1240 break;
1241 case 14: /* Thin 8 bpp. */
1242 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1243 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1244 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1245 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1246 NUM_BANKS(ADDR_SURF_16_BANK) |
1247 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1248 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1249 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1250 break;
1251 case 15: /* Thin 16 bpp. */
1252 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1253 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1254 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1255 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1256 NUM_BANKS(ADDR_SURF_16_BANK) |
1257 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1258 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1259 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1260 break;
1261 case 16: /* Thin 32 bpp. */
1262 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1263 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1264 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1265 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1266 NUM_BANKS(ADDR_SURF_16_BANK) |
1267 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1268 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1269 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1270 break;
1271 case 17: /* Thin 64 bpp. */
1272 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1273 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1274 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1275 TILE_SPLIT(split_equal_to_row_size) |
1276 NUM_BANKS(ADDR_SURF_16_BANK) |
1277 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1278 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1279 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1280 break;
1281 case 21: /* 8 bpp PRT. */
1282 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1283 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1284 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1285 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1286 NUM_BANKS(ADDR_SURF_16_BANK) |
1287 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1288 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1289 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1290 break;
1291 case 22: /* 16 bpp PRT */
1292 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1293 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1294 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1295 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1296 NUM_BANKS(ADDR_SURF_16_BANK) |
1297 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1298 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1299 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1300 break;
1301 case 23: /* 32 bpp PRT */
1302 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1303 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1304 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1305 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1306 NUM_BANKS(ADDR_SURF_16_BANK) |
1307 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1308 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1309 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1310 break;
1311 case 24: /* 64 bpp PRT */
1312 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1313 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1314 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1315 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1316 NUM_BANKS(ADDR_SURF_16_BANK) |
1317 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1318 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1319 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1320 break;
1321 case 25: /* 128 bpp PRT */
1322 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1323 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1324 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1325 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1326 NUM_BANKS(ADDR_SURF_8_BANK) |
1327 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1328 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1329 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1330 break;
1331 default:
1332 gb_tile_moden = 0;
1333 break;
1334 }
1335 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
1336 }
1337 } else if (rdev->family == CHIP_VERDE) {
1338 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1339 switch (reg_offset) {
1340 case 0: /* non-AA compressed depth or any compressed stencil */
1341 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1342 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1343 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1344 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1345 NUM_BANKS(ADDR_SURF_16_BANK) |
1346 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1347 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1348 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1349 break;
1350 case 1: /* 2xAA/4xAA compressed depth only */
1351 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1352 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1353 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1354 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1355 NUM_BANKS(ADDR_SURF_16_BANK) |
1356 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1357 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1358 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1359 break;
1360 case 2: /* 8xAA compressed depth only */
1361 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1362 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1363 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1364 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1365 NUM_BANKS(ADDR_SURF_16_BANK) |
1366 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1367 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1368 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1369 break;
1370 case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
1371 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1372 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1373 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1374 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1375 NUM_BANKS(ADDR_SURF_16_BANK) |
1376 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1377 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1378 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1379 break;
1380 case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
1381 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1382 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1383 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1384 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1385 NUM_BANKS(ADDR_SURF_16_BANK) |
1386 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1387 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1388 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1389 break;
1390 case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
1391 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1392 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1393 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1394 TILE_SPLIT(split_equal_to_row_size) |
1395 NUM_BANKS(ADDR_SURF_16_BANK) |
1396 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1397 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1398 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1399 break;
1400 case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
1401 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1402 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1403 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1404 TILE_SPLIT(split_equal_to_row_size) |
1405 NUM_BANKS(ADDR_SURF_16_BANK) |
1406 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1407 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1408 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1409 break;
1410 case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
1411 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1412 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1413 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1414 TILE_SPLIT(split_equal_to_row_size) |
1415 NUM_BANKS(ADDR_SURF_16_BANK) |
1416 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1417 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1418 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1419 break;
1420 case 8: /* 1D and 1D Array Surfaces */
1421 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1422 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1423 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1424 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1425 NUM_BANKS(ADDR_SURF_16_BANK) |
1426 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1427 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1428 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1429 break;
1430 case 9: /* Displayable maps. */
1431 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1432 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1433 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1434 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1435 NUM_BANKS(ADDR_SURF_16_BANK) |
1436 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1437 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1438 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1439 break;
1440 case 10: /* Display 8bpp. */
1441 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1442 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1443 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1444 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1445 NUM_BANKS(ADDR_SURF_16_BANK) |
1446 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1447 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1448 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1449 break;
1450 case 11: /* Display 16bpp. */
1451 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1452 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1453 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1454 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1455 NUM_BANKS(ADDR_SURF_16_BANK) |
1456 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1457 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1458 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1459 break;
1460 case 12: /* Display 32bpp. */
1461 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1462 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1463 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1464 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1465 NUM_BANKS(ADDR_SURF_16_BANK) |
1466 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1467 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1468 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1469 break;
1470 case 13: /* Thin. */
1471 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1472 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1473 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1474 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1475 NUM_BANKS(ADDR_SURF_16_BANK) |
1476 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1477 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1478 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1479 break;
1480 case 14: /* Thin 8 bpp. */
1481 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1482 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1483 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1484 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1485 NUM_BANKS(ADDR_SURF_16_BANK) |
1486 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1487 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1488 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1489 break;
1490 case 15: /* Thin 16 bpp. */
1491 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1492 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1493 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1494 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1495 NUM_BANKS(ADDR_SURF_16_BANK) |
1496 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1497 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1498 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1499 break;
1500 case 16: /* Thin 32 bpp. */
1501 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1502 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1503 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1504 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1505 NUM_BANKS(ADDR_SURF_16_BANK) |
1506 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1507 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1508 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1509 break;
1510 case 17: /* Thin 64 bpp. */
1511 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1512 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1513 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1514 TILE_SPLIT(split_equal_to_row_size) |
1515 NUM_BANKS(ADDR_SURF_16_BANK) |
1516 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1517 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1518 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1519 break;
1520 case 21: /* 8 bpp PRT. */
1521 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1522 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1523 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1524 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1525 NUM_BANKS(ADDR_SURF_16_BANK) |
1526 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1527 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1528 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1529 break;
1530 case 22: /* 16 bpp PRT */
1531 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1532 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1533 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1534 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1535 NUM_BANKS(ADDR_SURF_16_BANK) |
1536 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1537 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1538 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1539 break;
1540 case 23: /* 32 bpp PRT */
1541 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1542 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1543 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1544 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1545 NUM_BANKS(ADDR_SURF_16_BANK) |
1546 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1547 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1548 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1549 break;
1550 case 24: /* 64 bpp PRT */
1551 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1552 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1553 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1554 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1555 NUM_BANKS(ADDR_SURF_16_BANK) |
1556 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1557 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1558 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1559 break;
1560 case 25: /* 128 bpp PRT */
1561 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1562 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1563 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1564 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1565 NUM_BANKS(ADDR_SURF_8_BANK) |
1566 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1567 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1568 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1569 break;
1570 default:
1571 gb_tile_moden = 0;
1572 break;
1573 }
1574 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
1575 }
1576 } else
1577 DRM_ERROR("unknown asic: 0x%x\n", rdev->family);
1578 }
1579
si_gpu_init(struct radeon_device * rdev)1580 static void si_gpu_init(struct radeon_device *rdev)
1581 {
1582 u32 cc_rb_backend_disable = 0;
1583 u32 cc_gc_shader_array_config;
1584 u32 gb_addr_config = 0;
1585 u32 mc_shared_chmap, mc_arb_ramcfg;
1586 u32 gb_backend_map;
1587 u32 cgts_tcc_disable;
1588 u32 sx_debug_1;
1589 u32 gc_user_shader_array_config;
1590 u32 gc_user_rb_backend_disable;
1591 u32 cgts_user_tcc_disable;
1592 u32 hdp_host_path_cntl;
1593 u32 tmp;
1594 int i, j;
1595
1596 switch (rdev->family) {
1597 case CHIP_TAHITI:
1598 rdev->config.si.max_shader_engines = 2;
1599 rdev->config.si.max_pipes_per_simd = 4;
1600 rdev->config.si.max_tile_pipes = 12;
1601 rdev->config.si.max_simds_per_se = 8;
1602 rdev->config.si.max_backends_per_se = 4;
1603 rdev->config.si.max_texture_channel_caches = 12;
1604 rdev->config.si.max_gprs = 256;
1605 rdev->config.si.max_gs_threads = 32;
1606 rdev->config.si.max_hw_contexts = 8;
1607
1608 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
1609 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
1610 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1611 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1612 break;
1613 case CHIP_PITCAIRN:
1614 rdev->config.si.max_shader_engines = 2;
1615 rdev->config.si.max_pipes_per_simd = 4;
1616 rdev->config.si.max_tile_pipes = 8;
1617 rdev->config.si.max_simds_per_se = 5;
1618 rdev->config.si.max_backends_per_se = 4;
1619 rdev->config.si.max_texture_channel_caches = 8;
1620 rdev->config.si.max_gprs = 256;
1621 rdev->config.si.max_gs_threads = 32;
1622 rdev->config.si.max_hw_contexts = 8;
1623
1624 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
1625 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
1626 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1627 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1628 break;
1629 case CHIP_VERDE:
1630 default:
1631 rdev->config.si.max_shader_engines = 1;
1632 rdev->config.si.max_pipes_per_simd = 4;
1633 rdev->config.si.max_tile_pipes = 4;
1634 rdev->config.si.max_simds_per_se = 2;
1635 rdev->config.si.max_backends_per_se = 4;
1636 rdev->config.si.max_texture_channel_caches = 4;
1637 rdev->config.si.max_gprs = 256;
1638 rdev->config.si.max_gs_threads = 32;
1639 rdev->config.si.max_hw_contexts = 8;
1640
1641 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
1642 rdev->config.si.sc_prim_fifo_size_backend = 0x40;
1643 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1644 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1645 break;
1646 }
1647
1648 /* Initialize HDP */
1649 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1650 WREG32((0x2c14 + j), 0x00000000);
1651 WREG32((0x2c18 + j), 0x00000000);
1652 WREG32((0x2c1c + j), 0x00000000);
1653 WREG32((0x2c20 + j), 0x00000000);
1654 WREG32((0x2c24 + j), 0x00000000);
1655 }
1656
1657 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1658
1659 evergreen_fix_pci_max_read_req_size(rdev);
1660
1661 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
1662
1663 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1664 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1665
1666 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE);
1667 cc_gc_shader_array_config = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
1668 cgts_tcc_disable = 0xffff0000;
1669 for (i = 0; i < rdev->config.si.max_texture_channel_caches; i++)
1670 cgts_tcc_disable &= ~(1 << (16 + i));
1671 gc_user_rb_backend_disable = RREG32(GC_USER_RB_BACKEND_DISABLE);
1672 gc_user_shader_array_config = RREG32(GC_USER_SHADER_ARRAY_CONFIG);
1673 cgts_user_tcc_disable = RREG32(CGTS_USER_TCC_DISABLE);
1674
1675 rdev->config.si.num_shader_engines = rdev->config.si.max_shader_engines;
1676 rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes;
1677 tmp = ((~gc_user_rb_backend_disable) & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;
1678 rdev->config.si.num_backends_per_se = r600_count_pipe_bits(tmp);
1679 tmp = (gc_user_rb_backend_disable & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;
1680 rdev->config.si.backend_disable_mask_per_asic =
1681 si_get_disable_mask_per_asic(rdev, tmp, SI_MAX_BACKENDS_PER_SE_MASK,
1682 rdev->config.si.num_shader_engines);
1683 rdev->config.si.backend_map =
1684 si_get_tile_pipe_to_backend_map(rdev, rdev->config.si.num_tile_pipes,
1685 rdev->config.si.num_backends_per_se *
1686 rdev->config.si.num_shader_engines,
1687 &rdev->config.si.backend_disable_mask_per_asic,
1688 rdev->config.si.num_shader_engines);
1689 tmp = ((~cgts_user_tcc_disable) & TCC_DISABLE_MASK) >> TCC_DISABLE_SHIFT;
1690 rdev->config.si.num_texture_channel_caches = r600_count_pipe_bits(tmp);
1691 rdev->config.si.mem_max_burst_length_bytes = 256;
1692 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
1693 rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1694 if (rdev->config.si.mem_row_size_in_kb > 4)
1695 rdev->config.si.mem_row_size_in_kb = 4;
1696 /* XXX use MC settings? */
1697 rdev->config.si.shader_engine_tile_size = 32;
1698 rdev->config.si.num_gpus = 1;
1699 rdev->config.si.multi_gpu_tile_size = 64;
1700
1701 gb_addr_config = 0;
1702 switch (rdev->config.si.num_tile_pipes) {
1703 case 1:
1704 gb_addr_config |= NUM_PIPES(0);
1705 break;
1706 case 2:
1707 gb_addr_config |= NUM_PIPES(1);
1708 break;
1709 case 4:
1710 gb_addr_config |= NUM_PIPES(2);
1711 break;
1712 case 8:
1713 default:
1714 gb_addr_config |= NUM_PIPES(3);
1715 break;
1716 }
1717
1718 tmp = (rdev->config.si.mem_max_burst_length_bytes / 256) - 1;
1719 gb_addr_config |= PIPE_INTERLEAVE_SIZE(tmp);
1720 gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.si.num_shader_engines - 1);
1721 tmp = (rdev->config.si.shader_engine_tile_size / 16) - 1;
1722 gb_addr_config |= SHADER_ENGINE_TILE_SIZE(tmp);
1723 switch (rdev->config.si.num_gpus) {
1724 case 1:
1725 default:
1726 gb_addr_config |= NUM_GPUS(0);
1727 break;
1728 case 2:
1729 gb_addr_config |= NUM_GPUS(1);
1730 break;
1731 case 4:
1732 gb_addr_config |= NUM_GPUS(2);
1733 break;
1734 }
1735 switch (rdev->config.si.multi_gpu_tile_size) {
1736 case 16:
1737 gb_addr_config |= MULTI_GPU_TILE_SIZE(0);
1738 break;
1739 case 32:
1740 default:
1741 gb_addr_config |= MULTI_GPU_TILE_SIZE(1);
1742 break;
1743 case 64:
1744 gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
1745 break;
1746 case 128:
1747 gb_addr_config |= MULTI_GPU_TILE_SIZE(3);
1748 break;
1749 }
1750 switch (rdev->config.si.mem_row_size_in_kb) {
1751 case 1:
1752 default:
1753 gb_addr_config |= ROW_SIZE(0);
1754 break;
1755 case 2:
1756 gb_addr_config |= ROW_SIZE(1);
1757 break;
1758 case 4:
1759 gb_addr_config |= ROW_SIZE(2);
1760 break;
1761 }
1762
1763 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
1764 rdev->config.si.num_tile_pipes = (1 << tmp);
1765 tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
1766 rdev->config.si.mem_max_burst_length_bytes = (tmp + 1) * 256;
1767 tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
1768 rdev->config.si.num_shader_engines = tmp + 1;
1769 tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
1770 rdev->config.si.num_gpus = tmp + 1;
1771 tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
1772 rdev->config.si.multi_gpu_tile_size = 1 << tmp;
1773 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
1774 rdev->config.si.mem_row_size_in_kb = 1 << tmp;
1775
1776 gb_backend_map =
1777 si_get_tile_pipe_to_backend_map(rdev, rdev->config.si.num_tile_pipes,
1778 rdev->config.si.num_backends_per_se *
1779 rdev->config.si.num_shader_engines,
1780 &rdev->config.si.backend_disable_mask_per_asic,
1781 rdev->config.si.num_shader_engines);
1782
1783 /* setup tiling info dword. gb_addr_config is not adequate since it does
1784 * not have bank info, so create a custom tiling dword.
1785 * bits 3:0 num_pipes
1786 * bits 7:4 num_banks
1787 * bits 11:8 group_size
1788 * bits 15:12 row_size
1789 */
1790 rdev->config.si.tile_config = 0;
1791 switch (rdev->config.si.num_tile_pipes) {
1792 case 1:
1793 rdev->config.si.tile_config |= (0 << 0);
1794 break;
1795 case 2:
1796 rdev->config.si.tile_config |= (1 << 0);
1797 break;
1798 case 4:
1799 rdev->config.si.tile_config |= (2 << 0);
1800 break;
1801 case 8:
1802 default:
1803 /* XXX what about 12? */
1804 rdev->config.si.tile_config |= (3 << 0);
1805 break;
1806 }
1807 rdev->config.si.tile_config |=
1808 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
1809 rdev->config.si.tile_config |=
1810 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
1811 rdev->config.si.tile_config |=
1812 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
1813
1814 rdev->config.si.backend_map = gb_backend_map;
1815 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1816 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1817 WREG32(DMIF_ADDR_CALC, gb_addr_config);
1818 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1819
1820 /* primary versions */
1821 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1822 WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1823 WREG32(CC_GC_SHADER_ARRAY_CONFIG, cc_gc_shader_array_config);
1824
1825 WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
1826
1827 /* user versions */
1828 WREG32(GC_USER_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1829 WREG32(GC_USER_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1830 WREG32(GC_USER_SHADER_ARRAY_CONFIG, cc_gc_shader_array_config);
1831
1832 WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);
1833
1834 si_tiling_mode_table_init(rdev);
1835
1836 /* set HW defaults for 3D engine */
1837 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1838 ROQ_IB2_START(0x2b)));
1839 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
1840
1841 sx_debug_1 = RREG32(SX_DEBUG_1);
1842 WREG32(SX_DEBUG_1, sx_debug_1);
1843
1844 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1845
1846 WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_frontend) |
1847 SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_backend) |
1848 SC_HIZ_TILE_FIFO_SIZE(rdev->config.si.sc_hiz_tile_fifo_size) |
1849 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.si.sc_earlyz_tile_fifo_size)));
1850
1851 WREG32(VGT_NUM_INSTANCES, 1);
1852
1853 WREG32(CP_PERFMON_CNTL, 0);
1854
1855 WREG32(SQ_CONFIG, 0);
1856
1857 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1858 FORCE_EOV_MAX_REZ_CNT(255)));
1859
1860 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
1861 AUTO_INVLD_EN(ES_AND_GS_AUTO));
1862
1863 WREG32(VGT_GS_VERTEX_REUSE, 16);
1864 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1865
1866 WREG32(CB_PERFCOUNTER0_SELECT0, 0);
1867 WREG32(CB_PERFCOUNTER0_SELECT1, 0);
1868 WREG32(CB_PERFCOUNTER1_SELECT0, 0);
1869 WREG32(CB_PERFCOUNTER1_SELECT1, 0);
1870 WREG32(CB_PERFCOUNTER2_SELECT0, 0);
1871 WREG32(CB_PERFCOUNTER2_SELECT1, 0);
1872 WREG32(CB_PERFCOUNTER3_SELECT0, 0);
1873 WREG32(CB_PERFCOUNTER3_SELECT1, 0);
1874
1875 tmp = RREG32(HDP_MISC_CNTL);
1876 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
1877 WREG32(HDP_MISC_CNTL, tmp);
1878
1879 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1880 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1881
1882 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1883
1884 udelay(50);
1885 }
1886
1887 /*
1888 * GPU scratch registers helpers function.
1889 */
si_scratch_init(struct radeon_device * rdev)1890 static void si_scratch_init(struct radeon_device *rdev)
1891 {
1892 int i;
1893
1894 rdev->scratch.num_reg = 7;
1895 rdev->scratch.reg_base = SCRATCH_REG0;
1896 for (i = 0; i < rdev->scratch.num_reg; i++) {
1897 rdev->scratch.free[i] = true;
1898 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
1899 }
1900 }
1901
si_fence_ring_emit(struct radeon_device * rdev,struct radeon_fence * fence)1902 void si_fence_ring_emit(struct radeon_device *rdev,
1903 struct radeon_fence *fence)
1904 {
1905 struct radeon_ring *ring = &rdev->ring[fence->ring];
1906 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
1907
1908 /* flush read cache over gart */
1909 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1910 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
1911 radeon_ring_write(ring, 0);
1912 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1913 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1914 PACKET3_TC_ACTION_ENA |
1915 PACKET3_SH_KCACHE_ACTION_ENA |
1916 PACKET3_SH_ICACHE_ACTION_ENA);
1917 radeon_ring_write(ring, 0xFFFFFFFF);
1918 radeon_ring_write(ring, 0);
1919 radeon_ring_write(ring, 10); /* poll interval */
1920 /* EVENT_WRITE_EOP - flush caches, send int */
1921 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1922 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
1923 radeon_ring_write(ring, addr & 0xffffffff);
1924 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
1925 radeon_ring_write(ring, fence->seq);
1926 radeon_ring_write(ring, 0);
1927 }
1928
1929 /*
1930 * IB stuff
1931 */
si_ring_ib_execute(struct radeon_device * rdev,struct radeon_ib * ib)1932 void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1933 {
1934 struct radeon_ring *ring = &rdev->ring[ib->fence->ring];
1935 u32 header;
1936
1937 if (ib->is_const_ib)
1938 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
1939 else
1940 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
1941
1942 radeon_ring_write(ring, header);
1943 radeon_ring_write(ring,
1944 #ifdef __BIG_ENDIAN
1945 (2 << 0) |
1946 #endif
1947 (ib->gpu_addr & 0xFFFFFFFC));
1948 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
1949 radeon_ring_write(ring, ib->length_dw | (ib->vm_id << 24));
1950
1951 /* flush read cache over gart for this vmid */
1952 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1953 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
1954 radeon_ring_write(ring, ib->vm_id);
1955 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1956 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1957 PACKET3_TC_ACTION_ENA |
1958 PACKET3_SH_KCACHE_ACTION_ENA |
1959 PACKET3_SH_ICACHE_ACTION_ENA);
1960 radeon_ring_write(ring, 0xFFFFFFFF);
1961 radeon_ring_write(ring, 0);
1962 radeon_ring_write(ring, 10); /* poll interval */
1963 }
1964
1965 /*
1966 * CP.
1967 */
si_cp_enable(struct radeon_device * rdev,bool enable)1968 static void si_cp_enable(struct radeon_device *rdev, bool enable)
1969 {
1970 if (enable)
1971 WREG32(CP_ME_CNTL, 0);
1972 else {
1973 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1974 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
1975 WREG32(SCRATCH_UMSK, 0);
1976 }
1977 udelay(50);
1978 }
1979
si_cp_load_microcode(struct radeon_device * rdev)1980 static int si_cp_load_microcode(struct radeon_device *rdev)
1981 {
1982 const __be32 *fw_data;
1983 int i;
1984
1985 if (!rdev->me_fw || !rdev->pfp_fw)
1986 return -EINVAL;
1987
1988 si_cp_enable(rdev, false);
1989
1990 /* PFP */
1991 fw_data = (const __be32 *)rdev->pfp_fw->data;
1992 WREG32(CP_PFP_UCODE_ADDR, 0);
1993 for (i = 0; i < SI_PFP_UCODE_SIZE; i++)
1994 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1995 WREG32(CP_PFP_UCODE_ADDR, 0);
1996
1997 /* CE */
1998 fw_data = (const __be32 *)rdev->ce_fw->data;
1999 WREG32(CP_CE_UCODE_ADDR, 0);
2000 for (i = 0; i < SI_CE_UCODE_SIZE; i++)
2001 WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++));
2002 WREG32(CP_CE_UCODE_ADDR, 0);
2003
2004 /* ME */
2005 fw_data = (const __be32 *)rdev->me_fw->data;
2006 WREG32(CP_ME_RAM_WADDR, 0);
2007 for (i = 0; i < SI_PM4_UCODE_SIZE; i++)
2008 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
2009 WREG32(CP_ME_RAM_WADDR, 0);
2010
2011 WREG32(CP_PFP_UCODE_ADDR, 0);
2012 WREG32(CP_CE_UCODE_ADDR, 0);
2013 WREG32(CP_ME_RAM_WADDR, 0);
2014 WREG32(CP_ME_RAM_RADDR, 0);
2015 return 0;
2016 }
2017
si_cp_start(struct radeon_device * rdev)2018 static int si_cp_start(struct radeon_device *rdev)
2019 {
2020 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2021 int r, i;
2022
2023 r = radeon_ring_lock(rdev, ring, 7 + 4);
2024 if (r) {
2025 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2026 return r;
2027 }
2028 /* init the CP */
2029 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2030 radeon_ring_write(ring, 0x1);
2031 radeon_ring_write(ring, 0x0);
2032 radeon_ring_write(ring, rdev->config.si.max_hw_contexts - 1);
2033 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2034 radeon_ring_write(ring, 0);
2035 radeon_ring_write(ring, 0);
2036
2037 /* init the CE partitions */
2038 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2039 radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2040 radeon_ring_write(ring, 0xc000);
2041 radeon_ring_write(ring, 0xe000);
2042 radeon_ring_unlock_commit(rdev, ring);
2043
2044 si_cp_enable(rdev, true);
2045
2046 r = radeon_ring_lock(rdev, ring, si_default_size + 10);
2047 if (r) {
2048 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2049 return r;
2050 }
2051
2052 /* setup clear context state */
2053 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2054 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2055
2056 for (i = 0; i < si_default_size; i++)
2057 radeon_ring_write(ring, si_default_state[i]);
2058
2059 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2060 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2061
2062 /* set clear context state */
2063 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2064 radeon_ring_write(ring, 0);
2065
2066 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2067 radeon_ring_write(ring, 0x00000316);
2068 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
2069 radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
2070
2071 radeon_ring_unlock_commit(rdev, ring);
2072
2073 for (i = RADEON_RING_TYPE_GFX_INDEX; i <= CAYMAN_RING_TYPE_CP2_INDEX; ++i) {
2074 ring = &rdev->ring[i];
2075 r = radeon_ring_lock(rdev, ring, 2);
2076
2077 /* clear the compute context state */
2078 radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0));
2079 radeon_ring_write(ring, 0);
2080
2081 radeon_ring_unlock_commit(rdev, ring);
2082 }
2083
2084 return 0;
2085 }
2086
si_cp_fini(struct radeon_device * rdev)2087 static void si_cp_fini(struct radeon_device *rdev)
2088 {
2089 si_cp_enable(rdev, false);
2090 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
2091 radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]);
2092 radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]);
2093 }
2094
si_cp_resume(struct radeon_device * rdev)2095 static int si_cp_resume(struct radeon_device *rdev)
2096 {
2097 struct radeon_ring *ring;
2098 u32 tmp;
2099 u32 rb_bufsz;
2100 int r;
2101
2102 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
2103 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
2104 SOFT_RESET_PA |
2105 SOFT_RESET_VGT |
2106 SOFT_RESET_SPI |
2107 SOFT_RESET_SX));
2108 RREG32(GRBM_SOFT_RESET);
2109 mdelay(15);
2110 WREG32(GRBM_SOFT_RESET, 0);
2111 RREG32(GRBM_SOFT_RESET);
2112
2113 WREG32(CP_SEM_WAIT_TIMER, 0x0);
2114 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2115
2116 /* Set the write pointer delay */
2117 WREG32(CP_RB_WPTR_DELAY, 0);
2118
2119 WREG32(CP_DEBUG, 0);
2120 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2121
2122 /* ring 0 - compute and gfx */
2123 /* Set ring buffer size */
2124 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2125 rb_bufsz = drm_order(ring->ring_size / 8);
2126 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2127 #ifdef __BIG_ENDIAN
2128 tmp |= BUF_SWAP_32BIT;
2129 #endif
2130 WREG32(CP_RB0_CNTL, tmp);
2131
2132 /* Initialize the ring buffer's read and write pointers */
2133 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
2134 ring->wptr = 0;
2135 WREG32(CP_RB0_WPTR, ring->wptr);
2136
2137 /* set the wb address wether it's enabled or not */
2138 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
2139 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2140
2141 if (rdev->wb.enabled)
2142 WREG32(SCRATCH_UMSK, 0xff);
2143 else {
2144 tmp |= RB_NO_UPDATE;
2145 WREG32(SCRATCH_UMSK, 0);
2146 }
2147
2148 mdelay(1);
2149 WREG32(CP_RB0_CNTL, tmp);
2150
2151 WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);
2152
2153 ring->rptr = RREG32(CP_RB0_RPTR);
2154
2155 /* ring1 - compute only */
2156 /* Set ring buffer size */
2157 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
2158 rb_bufsz = drm_order(ring->ring_size / 8);
2159 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2160 #ifdef __BIG_ENDIAN
2161 tmp |= BUF_SWAP_32BIT;
2162 #endif
2163 WREG32(CP_RB1_CNTL, tmp);
2164
2165 /* Initialize the ring buffer's read and write pointers */
2166 WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
2167 ring->wptr = 0;
2168 WREG32(CP_RB1_WPTR, ring->wptr);
2169
2170 /* set the wb address wether it's enabled or not */
2171 WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);
2172 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);
2173
2174 mdelay(1);
2175 WREG32(CP_RB1_CNTL, tmp);
2176
2177 WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
2178
2179 ring->rptr = RREG32(CP_RB1_RPTR);
2180
2181 /* ring2 - compute only */
2182 /* Set ring buffer size */
2183 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
2184 rb_bufsz = drm_order(ring->ring_size / 8);
2185 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2186 #ifdef __BIG_ENDIAN
2187 tmp |= BUF_SWAP_32BIT;
2188 #endif
2189 WREG32(CP_RB2_CNTL, tmp);
2190
2191 /* Initialize the ring buffer's read and write pointers */
2192 WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
2193 ring->wptr = 0;
2194 WREG32(CP_RB2_WPTR, ring->wptr);
2195
2196 /* set the wb address wether it's enabled or not */
2197 WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);
2198 WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);
2199
2200 mdelay(1);
2201 WREG32(CP_RB2_CNTL, tmp);
2202
2203 WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
2204
2205 ring->rptr = RREG32(CP_RB2_RPTR);
2206
2207 /* start the rings */
2208 si_cp_start(rdev);
2209 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
2210 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = true;
2211 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = true;
2212 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
2213 if (r) {
2214 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
2215 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
2216 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
2217 return r;
2218 }
2219 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP1_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]);
2220 if (r) {
2221 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
2222 }
2223 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP2_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]);
2224 if (r) {
2225 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
2226 }
2227
2228 return 0;
2229 }
2230
si_gpu_is_lockup(struct radeon_device * rdev,struct radeon_ring * ring)2231 bool si_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2232 {
2233 u32 srbm_status;
2234 u32 grbm_status, grbm_status2;
2235 u32 grbm_status_se0, grbm_status_se1;
2236 struct r100_gpu_lockup *lockup = &rdev->config.si.lockup;
2237 int r;
2238
2239 srbm_status = RREG32(SRBM_STATUS);
2240 grbm_status = RREG32(GRBM_STATUS);
2241 grbm_status2 = RREG32(GRBM_STATUS2);
2242 grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2243 grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2244 if (!(grbm_status & GUI_ACTIVE)) {
2245 r100_gpu_lockup_update(lockup, ring);
2246 return false;
2247 }
2248 /* force CP activities */
2249 r = radeon_ring_lock(rdev, ring, 2);
2250 if (!r) {
2251 /* PACKET2 NOP */
2252 radeon_ring_write(ring, 0x80000000);
2253 radeon_ring_write(ring, 0x80000000);
2254 radeon_ring_unlock_commit(rdev, ring);
2255 }
2256 /* XXX deal with CP0,1,2 */
2257 ring->rptr = RREG32(ring->rptr_reg);
2258 return r100_gpu_cp_is_lockup(rdev, lockup, ring);
2259 }
2260
si_gpu_soft_reset(struct radeon_device * rdev)2261 static int si_gpu_soft_reset(struct radeon_device *rdev)
2262 {
2263 struct evergreen_mc_save save;
2264 u32 grbm_reset = 0;
2265
2266 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2267 return 0;
2268
2269 dev_info(rdev->dev, "GPU softreset \n");
2270 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2271 RREG32(GRBM_STATUS));
2272 dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n",
2273 RREG32(GRBM_STATUS2));
2274 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2275 RREG32(GRBM_STATUS_SE0));
2276 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2277 RREG32(GRBM_STATUS_SE1));
2278 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2279 RREG32(SRBM_STATUS));
2280 evergreen_mc_stop(rdev, &save);
2281 if (radeon_mc_wait_for_idle(rdev)) {
2282 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2283 }
2284 /* Disable CP parsing/prefetching */
2285 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
2286
2287 /* reset all the gfx blocks */
2288 grbm_reset = (SOFT_RESET_CP |
2289 SOFT_RESET_CB |
2290 SOFT_RESET_DB |
2291 SOFT_RESET_GDS |
2292 SOFT_RESET_PA |
2293 SOFT_RESET_SC |
2294 SOFT_RESET_SPI |
2295 SOFT_RESET_SX |
2296 SOFT_RESET_TC |
2297 SOFT_RESET_TA |
2298 SOFT_RESET_VGT |
2299 SOFT_RESET_IA);
2300
2301 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2302 WREG32(GRBM_SOFT_RESET, grbm_reset);
2303 (void)RREG32(GRBM_SOFT_RESET);
2304 udelay(50);
2305 WREG32(GRBM_SOFT_RESET, 0);
2306 (void)RREG32(GRBM_SOFT_RESET);
2307 /* Wait a little for things to settle down */
2308 udelay(50);
2309 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2310 RREG32(GRBM_STATUS));
2311 dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n",
2312 RREG32(GRBM_STATUS2));
2313 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2314 RREG32(GRBM_STATUS_SE0));
2315 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2316 RREG32(GRBM_STATUS_SE1));
2317 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2318 RREG32(SRBM_STATUS));
2319 evergreen_mc_resume(rdev, &save);
2320 return 0;
2321 }
2322
si_asic_reset(struct radeon_device * rdev)2323 int si_asic_reset(struct radeon_device *rdev)
2324 {
2325 return si_gpu_soft_reset(rdev);
2326 }
2327
2328 /* MC */
si_mc_program(struct radeon_device * rdev)2329 static void si_mc_program(struct radeon_device *rdev)
2330 {
2331 struct evergreen_mc_save save;
2332 u32 tmp;
2333 int i, j;
2334
2335 /* Initialize HDP */
2336 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
2337 WREG32((0x2c14 + j), 0x00000000);
2338 WREG32((0x2c18 + j), 0x00000000);
2339 WREG32((0x2c1c + j), 0x00000000);
2340 WREG32((0x2c20 + j), 0x00000000);
2341 WREG32((0x2c24 + j), 0x00000000);
2342 }
2343 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
2344
2345 evergreen_mc_stop(rdev, &save);
2346 if (radeon_mc_wait_for_idle(rdev)) {
2347 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2348 }
2349 /* Lockout access through VGA aperture*/
2350 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
2351 /* Update configuration */
2352 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
2353 rdev->mc.vram_start >> 12);
2354 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
2355 rdev->mc.vram_end >> 12);
2356 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
2357 rdev->vram_scratch.gpu_addr >> 12);
2358 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
2359 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
2360 WREG32(MC_VM_FB_LOCATION, tmp);
2361 /* XXX double check these! */
2362 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
2363 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
2364 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
2365 WREG32(MC_VM_AGP_BASE, 0);
2366 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
2367 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
2368 if (radeon_mc_wait_for_idle(rdev)) {
2369 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2370 }
2371 evergreen_mc_resume(rdev, &save);
2372 /* we need to own VRAM, so turn off the VGA renderer here
2373 * to stop it overwriting our objects */
2374 rv515_vga_render_disable(rdev);
2375 }
2376
2377 /* SI MC address space is 40 bits */
si_vram_location(struct radeon_device * rdev,struct radeon_mc * mc,u64 base)2378 static void si_vram_location(struct radeon_device *rdev,
2379 struct radeon_mc *mc, u64 base)
2380 {
2381 mc->vram_start = base;
2382 if (mc->mc_vram_size > (0xFFFFFFFFFFULL - base + 1)) {
2383 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
2384 mc->real_vram_size = mc->aper_size;
2385 mc->mc_vram_size = mc->aper_size;
2386 }
2387 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
2388 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
2389 mc->mc_vram_size >> 20, mc->vram_start,
2390 mc->vram_end, mc->real_vram_size >> 20);
2391 }
2392
si_gtt_location(struct radeon_device * rdev,struct radeon_mc * mc)2393 static void si_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
2394 {
2395 u64 size_af, size_bf;
2396
2397 size_af = ((0xFFFFFFFFFFULL - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
2398 size_bf = mc->vram_start & ~mc->gtt_base_align;
2399 if (size_bf > size_af) {
2400 if (mc->gtt_size > size_bf) {
2401 dev_warn(rdev->dev, "limiting GTT\n");
2402 mc->gtt_size = size_bf;
2403 }
2404 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
2405 } else {
2406 if (mc->gtt_size > size_af) {
2407 dev_warn(rdev->dev, "limiting GTT\n");
2408 mc->gtt_size = size_af;
2409 }
2410 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
2411 }
2412 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
2413 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
2414 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
2415 }
2416
si_vram_gtt_location(struct radeon_device * rdev,struct radeon_mc * mc)2417 static void si_vram_gtt_location(struct radeon_device *rdev,
2418 struct radeon_mc *mc)
2419 {
2420 if (mc->mc_vram_size > 0xFFC0000000ULL) {
2421 /* leave room for at least 1024M GTT */
2422 dev_warn(rdev->dev, "limiting VRAM\n");
2423 mc->real_vram_size = 0xFFC0000000ULL;
2424 mc->mc_vram_size = 0xFFC0000000ULL;
2425 }
2426 si_vram_location(rdev, &rdev->mc, 0);
2427 rdev->mc.gtt_base_align = 0;
2428 si_gtt_location(rdev, mc);
2429 }
2430
si_mc_init(struct radeon_device * rdev)2431 static int si_mc_init(struct radeon_device *rdev)
2432 {
2433 u32 tmp;
2434 int chansize, numchan;
2435
2436 /* Get VRAM informations */
2437 rdev->mc.vram_is_ddr = true;
2438 tmp = RREG32(MC_ARB_RAMCFG);
2439 if (tmp & CHANSIZE_OVERRIDE) {
2440 chansize = 16;
2441 } else if (tmp & CHANSIZE_MASK) {
2442 chansize = 64;
2443 } else {
2444 chansize = 32;
2445 }
2446 tmp = RREG32(MC_SHARED_CHMAP);
2447 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2448 case 0:
2449 default:
2450 numchan = 1;
2451 break;
2452 case 1:
2453 numchan = 2;
2454 break;
2455 case 2:
2456 numchan = 4;
2457 break;
2458 case 3:
2459 numchan = 8;
2460 break;
2461 case 4:
2462 numchan = 3;
2463 break;
2464 case 5:
2465 numchan = 6;
2466 break;
2467 case 6:
2468 numchan = 10;
2469 break;
2470 case 7:
2471 numchan = 12;
2472 break;
2473 case 8:
2474 numchan = 16;
2475 break;
2476 }
2477 rdev->mc.vram_width = numchan * chansize;
2478 /* Could aper size report 0 ? */
2479 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2480 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2481 /* size in MB on si */
2482 tmp = RREG32(CONFIG_MEMSIZE);
2483 /* some boards may have garbage in the upper 16 bits */
2484 if (tmp & 0xffff0000) {
2485 DRM_INFO("Probable bad vram size: 0x%08x\n", tmp);
2486 if (tmp & 0xffff)
2487 tmp &= 0xffff;
2488 }
2489 rdev->mc.mc_vram_size = tmp * 1024ULL * 1024ULL;
2490 rdev->mc.real_vram_size = rdev->mc.mc_vram_size;
2491 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2492 si_vram_gtt_location(rdev, &rdev->mc);
2493 radeon_update_bandwidth_info(rdev);
2494
2495 return 0;
2496 }
2497
2498 /*
2499 * GART
2500 */
si_pcie_gart_tlb_flush(struct radeon_device * rdev)2501 void si_pcie_gart_tlb_flush(struct radeon_device *rdev)
2502 {
2503 /* flush hdp cache */
2504 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2505
2506 /* bits 0-15 are the VM contexts0-15 */
2507 WREG32(VM_INVALIDATE_REQUEST, 1);
2508 }
2509
si_pcie_gart_enable(struct radeon_device * rdev)2510 int si_pcie_gart_enable(struct radeon_device *rdev)
2511 {
2512 int r, i;
2513
2514 if (rdev->gart.robj == NULL) {
2515 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
2516 return -EINVAL;
2517 }
2518 r = radeon_gart_table_vram_pin(rdev);
2519 if (r)
2520 return r;
2521 radeon_gart_restore(rdev);
2522 /* Setup TLB control */
2523 WREG32(MC_VM_MX_L1_TLB_CNTL,
2524 (0xA << 7) |
2525 ENABLE_L1_TLB |
2526 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
2527 ENABLE_ADVANCED_DRIVER_MODEL |
2528 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
2529 /* Setup L2 cache */
2530 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
2531 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
2532 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
2533 EFFECTIVE_L2_QUEUE_SIZE(7) |
2534 CONTEXT1_IDENTITY_ACCESS_MODE(1));
2535 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
2536 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
2537 L2_CACHE_BIGK_FRAGMENT_SIZE(0));
2538 /* setup context0 */
2539 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
2540 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
2541 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
2542 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
2543 (u32)(rdev->dummy_page.addr >> 12));
2544 WREG32(VM_CONTEXT0_CNTL2, 0);
2545 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
2546 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT));
2547
2548 WREG32(0x15D4, 0);
2549 WREG32(0x15D8, 0);
2550 WREG32(0x15DC, 0);
2551
2552 /* empty context1-15 */
2553 /* FIXME start with 4G, once using 2 level pt switch to full
2554 * vm size space
2555 */
2556 /* set vm size, must be a multiple of 4 */
2557 WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
2558 WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn);
2559 for (i = 1; i < 16; i++) {
2560 if (i < 8)
2561 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
2562 rdev->gart.table_addr >> 12);
2563 else
2564 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2),
2565 rdev->gart.table_addr >> 12);
2566 }
2567
2568 /* enable context1-15 */
2569 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
2570 (u32)(rdev->dummy_page.addr >> 12));
2571 WREG32(VM_CONTEXT1_CNTL2, 0);
2572 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
2573 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
2574
2575 si_pcie_gart_tlb_flush(rdev);
2576 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
2577 (unsigned)(rdev->mc.gtt_size >> 20),
2578 (unsigned long long)rdev->gart.table_addr);
2579 rdev->gart.ready = true;
2580 return 0;
2581 }
2582
si_pcie_gart_disable(struct radeon_device * rdev)2583 void si_pcie_gart_disable(struct radeon_device *rdev)
2584 {
2585 /* Disable all tables */
2586 WREG32(VM_CONTEXT0_CNTL, 0);
2587 WREG32(VM_CONTEXT1_CNTL, 0);
2588 /* Setup TLB control */
2589 WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS |
2590 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
2591 /* Setup L2 cache */
2592 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
2593 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
2594 EFFECTIVE_L2_QUEUE_SIZE(7) |
2595 CONTEXT1_IDENTITY_ACCESS_MODE(1));
2596 WREG32(VM_L2_CNTL2, 0);
2597 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
2598 L2_CACHE_BIGK_FRAGMENT_SIZE(0));
2599 radeon_gart_table_vram_unpin(rdev);
2600 }
2601
si_pcie_gart_fini(struct radeon_device * rdev)2602 void si_pcie_gart_fini(struct radeon_device *rdev)
2603 {
2604 si_pcie_gart_disable(rdev);
2605 radeon_gart_table_vram_free(rdev);
2606 radeon_gart_fini(rdev);
2607 }
2608
2609 /* vm parser */
si_vm_reg_valid(u32 reg)2610 static bool si_vm_reg_valid(u32 reg)
2611 {
2612 /* context regs are fine */
2613 if (reg >= 0x28000)
2614 return true;
2615
2616 /* check config regs */
2617 switch (reg) {
2618 case GRBM_GFX_INDEX:
2619 case CP_STRMOUT_CNTL:
2620 case VGT_VTX_VECT_EJECT_REG:
2621 case VGT_CACHE_INVALIDATION:
2622 case VGT_ESGS_RING_SIZE:
2623 case VGT_GSVS_RING_SIZE:
2624 case VGT_GS_VERTEX_REUSE:
2625 case VGT_PRIMITIVE_TYPE:
2626 case VGT_INDEX_TYPE:
2627 case VGT_NUM_INDICES:
2628 case VGT_NUM_INSTANCES:
2629 case VGT_TF_RING_SIZE:
2630 case VGT_HS_OFFCHIP_PARAM:
2631 case VGT_TF_MEMORY_BASE:
2632 case PA_CL_ENHANCE:
2633 case PA_SU_LINE_STIPPLE_VALUE:
2634 case PA_SC_LINE_STIPPLE_STATE:
2635 case PA_SC_ENHANCE:
2636 case SQC_CACHES:
2637 case SPI_STATIC_THREAD_MGMT_1:
2638 case SPI_STATIC_THREAD_MGMT_2:
2639 case SPI_STATIC_THREAD_MGMT_3:
2640 case SPI_PS_MAX_WAVE_ID:
2641 case SPI_CONFIG_CNTL:
2642 case SPI_CONFIG_CNTL_1:
2643 case TA_CNTL_AUX:
2644 return true;
2645 default:
2646 DRM_ERROR("Invalid register 0x%x in CS\n", reg);
2647 return false;
2648 }
2649 }
2650
si_vm_packet3_ce_check(struct radeon_device * rdev,u32 * ib,struct radeon_cs_packet * pkt)2651 static int si_vm_packet3_ce_check(struct radeon_device *rdev,
2652 u32 *ib, struct radeon_cs_packet *pkt)
2653 {
2654 switch (pkt->opcode) {
2655 case PACKET3_NOP:
2656 case PACKET3_SET_BASE:
2657 case PACKET3_SET_CE_DE_COUNTERS:
2658 case PACKET3_LOAD_CONST_RAM:
2659 case PACKET3_WRITE_CONST_RAM:
2660 case PACKET3_WRITE_CONST_RAM_OFFSET:
2661 case PACKET3_DUMP_CONST_RAM:
2662 case PACKET3_INCREMENT_CE_COUNTER:
2663 case PACKET3_WAIT_ON_DE_COUNTER:
2664 case PACKET3_CE_WRITE:
2665 break;
2666 default:
2667 DRM_ERROR("Invalid CE packet3: 0x%x\n", pkt->opcode);
2668 return -EINVAL;
2669 }
2670 return 0;
2671 }
2672
si_vm_packet3_gfx_check(struct radeon_device * rdev,u32 * ib,struct radeon_cs_packet * pkt)2673 static int si_vm_packet3_gfx_check(struct radeon_device *rdev,
2674 u32 *ib, struct radeon_cs_packet *pkt)
2675 {
2676 u32 idx = pkt->idx + 1;
2677 u32 idx_value = ib[idx];
2678 u32 start_reg, end_reg, reg, i;
2679
2680 switch (pkt->opcode) {
2681 case PACKET3_NOP:
2682 case PACKET3_SET_BASE:
2683 case PACKET3_CLEAR_STATE:
2684 case PACKET3_INDEX_BUFFER_SIZE:
2685 case PACKET3_DISPATCH_DIRECT:
2686 case PACKET3_DISPATCH_INDIRECT:
2687 case PACKET3_ALLOC_GDS:
2688 case PACKET3_WRITE_GDS_RAM:
2689 case PACKET3_ATOMIC_GDS:
2690 case PACKET3_ATOMIC:
2691 case PACKET3_OCCLUSION_QUERY:
2692 case PACKET3_SET_PREDICATION:
2693 case PACKET3_COND_EXEC:
2694 case PACKET3_PRED_EXEC:
2695 case PACKET3_DRAW_INDIRECT:
2696 case PACKET3_DRAW_INDEX_INDIRECT:
2697 case PACKET3_INDEX_BASE:
2698 case PACKET3_DRAW_INDEX_2:
2699 case PACKET3_CONTEXT_CONTROL:
2700 case PACKET3_INDEX_TYPE:
2701 case PACKET3_DRAW_INDIRECT_MULTI:
2702 case PACKET3_DRAW_INDEX_AUTO:
2703 case PACKET3_DRAW_INDEX_IMMD:
2704 case PACKET3_NUM_INSTANCES:
2705 case PACKET3_DRAW_INDEX_MULTI_AUTO:
2706 case PACKET3_STRMOUT_BUFFER_UPDATE:
2707 case PACKET3_DRAW_INDEX_OFFSET_2:
2708 case PACKET3_DRAW_INDEX_MULTI_ELEMENT:
2709 case PACKET3_DRAW_INDEX_INDIRECT_MULTI:
2710 case PACKET3_MPEG_INDEX:
2711 case PACKET3_WAIT_REG_MEM:
2712 case PACKET3_MEM_WRITE:
2713 case PACKET3_PFP_SYNC_ME:
2714 case PACKET3_SURFACE_SYNC:
2715 case PACKET3_EVENT_WRITE:
2716 case PACKET3_EVENT_WRITE_EOP:
2717 case PACKET3_EVENT_WRITE_EOS:
2718 case PACKET3_SET_CONTEXT_REG:
2719 case PACKET3_SET_CONTEXT_REG_INDIRECT:
2720 case PACKET3_SET_SH_REG:
2721 case PACKET3_SET_SH_REG_OFFSET:
2722 case PACKET3_INCREMENT_DE_COUNTER:
2723 case PACKET3_WAIT_ON_CE_COUNTER:
2724 case PACKET3_WAIT_ON_AVAIL_BUFFER:
2725 case PACKET3_ME_WRITE:
2726 break;
2727 case PACKET3_COPY_DATA:
2728 if ((idx_value & 0xf00) == 0) {
2729 reg = ib[idx + 3] * 4;
2730 if (!si_vm_reg_valid(reg))
2731 return -EINVAL;
2732 }
2733 break;
2734 case PACKET3_WRITE_DATA:
2735 if ((idx_value & 0xf00) == 0) {
2736 start_reg = ib[idx + 1] * 4;
2737 if (idx_value & 0x10000) {
2738 if (!si_vm_reg_valid(start_reg))
2739 return -EINVAL;
2740 } else {
2741 for (i = 0; i < (pkt->count - 2); i++) {
2742 reg = start_reg + (4 * i);
2743 if (!si_vm_reg_valid(reg))
2744 return -EINVAL;
2745 }
2746 }
2747 }
2748 break;
2749 case PACKET3_COND_WRITE:
2750 if (idx_value & 0x100) {
2751 reg = ib[idx + 5] * 4;
2752 if (!si_vm_reg_valid(reg))
2753 return -EINVAL;
2754 }
2755 break;
2756 case PACKET3_COPY_DW:
2757 if (idx_value & 0x2) {
2758 reg = ib[idx + 3] * 4;
2759 if (!si_vm_reg_valid(reg))
2760 return -EINVAL;
2761 }
2762 break;
2763 case PACKET3_SET_CONFIG_REG:
2764 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
2765 end_reg = 4 * pkt->count + start_reg - 4;
2766 if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
2767 (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
2768 (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
2769 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
2770 return -EINVAL;
2771 }
2772 for (i = 0; i < pkt->count; i++) {
2773 reg = start_reg + (4 * i);
2774 if (!si_vm_reg_valid(reg))
2775 return -EINVAL;
2776 }
2777 break;
2778 default:
2779 DRM_ERROR("Invalid GFX packet3: 0x%x\n", pkt->opcode);
2780 return -EINVAL;
2781 }
2782 return 0;
2783 }
2784
si_vm_packet3_compute_check(struct radeon_device * rdev,u32 * ib,struct radeon_cs_packet * pkt)2785 static int si_vm_packet3_compute_check(struct radeon_device *rdev,
2786 u32 *ib, struct radeon_cs_packet *pkt)
2787 {
2788 u32 idx = pkt->idx + 1;
2789 u32 idx_value = ib[idx];
2790 u32 start_reg, reg, i;
2791
2792 switch (pkt->opcode) {
2793 case PACKET3_NOP:
2794 case PACKET3_SET_BASE:
2795 case PACKET3_CLEAR_STATE:
2796 case PACKET3_DISPATCH_DIRECT:
2797 case PACKET3_DISPATCH_INDIRECT:
2798 case PACKET3_ALLOC_GDS:
2799 case PACKET3_WRITE_GDS_RAM:
2800 case PACKET3_ATOMIC_GDS:
2801 case PACKET3_ATOMIC:
2802 case PACKET3_OCCLUSION_QUERY:
2803 case PACKET3_SET_PREDICATION:
2804 case PACKET3_COND_EXEC:
2805 case PACKET3_PRED_EXEC:
2806 case PACKET3_CONTEXT_CONTROL:
2807 case PACKET3_STRMOUT_BUFFER_UPDATE:
2808 case PACKET3_WAIT_REG_MEM:
2809 case PACKET3_MEM_WRITE:
2810 case PACKET3_PFP_SYNC_ME:
2811 case PACKET3_SURFACE_SYNC:
2812 case PACKET3_EVENT_WRITE:
2813 case PACKET3_EVENT_WRITE_EOP:
2814 case PACKET3_EVENT_WRITE_EOS:
2815 case PACKET3_SET_CONTEXT_REG:
2816 case PACKET3_SET_CONTEXT_REG_INDIRECT:
2817 case PACKET3_SET_SH_REG:
2818 case PACKET3_SET_SH_REG_OFFSET:
2819 case PACKET3_INCREMENT_DE_COUNTER:
2820 case PACKET3_WAIT_ON_CE_COUNTER:
2821 case PACKET3_WAIT_ON_AVAIL_BUFFER:
2822 case PACKET3_ME_WRITE:
2823 break;
2824 case PACKET3_COPY_DATA:
2825 if ((idx_value & 0xf00) == 0) {
2826 reg = ib[idx + 3] * 4;
2827 if (!si_vm_reg_valid(reg))
2828 return -EINVAL;
2829 }
2830 break;
2831 case PACKET3_WRITE_DATA:
2832 if ((idx_value & 0xf00) == 0) {
2833 start_reg = ib[idx + 1] * 4;
2834 if (idx_value & 0x10000) {
2835 if (!si_vm_reg_valid(start_reg))
2836 return -EINVAL;
2837 } else {
2838 for (i = 0; i < (pkt->count - 2); i++) {
2839 reg = start_reg + (4 * i);
2840 if (!si_vm_reg_valid(reg))
2841 return -EINVAL;
2842 }
2843 }
2844 }
2845 break;
2846 case PACKET3_COND_WRITE:
2847 if (idx_value & 0x100) {
2848 reg = ib[idx + 5] * 4;
2849 if (!si_vm_reg_valid(reg))
2850 return -EINVAL;
2851 }
2852 break;
2853 case PACKET3_COPY_DW:
2854 if (idx_value & 0x2) {
2855 reg = ib[idx + 3] * 4;
2856 if (!si_vm_reg_valid(reg))
2857 return -EINVAL;
2858 }
2859 break;
2860 default:
2861 DRM_ERROR("Invalid Compute packet3: 0x%x\n", pkt->opcode);
2862 return -EINVAL;
2863 }
2864 return 0;
2865 }
2866
si_ib_parse(struct radeon_device * rdev,struct radeon_ib * ib)2867 int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
2868 {
2869 int ret = 0;
2870 u32 idx = 0;
2871 struct radeon_cs_packet pkt;
2872
2873 do {
2874 pkt.idx = idx;
2875 pkt.type = CP_PACKET_GET_TYPE(ib->ptr[idx]);
2876 pkt.count = CP_PACKET_GET_COUNT(ib->ptr[idx]);
2877 pkt.one_reg_wr = 0;
2878 switch (pkt.type) {
2879 case PACKET_TYPE0:
2880 dev_err(rdev->dev, "Packet0 not allowed!\n");
2881 ret = -EINVAL;
2882 break;
2883 case PACKET_TYPE2:
2884 idx += 1;
2885 break;
2886 case PACKET_TYPE3:
2887 pkt.opcode = CP_PACKET3_GET_OPCODE(ib->ptr[idx]);
2888 if (ib->is_const_ib)
2889 ret = si_vm_packet3_ce_check(rdev, ib->ptr, &pkt);
2890 else {
2891 switch (ib->fence->ring) {
2892 case RADEON_RING_TYPE_GFX_INDEX:
2893 ret = si_vm_packet3_gfx_check(rdev, ib->ptr, &pkt);
2894 break;
2895 case CAYMAN_RING_TYPE_CP1_INDEX:
2896 case CAYMAN_RING_TYPE_CP2_INDEX:
2897 ret = si_vm_packet3_compute_check(rdev, ib->ptr, &pkt);
2898 break;
2899 default:
2900 dev_err(rdev->dev, "Non-PM4 ring %d !\n", ib->fence->ring);
2901 ret = -EINVAL;
2902 break;
2903 }
2904 }
2905 idx += pkt.count + 2;
2906 break;
2907 default:
2908 dev_err(rdev->dev, "Unknown packet type %d !\n", pkt.type);
2909 ret = -EINVAL;
2910 break;
2911 }
2912 if (ret)
2913 break;
2914 } while (idx < ib->length_dw);
2915
2916 return ret;
2917 }
2918
2919 /*
2920 * vm
2921 */
si_vm_init(struct radeon_device * rdev)2922 int si_vm_init(struct radeon_device *rdev)
2923 {
2924 /* number of VMs */
2925 rdev->vm_manager.nvm = 16;
2926 /* base offset of vram pages */
2927 rdev->vm_manager.vram_base_offset = 0;
2928
2929 return 0;
2930 }
2931
si_vm_fini(struct radeon_device * rdev)2932 void si_vm_fini(struct radeon_device *rdev)
2933 {
2934 }
2935
si_vm_bind(struct radeon_device * rdev,struct radeon_vm * vm,int id)2936 int si_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm, int id)
2937 {
2938 if (id < 8)
2939 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (id << 2), vm->pt_gpu_addr >> 12);
2940 else
2941 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((id - 8) << 2),
2942 vm->pt_gpu_addr >> 12);
2943 /* flush hdp cache */
2944 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2945 /* bits 0-15 are the VM contexts0-15 */
2946 WREG32(VM_INVALIDATE_REQUEST, 1 << id);
2947 return 0;
2948 }
2949
si_vm_unbind(struct radeon_device * rdev,struct radeon_vm * vm)2950 void si_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm)
2951 {
2952 if (vm->id < 8)
2953 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0);
2954 else
2955 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2), 0);
2956 /* flush hdp cache */
2957 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2958 /* bits 0-15 are the VM contexts0-15 */
2959 WREG32(VM_INVALIDATE_REQUEST, 1 << vm->id);
2960 }
2961
si_vm_tlb_flush(struct radeon_device * rdev,struct radeon_vm * vm)2962 void si_vm_tlb_flush(struct radeon_device *rdev, struct radeon_vm *vm)
2963 {
2964 if (vm->id == -1)
2965 return;
2966
2967 /* flush hdp cache */
2968 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2969 /* bits 0-15 are the VM contexts0-15 */
2970 WREG32(VM_INVALIDATE_REQUEST, 1 << vm->id);
2971 }
2972
2973 /*
2974 * RLC
2975 */
si_rlc_fini(struct radeon_device * rdev)2976 void si_rlc_fini(struct radeon_device *rdev)
2977 {
2978 int r;
2979
2980 /* save restore block */
2981 if (rdev->rlc.save_restore_obj) {
2982 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
2983 if (unlikely(r != 0))
2984 dev_warn(rdev->dev, "(%d) reserve RLC sr bo failed\n", r);
2985 radeon_bo_unpin(rdev->rlc.save_restore_obj);
2986 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
2987
2988 radeon_bo_unref(&rdev->rlc.save_restore_obj);
2989 rdev->rlc.save_restore_obj = NULL;
2990 }
2991
2992 /* clear state block */
2993 if (rdev->rlc.clear_state_obj) {
2994 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
2995 if (unlikely(r != 0))
2996 dev_warn(rdev->dev, "(%d) reserve RLC c bo failed\n", r);
2997 radeon_bo_unpin(rdev->rlc.clear_state_obj);
2998 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
2999
3000 radeon_bo_unref(&rdev->rlc.clear_state_obj);
3001 rdev->rlc.clear_state_obj = NULL;
3002 }
3003 }
3004
si_rlc_init(struct radeon_device * rdev)3005 int si_rlc_init(struct radeon_device *rdev)
3006 {
3007 int r;
3008
3009 /* save restore block */
3010 if (rdev->rlc.save_restore_obj == NULL) {
3011 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
3012 RADEON_GEM_DOMAIN_VRAM, &rdev->rlc.save_restore_obj);
3013 if (r) {
3014 dev_warn(rdev->dev, "(%d) create RLC sr bo failed\n", r);
3015 return r;
3016 }
3017 }
3018
3019 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
3020 if (unlikely(r != 0)) {
3021 si_rlc_fini(rdev);
3022 return r;
3023 }
3024 r = radeon_bo_pin(rdev->rlc.save_restore_obj, RADEON_GEM_DOMAIN_VRAM,
3025 &rdev->rlc.save_restore_gpu_addr);
3026 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
3027 if (r) {
3028 dev_warn(rdev->dev, "(%d) pin RLC sr bo failed\n", r);
3029 si_rlc_fini(rdev);
3030 return r;
3031 }
3032
3033 /* clear state block */
3034 if (rdev->rlc.clear_state_obj == NULL) {
3035 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
3036 RADEON_GEM_DOMAIN_VRAM, &rdev->rlc.clear_state_obj);
3037 if (r) {
3038 dev_warn(rdev->dev, "(%d) create RLC c bo failed\n", r);
3039 si_rlc_fini(rdev);
3040 return r;
3041 }
3042 }
3043 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
3044 if (unlikely(r != 0)) {
3045 si_rlc_fini(rdev);
3046 return r;
3047 }
3048 r = radeon_bo_pin(rdev->rlc.clear_state_obj, RADEON_GEM_DOMAIN_VRAM,
3049 &rdev->rlc.clear_state_gpu_addr);
3050 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
3051 if (r) {
3052 dev_warn(rdev->dev, "(%d) pin RLC c bo failed\n", r);
3053 si_rlc_fini(rdev);
3054 return r;
3055 }
3056
3057 return 0;
3058 }
3059
si_rlc_stop(struct radeon_device * rdev)3060 static void si_rlc_stop(struct radeon_device *rdev)
3061 {
3062 WREG32(RLC_CNTL, 0);
3063 }
3064
si_rlc_start(struct radeon_device * rdev)3065 static void si_rlc_start(struct radeon_device *rdev)
3066 {
3067 WREG32(RLC_CNTL, RLC_ENABLE);
3068 }
3069
si_rlc_resume(struct radeon_device * rdev)3070 static int si_rlc_resume(struct radeon_device *rdev)
3071 {
3072 u32 i;
3073 const __be32 *fw_data;
3074
3075 if (!rdev->rlc_fw)
3076 return -EINVAL;
3077
3078 si_rlc_stop(rdev);
3079
3080 WREG32(RLC_RL_BASE, 0);
3081 WREG32(RLC_RL_SIZE, 0);
3082 WREG32(RLC_LB_CNTL, 0);
3083 WREG32(RLC_LB_CNTR_MAX, 0xffffffff);
3084 WREG32(RLC_LB_CNTR_INIT, 0);
3085
3086 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
3087 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
3088
3089 WREG32(RLC_MC_CNTL, 0);
3090 WREG32(RLC_UCODE_CNTL, 0);
3091
3092 fw_data = (const __be32 *)rdev->rlc_fw->data;
3093 for (i = 0; i < SI_RLC_UCODE_SIZE; i++) {
3094 WREG32(RLC_UCODE_ADDR, i);
3095 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3096 }
3097 WREG32(RLC_UCODE_ADDR, 0);
3098
3099 si_rlc_start(rdev);
3100
3101 return 0;
3102 }
3103
si_enable_interrupts(struct radeon_device * rdev)3104 static void si_enable_interrupts(struct radeon_device *rdev)
3105 {
3106 u32 ih_cntl = RREG32(IH_CNTL);
3107 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3108
3109 ih_cntl |= ENABLE_INTR;
3110 ih_rb_cntl |= IH_RB_ENABLE;
3111 WREG32(IH_CNTL, ih_cntl);
3112 WREG32(IH_RB_CNTL, ih_rb_cntl);
3113 rdev->ih.enabled = true;
3114 }
3115
si_disable_interrupts(struct radeon_device * rdev)3116 static void si_disable_interrupts(struct radeon_device *rdev)
3117 {
3118 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3119 u32 ih_cntl = RREG32(IH_CNTL);
3120
3121 ih_rb_cntl &= ~IH_RB_ENABLE;
3122 ih_cntl &= ~ENABLE_INTR;
3123 WREG32(IH_RB_CNTL, ih_rb_cntl);
3124 WREG32(IH_CNTL, ih_cntl);
3125 /* set rptr, wptr to 0 */
3126 WREG32(IH_RB_RPTR, 0);
3127 WREG32(IH_RB_WPTR, 0);
3128 rdev->ih.enabled = false;
3129 rdev->ih.wptr = 0;
3130 rdev->ih.rptr = 0;
3131 }
3132
si_disable_interrupt_state(struct radeon_device * rdev)3133 static void si_disable_interrupt_state(struct radeon_device *rdev)
3134 {
3135 u32 tmp;
3136
3137 WREG32(CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
3138 WREG32(CP_INT_CNTL_RING1, 0);
3139 WREG32(CP_INT_CNTL_RING2, 0);
3140 WREG32(GRBM_INT_CNTL, 0);
3141 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
3142 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
3143 if (rdev->num_crtc >= 4) {
3144 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
3145 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
3146 }
3147 if (rdev->num_crtc >= 6) {
3148 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
3149 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
3150 }
3151
3152 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
3153 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
3154 if (rdev->num_crtc >= 4) {
3155 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
3156 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
3157 }
3158 if (rdev->num_crtc >= 6) {
3159 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
3160 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
3161 }
3162
3163 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
3164
3165 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3166 WREG32(DC_HPD1_INT_CONTROL, tmp);
3167 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3168 WREG32(DC_HPD2_INT_CONTROL, tmp);
3169 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3170 WREG32(DC_HPD3_INT_CONTROL, tmp);
3171 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3172 WREG32(DC_HPD4_INT_CONTROL, tmp);
3173 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3174 WREG32(DC_HPD5_INT_CONTROL, tmp);
3175 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3176 WREG32(DC_HPD6_INT_CONTROL, tmp);
3177
3178 }
3179
si_irq_init(struct radeon_device * rdev)3180 static int si_irq_init(struct radeon_device *rdev)
3181 {
3182 int ret = 0;
3183 int rb_bufsz;
3184 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
3185
3186 /* allocate ring */
3187 ret = r600_ih_ring_alloc(rdev);
3188 if (ret)
3189 return ret;
3190
3191 /* disable irqs */
3192 si_disable_interrupts(rdev);
3193
3194 /* init rlc */
3195 ret = si_rlc_resume(rdev);
3196 if (ret) {
3197 r600_ih_ring_fini(rdev);
3198 return ret;
3199 }
3200
3201 /* setup interrupt control */
3202 /* set dummy read address to ring address */
3203 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
3204 interrupt_cntl = RREG32(INTERRUPT_CNTL);
3205 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
3206 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
3207 */
3208 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
3209 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3210 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
3211 WREG32(INTERRUPT_CNTL, interrupt_cntl);
3212
3213 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
3214 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
3215
3216 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
3217 IH_WPTR_OVERFLOW_CLEAR |
3218 (rb_bufsz << 1));
3219
3220 if (rdev->wb.enabled)
3221 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
3222
3223 /* set the writeback address whether it's enabled or not */
3224 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3225 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
3226
3227 WREG32(IH_RB_CNTL, ih_rb_cntl);
3228
3229 /* set rptr, wptr to 0 */
3230 WREG32(IH_RB_RPTR, 0);
3231 WREG32(IH_RB_WPTR, 0);
3232
3233 /* Default settings for IH_CNTL (disabled at first) */
3234 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0);
3235 /* RPTR_REARM only works if msi's are enabled */
3236 if (rdev->msi_enabled)
3237 ih_cntl |= RPTR_REARM;
3238 WREG32(IH_CNTL, ih_cntl);
3239
3240 /* force the active interrupt state to all disabled */
3241 si_disable_interrupt_state(rdev);
3242
3243 /* enable irqs */
3244 si_enable_interrupts(rdev);
3245
3246 return ret;
3247 }
3248
si_irq_set(struct radeon_device * rdev)3249 int si_irq_set(struct radeon_device *rdev)
3250 {
3251 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3252 u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
3253 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
3254 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
3255 u32 grbm_int_cntl = 0;
3256 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
3257
3258 if (!rdev->irq.installed) {
3259 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
3260 return -EINVAL;
3261 }
3262 /* don't enable anything if the ih is disabled */
3263 if (!rdev->ih.enabled) {
3264 si_disable_interrupts(rdev);
3265 /* force the active interrupt state to all disabled */
3266 si_disable_interrupt_state(rdev);
3267 return 0;
3268 }
3269
3270 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3271 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3272 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3273 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3274 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3275 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3276
3277 /* enable CP interrupts on all rings */
3278 if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
3279 DRM_DEBUG("si_irq_set: sw int gfx\n");
3280 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3281 }
3282 if (rdev->irq.sw_int[CAYMAN_RING_TYPE_CP1_INDEX]) {
3283 DRM_DEBUG("si_irq_set: sw int cp1\n");
3284 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
3285 }
3286 if (rdev->irq.sw_int[CAYMAN_RING_TYPE_CP2_INDEX]) {
3287 DRM_DEBUG("si_irq_set: sw int cp2\n");
3288 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
3289 }
3290 if (rdev->irq.crtc_vblank_int[0] ||
3291 rdev->irq.pflip[0]) {
3292 DRM_DEBUG("si_irq_set: vblank 0\n");
3293 crtc1 |= VBLANK_INT_MASK;
3294 }
3295 if (rdev->irq.crtc_vblank_int[1] ||
3296 rdev->irq.pflip[1]) {
3297 DRM_DEBUG("si_irq_set: vblank 1\n");
3298 crtc2 |= VBLANK_INT_MASK;
3299 }
3300 if (rdev->irq.crtc_vblank_int[2] ||
3301 rdev->irq.pflip[2]) {
3302 DRM_DEBUG("si_irq_set: vblank 2\n");
3303 crtc3 |= VBLANK_INT_MASK;
3304 }
3305 if (rdev->irq.crtc_vblank_int[3] ||
3306 rdev->irq.pflip[3]) {
3307 DRM_DEBUG("si_irq_set: vblank 3\n");
3308 crtc4 |= VBLANK_INT_MASK;
3309 }
3310 if (rdev->irq.crtc_vblank_int[4] ||
3311 rdev->irq.pflip[4]) {
3312 DRM_DEBUG("si_irq_set: vblank 4\n");
3313 crtc5 |= VBLANK_INT_MASK;
3314 }
3315 if (rdev->irq.crtc_vblank_int[5] ||
3316 rdev->irq.pflip[5]) {
3317 DRM_DEBUG("si_irq_set: vblank 5\n");
3318 crtc6 |= VBLANK_INT_MASK;
3319 }
3320 if (rdev->irq.hpd[0]) {
3321 DRM_DEBUG("si_irq_set: hpd 1\n");
3322 hpd1 |= DC_HPDx_INT_EN;
3323 }
3324 if (rdev->irq.hpd[1]) {
3325 DRM_DEBUG("si_irq_set: hpd 2\n");
3326 hpd2 |= DC_HPDx_INT_EN;
3327 }
3328 if (rdev->irq.hpd[2]) {
3329 DRM_DEBUG("si_irq_set: hpd 3\n");
3330 hpd3 |= DC_HPDx_INT_EN;
3331 }
3332 if (rdev->irq.hpd[3]) {
3333 DRM_DEBUG("si_irq_set: hpd 4\n");
3334 hpd4 |= DC_HPDx_INT_EN;
3335 }
3336 if (rdev->irq.hpd[4]) {
3337 DRM_DEBUG("si_irq_set: hpd 5\n");
3338 hpd5 |= DC_HPDx_INT_EN;
3339 }
3340 if (rdev->irq.hpd[5]) {
3341 DRM_DEBUG("si_irq_set: hpd 6\n");
3342 hpd6 |= DC_HPDx_INT_EN;
3343 }
3344 if (rdev->irq.gui_idle) {
3345 DRM_DEBUG("gui idle\n");
3346 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
3347 }
3348
3349 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
3350 WREG32(CP_INT_CNTL_RING1, cp_int_cntl1);
3351 WREG32(CP_INT_CNTL_RING2, cp_int_cntl2);
3352
3353 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3354
3355 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
3356 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
3357 if (rdev->num_crtc >= 4) {
3358 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
3359 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
3360 }
3361 if (rdev->num_crtc >= 6) {
3362 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
3363 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
3364 }
3365
3366 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
3367 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
3368 if (rdev->num_crtc >= 4) {
3369 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
3370 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
3371 }
3372 if (rdev->num_crtc >= 6) {
3373 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
3374 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
3375 }
3376
3377 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3378 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3379 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3380 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3381 WREG32(DC_HPD5_INT_CONTROL, hpd5);
3382 WREG32(DC_HPD6_INT_CONTROL, hpd6);
3383
3384 return 0;
3385 }
3386
si_irq_ack(struct radeon_device * rdev)3387 static inline void si_irq_ack(struct radeon_device *rdev)
3388 {
3389 u32 tmp;
3390
3391 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3392 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3393 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
3394 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
3395 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
3396 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
3397 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
3398 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
3399 if (rdev->num_crtc >= 4) {
3400 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
3401 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
3402 }
3403 if (rdev->num_crtc >= 6) {
3404 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
3405 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
3406 }
3407
3408 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
3409 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3410 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
3411 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3412 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
3413 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
3414 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
3415 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
3416 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
3417 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
3418 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
3419 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
3420
3421 if (rdev->num_crtc >= 4) {
3422 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
3423 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3424 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
3425 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3426 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
3427 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
3428 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
3429 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
3430 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
3431 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
3432 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
3433 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
3434 }
3435
3436 if (rdev->num_crtc >= 6) {
3437 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
3438 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3439 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
3440 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3441 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
3442 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
3443 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
3444 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
3445 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
3446 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
3447 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
3448 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
3449 }
3450
3451 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
3452 tmp = RREG32(DC_HPD1_INT_CONTROL);
3453 tmp |= DC_HPDx_INT_ACK;
3454 WREG32(DC_HPD1_INT_CONTROL, tmp);
3455 }
3456 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
3457 tmp = RREG32(DC_HPD2_INT_CONTROL);
3458 tmp |= DC_HPDx_INT_ACK;
3459 WREG32(DC_HPD2_INT_CONTROL, tmp);
3460 }
3461 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
3462 tmp = RREG32(DC_HPD3_INT_CONTROL);
3463 tmp |= DC_HPDx_INT_ACK;
3464 WREG32(DC_HPD3_INT_CONTROL, tmp);
3465 }
3466 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
3467 tmp = RREG32(DC_HPD4_INT_CONTROL);
3468 tmp |= DC_HPDx_INT_ACK;
3469 WREG32(DC_HPD4_INT_CONTROL, tmp);
3470 }
3471 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
3472 tmp = RREG32(DC_HPD5_INT_CONTROL);
3473 tmp |= DC_HPDx_INT_ACK;
3474 WREG32(DC_HPD5_INT_CONTROL, tmp);
3475 }
3476 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
3477 tmp = RREG32(DC_HPD5_INT_CONTROL);
3478 tmp |= DC_HPDx_INT_ACK;
3479 WREG32(DC_HPD6_INT_CONTROL, tmp);
3480 }
3481 }
3482
si_irq_disable(struct radeon_device * rdev)3483 static void si_irq_disable(struct radeon_device *rdev)
3484 {
3485 si_disable_interrupts(rdev);
3486 /* Wait and acknowledge irq */
3487 mdelay(1);
3488 si_irq_ack(rdev);
3489 si_disable_interrupt_state(rdev);
3490 }
3491
si_irq_suspend(struct radeon_device * rdev)3492 static void si_irq_suspend(struct radeon_device *rdev)
3493 {
3494 si_irq_disable(rdev);
3495 si_rlc_stop(rdev);
3496 }
3497
si_irq_fini(struct radeon_device * rdev)3498 static void si_irq_fini(struct radeon_device *rdev)
3499 {
3500 si_irq_suspend(rdev);
3501 r600_ih_ring_fini(rdev);
3502 }
3503
si_get_ih_wptr(struct radeon_device * rdev)3504 static inline u32 si_get_ih_wptr(struct radeon_device *rdev)
3505 {
3506 u32 wptr, tmp;
3507
3508 if (rdev->wb.enabled)
3509 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
3510 else
3511 wptr = RREG32(IH_RB_WPTR);
3512
3513 if (wptr & RB_OVERFLOW) {
3514 /* When a ring buffer overflow happen start parsing interrupt
3515 * from the last not overwritten vector (wptr + 16). Hopefully
3516 * this should allow us to catchup.
3517 */
3518 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3519 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3520 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3521 tmp = RREG32(IH_RB_CNTL);
3522 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3523 WREG32(IH_RB_CNTL, tmp);
3524 }
3525 return (wptr & rdev->ih.ptr_mask);
3526 }
3527
3528 /* SI IV Ring
3529 * Each IV ring entry is 128 bits:
3530 * [7:0] - interrupt source id
3531 * [31:8] - reserved
3532 * [59:32] - interrupt source data
3533 * [63:60] - reserved
3534 * [71:64] - RINGID
3535 * [79:72] - VMID
3536 * [127:80] - reserved
3537 */
si_irq_process(struct radeon_device * rdev)3538 int si_irq_process(struct radeon_device *rdev)
3539 {
3540 u32 wptr;
3541 u32 rptr;
3542 u32 src_id, src_data, ring_id;
3543 u32 ring_index;
3544 unsigned long flags;
3545 bool queue_hotplug = false;
3546
3547 if (!rdev->ih.enabled || rdev->shutdown)
3548 return IRQ_NONE;
3549
3550 wptr = si_get_ih_wptr(rdev);
3551 rptr = rdev->ih.rptr;
3552 DRM_DEBUG("si_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3553
3554 spin_lock_irqsave(&rdev->ih.lock, flags);
3555 if (rptr == wptr) {
3556 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3557 return IRQ_NONE;
3558 }
3559 restart_ih:
3560 /* Order reading of wptr vs. reading of IH ring data */
3561 rmb();
3562
3563 /* display interrupts */
3564 si_irq_ack(rdev);
3565
3566 rdev->ih.wptr = wptr;
3567 while (rptr != wptr) {
3568 /* wptr/rptr are in bytes! */
3569 ring_index = rptr / 4;
3570 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
3571 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
3572 ring_id = le32_to_cpu(rdev->ih.ring[ring_index + 2]) & 0xff;
3573
3574 switch (src_id) {
3575 case 1: /* D1 vblank/vline */
3576 switch (src_data) {
3577 case 0: /* D1 vblank */
3578 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
3579 if (rdev->irq.crtc_vblank_int[0]) {
3580 drm_handle_vblank(rdev->ddev, 0);
3581 rdev->pm.vblank_sync = true;
3582 wake_up(&rdev->irq.vblank_queue);
3583 }
3584 if (rdev->irq.pflip[0])
3585 radeon_crtc_handle_flip(rdev, 0);
3586 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3587 DRM_DEBUG("IH: D1 vblank\n");
3588 }
3589 break;
3590 case 1: /* D1 vline */
3591 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
3592 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
3593 DRM_DEBUG("IH: D1 vline\n");
3594 }
3595 break;
3596 default:
3597 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3598 break;
3599 }
3600 break;
3601 case 2: /* D2 vblank/vline */
3602 switch (src_data) {
3603 case 0: /* D2 vblank */
3604 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
3605 if (rdev->irq.crtc_vblank_int[1]) {
3606 drm_handle_vblank(rdev->ddev, 1);
3607 rdev->pm.vblank_sync = true;
3608 wake_up(&rdev->irq.vblank_queue);
3609 }
3610 if (rdev->irq.pflip[1])
3611 radeon_crtc_handle_flip(rdev, 1);
3612 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
3613 DRM_DEBUG("IH: D2 vblank\n");
3614 }
3615 break;
3616 case 1: /* D2 vline */
3617 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
3618 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
3619 DRM_DEBUG("IH: D2 vline\n");
3620 }
3621 break;
3622 default:
3623 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3624 break;
3625 }
3626 break;
3627 case 3: /* D3 vblank/vline */
3628 switch (src_data) {
3629 case 0: /* D3 vblank */
3630 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
3631 if (rdev->irq.crtc_vblank_int[2]) {
3632 drm_handle_vblank(rdev->ddev, 2);
3633 rdev->pm.vblank_sync = true;
3634 wake_up(&rdev->irq.vblank_queue);
3635 }
3636 if (rdev->irq.pflip[2])
3637 radeon_crtc_handle_flip(rdev, 2);
3638 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
3639 DRM_DEBUG("IH: D3 vblank\n");
3640 }
3641 break;
3642 case 1: /* D3 vline */
3643 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
3644 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
3645 DRM_DEBUG("IH: D3 vline\n");
3646 }
3647 break;
3648 default:
3649 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3650 break;
3651 }
3652 break;
3653 case 4: /* D4 vblank/vline */
3654 switch (src_data) {
3655 case 0: /* D4 vblank */
3656 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
3657 if (rdev->irq.crtc_vblank_int[3]) {
3658 drm_handle_vblank(rdev->ddev, 3);
3659 rdev->pm.vblank_sync = true;
3660 wake_up(&rdev->irq.vblank_queue);
3661 }
3662 if (rdev->irq.pflip[3])
3663 radeon_crtc_handle_flip(rdev, 3);
3664 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
3665 DRM_DEBUG("IH: D4 vblank\n");
3666 }
3667 break;
3668 case 1: /* D4 vline */
3669 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
3670 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
3671 DRM_DEBUG("IH: D4 vline\n");
3672 }
3673 break;
3674 default:
3675 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3676 break;
3677 }
3678 break;
3679 case 5: /* D5 vblank/vline */
3680 switch (src_data) {
3681 case 0: /* D5 vblank */
3682 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
3683 if (rdev->irq.crtc_vblank_int[4]) {
3684 drm_handle_vblank(rdev->ddev, 4);
3685 rdev->pm.vblank_sync = true;
3686 wake_up(&rdev->irq.vblank_queue);
3687 }
3688 if (rdev->irq.pflip[4])
3689 radeon_crtc_handle_flip(rdev, 4);
3690 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
3691 DRM_DEBUG("IH: D5 vblank\n");
3692 }
3693 break;
3694 case 1: /* D5 vline */
3695 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
3696 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
3697 DRM_DEBUG("IH: D5 vline\n");
3698 }
3699 break;
3700 default:
3701 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3702 break;
3703 }
3704 break;
3705 case 6: /* D6 vblank/vline */
3706 switch (src_data) {
3707 case 0: /* D6 vblank */
3708 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
3709 if (rdev->irq.crtc_vblank_int[5]) {
3710 drm_handle_vblank(rdev->ddev, 5);
3711 rdev->pm.vblank_sync = true;
3712 wake_up(&rdev->irq.vblank_queue);
3713 }
3714 if (rdev->irq.pflip[5])
3715 radeon_crtc_handle_flip(rdev, 5);
3716 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
3717 DRM_DEBUG("IH: D6 vblank\n");
3718 }
3719 break;
3720 case 1: /* D6 vline */
3721 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
3722 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
3723 DRM_DEBUG("IH: D6 vline\n");
3724 }
3725 break;
3726 default:
3727 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3728 break;
3729 }
3730 break;
3731 case 42: /* HPD hotplug */
3732 switch (src_data) {
3733 case 0:
3734 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
3735 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
3736 queue_hotplug = true;
3737 DRM_DEBUG("IH: HPD1\n");
3738 }
3739 break;
3740 case 1:
3741 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
3742 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
3743 queue_hotplug = true;
3744 DRM_DEBUG("IH: HPD2\n");
3745 }
3746 break;
3747 case 2:
3748 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
3749 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
3750 queue_hotplug = true;
3751 DRM_DEBUG("IH: HPD3\n");
3752 }
3753 break;
3754 case 3:
3755 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
3756 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
3757 queue_hotplug = true;
3758 DRM_DEBUG("IH: HPD4\n");
3759 }
3760 break;
3761 case 4:
3762 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
3763 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
3764 queue_hotplug = true;
3765 DRM_DEBUG("IH: HPD5\n");
3766 }
3767 break;
3768 case 5:
3769 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
3770 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
3771 queue_hotplug = true;
3772 DRM_DEBUG("IH: HPD6\n");
3773 }
3774 break;
3775 default:
3776 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3777 break;
3778 }
3779 break;
3780 case 176: /* RINGID0 CP_INT */
3781 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3782 break;
3783 case 177: /* RINGID1 CP_INT */
3784 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
3785 break;
3786 case 178: /* RINGID2 CP_INT */
3787 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
3788 break;
3789 case 181: /* CP EOP event */
3790 DRM_DEBUG("IH: CP EOP\n");
3791 switch (ring_id) {
3792 case 0:
3793 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3794 break;
3795 case 1:
3796 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
3797 break;
3798 case 2:
3799 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
3800 break;
3801 }
3802 break;
3803 case 233: /* GUI IDLE */
3804 DRM_DEBUG("IH: GUI idle\n");
3805 rdev->pm.gui_idle = true;
3806 wake_up(&rdev->irq.idle_queue);
3807 break;
3808 default:
3809 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3810 break;
3811 }
3812
3813 /* wptr/rptr are in bytes! */
3814 rptr += 16;
3815 rptr &= rdev->ih.ptr_mask;
3816 }
3817 /* make sure wptr hasn't changed while processing */
3818 wptr = si_get_ih_wptr(rdev);
3819 if (wptr != rdev->ih.wptr)
3820 goto restart_ih;
3821 if (queue_hotplug)
3822 schedule_work(&rdev->hotplug_work);
3823 rdev->ih.rptr = rptr;
3824 WREG32(IH_RB_RPTR, rdev->ih.rptr);
3825 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3826 return IRQ_HANDLED;
3827 }
3828
3829 /*
3830 * startup/shutdown callbacks
3831 */
si_startup(struct radeon_device * rdev)3832 static int si_startup(struct radeon_device *rdev)
3833 {
3834 struct radeon_ring *ring;
3835 int r;
3836
3837 si_mc_program(rdev);
3838
3839 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
3840 !rdev->rlc_fw || !rdev->mc_fw) {
3841 r = si_init_microcode(rdev);
3842 if (r) {
3843 DRM_ERROR("Failed to load firmware!\n");
3844 return r;
3845 }
3846 }
3847
3848 r = si_mc_load_microcode(rdev);
3849 if (r) {
3850 DRM_ERROR("Failed to load MC firmware!\n");
3851 return r;
3852 }
3853
3854 r = r600_vram_scratch_init(rdev);
3855 if (r)
3856 return r;
3857
3858 r = si_pcie_gart_enable(rdev);
3859 if (r)
3860 return r;
3861 si_gpu_init(rdev);
3862
3863 #if 0
3864 r = evergreen_blit_init(rdev);
3865 if (r) {
3866 r600_blit_fini(rdev);
3867 rdev->asic->copy = NULL;
3868 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
3869 }
3870 #endif
3871 /* allocate rlc buffers */
3872 r = si_rlc_init(rdev);
3873 if (r) {
3874 DRM_ERROR("Failed to init rlc BOs!\n");
3875 return r;
3876 }
3877
3878 /* allocate wb buffer */
3879 r = radeon_wb_init(rdev);
3880 if (r)
3881 return r;
3882
3883 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3884 if (r) {
3885 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3886 return r;
3887 }
3888
3889 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
3890 if (r) {
3891 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3892 return r;
3893 }
3894
3895 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
3896 if (r) {
3897 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3898 return r;
3899 }
3900
3901 /* Enable IRQ */
3902 if (!rdev->irq.installed) {
3903 r = radeon_irq_kms_init(rdev);
3904 if (r)
3905 return r;
3906 }
3907
3908 r = si_irq_init(rdev);
3909 if (r) {
3910 DRM_ERROR("radeon: IH init failed (%d).\n", r);
3911 radeon_irq_kms_fini(rdev);
3912 return r;
3913 }
3914 si_irq_set(rdev);
3915
3916 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3917 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
3918 CP_RB0_RPTR, CP_RB0_WPTR,
3919 0, 0xfffff, RADEON_CP_PACKET2);
3920 if (r)
3921 return r;
3922
3923 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
3924 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET,
3925 CP_RB1_RPTR, CP_RB1_WPTR,
3926 0, 0xfffff, RADEON_CP_PACKET2);
3927 if (r)
3928 return r;
3929
3930 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
3931 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET,
3932 CP_RB2_RPTR, CP_RB2_WPTR,
3933 0, 0xfffff, RADEON_CP_PACKET2);
3934 if (r)
3935 return r;
3936
3937 r = si_cp_load_microcode(rdev);
3938 if (r)
3939 return r;
3940 r = si_cp_resume(rdev);
3941 if (r)
3942 return r;
3943
3944 r = radeon_ib_pool_start(rdev);
3945 if (r)
3946 return r;
3947
3948 r = radeon_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
3949 if (r) {
3950 DRM_ERROR("radeon: failed testing IB (%d) on CP ring 0\n", r);
3951 rdev->accel_working = false;
3952 return r;
3953 }
3954
3955 r = radeon_ib_test(rdev, CAYMAN_RING_TYPE_CP1_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]);
3956 if (r) {
3957 DRM_ERROR("radeon: failed testing IB (%d) on CP ring 1\n", r);
3958 rdev->accel_working = false;
3959 return r;
3960 }
3961
3962 r = radeon_ib_test(rdev, CAYMAN_RING_TYPE_CP2_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]);
3963 if (r) {
3964 DRM_ERROR("radeon: failed testing IB (%d) on CP ring 2\n", r);
3965 rdev->accel_working = false;
3966 return r;
3967 }
3968
3969 r = radeon_vm_manager_start(rdev);
3970 if (r)
3971 return r;
3972
3973 return 0;
3974 }
3975
si_resume(struct radeon_device * rdev)3976 int si_resume(struct radeon_device *rdev)
3977 {
3978 int r;
3979
3980 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
3981 * posting will perform necessary task to bring back GPU into good
3982 * shape.
3983 */
3984 /* post card */
3985 atom_asic_init(rdev->mode_info.atom_context);
3986
3987 rdev->accel_working = true;
3988 r = si_startup(rdev);
3989 if (r) {
3990 DRM_ERROR("si startup failed on resume\n");
3991 rdev->accel_working = false;
3992 return r;
3993 }
3994
3995 return r;
3996
3997 }
3998
si_suspend(struct radeon_device * rdev)3999 int si_suspend(struct radeon_device *rdev)
4000 {
4001 /* FIXME: we should wait for ring to be empty */
4002 radeon_ib_pool_suspend(rdev);
4003 radeon_vm_manager_suspend(rdev);
4004 #if 0
4005 r600_blit_suspend(rdev);
4006 #endif
4007 si_cp_enable(rdev, false);
4008 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
4009 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
4010 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
4011 si_irq_suspend(rdev);
4012 radeon_wb_disable(rdev);
4013 si_pcie_gart_disable(rdev);
4014 return 0;
4015 }
4016
4017 /* Plan is to move initialization in that function and use
4018 * helper function so that radeon_device_init pretty much
4019 * do nothing more than calling asic specific function. This
4020 * should also allow to remove a bunch of callback function
4021 * like vram_info.
4022 */
si_init(struct radeon_device * rdev)4023 int si_init(struct radeon_device *rdev)
4024 {
4025 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
4026 int r;
4027
4028 /* This don't do much */
4029 r = radeon_gem_init(rdev);
4030 if (r)
4031 return r;
4032 /* Read BIOS */
4033 if (!radeon_get_bios(rdev)) {
4034 if (ASIC_IS_AVIVO(rdev))
4035 return -EINVAL;
4036 }
4037 /* Must be an ATOMBIOS */
4038 if (!rdev->is_atom_bios) {
4039 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
4040 return -EINVAL;
4041 }
4042 r = radeon_atombios_init(rdev);
4043 if (r)
4044 return r;
4045
4046 /* Post card if necessary */
4047 if (!radeon_card_posted(rdev)) {
4048 if (!rdev->bios) {
4049 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
4050 return -EINVAL;
4051 }
4052 DRM_INFO("GPU not posted. posting now...\n");
4053 atom_asic_init(rdev->mode_info.atom_context);
4054 }
4055 /* Initialize scratch registers */
4056 si_scratch_init(rdev);
4057 /* Initialize surface registers */
4058 radeon_surface_init(rdev);
4059 /* Initialize clocks */
4060 radeon_get_clock_info(rdev->ddev);
4061
4062 /* Fence driver */
4063 r = radeon_fence_driver_init(rdev);
4064 if (r)
4065 return r;
4066
4067 /* initialize memory controller */
4068 r = si_mc_init(rdev);
4069 if (r)
4070 return r;
4071 /* Memory manager */
4072 r = radeon_bo_init(rdev);
4073 if (r)
4074 return r;
4075
4076 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
4077 ring->ring_obj = NULL;
4078 r600_ring_init(rdev, ring, 1024 * 1024);
4079
4080 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
4081 ring->ring_obj = NULL;
4082 r600_ring_init(rdev, ring, 1024 * 1024);
4083
4084 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
4085 ring->ring_obj = NULL;
4086 r600_ring_init(rdev, ring, 1024 * 1024);
4087
4088 rdev->ih.ring_obj = NULL;
4089 r600_ih_ring_init(rdev, 64 * 1024);
4090
4091 r = r600_pcie_gart_init(rdev);
4092 if (r)
4093 return r;
4094
4095 r = radeon_ib_pool_init(rdev);
4096 rdev->accel_working = true;
4097 if (r) {
4098 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
4099 rdev->accel_working = false;
4100 }
4101 r = radeon_vm_manager_init(rdev);
4102 if (r) {
4103 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
4104 }
4105
4106 r = si_startup(rdev);
4107 if (r) {
4108 dev_err(rdev->dev, "disabling GPU acceleration\n");
4109 si_cp_fini(rdev);
4110 si_irq_fini(rdev);
4111 si_rlc_fini(rdev);
4112 radeon_wb_fini(rdev);
4113 r100_ib_fini(rdev);
4114 radeon_vm_manager_fini(rdev);
4115 radeon_irq_kms_fini(rdev);
4116 si_pcie_gart_fini(rdev);
4117 rdev->accel_working = false;
4118 }
4119
4120 /* Don't start up if the MC ucode is missing.
4121 * The default clocks and voltages before the MC ucode
4122 * is loaded are not suffient for advanced operations.
4123 */
4124 if (!rdev->mc_fw) {
4125 DRM_ERROR("radeon: MC ucode required for NI+.\n");
4126 return -EINVAL;
4127 }
4128
4129 return 0;
4130 }
4131
si_fini(struct radeon_device * rdev)4132 void si_fini(struct radeon_device *rdev)
4133 {
4134 #if 0
4135 r600_blit_fini(rdev);
4136 #endif
4137 si_cp_fini(rdev);
4138 si_irq_fini(rdev);
4139 si_rlc_fini(rdev);
4140 radeon_wb_fini(rdev);
4141 radeon_vm_manager_fini(rdev);
4142 r100_ib_fini(rdev);
4143 radeon_irq_kms_fini(rdev);
4144 si_pcie_gart_fini(rdev);
4145 r600_vram_scratch_fini(rdev);
4146 radeon_gem_fini(rdev);
4147 radeon_semaphore_driver_fini(rdev);
4148 radeon_fence_driver_fini(rdev);
4149 radeon_bo_fini(rdev);
4150 radeon_atombios_fini(rdev);
4151 kfree(rdev->bios);
4152 rdev->bios = NULL;
4153 }
4154
4155