1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2/*
3 * IPQ5018 SoC device tree source
4 *
5 * Copyright (c) 2023 The Linux Foundation. All rights reserved.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/clock/qcom,gcc-ipq5018.h>
10#include <dt-bindings/reset/qcom,gcc-ipq5018.h>
11
12/ {
13	interrupt-parent = <&intc>;
14	#address-cells = <2>;
15	#size-cells = <2>;
16
17	clocks {
18		sleep_clk: sleep-clk {
19			compatible = "fixed-clock";
20			#clock-cells = <0>;
21		};
22
23		xo_board_clk: xo-board-clk {
24			compatible = "fixed-clock";
25			#clock-cells = <0>;
26		};
27	};
28
29	cpus {
30		#address-cells = <1>;
31		#size-cells = <0>;
32
33		CPU0: cpu@0 {
34			device_type = "cpu";
35			compatible = "arm,cortex-a53";
36			reg = <0x0>;
37			enable-method = "psci";
38			next-level-cache = <&L2_0>;
39		};
40
41		CPU1: cpu@1 {
42			device_type = "cpu";
43			compatible = "arm,cortex-a53";
44			reg = <0x1>;
45			enable-method = "psci";
46			next-level-cache = <&L2_0>;
47		};
48
49		L2_0: l2-cache {
50			compatible = "cache";
51			cache-level = <2>;
52			cache-size = <0x80000>;
53			cache-unified;
54		};
55	};
56
57	firmware {
58		scm {
59			compatible = "qcom,scm-ipq5018", "qcom,scm";
60		};
61	};
62
63	memory@40000000 {
64		device_type = "memory";
65		/* We expect the bootloader to fill in the size */
66		reg = <0x0 0x40000000 0x0 0x0>;
67	};
68
69	pmu {
70		compatible = "arm,cortex-a53-pmu";
71		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
72	};
73
74	psci {
75		compatible = "arm,psci-1.0";
76		method = "smc";
77	};
78
79	reserved-memory {
80		#address-cells = <2>;
81		#size-cells = <2>;
82		ranges;
83
84		tz_region: tz@4ac00000 {
85			reg = <0x0 0x4ac00000 0x0 0x200000>;
86			no-map;
87		};
88	};
89
90	soc: soc@0 {
91		compatible = "simple-bus";
92		#address-cells = <1>;
93		#size-cells = <1>;
94		ranges = <0 0 0 0xffffffff>;
95
96		tlmm: pinctrl@1000000 {
97			compatible = "qcom,ipq5018-tlmm";
98			reg = <0x01000000 0x300000>;
99			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
100			gpio-controller;
101			#gpio-cells = <2>;
102			gpio-ranges = <&tlmm 0 0 47>;
103			interrupt-controller;
104			#interrupt-cells = <2>;
105
106			uart1_pins: uart1-state {
107				pins = "gpio31", "gpio32", "gpio33", "gpio34";
108				function = "blsp1_uart1";
109				drive-strength = <8>;
110				bias-pull-down;
111			};
112		};
113
114		gcc: clock-controller@1800000 {
115			compatible = "qcom,gcc-ipq5018";
116			reg = <0x01800000 0x80000>;
117			clocks = <&xo_board_clk>,
118				 <&sleep_clk>,
119				 <0>,
120				 <0>,
121				 <0>,
122				 <0>,
123				 <0>,
124				 <0>,
125				 <0>;
126			#clock-cells = <1>;
127			#reset-cells = <1>;
128			#power-domain-cells = <1>;
129		};
130
131		sdhc_1: mmc@7804000 {
132			compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5";
133			reg = <0x7804000 0x1000>;
134			reg-names = "hc";
135
136			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
137				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
138			interrupt-names = "hc_irq", "pwr_irq";
139
140			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
141				 <&gcc GCC_SDCC1_APPS_CLK>,
142				 <&xo_board_clk>;
143			clock-names = "iface", "core", "xo";
144			non-removable;
145			status = "disabled";
146		};
147
148		blsp1_uart1: serial@78af000 {
149			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
150			reg = <0x078af000 0x200>;
151			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
152			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
153				 <&gcc GCC_BLSP1_AHB_CLK>;
154			clock-names = "core", "iface";
155			status = "disabled";
156		};
157
158		intc: interrupt-controller@b000000 {
159			compatible = "qcom,msm-qgic2";
160			reg = <0x0b000000 0x1000>,  /* GICD */
161			      <0x0b002000 0x2000>,  /* GICC */
162			      <0x0b001000 0x1000>,  /* GICH */
163			      <0x0b004000 0x2000>;  /* GICV */
164			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
165			interrupt-controller;
166			#interrupt-cells = <3>;
167			#address-cells = <1>;
168			#size-cells = <1>;
169			ranges = <0 0x0b00a000 0x1ffa>;
170
171			v2m0: v2m@0 {
172				compatible = "arm,gic-v2m-frame";
173				reg = <0x00000000 0xff8>;
174				msi-controller;
175			};
176
177			v2m1: v2m@1000 {
178				compatible = "arm,gic-v2m-frame";
179				reg = <0x00001000 0xff8>;
180				msi-controller;
181			};
182		};
183
184		timer@b120000 {
185			compatible = "arm,armv7-timer-mem";
186			reg = <0x0b120000 0x1000>;
187			#address-cells = <1>;
188			#size-cells = <1>;
189			ranges;
190
191			frame@b120000 {
192				reg = <0x0b121000 0x1000>,
193				      <0x0b122000 0x1000>;
194				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
195					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
196				frame-number = <0>;
197			};
198
199			frame@b123000 {
200				reg = <0xb123000 0x1000>;
201				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
202				frame-number = <1>;
203				status = "disabled";
204			};
205
206			frame@b124000 {
207				frame-number = <2>;
208				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
209				reg = <0x0b124000 0x1000>;
210				status = "disabled";
211			};
212
213			frame@b125000 {
214				reg = <0x0b125000 0x1000>;
215				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
216				frame-number = <3>;
217				status = "disabled";
218			};
219
220			frame@b126000 {
221				reg = <0x0b126000 0x1000>;
222				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
223				frame-number = <4>;
224				status = "disabled";
225			};
226
227			frame@b127000 {
228				reg = <0x0b127000 0x1000>;
229				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
230				frame-number = <5>;
231				status = "disabled";
232			};
233
234			frame@b128000 {
235				reg = <0x0b128000 0x1000>;
236				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
237				frame-number = <6>;
238				status = "disabled";
239			};
240		};
241	};
242
243	timer {
244		compatible = "arm,armv8-timer";
245		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
246			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
247			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
248			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
249	};
250};
251