1 /* -*- linux-c -*- */
2 /*
3 * Copyright (C) 2001 By Joachim Martillo, Telford Tools, Inc.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 *
10 **/
11
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/pci.h>
15 #include <linux/stddef.h>
16 #include <linux/string.h>
17 #include <linux/sockios.h>
18 #include <asm/io.h>
19 #include <asm/byteorder.h>
20 #include <asm/pgtable.h>
21 #include <linux/skbuff.h>
22 #include <linux/if_arp.h>
23 #include <linux/fs.h>
24 #include <linux/sched.h>
25 #include <asm/uaccess.h>
26 #include <linux/version.h>
27 #include <linux/etherdevice.h>
28 #include <linux/init.h>
29 #include "Reg9050.h"
30 #include "8253xctl.h"
31 #include "ring.h"
32 #include "8253x.h"
33 #include "crc32dcl.h"
34 #include "8253xmcs.h"
35 #include "sp502.h"
36
37 /* card names */
38
39 char *aura_functionality[] =
40 {
41 "NR",
42 "AO",
43 "NA",
44 "UN"
45 };
46
47 char *board_type[] =
48 {
49 "unknown",
50 "1020P",
51 "1520P",
52 "2020P",
53 "2520P",
54 "4020P",
55 "4520P",
56 "8020P",
57 "8520P",
58 "SUNSE",
59 "WANMS",
60 "1020C",
61 "1520C",
62 "2020C",
63 "2520C",
64 "4020C",
65 "4520C",
66 "8020C",
67 "8520C",
68 };
69
70 unsigned int sab8253x_rebootflag = 0;
71
72 AURAXX20PARAMS AuraXX20DriverParams; /* loaded at startup */
73 /* from variables below */
74 SAB_BOARD *AuraBoardRoot = NULL; /* The order of this list is not important */
75 SAB_CHIP *AuraChipRoot = NULL; /* chips grouped by board chip0 before chip1 */
76 SAB_PORT *AuraPortRoot = NULL; /* ports grouped by board and by chip, chip0, chip1, etc */
77 AURA_CIM *AuraCimRoot = NULL; /* only used for deallocating the cim structures, etc */
78 /* CIM stands for Communications Interface Module -- the G.Link logic provided by the Altera parts. */
79
80 /* Arrays of lists of boards of each type on a given interrupt */
81 SAB_BOARD *AuraBoardESCC2IrqRoot[NUMINTS];
82 SAB_BOARD *AuraBoardESCC8IrqRoot[NUMINTS];
83 SAB_BOARD *AuraBoardMCSIrqRoot[NUMINTS];
84
85 unsigned int NumSab8253xPorts = 0;
86
87 unsigned BD1020Pcounter = 0; /* keep count of each board */
88 unsigned BD1520Pcounter = 0; /* may change to just keeping count */
89 unsigned BD2020Pcounter = 0; /* of the total number of boards */
90 unsigned BD2520Pcounter = 0;
91 unsigned BD4020Pcounter = 0;
92 unsigned BD4520Pcounter = 0;
93 unsigned BD8020Pcounter = 0;
94 unsigned BD8520Pcounter = 0;
95
96 unsigned BD1020CPcounter = 0; /* keep count of each board */
97 unsigned BD1520CPcounter = 0; /* may change to just keeping count */
98 unsigned BD2020CPcounter = 0; /* of the total number of boards */
99 unsigned BD2520CPcounter = 0;
100 unsigned BD4020CPcounter = 0;
101 unsigned BD4520CPcounter = 0;
102 unsigned BD8020CPcounter = 0;
103 unsigned BD8520CPcounter = 0;
104
105 unsigned BDMCScounter = 0;
106
107
108 static int auraXX20n_debug = 0; /* turns on lots of */
109 /* debugging messages*/
110 static char* auraXX20n_name = 0;/* set net dev name on command line */
111 static char *sab8253xc_name = "sab8253xc";
112 static int sab8253xc_major = 0;
113 int sab8253xn_listsize = 32; /* recommend descriptor list size */
114 int sab8253xn_rbufsize = RXSIZE; /* recommend rbuf list size */
115 int sab8253xt_listsize = 256; /* recommend descriptor list size */
116 int sab8253xt_rbufsize = 32; /* recommend rbuf list size for tty */
117 int sab8253xs_listsize = 64; /* recommend descriptor list size */
118 int sab8253xs_rbufsize = RXSIZE; /* recommend rbuf list size */
119 int sab8253xc_listsize = 64; /* recommend descriptor list size */
120 int sab8253xc_rbufsize = RXSIZE; /* recommend rbuf list size for tty */
121 int xx20_minorstart = 128;
122 int sab8253x_vendor_id = PCI_VENDOR_ID_AURORATECH;
123 int sab8253x_cpci_device_id = PCI_DEVICE_ID_AURORATECH_CPCI;
124 int sab8253x_wmcs_device_id = PCI_DEVICE_ID_AURORATECH_WANMS;
125 int sab8253x_mpac_device_id = PCI_DEVICE_ID_AURORATECH_MULTI;
126 int sab8253x_default_sp502_mode = SP502_RS232_MODE;
127
128 MODULE_PARM(sab8253x_vendor_id, "i");
129 MODULE_PARM(sab8253x_cpci_device_id, "i");
130 MODULE_PARM(sab8253x_wmcs_device_id, "i");
131 MODULE_PARM(sab8253x_mpac_device_id, "i");
132 MODULE_PARM(sab8253x_default_sp502_mode, "i");
133
134 MODULE_PARM(xx20_minorstart, "i");
135 MODULE_PARM(sab8253xc_major, "i");
136 MODULE_PARM(auraXX20n_debug, "i");
137 MODULE_PARM(auraXX20n_name, "s"); /* this and the following for sync */
138 MODULE_PARM(sab8253xn_listsize, "i"); /* network driver */
139 MODULE_PARM(sab8253xn_rbufsize, "i"); /* network driver */
140 MODULE_PARM(sab8253xt_listsize, "i"); /* tty driver */
141 MODULE_PARM(sab8253xt_rbufsize, "i"); /* tty driver */
142 MODULE_PARM(sab8253xc_listsize, "i"); /* network driver */
143 MODULE_PARM(sab8253xc_rbufsize, "i"); /* network driver */
144 MODULE_PARM(sab8253xs_listsize, "i"); /* tty driver */
145 MODULE_PARM(sab8253xs_rbufsize, "i"); /* tty driver */
146 MODULE_PARM(sab8253xc_name, "s");
147
148 struct pci_dev *XX20lastpdev = NULL; /* just used for finding all PCI devices */
149 static SAB_BOARD *find_ati_multiport_card(void); /* actually implemented */
150 static SAB_BOARD *find_ati_cpci_card(void); /* to be done */
151 static SAB_BOARD *find_ati_wanms_card(void); /* to be done */
152
153 #if (!defined(MODULE)) && (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 0))
154 /* unpleasantness for 2.2 kernels
155 * and probe illogic */
156
157 /* The LRP project is still working on
158 2.2.* kernels but I suspect
159 that initially we will see more
160 purchases for complete Linux
161 machines using 2.4.*, LRP
162 machines tend to be underpowered
163 and have a paucity of PCI slots
164 */
165
166 unsigned int do_probe = 1;
167 #endif
168
169 /* One could argue that these could be in */
170 /* the 8253xnet.c file but they are fairly */
171 /* intimately involved with initialization.*/
172 struct net_device *Sab8253xRoot = NULL;
173
174 struct net_device auraXX20n_prototype = /* used for the network device */
175 {
176 "8253x0",
177 0, 0, 0, 0,
178 0x000,
179 -1, /* bad irq */
180 0, 0, 0,
181 NULL,
182 sab8253xn_init /* network driver initialization */
183 };
184
185 struct file_operations sab8253xc_fops =
186 {
187 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 4, 0))
188 NULL,
189 #endif
190 NULL, /* llseek */
191 sab8253xc_read, /* read */
192 sab8253xc_write, /* write */
193 NULL, /* readdir */
194 sab8253xc_poll, /* poll */
195 sab8253xc_ioctl, /* ioctl */
196 NULL, /* mmap */
197 sab8253xc_open, /* open */
198 NULL, /* flush */
199 sab8253xc_release, /* release */
200 NULL, /* fsync */
201 sab8253xc_fasync, /* fasync */
202 NULL, /* check_media_change */
203 NULL, /* revalidate */
204 NULL /* lock */
205 };
206
207
208 /* A few function defined in this file */
209 /* These functions are basically functionality */
210 /* independent -- they are used with asynchronous ttys */
211 /* synchronous ttys, the network device and the */
212 /* raw character device */
213
214 /* used for reading and writing ports
215 readw and writew require some reprogramming
216 of the PLX9050
217 */
218 static unsigned char aura_readb(struct sab_port *port, unsigned char *reg);
219 static unsigned char wmsaura_readb(struct sab_port *port, unsigned char *reg);
220 static unsigned short aura_readw(struct sab_port *port, unsigned short *reg);
221 static unsigned short wmsaura_readw(struct sab_port *port, unsigned short *reg);
222 static void aura_writeb(struct sab_port *port, unsigned char *reg,unsigned char val);
223 static void wmsaura_writeb(struct sab_port *port, unsigned char *reg,unsigned char val);
224 static void aura_writew(struct sab_port *port, unsigned short *reg,unsigned short val);
225 static void wmsaura_writew(struct sab_port *port, unsigned short *reg,unsigned short val);
226
227 static void aura_readfifo(struct sab_port *port, unsigned char *buf, unsigned int nbytes);
228 static void aura_writefifo(struct sab_port *port);
229
230 static void wmsaura_readfifo(struct sab_port *port, unsigned char *buf, unsigned int nbytes);
231 static void wmsaura_writefifo(struct sab_port *port);
232
233 /* function definitions */
234
235 /* [124]X20 type cards */
DisableESCC2Interrupts(SAB_CHIP * chipptr)236 static void DisableESCC2Interrupts(SAB_CHIP *chipptr) /* in processing ports may have to disable ints */
237 {
238 struct sab82532_async_wr_regs *regs;
239
240 regs = chipptr->c_regs;
241 writeb(0xff,®s->pim); /* All interrupts off */
242 /* Note that regs/->c_regs
243 is set to base reg
244 address, thus taking
245 address or regs->pim
246 gets the address of
247 the PIM register/int mask */
248 }
249
CreateESCC2(SAB_BOARD * bptr,unsigned int offset)250 static SAB_CHIP* CreateESCC2(SAB_BOARD *bptr, unsigned int offset)
251 {
252 SAB_CHIP *cptr;
253 struct sab82532_async_wr_regs *regs;
254
255 printk(KERN_ALERT
256 "auraXX20n: creating ESCC2 structure on board %p at offset %x.\n",
257 bptr, offset);
258
259 cptr = (SAB_CHIP*) kmalloc(sizeof(SAB_CHIP), GFP_KERNEL);
260 if(cptr == NULL)
261 {
262 printk(KERN_ALERT
263 "auraXX20n: Failed to create ESCC2 structure on board %p at offset %x.\n",
264 bptr, offset);
265 return NULL;
266 }
267 memset(cptr, 0, sizeof(SAB_CHIP));
268 cptr->chip_type = ESCC2;
269 cptr->c_board = bptr;
270 cptr->c_cim = NULL;
271 cptr->c_chipno = (offset ? 1 : 0); /* first or second chip on board */
272 cptr->c_revision =
273 (readb(((char *)bptr->virtbaseaddress2) + offset + SAB85232_REG_VSTR) &
274 SAB82532_VSTR_VN_MASK);
275 cptr->c_nports = 2;
276 cptr->c_portbase = NULL;
277 cptr->next = AuraChipRoot; /* chips are added to chiplist in reverse order */
278 AuraChipRoot = cptr;
279 cptr->next_by_board = bptr->board_chipbase; /* likewise for the local board chiplist */
280 bptr->board_chipbase = cptr;
281 printk(KERN_ALERT "auraXX20n: chip %d on board %p is revision %d.\n",
282 cptr->c_chipno, bptr, cptr->c_revision);
283
284 /* lets set up the generic parallel
285 * port register which is used to
286 * control signaling and other stuff*/
287 /*
288 * SAB82532 (Aurora) 1 8-bit parallel port
289 * To summarize the use of the parallel port:
290 * RS-232
291 * A B I/O descr
292 * P0 P4 output TxClk ctrl
293 * P1 P5 output DTR
294 * P2 P6 input DSR
295 * P3 P7 output 485 control
296 *
297 */
298 /*
299 * Configuring the parallel port
300 */
301
302 regs = (struct sab82532_async_wr_regs *)(((char *)bptr->virtbaseaddress2) + offset);
303
304 DEBUGPRINT((KERN_ALERT "Writing 0x44 to 0x%p + 0x%x for chip %d\n",
305 regs, SAB82532_REG_PCR, cptr->c_chipno));
306
307 writeb(0x44,®s->pcr); /* 2 input bits */
308 writeb(0xff,®s->pim);/* All interrupts off */
309 writeb(0x33,®s->pvr); /* Txclk and DTR low */
310
311 cptr->c_regs = (void*) regs;
312 cptr->int_disable = DisableESCC2Interrupts;
313 return cptr;
314 }
315
CreateESCC2Port(SAB_CHIP * cptr,unsigned int portno,unsigned int function)316 static void CreateESCC2Port(SAB_CHIP *cptr, unsigned int portno, unsigned int function)
317 {
318 SAB_BOARD *bptr;
319 SAB_PORT *pptr;
320 extern void sab8253x_setup_ttyport(struct sab_port *p_port) ;
321
322 ++NumSab8253xPorts;
323 bptr = cptr->c_board;
324 pptr = (SAB_PORT*) kmalloc(sizeof(SAB_PORT), GFP_KERNEL);
325 if(pptr == NULL)
326 {
327 printk(KERN_ALERT
328 "auraXX20n: Failed to create ESCC2 port structure on chip %p on board %p.\n",
329 cptr, bptr);
330 return;
331 }
332 memset(pptr, 0, sizeof(SAB_PORT));
333 DEBUGPRINT
334 ((KERN_ALERT "Setting up port %d, chipno %d for %s type board number %d.\n",
335 portno, cptr->c_chipno, board_type[bptr->b_type],bptr->board_number));
336 pptr->portno = portno;
337 pptr->chip=cptr;
338 pptr->board=bptr;
339 pptr->open_type=OPEN_NOT;
340 pptr->is_console=0;
341 pptr->regs=
342 (union sab82532_regs *)
343 (((unsigned int)cptr->c_regs) +
344 (portno * SAB82532_REG_SIZE));
345 pptr->type = cptr->c_revision;
346 pptr->function = function;
347
348 /* Simpify reading */
349 #define PVR pptr->regs->async_write.pvr
350 #define PCR pptr->regs->async_write.pcr
351 #define PIM pptr->regs->async_write.pim
352 #define ISR0 pptr->regs->async_read.isr0
353 #define IMR0 pptr->regs->async_write.imr0
354 #define IMR1 pptr->regs->async_write.imr1
355 #define PIS pptr->regs->async_read.pis
356 #define VSTR pptr->regs->async_read.vstr
357 #define STAR pptr->regs->async_read.star
358 #define MODE pptr->regs->async_read.mode
359
360 pptr->irq = bptr->b_irq;
361 if(portno == 0)
362 { /* Port A .... */
363 pptr->dsr.reg=(unsigned char *)&(PVR);
364 pptr->dsr.mask=0x04;
365 pptr->dsr.irq=PIS_IDX;
366 pptr->dsr.irqmask=0x04;
367
368 pptr->dtr.reg=(unsigned char *)&(PVR);
369 pptr->dtr.mask=0x02;
370
371 pptr->txclkdir.reg=(unsigned char *)&(PVR);
372 pptr->txclkdir.mask=0x01;
373 }
374 else
375 { /* Port B */
376 pptr->dsr.reg=(unsigned char *)&(PVR);
377 pptr->dsr.mask=0x40;
378 pptr->dsr.irq=PIS_IDX;
379 pptr->dsr.irqmask=0x40;
380
381 pptr->dtr.reg=(unsigned char *)&(PVR);
382 pptr->dtr.mask=0x20;
383
384 pptr->txclkdir.reg=(unsigned char *)&(PVR);
385 pptr->txclkdir.mask=0x10;
386 }
387 pptr->dsr.inverted=1;
388 pptr->dsr.cnst = 0;
389 pptr->dtr.inverted=1;
390 pptr->dtr.cnst = 0;
391 pptr->txclkdir.inverted=1;
392
393 pptr ->dcd.reg =(unsigned char *) &(VSTR);
394
395 DEBUGPRINT((KERN_ALERT "cd register set to 0x%p\n", pptr ->dcd.reg));
396
397 pptr->dcd.mask = SAB82532_VSTR_CD;
398 pptr->dcd.inverted = 1;
399 pptr->dcd.irq=ISR0_IDX;
400 pptr->dcd.irqmask=SAB82532_ISR0_CDSC;
401 pptr->dcd.cnst = 0;
402
403 pptr->cts.reg = (unsigned char *)&(STAR);
404 pptr->cts.mask = SAB82532_STAR_CTS;
405 pptr->cts.inverted = 0;
406 pptr->cts.irq=ISR1_IDX;
407 pptr->cts.irqmask=SAB82532_ISR1_CSC;
408 pptr->cts.cnst = 0;
409
410 pptr->rts.reg = (unsigned char *)&(MODE);
411 pptr->rts.mask = SAB82532_MODE_FRTS;
412 pptr->rts.inverted = 1;
413 pptr->rts.cnst = SAB82532_MODE_RTS;
414
415
416 /* Set the read and write function */
417 pptr->readbyte=aura_readb;
418 pptr->readword=aura_readw;
419 pptr->writebyte=aura_writeb;
420 pptr->writeword=aura_writew;
421 pptr->readfifo=aura_readfifo;
422 pptr->writefifo=aura_writefifo;
423
424 sab8253x_setup_ttyport(pptr); /* asynchronous */
425 /* ttys are default, basic */
426 /* initialization, everything */
427 /* else works as a modification */
428 /* thereof */
429
430 pptr->next = AuraPortRoot;
431 AuraPortRoot = pptr;
432 pptr->next_by_chip = cptr->c_portbase;
433 cptr->c_portbase = pptr;
434 pptr->next_by_board = bptr->board_portbase;
435 bptr->board_portbase = pptr;
436 }
437
438 /* 8x20 type functions */
439
DisableESCC8Interrupts(SAB_CHIP * chipptr)440 static void DisableESCC8Interrupts(SAB_CHIP *chipptr)
441 {
442 unsigned int regbase; /* a lot more to do for ESCC8 */
443
444 regbase = (unsigned int) chipptr->c_regs;
445 writeb(0xff,((unsigned char *)regbase) + SAB82538_REG_PIM_A); /* All interrupts off */
446 writeb(0xff,((unsigned char *)regbase) + SAB82538_REG_PIM_B); /* All interrupts off */
447 writeb(0xff,((unsigned char *)regbase) + SAB82538_REG_PIM_C); /* All interrupts off */
448 writeb(0xff,((unsigned char *)regbase) + SAB82538_REG_PIM_D); /* All interrupts off */
449 }
450
CreateESCC8(SAB_BOARD * bptr,unsigned int offset)451 static SAB_CHIP* CreateESCC8(SAB_BOARD *bptr, unsigned int offset)
452 {
453 SAB_CHIP *cptr;
454 unsigned int regbase;
455
456 printk(KERN_ALERT
457 "auraXX20n: creating ESCC8 structure on board %p at offset %x.\n",
458 bptr, offset);
459
460 cptr = (SAB_CHIP*) kmalloc(sizeof(SAB_CHIP), GFP_KERNEL);
461 if(cptr == NULL)
462 {
463 printk(KERN_ALERT
464 "auraXX20n: Failed to create ESCC8 structure on board %p at offset %x.\n",
465 bptr, offset);
466 return NULL;
467 }
468 memset(cptr, 0, sizeof(SAB_CHIP));
469 cptr->chip_type = ESCC8;
470 cptr->c_board = bptr;
471 cptr->c_cim = NULL;
472 cptr->c_chipno = (offset ? 1 : 0); /* no card actually has 2 ESCC8s on it */
473 cptr->c_revision =
474 (readb(((char *)bptr->virtbaseaddress2) + offset + SAB85232_REG_VSTR) &
475 SAB82532_VSTR_VN_MASK);
476 cptr->c_nports = 8;
477 cptr->c_portbase = NULL; /* used for the list of ports associated
478 with this chip
479 */
480 cptr->next = AuraChipRoot;
481 AuraChipRoot = cptr;
482 cptr->next_by_board = bptr->board_chipbase;
483 bptr->board_chipbase = cptr;
484 printk(KERN_ALERT "auraXX20n: chip %d on board %p is revision %d.\n",
485 cptr->c_chipno, bptr, cptr->c_revision);
486
487 /* lets set up the generic parallel
488 * port register which is used to
489 * control signaling and other stuff*/
490
491 /* SAB82538 4 8-bits parallel ports
492 * To summarize the use of the parallel port:
493 * RS-232
494 * Parallel port A -- TxClkdir control (output) ports 0 - 7
495 * Parallel port B -- DTR (output) ports 0 - 7
496 * Parallel port C -- DSR (input) ports 0 - 7
497 * Parallel port D -- driver power down (output) drivers 0 - 3
498 *
499 * Note port D is not used on recent boards
500 */
501
502 regbase = (unsigned int)(((char *)bptr->virtbaseaddress2) + offset);
503
504 DEBUGPRINT((KERN_ALERT "Setting up parallel port A (0x%x), 0x%x, 0x%x, 0x%x\n", regbase,
505 SAB82538_REG_PCR_A, SAB82538_REG_PIM_A, SAB82538_REG_PVR_A));
506
507 /* Configuring Parallel Port A (Clkdir)*/
508 writeb(0x0,((unsigned char *)regbase) + SAB82538_REG_PCR_A); /* All output bits */
509 writeb(0xff,((unsigned char *)regbase) + SAB82538_REG_PIM_A); /* All interrupts off */
510 writeb(0xff,((unsigned char *)regbase) + SAB82538_REG_PVR_A); /* All low */
511
512 DEBUGPRINT((KERN_ALERT "Setting up parallel port B (0x%x), 0x%x, 0x%x, 0x%x\n", regbase,
513 SAB82538_REG_PCR_B,SAB82538_REG_PIM_B,SAB82538_REG_PVR_B));
514
515 writeb(0x0,((unsigned char *)regbase) + SAB82538_REG_PCR_B); /* All output bits */
516 writeb(0xff,((unsigned char *)regbase) + SAB82538_REG_PIM_B); /* All interrupts off */
517 writeb(0xff,((unsigned char *)regbase) + SAB82538_REG_PVR_B); /* All low */
518
519 DEBUGPRINT((KERN_ALERT "Setting up parallel port C (0x%x), 0x%x, 0x%x, 0x%x\n", regbase,
520 SAB82538_REG_PCR_C, SAB82538_REG_PIM_C, SAB82538_REG_PVR_C));
521
522 writeb(0xff,((unsigned char *)regbase) + SAB82538_REG_PCR_C); /* All intput bits */
523 writeb(0xff,((unsigned char *)regbase) + SAB82538_REG_PIM_C); /* All interrupts off */
524 /* don't set port value register on input register */
525
526 /* Configuring Parallel Port D */
527
528 DEBUGPRINT((KERN_ALERT "Setting up parallel port D (0x%x), 0x%x, 0x%x, 0x%x\n", regbase,
529 SAB82538_REG_PCR_D, SAB82538_REG_PIM_D, SAB82538_REG_PVR_D));
530 writeb(0x0f,((unsigned char *)regbase) + SAB82538_REG_PCR_D); /* 4 input bits */
531 writeb(0xff,((unsigned char *)regbase) + SAB82538_REG_PIM_D); /* All interrupts off */
532 /* don't set port value register on input register */
533
534 /* The priority rotation thing */
535
536 DEBUGPRINT((KERN_ALERT "Setting IVA (0x%x + 0x%x = 0x%x\n", regbase,
537 SAB82532_REG_IVA, regbase + SAB82532_REG_IVA));
538
539 writeb(SAB82538_IVA_ROT, ((unsigned char *)regbase) + SAB82532_REG_IVA);
540
541 cptr->c_regs = (void*) regbase;
542 cptr->int_disable = DisableESCC8Interrupts;
543 return cptr;
544 }
545
DisableESCC8InterruptsFromCIM(SAB_CHIP * chipptr)546 static void DisableESCC8InterruptsFromCIM(SAB_CHIP *chipptr)
547 {
548 unsigned int regbase; /* a lot more to do for ESCC8 */
549
550 regbase = (unsigned int) chipptr->c_regs;
551 writeb(0xff,((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82538_REG_PIM_A)); /* All interrupts off */
552 writeb(0xff,((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82538_REG_PIM_B)); /* All interrupts off */
553 writeb(0xff,((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82538_REG_PIM_C)); /* All interrupts off */
554 writeb(0xff,((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82538_REG_PIM_D)); /* All interrupts off */
555 }
556
CreateESCC8Port(SAB_CHIP * cptr,unsigned int portno,unsigned int function)557 static void CreateESCC8Port(SAB_CHIP *cptr, unsigned int portno, unsigned int function)
558 {
559 SAB_BOARD *bptr;
560 SAB_PORT *pptr;
561 extern void sab8253x_setup_ttyport(struct sab_port *p_port) ;
562
563 ++NumSab8253xPorts;
564 bptr = cptr->c_board;
565 pptr = (SAB_PORT*) kmalloc(sizeof(SAB_PORT), GFP_KERNEL);
566 if(pptr == NULL)
567 {
568 printk(KERN_ALERT
569 "auraXX20n: Failed to create ESCC2 port structure on chip %p on board %p.\n",
570 cptr, bptr);
571 return;
572 }
573 memset(pptr, 0, sizeof(SAB_PORT));
574 DEBUGPRINT
575 ((KERN_ALERT "Setting up port %d, chipno %d for %s type board number %d.\n",
576 portno, cptr->c_chipno, board_type[bptr->b_type],bptr->board_number));
577 pptr->portno = portno;
578 pptr->chip=cptr;
579 pptr->board=bptr;
580 pptr->open_type=OPEN_NOT;
581 pptr->is_console=0;
582 pptr->regs=
583 (union sab82532_regs *)
584 (((unsigned int)cptr->c_regs) +
585 (portno * SAB82538_REG_SIZE));
586 pptr->type = cptr->c_revision;
587 pptr->function = function;
588
589 pptr->irq = bptr->b_irq;
590
591 pptr->dsr.reg = ((unsigned char *)cptr->c_regs) + SAB82538_REG_PVR_C;
592 pptr->dsr.mask = 0x1 << portno;
593 pptr->dsr.inverted = 1;
594 pptr->dsr.irq=PIS_IDX; /* need to check this constant */
595 pptr->dsr.irqmask=0x1 << portno;
596 pptr->dsr.cnst = 0;
597
598 pptr->txclkdir.reg = ((unsigned char *)cptr->c_regs) + SAB82538_REG_PVR_A;
599 pptr->txclkdir.mask = 0x1 << portno;
600 /* NOTE: Early 8 ports boards had different tx clkdir sense */
601 pptr->txclkdir.inverted = 1;
602
603 pptr->dtr.reg = ((unsigned char *)cptr->c_regs) + SAB82538_REG_PVR_B;
604 pptr->dtr.mask = 0x1 << portno;
605 pptr->dtr.inverted = 1;
606 pptr->dtr.cnst = 0;
607
608 pptr ->dcd.reg = (unsigned char *)&(VSTR);
609
610 DEBUGPRINT((KERN_ALERT "cd register set to 0x%p\n", pptr ->dcd.reg));
611
612 pptr->dcd.mask = SAB82532_VSTR_CD;
613 pptr->dcd.inverted = 1;
614 pptr->dcd.irq=ISR0_IDX;
615 pptr->dcd.irqmask=SAB82532_ISR0_CDSC;
616 pptr->dcd.cnst = 0;
617
618 pptr->cts.reg = (unsigned char *)&(STAR);
619 pptr->cts.mask = SAB82532_STAR_CTS;
620 pptr->cts.inverted = 0;
621 pptr->cts.irq=ISR1_IDX;
622 pptr->cts.irqmask=SAB82532_ISR1_CSC;
623 pptr->cts.cnst = 0;
624
625 pptr->rts.reg = (unsigned char *)&(MODE);
626 pptr->rts.mask = SAB82532_MODE_FRTS;
627 pptr->rts.inverted = 1;
628 pptr->rts.cnst = SAB82532_MODE_RTS;
629
630
631 /* Set the read and write function */
632 pptr->readbyte=aura_readb;
633 pptr->readword=aura_readw;
634 pptr->writebyte=aura_writeb;
635 pptr->writeword=aura_writew;
636 pptr->readfifo=aura_readfifo;
637 pptr->writefifo=aura_writefifo;
638
639 sab8253x_setup_ttyport(pptr); /* asynchronous */
640 /* ttys are default, basic */
641 /* initialization, everything */
642 /* else works as a modification */
643 /* thereof */
644
645 pptr->next = AuraPortRoot;
646 AuraPortRoot = pptr;
647 pptr->next_by_chip = cptr->c_portbase;
648 cptr->c_portbase = pptr;
649 pptr->next_by_board = bptr->board_portbase;
650 bptr->board_portbase = pptr;
651 }
652
653 /* Multichannel server functions */
654
CreateESCC8fromCIM(SAB_BOARD * bptr,AURA_CIM * cim,unsigned int chipno)655 static SAB_CHIP* CreateESCC8fromCIM(SAB_BOARD *bptr, AURA_CIM *cim, unsigned int chipno)
656 {
657 SAB_CHIP *cptr;
658 unsigned int regbase;
659
660 printk(KERN_ALERT
661 "auraXX20n: creating ESCC8 %d structure on board %p from cim %p.\n",
662 chipno, bptr, cim);
663
664 cptr = (SAB_CHIP*) kmalloc(sizeof(SAB_CHIP), GFP_KERNEL);
665 if(cptr == NULL)
666 {
667 printk(KERN_ALERT
668 "auraXX20n: Failed to create ESCC8 structure %d on board %p at from cim %p.\n",
669 chipno, bptr, cim);
670 return NULL;
671 }
672
673 memset(cptr, 0, sizeof(SAB_CHIP));
674 cptr->chip_type = ESCC8;
675 cptr->c_board = bptr;
676 cptr->c_cim = cim;
677 cptr->c_chipno = chipno;
678 cptr->c_revision =
679 (readb((unsigned char *) (bptr->CIMCMD_REG +
680 (CIMCMD_RDREGB | (((chipno*8) << 6) | SAB85232_REG_VSTR))))
681 & SAB82532_VSTR_VN_MASK);
682 cptr->c_nports = 8;
683 cptr->c_portbase = NULL; /* used for the list of ports associated
684 with this chip
685 */
686 cptr->next = AuraChipRoot;
687 AuraChipRoot = cptr;
688 cptr->next_by_board = bptr->board_chipbase;
689 bptr->board_chipbase = cptr;
690
691 cptr->next_by_cim = cim->ci_chipbase;
692 cim->ci_chipbase = cptr;
693
694 printk(KERN_ALERT "auraXX20n: chip %d on board %p is revision %d.\n",
695 cptr->c_chipno, bptr, cptr->c_revision);
696
697 /* lets set up the generic parallel
698 * port register which is used to
699 * control signaling and other stuff*/
700
701 /* SAB82538 4 8-bits parallel ports
702 * To summarize the use of the parallel port:
703 * RS-232
704 * Parallel port A -- TxClkdir control (output) ports 0 - 7
705 * Parallel port B -- DTR (output) ports 0 - 7
706 * Parallel port C -- DSR (input) ports 0 - 7
707 * Parallel port D -- driver power down (output) drivers 0 - 3
708 *
709 * Note port D is not used on recent boards
710 */
711
712 regbase = (unsigned int)
713 (bptr->CIMCMD_REG + (0 | (((chipno*8) << 6) | 0))); /* need to add in RDB/WRB cmd bits
714 * and reg offset (> 32) */
715
716 DEBUGPRINT((KERN_ALERT "Setting up parallel port A (0x%x), 0x%x, 0x%x, 0x%x\n", regbase,
717 SAB82538_REG_PCR_A, SAB82538_REG_PIM_A, SAB82538_REG_PVR_A));
718
719 /* Configuring Parallel Port A (Clkdir)*/
720 writeb(0x00,((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82538_REG_PCR_A)); /* All output bits */
721 writeb(0xff,((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82538_REG_PIM_A)); /* All interrupts off */
722 writeb(0xff,((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82538_REG_PVR_A)); /* All low */
723
724 DEBUGPRINT((KERN_ALERT "Setting up parallel port B (0x%x), 0x%x, 0x%x, 0x%x\n", regbase,
725 SAB82538_REG_PCR_B,SAB82538_REG_PIM_B,SAB82538_REG_PVR_B));
726
727 writeb(0x00,((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82538_REG_PCR_B)); /* All output bits */
728 writeb(0xff,((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82538_REG_PIM_B)); /* All interrupts off */
729 writeb(0xff,((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82538_REG_PVR_B)); /* All low */
730
731 DEBUGPRINT((KERN_ALERT "Setting up parallel port C (0x%x), 0x%x, 0x%x, 0x%x\n", regbase,
732 SAB82538_REG_PCR_C, SAB82538_REG_PIM_C, SAB82538_REG_PVR_C));
733
734 writeb(0xff,((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82538_REG_PCR_C)); /* All intput bits */
735 writeb(0xff,((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82538_REG_PIM_C)); /* All interrupts off */
736 /* don't set port value register on input register */
737
738 /* Configuring Parallel Port D */
739
740 DEBUGPRINT((KERN_ALERT "Setting up parallel port D (0x%x), 0x%x, 0x%x, 0x%x\n", regbase,
741 SAB82538_REG_PCR_D, SAB82538_REG_PIM_D, SAB82538_REG_PVR_D));
742 writeb(0x0f,((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82538_REG_PCR_D)); /* 4 input bits */
743 writeb(0xff,((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82538_REG_PIM_D)); /* All interrupts off */
744 /* don't set port value register on input register */
745
746 /* The priority rotation thing */
747
748 DEBUGPRINT((KERN_ALERT "Setting IVA (0x%x + 0x%x = 0x%x\n", regbase,
749 SAB82532_REG_IVA, regbase + SAB82532_REG_IVA));
750
751 writeb(SAB82538_IVA_ROT, ((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82532_REG_IVA));
752 writeb(0, ((unsigned char *)regbase) + (CIMCMD_WRREGB | SAB82532_REG_IPC));
753
754 cptr->c_regs = (void*) regbase;
755 cptr->int_disable = DisableESCC8InterruptsFromCIM;
756 return cptr;
757 }
758
CreateESCC8PortWithCIM(SAB_CHIP * cptr,unsigned int portno,AURA_CIM * cim,unsigned flag)759 static void CreateESCC8PortWithCIM(SAB_CHIP *cptr, unsigned int portno,
760 AURA_CIM *cim, unsigned flag)
761 {
762 SAB_BOARD *bptr;
763 SAB_PORT *pptr;
764 extern void sab8253x_setup_ttyport(struct sab_port *p_port) ;
765
766 ++NumSab8253xPorts;
767 bptr = cptr->c_board;
768 pptr = (SAB_PORT*) kmalloc(sizeof(SAB_PORT), GFP_KERNEL);
769 if(pptr == NULL)
770 {
771 printk(KERN_ALERT
772 "auraXX20n: Failed to create ESCC2 port structure on chip %p on board %p.\n",
773 cptr, bptr);
774 return;
775 }
776 memset(pptr, 0, sizeof(SAB_PORT));
777 DEBUGPRINT
778 ((KERN_ALERT "Setting up port %d, chipno %d for %s type board number %d.\n",
779 portno, cptr->c_chipno, board_type[bptr->b_type],bptr->board_number));
780 pptr->portno = portno;
781 pptr->chip=cptr;
782 pptr->board=bptr;
783 pptr->open_type=OPEN_NOT;
784 pptr->is_console=0;
785 pptr->regs=
786 (union sab82532_regs *)
787 (((unsigned int)cptr->c_regs) +
788 (portno << 6)); /* addressing is different when there is a cim */
789 pptr->type = cptr->c_revision;
790 pptr->function = (((cim->ci_flags & CIM_SYNC) || flag) ? FUNCTION_NR :
791 FUNCTION_AO);
792
793 pptr->irq = bptr->b_irq;
794
795 pptr->dsr.reg = ((unsigned char *)cptr->c_regs) + SAB82538_REG_PVR_C;
796 pptr->dsr.mask = 0x1 << portno;
797 pptr->dsr.inverted = 1;
798 pptr->dsr.irq=PIS_IDX; /* need to check this constant */
799 pptr->dsr.irqmask=0x1 << portno;
800 pptr->dsr.cnst = 0;
801
802 pptr->txclkdir.reg = ((unsigned char *)cptr->c_regs) + SAB82538_REG_PVR_A;
803 pptr->txclkdir.mask = 0x1 << portno;
804 /* NOTE: Early 8 ports boards had different tx clkdir sense */
805 pptr->txclkdir.inverted = 1;
806
807 pptr->dtr.reg = ((unsigned char *)cptr->c_regs) + SAB82538_REG_PVR_B;
808 pptr->dtr.mask = 0x1 << portno;
809 pptr->dtr.inverted = 1;
810 pptr->dtr.cnst = 0;
811
812 pptr->dcd.reg = ((unsigned char *)pptr->regs) + SAB85232_REG_VSTR;
813
814 DEBUGPRINT((KERN_ALERT "cd register set to 0x%p\n", pptr->dcd.reg));
815
816 pptr->dcd.mask = SAB82532_VSTR_CD;
817 pptr->dcd.inverted = 1;
818 pptr->dcd.irq=ISR0_IDX;
819 pptr->dcd.irqmask=SAB82532_ISR0_CDSC;
820 pptr->dcd.cnst = 0;
821
822 pptr->cts.reg = (unsigned char *)&(STAR);
823 pptr->cts.mask = SAB82532_STAR_CTS;
824 pptr->cts.inverted = 0;
825 pptr->cts.irq=ISR1_IDX;
826 pptr->cts.irqmask=SAB82532_ISR1_CSC;
827 pptr->cts.cnst = 0;
828
829 pptr->rts.reg = (unsigned char *)&(MODE);
830 pptr->rts.mask = SAB82532_MODE_FRTS;
831 pptr->rts.inverted = 1;
832 pptr->rts.cnst = SAB82532_MODE_RTS;
833
834
835 /* Set the read and write function */
836 pptr->readbyte=wmsaura_readb;
837 pptr->readword=wmsaura_readw;
838 pptr->writebyte=wmsaura_writeb;
839 pptr->writeword=wmsaura_writew;
840 pptr->readfifo=wmsaura_readfifo;
841 pptr->writefifo=wmsaura_writefifo;
842
843 sab8253x_setup_ttyport(pptr); /* asynchronous */
844 /* ttys are default, basic */
845 /* initialization, everything */
846 /* else works as a modification */
847 /* thereof */
848
849 pptr->next = AuraPortRoot;
850 AuraPortRoot = pptr;
851
852 pptr->next_by_chip = cptr->c_portbase;
853 cptr->c_portbase = pptr;
854
855 pptr->next_by_board = bptr->board_portbase;
856 bptr->board_portbase = pptr;
857
858 pptr->next_by_cim = cim->ci_portbase;
859 cim->ci_portbase = pptr;
860 }
861
CreateCIMs(SAB_BOARD * bptr)862 static void CreateCIMs(SAB_BOARD *bptr)
863 {
864 unsigned int cimnum;
865 unsigned char *wrcsr;
866 unsigned char *rdcsr;
867 unsigned char tmp;
868 AURA_CIM *cim;
869 unsigned short intrmask;
870
871 for(intrmask = 0, cimnum = 0; cimnum < MAX_NCIMS; ++cimnum)
872 {
873 intrmask >>= 2;
874
875 /*
876 * The hardware is mapped. Try writing to CIM CSR.
877 */
878 wrcsr = bptr->CIMCMD_REG +
879 (CIMCMD_WRCIMCSR | (cimnum << CIMCMD_CIMSHIFT));
880 rdcsr = bptr->CIMCMD_REG +
881 (CIMCMD_RDCIMCSR | (cimnum << CIMCMD_CIMSHIFT));
882
883 /* Try to write an 0xff */
884 writeb((unsigned char) 0xff, (unsigned char *) wrcsr);
885 /* and read it back */
886 tmp = (unsigned char) readb((unsigned char *) rdcsr);
887 DEBUGPRINT((KERN_ALERT
888 "aura wan mcs: wrcsr %p rdcsr %p cim %d 0xff readback: 0x%x.\n",
889 (void*) wrcsr, (void*) rdcsr, cimnum, tmp));
890
891 /* make sure it's really all ones. */
892 if ((tmp & CIMCMD_CIMCSR_TESTMASK) != CIMCMD_CIMCSR_TESTMASK)
893 {
894 printk(KERN_ALERT
895 "aura wan mcs: not found -- wrcsr %p rdcsr %p cim %d 0xff readback: 0x%x.\n",
896 (void*) wrcsr, (void*) rdcsr, cimnum, tmp);
897 continue;
898 }
899
900 /* Try to write a zero */
901 writeb((unsigned char) 0, (unsigned char*) wrcsr);
902 /* and read it back */
903 tmp = (unsigned char) readb((unsigned char *) rdcsr);
904 DEBUGPRINT((KERN_ALERT
905 "aura wan mcs: wrcsr %p rdcsr %p cim %d 0x0 readback: 0x%x.\n",
906 (void*) wrcsr, (void*) rdcsr, cimnum, tmp));
907
908 /* make sure it's really zero. */
909 if ((tmp & CIMCMD_CIMCSR_TESTMASK) != 0)
910 {
911 printk(KERN_ALERT
912 "aura wan mcs: not found -- wrcsr %p rdcsr %p cim %d 0x0 readback: 0x%x.\n",
913 (void*) wrcsr, (void*) rdcsr, cimnum, tmp);
914 continue;
915 }
916 cim = (AURA_CIM*) kmalloc(sizeof(AURA_CIM), GFP_KERNEL);
917 if(cim == NULL)
918 {
919 printk(KERN_ALERT
920 "aura wan mcs: unable to allocate memory, board %p, cim %d.\n",
921 bptr, cimnum);
922 continue;
923 }
924 cim->ci_num = cimnum;
925 cim->ci_board = bptr;
926 cim->ci_chipbase = NULL;
927 cim->ci_portbase = NULL;
928 cim->ci_nports = CIM_NPORTS;
929 cim->ci_port0lbl = cimnum * CIM_NPORTS;
930 if (mcs_ciminit(bptr, cim) == FALSE)
931 {
932 kfree(cim);
933 continue;
934 }
935 intrmask |= 0xc0; /* turn on the high two bits
936 * a little obscure, borrowed
937 * from solaris driver 0th cim
938 * gets lowest two bits*/
939 cim->next = AuraCimRoot;
940 AuraCimRoot = cim;
941 cim->next_by_mcs = bptr->b_cimbase;
942 bptr->b_cimbase = cim;
943 printk(KERN_ALERT
944 "aura wan mcs: Created cim %d type %d on board %p.\n",
945 cim->ci_num, cim->ci_type, bptr);
946 }
947 bptr->b_intrmask = intrmask;
948 }
949
950 /* put the chips on the boards */
951
SetupAllChips(SAB_BOARD * bptr)952 static void SetupAllChips(SAB_BOARD *bptr)
953 { /* note that port ordering */
954 /* is important in chip setup */
955 /* the open routine walks the */
956 /* port list for sync and async */
957 /* ttys */
958 SAB_CHIP *chip;
959 AURA_CIM *cim;
960 unsigned int chipno;
961
962 switch(bptr->b_type)
963 {
964 case BD_1020P:
965 case BD_1020CP:
966 /* setup 1 ESCC2 */
967 chip = CreateESCC2(bptr, 0);
968 if(chip != NULL)
969 {
970 CreateESCC2Port(chip, 1, FUNCTION_NA);
971 CreateESCC2Port(chip, 0, FUNCTION_AO);
972 }
973
974 break;
975 case BD_1520P:
976 case BD_1520CP:
977 /* setup 1 ESCC2 */
978 chip = CreateESCC2(bptr, 0);
979 if(chip != NULL)
980 {
981 CreateESCC2Port(chip, 1, FUNCTION_NA);
982 CreateESCC2Port(chip, 0, FUNCTION_NR);
983 }
984 break;
985 case BD_2020P:
986 case BD_2020CP:
987 /* setup 1 ESCC2 */
988 chip = CreateESCC2(bptr, 0);
989 if(chip != NULL)
990 {
991 CreateESCC2Port(chip, 1, FUNCTION_AO);
992 CreateESCC2Port(chip, 0, FUNCTION_AO);
993 }
994 break;
995 case BD_2520P:
996 case BD_2520CP:
997 /* setup 1 ESCC2 */
998 chip = CreateESCC2(bptr, 0);
999 if(chip != NULL)
1000 {
1001 CreateESCC2Port(chip, 1, FUNCTION_NR);
1002 CreateESCC2Port(chip, 0, FUNCTION_NR);
1003 }
1004 break;
1005 case BD_4020P:
1006 case BD_4020CP: /* do chips in reverCse
1007 order so that they
1008 are on lists in forward
1009 order
1010 */
1011 /* setup 2 ESCC2 */
1012 chip = CreateESCC2(bptr, AURORA_4X20_CHIP_OFFSET);
1013 if(chip != NULL)
1014 {
1015 CreateESCC2Port(chip, 1, FUNCTION_AO);
1016 CreateESCC2Port(chip, 0, FUNCTION_AO);
1017 }
1018 chip = CreateESCC2(bptr, 0);
1019 if(chip != NULL)
1020 {
1021 CreateESCC2Port(chip, 1, FUNCTION_AO);
1022 CreateESCC2Port(chip, 0, FUNCTION_AO);
1023 }
1024 break;
1025 case BD_4520P:
1026 case BD_4520CP:
1027 /* setup 2 ESCC2 */
1028 chip = CreateESCC2(bptr, AURORA_4X20_CHIP_OFFSET);
1029 if(chip != NULL)
1030 {
1031 CreateESCC2Port(chip, 1, FUNCTION_NR);
1032 CreateESCC2Port(chip, 0, FUNCTION_NR);
1033 }
1034 chip = CreateESCC2(bptr, 0);
1035 if(chip != NULL)
1036 {
1037 CreateESCC2Port(chip, 1, FUNCTION_NR);
1038 CreateESCC2Port(chip, 0, FUNCTION_NR);
1039 }
1040 break;
1041 case BD_8020P:
1042 case BD_8020CP:
1043 /* setup 1 ESCC8 */
1044 chip = CreateESCC8(bptr, 0);
1045 if(chip != NULL)
1046 {
1047 CreateESCC8Port(chip, 7, FUNCTION_AO);
1048 CreateESCC8Port(chip, 6, FUNCTION_AO);
1049 CreateESCC8Port(chip, 5, FUNCTION_AO);
1050 CreateESCC8Port(chip, 4, FUNCTION_AO);
1051 CreateESCC8Port(chip, 3, FUNCTION_AO);
1052 CreateESCC8Port(chip, 2, FUNCTION_AO);
1053 CreateESCC8Port(chip, 1, FUNCTION_AO);
1054 CreateESCC8Port(chip, 0, FUNCTION_AO);
1055 }
1056 break;
1057 case BD_8520P:
1058 case BD_8520CP:
1059 /* setup 1 ESCC8 */
1060 chip = CreateESCC8(bptr, 0);
1061 if(chip != NULL)
1062 {
1063 CreateESCC8Port(chip, 7, FUNCTION_NR);
1064 CreateESCC8Port(chip, 6, FUNCTION_NR);
1065 CreateESCC8Port(chip, 5, FUNCTION_NR);
1066 CreateESCC8Port(chip, 4, FUNCTION_NR);
1067 CreateESCC8Port(chip, 3, FUNCTION_NR);
1068 CreateESCC8Port(chip, 2, FUNCTION_NR);
1069 CreateESCC8Port(chip, 1, FUNCTION_NR);
1070 CreateESCC8Port(chip, 0, FUNCTION_NR);
1071 }
1072 break;
1073
1074 case BD_WANMCS:
1075 CreateCIMs(bptr);
1076 for(chipno = 7, cim = bptr->b_cimbase;
1077 cim != NULL; cim = cim->next_by_mcs)
1078 {
1079 chip = CreateESCC8fromCIM(bptr, cim, chipno--);
1080 if(chip != NULL)
1081 {
1082 CreateESCC8PortWithCIM(chip, 7, cim, 0);
1083 CreateESCC8PortWithCIM(chip, 6, cim, 0);
1084 CreateESCC8PortWithCIM(chip, 5, cim, 0);
1085 CreateESCC8PortWithCIM(chip, 4, cim, 0);
1086 CreateESCC8PortWithCIM(chip, 3, cim, 0);
1087 CreateESCC8PortWithCIM(chip, 2, cim, 0);
1088 CreateESCC8PortWithCIM(chip, 1, cim, 0);
1089 CreateESCC8PortWithCIM(chip, 0, cim, 0);
1090 }
1091 chip = CreateESCC8fromCIM(bptr, cim, chipno--);
1092 if(chip != NULL)
1093 {
1094 CreateESCC8PortWithCIM(chip, 7, cim, 0);
1095 CreateESCC8PortWithCIM(chip, 6, cim, 0);
1096 CreateESCC8PortWithCIM(chip, 5, cim, 0);
1097 CreateESCC8PortWithCIM(chip, 4, cim, 0);
1098 CreateESCC8PortWithCIM(chip, 3, cim, 0);
1099 CreateESCC8PortWithCIM(chip, 2, cim, 0);
1100 CreateESCC8PortWithCIM(chip, 1, cim, 0);
1101 CreateESCC8PortWithCIM(chip, 0, cim, 1);
1102 }
1103 }
1104 break;
1105
1106 default:
1107 printk(KERN_ALERT "auraXX20n: unable to set up chip for board %p.\n", bptr);
1108 break;
1109 }
1110 }
1111
1112 /* finding the cards by PCI device type */
1113
find_ati_cpci_card(void)1114 static SAB_BOARD* find_ati_cpci_card(void)
1115 {
1116 struct pci_dev *pdev;
1117 unsigned char bus;
1118 unsigned char devfn;
1119 unsigned char pci_latency;
1120 unsigned short pci_command;
1121 SAB_BOARD *bptr;
1122 unsigned control;
1123 unsigned does_sync;
1124 unsigned use_1port;
1125
1126 printk(KERN_ALERT "auraXX20n: finding ati cpci cards.\n");
1127
1128 bptr = (SAB_BOARD*)kmalloc(sizeof(SAB_BOARD), GFP_KERNEL);
1129 if(bptr == NULL)
1130 {
1131 printk(KERN_ALERT "auraXX20n: could not allocate board memory!\n");
1132 return 0;
1133 }
1134 memset(bptr, 0, sizeof(SAB_BOARD));
1135
1136 if(!pcibios_present())
1137 {
1138 printk(KERN_ALERT "auraXX20n: system does not support PCI bus.\n");
1139 kfree(bptr);
1140 return 0;
1141 }
1142 DEBUGPRINT((KERN_ALERT "auraXX20n: System supports PCI bus.\n"));
1143
1144 CPCIRESTART:
1145 if(pdev = pci_find_device(sab8253x_vendor_id, sab8253x_cpci_device_id, XX20lastpdev),
1146 pdev == NULL)
1147 {
1148 printk(KERN_ALERT "auraXX20n: could not find cpci card.\n");
1149 kfree(bptr);
1150 return 0;
1151 }
1152
1153 DEBUGPRINT((KERN_ALERT "auraXX20n: found multiport CPCI serial card.\n"));
1154
1155 XX20lastpdev = pdev;
1156 DEBUGPRINT((KERN_ALERT "auraXX20n: found ATI PLX 9050, %p.\n", pdev));
1157 bptr->b_dev = *pdev;
1158
1159 /* the Solaris and model linux drivers
1160 * comment that there are problems with
1161 * getting the length via PCI operations
1162 * seems to work for 2.4
1163 */
1164 bptr->length0 = (unsigned int) pci_resource_len(pdev, 0);
1165 bptr->length1 = (unsigned int) pci_resource_len(pdev, 1);
1166 bptr->length2 = (unsigned int) pci_resource_len(pdev, 2);
1167 bptr->b_irq = pdev->irq;
1168
1169
1170 DEBUGPRINT((KERN_ALERT
1171 "auraXX20n: base address 0 is %p, len is %x.\n",
1172 (void*) pci_base_address(pdev, 0), bptr->length0));
1173 DEBUGPRINT((KERN_ALERT
1174 "auraXX20n: base address 1 is %p, len is %x.\n",
1175 (void*) pci_base_address(pdev, 1), bptr->length1));
1176 DEBUGPRINT((KERN_ALERT
1177 "auraXX20n: base address 2 is %p, len is %x.\n",
1178 (void*) pci_base_address(pdev, 2),
1179 bptr->length2));
1180
1181 DEBUGPRINT((KERN_ALERT "auraXX20n: interrupt is %i.\n", pdev->irq));
1182 bus = pdev->bus->number;
1183 devfn = pdev->devfn;
1184 DEBUGPRINT((KERN_ALERT "auraXX20n: bus is %x, slot is %x.\n", bus, PCI_SLOT(devfn)));
1185 pcibios_read_config_word(bus, devfn, PCI_COMMAND, &pci_command);
1186 #if 0
1187 /* The Aurora card does not act as a PCI master
1188 * ugh!!
1189 */
1190 new_command = pci_command | PCI_COMMAND_MASTER;
1191 if(pci_command != new_command)
1192 {
1193 DEBUGPRINT((KERN_ALERT
1194 "auraXX20n: the PCI BIOS has not enabled this device!"
1195 " Updating PCI command %4.4x->%4.4x.\n",
1196 pci_command,
1197 new_command));
1198 pcibios_write_config_word(bus, devfn, PCI_COMMAND,
1199 new_command);
1200 }
1201 else
1202 {
1203 DEBUGPRINT
1204 ((KERN_ALERT
1205 "auraXX20n: the PCI BIOS has enabled this device as master!\n"));
1206 }
1207 #endif
1208 if((pci_command & PCI_COMMAND_MASTER) != PCI_COMMAND_MASTER)
1209 {
1210 DEBUGPRINT((KERN_ALERT "auraXX20n: Aurora card is not a bus master.\n"));
1211 }
1212
1213 pcibios_read_config_byte(bus, devfn, PCI_LATENCY_TIMER,
1214 &pci_latency);
1215 if (pci_latency < 32)
1216 {
1217 DEBUGPRINT
1218 ((KERN_ALERT
1219 "auraXX20n: PCI latency timer (CFLT) is low at %i.\n", pci_latency));
1220 /* may need to change the latency */
1221 #if 0
1222 pcibios_write_config_byte(bus, devfn, PCI_LATENCY_TIMER, 32);
1223 #endif
1224 }
1225 else
1226 {
1227 DEBUGPRINT((KERN_ALERT
1228 "auraXX20n: PCI latency timer (CFLT) is %#x.\n",
1229 pci_latency));
1230 }
1231 bptr->virtbaseaddress0 = ioremap_nocache(pci_base_address(pdev, 0),
1232 bptr->length0);
1233 if(bptr->virtbaseaddress0 == NULL)
1234 {
1235 printk(KERN_ALERT
1236 "auraXX20n: unable to remap physical address %p.\n",
1237 (void*) pci_base_address(pdev, 0));
1238
1239 goto CPCIRESTART;
1240 }
1241
1242 bptr->b_bridge = (PLX9050*) bptr->virtbaseaddress0; /* MAKE SURE INTS ARE OFF */
1243 writel(PLX_INT_OFF, &(bptr->b_bridge->intr));
1244
1245 printk
1246 (KERN_ALERT
1247 "auraXX20n: remapped physical address %p to virtual address %p.\n",
1248 (void*) pci_base_address(pdev, 0), (void*) bptr->virtbaseaddress0);
1249
1250 dump_ati_adapter_registers((unsigned int*) bptr->virtbaseaddress0, bptr->length0);
1251
1252 if(*(unsigned int*)bptr->virtbaseaddress0 == -1) /* XP7 problem? */
1253 {
1254 printk(KERN_ALERT
1255 "auraXX20n: unable to access PLX 9050 registers at %p.\n",
1256 (void*)bptr->virtbaseaddress0);
1257 printk(KERN_ALERT "auraXX20n: unmapping virtual address %p.\n",
1258 (void*)bptr->virtbaseaddress0);
1259 iounmap((void*)bptr->virtbaseaddress0);
1260 bptr->virtbaseaddress0 = 0;
1261
1262 goto CPCIRESTART;
1263 }
1264
1265 bptr->virtbaseaddress2 = ioremap_nocache(pci_base_address(pdev, 2),
1266 bptr->length2);
1267 if(bptr->virtbaseaddress2 == NULL)
1268 {
1269 printk(KERN_ALERT
1270 "auraXX20n: unable to remap physical address %p.\n",
1271 (void*) pci_base_address(pdev, 2));
1272 printk(KERN_ALERT "auraXX20n: unmapping virtual address %p.\n",
1273 (void*)bptr->virtbaseaddress0);
1274 iounmap((void*)bptr->virtbaseaddress0);
1275 bptr->virtbaseaddress0 = 0;
1276
1277 goto CPCIRESTART;
1278 }
1279
1280 DEBUGPRINT
1281 ((KERN_ALERT
1282 "auraXX20n: remapped physical address %p to virtual address %p.\n",
1283 (void*) pci_base_address(pdev, 2), (void*) bptr->virtbaseaddress2));
1284
1285 /* we get clockrate from serial eeprom */
1286 if (!plx9050_eprom_read(&((PLX9050*)(bptr->virtbaseaddress0))->ctrl,
1287 (unsigned short*) bptr->b_eprom,
1288 (unsigned char) 0, EPROM9050_SIZE))
1289 {
1290 printk(KERN_ALERT "auraXX20n: Could not read serial eprom.\n");
1291 iounmap((void*)bptr->virtbaseaddress0);
1292 bptr->virtbaseaddress0 = 0;
1293 iounmap((void*)bptr->virtbaseaddress2);
1294 bptr->virtbaseaddress2 = 0;
1295
1296 goto CPCIRESTART;
1297 }
1298
1299 printk(KERN_ALERT "auraXX20n: dumping serial eprom.\n");
1300 dump_ati_adapter_registers((unsigned int*) bptr->b_eprom, 2 * EPROM9050_SIZE);
1301
1302 if(*(unsigned int*)bptr->b_eprom != PCIMEMVALIDCPCI) /* bridge problem? */
1303 {
1304 printk(KERN_ALERT "auraXX20n: unable to access valid serial eprom data.\n");
1305 iounmap((void*)bptr->virtbaseaddress0);
1306 bptr->virtbaseaddress0 = 0;
1307 iounmap((void*)bptr->virtbaseaddress2);
1308 bptr->virtbaseaddress2 = 0;
1309
1310 goto CPCIRESTART;
1311 }
1312
1313 if(((unsigned short*) bptr->b_eprom)[EPROMPREFETCHOFFSET] & PREFETCHBIT)
1314 {
1315 ++sab8253x_rebootflag;
1316 printk(KERN_ALERT "8253x: eeprom programmed for prefetchable memory resources; must reprogram!!\n");
1317 plx9050_eprom_cmd(&((PLX9050*)(bptr->virtbaseaddress0))->ctrl,
1318 NM93_WENCMD, NM93_WENADDR, 0);
1319 plx9050_eprom_cmd(&((PLX9050*)(bptr->virtbaseaddress0))->ctrl,
1320 NM93_WRITECMD,
1321 9,
1322 (((unsigned short*) bptr->b_eprom)[EPROMPREFETCHOFFSET] & (~PREFETCHBIT)));
1323 plx9050_eprom_cmd(&((PLX9050*)(bptr->virtbaseaddress0))->ctrl,
1324 NM93_WDSCMD, NM93_WDSADDR, 0);
1325 }
1326 /* get SYNC and ONEPORT values */
1327
1328 control = readl(&((PLX9050*)(bptr->virtbaseaddress0))->ctrl);
1329 /* note we use the actual address
1330 * of the control register in
1331 * memory
1332 */
1333
1334 if(control & AURORA_MULTI_SYNCBIT)
1335 {
1336 does_sync = 0;
1337 }
1338 else
1339 {
1340 does_sync = 1;
1341 }
1342
1343 if(control & AURORA_MULTI_1PORTBIT)
1344 {
1345 use_1port = 1;
1346 }
1347 else
1348 {
1349 use_1port = 0;
1350 }
1351
1352
1353 /* Figure out the board */
1354 switch(bptr->length2)
1355 {
1356 case AURORA_4X20_SIZE:
1357 if(does_sync)
1358 {
1359 bptr->b_type = BD_4520CP;
1360 bptr->b_nchips = 2;
1361 bptr->b_nports = 4;
1362 bptr->b_flags = BD_SYNC;
1363 bptr->b_cimbase = NULL;
1364 bptr->board_number = BD4520CPcounter; /* keep track of boardnumber for naming devices */
1365 ++BD4520CPcounter;
1366 printk(KERN_ALERT "auraXX20n: Found Saturn 4520CP.\n");
1367 }
1368 else
1369 {
1370 bptr->b_type = BD_4020CP;
1371 bptr->b_nchips = 2;
1372 bptr->b_nports = 4;
1373 bptr->b_flags = 0x0;
1374 bptr->b_cimbase = NULL;
1375 bptr->board_number = BD4020CPcounter;
1376 ++BD4020CPcounter;
1377 printk(KERN_ALERT "auraXX20n: Found Apollo 4020CP.\n");
1378 }
1379 break;
1380 case AURORA_8X20_SIZE:
1381 if(does_sync)
1382 {
1383 bptr->b_type = BD_8520CP;
1384 bptr->b_nchips = 1;
1385 bptr->b_nports = 8;
1386 bptr->b_flags = BD_SYNC;
1387 bptr->b_cimbase = NULL;
1388 bptr->board_number = BD8520CPcounter;
1389 ++BD8520CPcounter;
1390 printk(KERN_ALERT "auraXX20n: Found Saturn 8520CP.\n");
1391 }
1392 else
1393 {
1394 bptr->b_type = BD_8020CP;
1395 bptr->b_nchips = 1;
1396 bptr->b_nports = 8;
1397 bptr->b_flags = 0x0;
1398 bptr->b_cimbase = NULL;
1399 bptr->board_number = BD8020CPcounter;
1400 ++BD8020CPcounter;
1401 printk(KERN_ALERT "auraXX20n: Found Apollo 8020CP.\n");
1402 }
1403 break;
1404 case AURORA_2X20_SIZE:
1405 if(does_sync)
1406 {
1407 if(use_1port)
1408 {
1409 bptr->b_type = BD_1520CP;
1410 printk(KERN_ALERT "auraXX20n: Found Saturn 1520CP.\n");
1411 bptr->b_nchips = 1;
1412 bptr->b_nports = 1;
1413 bptr->b_flags = BD_SYNC;
1414 bptr->b_cimbase = NULL;
1415 bptr->board_number = BD1520CPcounter;
1416 ++BD1520CPcounter;
1417 printk(KERN_ALERT "auraXX20n: Found Saturn 1520CP.\n");
1418 }
1419 else
1420 {
1421 bptr->b_type = BD_2520CP;
1422 bptr->b_nchips = 1;
1423 bptr->b_nports = 2;
1424 bptr->b_flags = BD_SYNC;
1425 bptr->b_cimbase = NULL;
1426 bptr->board_number = BD2520CPcounter;
1427 ++BD2520CPcounter;
1428 printk(KERN_ALERT "auraXX20n: Found Saturn 2520CP.\n");
1429 }
1430 }
1431 else
1432 {
1433 if(use_1port)
1434 {
1435 bptr->b_type = BD_1020CP;
1436 bptr->b_nchips = 1;
1437 bptr->b_nports = 1;
1438 bptr->b_flags = 0x0;
1439 bptr->b_cimbase = NULL;
1440 bptr->board_number = BD1020CPcounter;
1441 ++BD1020CPcounter;
1442 printk(KERN_ALERT "auraXX20n: Found Apollo 1020CP.\n");
1443 }
1444 else
1445 {
1446 bptr->b_type = BD_2020CP;
1447 bptr->b_nchips = 1;
1448 bptr->b_nports = 2;
1449 bptr->b_flags = 0x0;
1450 bptr->b_cimbase = NULL;
1451 bptr->board_number = BD2020CPcounter;
1452 ++BD2020CPcounter;
1453 printk(KERN_ALERT "auraXX20n: Found Apollo 2020CP.\n");
1454 }
1455 }
1456 break;
1457 default:
1458 printk(KERN_ALERT "Error: Board could not be identified\n");
1459 iounmap((void*)bptr->virtbaseaddress0);
1460 bptr->virtbaseaddress0 = 0;
1461 iounmap((void*)bptr->virtbaseaddress2);
1462 bptr->virtbaseaddress2 = 0;
1463
1464 goto CPCIRESTART;
1465 }
1466
1467 /* Let's get the clockrate right -- ugh!*/
1468
1469 bptr->b_clkspeed = bptr->b_eprom[AURORA_MULTI_EPROM_CLKLSW/2];
1470
1471 if(bptr->b_clkspeed == -1) /* misprogrammed -- ugh. */
1472 {
1473 switch(bptr->b_type)
1474 {
1475 case BD_8520CP:
1476 case BD_8020CP:
1477 bptr->b_clkspeed = AURORA_MULTI_CLKSPEED/4;
1478 break;
1479 default:
1480 bptr->b_clkspeed = AURORA_MULTI_CLKSPEED;
1481 break;
1482
1483 }
1484 printk(KERN_ALERT "auraXX20n: UNKNOWN CLOCKSPEED -- ASSUMING %ld.\n", bptr->b_clkspeed);
1485
1486 plx9050_eprom_cmd(&((PLX9050*)(bptr->virtbaseaddress0))->ctrl,
1487 NM93_WENCMD, NM93_WENADDR, 0);
1488 plx9050_eprom_cmd(&((PLX9050*)(bptr->virtbaseaddress0))->ctrl,
1489 NM93_WRITECMD,
1490 54, (unsigned short) bptr->b_clkspeed);
1491 plx9050_eprom_cmd(&((PLX9050*)(bptr->virtbaseaddress0))->ctrl,
1492 NM93_WRITECMD,
1493 55, (unsigned short) (bptr->b_clkspeed >> 16));
1494 plx9050_eprom_cmd(&((PLX9050*)(bptr->virtbaseaddress0))->ctrl,
1495 NM93_WDSCMD, NM93_WDSADDR, 0);
1496 }
1497
1498 return bptr;
1499 }
1500
find_ati_wanms_card(void)1501 static SAB_BOARD* find_ati_wanms_card(void) /* wan multichanner server == mcs [ multichannel server] */
1502 {
1503 struct pci_dev *pdev;
1504 unsigned char bus;
1505 unsigned char devfn;
1506 unsigned char pci_latency;
1507 unsigned short pci_command;
1508 SAB_BOARD *bptr;
1509 int resetresult;
1510
1511 printk(KERN_ALERT "auraXX20n: finding ati mcs cards.\n");
1512
1513 bptr = (SAB_BOARD*)kmalloc(sizeof(SAB_BOARD), GFP_KERNEL);
1514 if(bptr == NULL)
1515 {
1516 printk(KERN_ALERT "auraXX20n: could not allocate board memory!\n");
1517 return 0;
1518 }
1519 memset(bptr, 0, sizeof(SAB_BOARD));
1520
1521 if(!pcibios_present())
1522 {
1523 printk(KERN_ALERT "auraXX20n: system does not support PCI bus.\n");
1524 kfree(bptr);
1525 return 0;
1526 }
1527 DEBUGPRINT((KERN_ALERT "auraXX20n: System supports PCI bus.\n"));
1528
1529 MCSRESTART:
1530 if(pdev = pci_find_device(sab8253x_vendor_id, sab8253x_wmcs_device_id, XX20lastpdev),
1531 pdev == NULL)
1532 {
1533 printk(KERN_ALERT "auraXX20n: could not find mcs card.\n");
1534 kfree(bptr);
1535 return 0;
1536 }
1537
1538 DEBUGPRINT((KERN_ALERT "auraXX20n: found mcs card.\n"));
1539
1540 XX20lastpdev = pdev;
1541 DEBUGPRINT((KERN_ALERT "auraXX20n: found ATI S5920, %p.\n", pdev));
1542 bptr->b_dev = *pdev;
1543
1544 /* the Solaris and model linux drivers
1545 * comment that there are problems with
1546 * getting the length via PCI operations
1547 * seems to work for 2.4
1548 */
1549 bptr->length0 = (unsigned int) pci_resource_len(pdev, 0); /* AMCC 5920 operation registers
1550 includes access to serial eprom */
1551 bptr->length1 = (unsigned int) pci_resource_len(pdev, 1); /* commands to remote cards */
1552 bptr->length2 = (unsigned int) pci_resource_len(pdev, 2); /* command to host card */
1553 bptr->length3 = (unsigned int) pci_resource_len(pdev, 3); /* RFIFO cache */
1554 bptr->b_irq = pdev->irq;
1555
1556 DEBUGPRINT((KERN_ALERT
1557 "auraXX20n: base address 0 is %p, len is %x.\n",
1558 (void*) pci_base_address(pdev, 0), bptr->length0));
1559 DEBUGPRINT((KERN_ALERT
1560 "auraXX20n: base address 1 is %p, len is %x.\n",
1561 (void*) pci_base_address(pdev, 1), bptr->length1));
1562 DEBUGPRINT((KERN_ALERT
1563 "auraXX20n: base address 2 is %p, len is %x.\n",
1564 (void*) pci_base_address(pdev, 2),
1565 bptr->length2));
1566 DEBUGPRINT((KERN_ALERT
1567 "auraXX20n: base address 3 is %p, len is %x.\n",
1568 (void*) pci_base_address(pdev, 3),
1569 bptr->length3));
1570
1571 DEBUGPRINT((KERN_ALERT "auraXX20n: interrupt is %i.\n", pdev->irq));
1572 bus = pdev->bus->number;
1573 devfn = pdev->devfn;
1574 DEBUGPRINT((KERN_ALERT "auraXX20n: bus is %x, slot is %x.\n", bus, PCI_SLOT(devfn)));
1575 pcibios_read_config_word(bus, devfn, PCI_COMMAND, &pci_command);
1576
1577 #if 0
1578 /* The Aurora card does not act as a PCI master
1579 * ugh!!
1580 */
1581 new_command = pci_command | PCI_COMMAND_MASTER;
1582 if(pci_command != new_command)
1583 {
1584 DEBUGPRINT((KERN_ALERT
1585 "auraXX20n: the PCI BIOS has not enabled this device!"
1586 " Updating PCI command %4.4x->%4.4x.\n",
1587 pci_command,
1588 new_command));
1589 pcibios_write_config_word(bus, devfn, PCI_COMMAND,
1590 new_command);
1591 }
1592 else
1593 {
1594 DEBUGPRINT
1595 ((KERN_ALERT
1596 "auraXX20n: the PCI BIOS has enabled this device as master!\n"));
1597 }
1598 #endif
1599
1600 if((pci_command & PCI_COMMAND_MASTER) != PCI_COMMAND_MASTER)
1601 {
1602 DEBUGPRINT((KERN_ALERT "auraXX20n: Aurora card is not a bus master.\n"));
1603 }
1604
1605 pcibios_read_config_byte(bus, devfn, PCI_LATENCY_TIMER,
1606 &pci_latency);
1607 if (pci_latency < 32)
1608 {
1609 DEBUGPRINT
1610 ((KERN_ALERT
1611 "auraXX20n: PCI latency timer (CFLT) is low at %i.\n", pci_latency));
1612 /* may need to change the latency */
1613 #if 0
1614 pcibios_write_config_byte(bus, devfn, PCI_LATENCY_TIMER, 32);
1615 #endif
1616 }
1617 else
1618 {
1619 DEBUGPRINT((KERN_ALERT
1620 "auraXX20n: PCI latency timer (CFLT) is %#x.\n",
1621 pci_latency));
1622 }
1623
1624 bptr->virtbaseaddress0 = ioremap_nocache(pci_base_address(pdev, 0),
1625 bptr->length0);
1626 if(bptr->virtbaseaddress0 == NULL)
1627 {
1628 printk(KERN_ALERT
1629 "auraXX20n: unable to remap physical address %p.\n",
1630 (void*) pci_base_address(pdev, 0));
1631 goto MCSRESTART;
1632 }
1633
1634 bptr->b_bridge = (void*) bptr->virtbaseaddress0; /* b_bridge is not supposed
1635 to be used by the AMCC based
1636 products -- it is set just
1637 in case */
1638
1639 printk(KERN_ALERT
1640 "auraXX20n: remapped physical address %p to virtual address %p.\n",
1641 (void*) pci_base_address(pdev, 0), (void*) bptr->virtbaseaddress0);
1642
1643 /* unfortunate name -- works for any bridge */
1644 dump_ati_adapter_registers((unsigned int*) bptr->virtbaseaddress0, bptr->length0);
1645
1646 if(*(unsigned int*)bptr->virtbaseaddress0 == -1) /* XP7 problem? */
1647 {
1648 printk(KERN_ALERT
1649 "auraXX20n: unable to access AMCC registers at %p.\n",
1650 (void*)bptr->virtbaseaddress0);
1651 printk(KERN_ALERT "auraXX20n: unmapping virtual address %p.\n",
1652 (void*)bptr->virtbaseaddress0);
1653 iounmap((void*)bptr->virtbaseaddress0);
1654 bptr->virtbaseaddress0 = 0;
1655 goto MCSRESTART; /* try the next one if any */
1656 }
1657
1658 writel(AMCC_INT_OFF, (unsigned int*)(bptr->AMCC_REG + AMCC_INTCSR));
1659
1660 bptr->virtbaseaddress1 = ioremap_nocache(pci_base_address(pdev, 1),
1661 bptr->length1);
1662 if(bptr->virtbaseaddress1 == NULL)
1663 {
1664 printk(KERN_ALERT
1665 "auraXX20n: unable to remap physical address %p.\n",
1666 (void*) pci_base_address(pdev, 1));
1667 printk(KERN_ALERT "auraXX20n: unmapping virtual address %p.\n",
1668 (void*)bptr->virtbaseaddress0);
1669 iounmap((void*)bptr->virtbaseaddress0);
1670 bptr->virtbaseaddress0 = 0;
1671 goto MCSRESTART;
1672 }
1673
1674 DEBUGPRINT
1675 ((KERN_ALERT
1676 "auraXX20n: remapped physical address %p to virtual address %p.\n",
1677 (void*) pci_base_address(pdev, 1), (void*) bptr->virtbaseaddress1));
1678
1679 /* next address space */
1680 bptr->virtbaseaddress2 = ioremap_nocache(pci_base_address(pdev, 2),
1681 bptr->length2);
1682 if(bptr->virtbaseaddress2 == NULL)
1683 {
1684 printk(KERN_ALERT
1685 "auraXX20n: unable to remap physical address %p.\n",
1686 (void*) pci_base_address(pdev, 2));
1687
1688 printk(KERN_ALERT "auraXX20n: unmapping virtual address %p.\n",
1689 (void*)bptr->virtbaseaddress0);
1690 iounmap((void*)bptr->virtbaseaddress0);
1691 bptr->virtbaseaddress0 = 0;
1692
1693 printk(KERN_ALERT "auraXX20n: unmapping virtual address %p.\n",
1694 (void*)bptr->virtbaseaddress1);
1695 iounmap((void*)bptr->virtbaseaddress1);
1696 bptr->virtbaseaddress1 = 0;
1697 goto MCSRESTART;
1698 }
1699
1700 DEBUGPRINT
1701 ((KERN_ALERT
1702 "auraXX20n: remapped physical address %p to virtual address %p.\n",
1703 (void*) pci_base_address(pdev, 2), (void*) bptr->virtbaseaddress2));
1704
1705 bptr->virtbaseaddress3 = ioremap_nocache(pci_base_address(pdev, 3),
1706 bptr->length3);
1707 if(bptr->virtbaseaddress3 == NULL)
1708 {
1709 printk(KERN_ALERT
1710 "auraXX20n: unable to remap physical address %p.\n",
1711 (void*) pci_base_address(pdev, 3));
1712 printk(KERN_ALERT "auraXX20n: unmapping virtual address %p.\n",
1713 (void*)bptr->virtbaseaddress0);
1714 iounmap((void*)bptr->virtbaseaddress0);
1715 bptr->virtbaseaddress0 = 0;
1716
1717 printk(KERN_ALERT "auraXX20n: unmapping virtual address %p.\n",
1718 (void*)bptr->virtbaseaddress1);
1719 iounmap((void*)bptr->virtbaseaddress1);
1720 bptr->virtbaseaddress1 = 0;
1721
1722 printk(KERN_ALERT "auraXX20n: unmapping virtual address %p.\n",
1723 (void*)bptr->virtbaseaddress2);
1724 iounmap((void*)bptr->virtbaseaddress2);
1725 bptr->virtbaseaddress2 = 0;
1726
1727 goto MCSRESTART;
1728 }
1729
1730 DEBUGPRINT
1731 ((KERN_ALERT
1732 "auraXX20n: remapped physical address %p to virtual address %p.\n",
1733 (void*) pci_base_address(pdev, 3), (void*) bptr->virtbaseaddress3));
1734
1735 bptr->b_type = BD_WANMCS;
1736
1737 resetresult = wanmcs_reset(bptr);
1738 writel(AMCC_INT_OFF, (unsigned int*)(bptr->AMCC_REG + AMCC_INTCSR));
1739
1740 if(resetresult == FALSE)
1741 {
1742 printk(KERN_ALERT "auraXX20n: unable to reset wan mcs %p.\n", bptr);
1743
1744 printk(KERN_ALERT "auraXX20n: unmapping virtual address %p.\n",
1745 (void*)bptr->virtbaseaddress0);
1746 iounmap((void*)bptr->virtbaseaddress0);
1747 bptr->virtbaseaddress0 = 0;
1748
1749 printk(KERN_ALERT "auraXX20n: unmapping virtual address %p.\n",
1750 (void*)bptr->virtbaseaddress1);
1751 iounmap((void*)bptr->virtbaseaddress1);
1752 bptr->virtbaseaddress1 = 0;
1753
1754 printk(KERN_ALERT "auraXX20n: unmapping virtual address %p.\n",
1755 (void*)bptr->virtbaseaddress2);
1756 iounmap((void*)bptr->virtbaseaddress2);
1757 bptr->virtbaseaddress2 = 0;
1758
1759
1760 printk(KERN_ALERT "auraXX20n: unmapping virtual address %p.\n",
1761 (void*)bptr->virtbaseaddress3);
1762 iounmap((void*)bptr->virtbaseaddress3);
1763 bptr->virtbaseaddress3 = 0;
1764
1765 goto MCSRESTART;
1766 }
1767
1768 /* we get clockrate from serial eeprom */
1769 if (amcc_read_nvram((unsigned char*) bptr->b_eprom,
1770 AMCC_NVRAM_SIZE, bptr->AMCC_REG) == FALSE)
1771 {
1772 printk(KERN_ALERT "auraXX20n: Could not read serial eprom.\n");
1773 iounmap((void*)bptr->virtbaseaddress0);
1774 bptr->virtbaseaddress0 = 0;
1775 iounmap((void*)bptr->virtbaseaddress1);
1776 bptr->virtbaseaddress1 = 0;
1777 iounmap((void*)bptr->virtbaseaddress2);
1778 bptr->virtbaseaddress2 = 0;
1779 iounmap((void*)bptr->virtbaseaddress3);
1780 bptr->virtbaseaddress3 = 0;
1781 goto MCSRESTART;
1782 }
1783 printk(KERN_ALERT "auraXX20n: dumping serial eprom.\n");
1784 dump_ati_adapter_registers((unsigned int*) bptr->b_eprom, 2 * AMCC_NVRAM_SIZE);
1785 if(bptr->b_eprom[AMCC_NVR_VENDEVID] != PCIMEMVALIDWMCS)
1786 {
1787 printk(KERN_ALERT "auraXX20: bad serial eprom, board %p.\n", bptr);
1788 iounmap((void*)bptr->virtbaseaddress0);
1789 bptr->virtbaseaddress0 = 0;
1790 iounmap((void*)bptr->virtbaseaddress1);
1791 bptr->virtbaseaddress1 = 0;
1792 iounmap((void*)bptr->virtbaseaddress2);
1793 bptr->virtbaseaddress2 = 0;
1794 iounmap((void*)bptr->virtbaseaddress3);
1795 bptr->virtbaseaddress3 = 0;
1796 goto MCSRESTART;
1797 }
1798 return bptr;
1799 }
1800
1801 /* initialize the auraXX20 */
find_ati_multiport_card(void)1802 static SAB_BOARD* find_ati_multiport_card(void)
1803 {
1804 struct pci_dev *pdev;
1805 unsigned char bus;
1806 unsigned char devfn;
1807 unsigned char pci_latency;
1808 unsigned short pci_command;
1809 SAB_BOARD *bptr;
1810 unsigned control;
1811 unsigned does_sync;
1812 unsigned use_1port;
1813
1814 printk(KERN_ALERT "auraXX20n: finding ati cards.\n");
1815
1816 bptr = (SAB_BOARD*)kmalloc(sizeof(SAB_BOARD), GFP_KERNEL);
1817 if(bptr == NULL)
1818 {
1819 printk(KERN_ALERT "auraXX20n: could not allocate board memory!\n");
1820 return 0;
1821 }
1822 memset(bptr, 0, sizeof(SAB_BOARD));
1823
1824 if(!pcibios_present())
1825 {
1826 printk(KERN_ALERT "auraXX20n: system does not support PCI bus.\n");
1827 kfree(bptr);
1828 return 0;
1829 }
1830 DEBUGPRINT((KERN_ALERT "auraXX20n: System supports PCI bus.\n"));
1831
1832 MULTIPORTRESTART:
1833 if(pdev = pci_find_device(sab8253x_vendor_id, sab8253x_mpac_device_id, XX20lastpdev),
1834 pdev == NULL)
1835 {
1836 printk(KERN_ALERT "auraXX20n: could not find multiport card.\n");
1837 kfree(bptr);
1838 return 0;
1839 }
1840
1841 DEBUGPRINT((KERN_ALERT "auraXX20n: found multiport PCI serial card.\n"));
1842
1843 XX20lastpdev = pdev;
1844 DEBUGPRINT((KERN_ALERT "auraXX20n: found ATI PLX 9050, %p.\n", pdev));
1845 bptr->b_dev = *pdev;
1846
1847 /* the Solaris and model linux drivers
1848 * comment that there are problems with
1849 * getting the length via PCI operations
1850 * seems to work for 2.4
1851 */
1852 bptr->length0 = (unsigned int) pci_resource_len(pdev, 0);
1853 bptr->length1 = (unsigned int) pci_resource_len(pdev, 1);
1854 bptr->length2 = (unsigned int) pci_resource_len(pdev, 2);
1855 bptr->b_irq = pdev->irq;
1856
1857
1858 DEBUGPRINT((KERN_ALERT
1859 "auraXX20n: base address 0 is %p, len is %x.\n",
1860 (void*) pci_base_address(pdev, 0), bptr->length0));
1861 DEBUGPRINT((KERN_ALERT
1862 "auraXX20n: base address 1 is %p, len is %x.\n",
1863 (void*) pci_base_address(pdev, 1), bptr->length1));
1864 DEBUGPRINT((KERN_ALERT
1865 "auraXX20n: base address 2 is %p, len is %x.\n",
1866 (void*) pci_base_address(pdev, 2),
1867 bptr->length2));
1868
1869 DEBUGPRINT((KERN_ALERT "auraXX20n: interrupt is %i.\n", pdev->irq));
1870 bus = pdev->bus->number;
1871 devfn = pdev->devfn;
1872 DEBUGPRINT((KERN_ALERT "auraXX20n: bus is %x, slot is %x.\n", bus, PCI_SLOT(devfn)));
1873 pcibios_read_config_word(bus, devfn, PCI_COMMAND, &pci_command);
1874 #if 0
1875 /* The Aurora card does not act as a PCI master
1876 * ugh!!
1877 */
1878 new_command = pci_command | PCI_COMMAND_MASTER;
1879 if(pci_command != new_command)
1880 {
1881 DEBUGPRINT((KERN_ALERT
1882 "auraXX20n: the PCI BIOS has not enabled this device!"
1883 " Updating PCI command %4.4x->%4.4x.\n",
1884 pci_command,
1885 new_command));
1886 pcibios_write_config_word(bus, devfn, PCI_COMMAND,
1887 new_command);
1888 }
1889 else
1890 {
1891 DEBUGPRINT
1892 ((KERN_ALERT
1893 "auraXX20n: the PCI BIOS has enabled this device as master!\n"));
1894 }
1895 #endif
1896 if((pci_command & PCI_COMMAND_MASTER) != PCI_COMMAND_MASTER)
1897 {
1898 DEBUGPRINT((KERN_ALERT "auraXX20n: Aurora card is not a bus master.\n"));
1899 }
1900
1901 pcibios_read_config_byte(bus, devfn, PCI_LATENCY_TIMER,
1902 &pci_latency);
1903 if (pci_latency < 32)
1904 {
1905 DEBUGPRINT
1906 ((KERN_ALERT
1907 "auraXX20n: PCI latency timer (CFLT) is low at %i.\n", pci_latency));
1908 /* may need to change the latency */
1909 #if 0
1910 pcibios_write_config_byte(bus, devfn, PCI_LATENCY_TIMER, 32);
1911 #endif
1912 }
1913 else
1914 {
1915 DEBUGPRINT((KERN_ALERT
1916 "auraXX20n: PCI latency timer (CFLT) is %#x.\n",
1917 pci_latency));
1918 }
1919 bptr->virtbaseaddress0 = ioremap_nocache(pci_base_address(pdev, 0),
1920 bptr->length0);
1921 if(bptr->virtbaseaddress0 == NULL)
1922 {
1923 printk(KERN_ALERT
1924 "auraXX20n: unable to remap physical address %p.\n",
1925 (void*) pci_base_address(pdev, 0));
1926
1927 goto MULTIPORTRESTART;
1928 }
1929
1930 bptr->b_bridge = (PLX9050*) bptr->virtbaseaddress0; /* MAKE SURE INTS ARE OFF */
1931 writel(PLX_INT_OFF, &(bptr->b_bridge->intr));
1932
1933 printk(KERN_ALERT
1934 "auraXX20n: remapped physical address %p to virtual address %p.\n",
1935 (void*) pci_base_address(pdev, 0), (void*) bptr->virtbaseaddress0);
1936
1937 dump_ati_adapter_registers((unsigned int*) bptr->virtbaseaddress0, bptr->length0);
1938
1939 if(*(unsigned int*)bptr->virtbaseaddress0 == -1) /* XP7 problem? */
1940 {
1941 printk(KERN_ALERT
1942 "auraXX20n: unable to access PLX 9050 registers at %p.\n",
1943 (void*)bptr->virtbaseaddress0);
1944 printk(KERN_ALERT "auraXX20n: unmapping virtual address %p.\n",
1945 (void*)bptr->virtbaseaddress0);
1946 iounmap((void*)bptr->virtbaseaddress0);
1947 bptr->virtbaseaddress0 = 0;
1948
1949 goto MULTIPORTRESTART;
1950 }
1951
1952 bptr->virtbaseaddress2 = ioremap_nocache(pci_base_address(pdev, 2),
1953 bptr->length2);
1954 if(bptr->virtbaseaddress2 == NULL)
1955 {
1956 printk(KERN_ALERT
1957 "auraXX20n: unable to remap physical address %p.\n",
1958 (void*) pci_base_address(pdev, 2));
1959 printk(KERN_ALERT "auraXX20n: unmapping virtual address %p.\n",
1960 (void*)bptr->virtbaseaddress0);
1961 iounmap((void*)bptr->virtbaseaddress0);
1962 bptr->virtbaseaddress0 = 0;
1963
1964 goto MULTIPORTRESTART;
1965 }
1966
1967 DEBUGPRINT((KERN_ALERT
1968 "auraXX20n: remapped physical address %p to virtual address %p.\n",
1969 (void*) pci_base_address(pdev, 2), (void*) bptr->virtbaseaddress2));
1970
1971 if (!plx9050_eprom_read(&((PLX9050*)(bptr->virtbaseaddress0))->ctrl,
1972 (unsigned short*) bptr->b_eprom,
1973 (unsigned char) 0, EPROM9050_SIZE))
1974 {
1975 printk(KERN_ALERT "auraXX20n: Could not read serial eprom.\n");
1976 iounmap((void*)bptr->virtbaseaddress0);
1977 bptr->virtbaseaddress0 = 0;
1978 iounmap((void*)bptr->virtbaseaddress2);
1979 bptr->virtbaseaddress2 = 0;
1980
1981 goto MULTIPORTRESTART;
1982 }
1983
1984 printk(KERN_ALERT "auraXX20n: dumping serial eprom.\n");
1985 dump_ati_adapter_registers((unsigned int*) bptr->b_eprom, 2 * EPROM9050_SIZE);
1986
1987 if(*(unsigned int*)bptr->b_eprom != PCIMEMVALIDMULTI) /* bridge problem? */
1988 {
1989 printk(KERN_ALERT "auraXX20n: unable to access valid serial eprom data.\n");
1990 iounmap((void*)bptr->virtbaseaddress0);
1991 bptr->virtbaseaddress0 = 0;
1992 iounmap((void*)bptr->virtbaseaddress2);
1993 bptr->virtbaseaddress2 = 0;
1994
1995 goto MULTIPORTRESTART;
1996 }
1997
1998 if(((unsigned short*) bptr->b_eprom)[EPROMPREFETCHOFFSET] & PREFETCHBIT)
1999 {
2000 ++sab8253x_rebootflag;
2001 printk(KERN_ALERT "8253x: eeprom programmed for prefetchable memory resources; must reprogram!!\n");
2002 plx9050_eprom_cmd(&((PLX9050*)(bptr->virtbaseaddress0))->ctrl,
2003 NM93_WENCMD, NM93_WENADDR, 0);
2004 plx9050_eprom_cmd(&((PLX9050*)(bptr->virtbaseaddress0))->ctrl,
2005 NM93_WRITECMD,
2006 9,
2007 (((unsigned short*) bptr->b_eprom)[EPROMPREFETCHOFFSET] & (~PREFETCHBIT)));
2008 plx9050_eprom_cmd(&((PLX9050*)(bptr->virtbaseaddress0))->ctrl,
2009 NM93_WDSCMD, NM93_WDSADDR, 0);
2010 }
2011
2012 /* get SYNC and ONEPORT values */
2013
2014 control = readl(&((PLX9050*)(bptr->virtbaseaddress0))->ctrl);
2015 /* note we use the actual address
2016 * of the control register in
2017 * memory
2018 */
2019
2020 if(control & AURORA_MULTI_SYNCBIT)
2021 {
2022 does_sync = 0;
2023 }
2024 else
2025 {
2026 does_sync = 1;
2027 }
2028
2029 if(control & AURORA_MULTI_1PORTBIT)
2030 {
2031 use_1port = 1;
2032 }
2033 else
2034 {
2035 use_1port = 0;
2036 }
2037
2038
2039 /* Figure out the board */
2040 switch(bptr->length2)
2041 {
2042 case AURORA_4X20_SIZE:
2043 if(does_sync)
2044 {
2045 bptr->b_type = BD_4520P;
2046 bptr->b_nchips = 2;
2047 bptr->b_nports = 4;
2048 bptr->b_flags = BD_SYNC;
2049 bptr->b_cimbase = NULL;
2050 bptr->board_number = BD4520Pcounter; /* keep track of boardnumber for naming devices */
2051 ++BD4520Pcounter;
2052 printk(KERN_ALERT "auraXX20n: Found Saturn 4520P.\n");
2053 }
2054 else
2055 {
2056 bptr->b_type = BD_4020P;
2057 bptr->b_nchips = 2;
2058 bptr->b_nports = 4;
2059 bptr->b_flags = 0x0;
2060 bptr->b_cimbase = NULL;
2061 bptr->board_number = BD4020Pcounter;
2062 ++BD4020Pcounter;
2063 printk(KERN_ALERT "auraXX20n: Found Apollo 4020P.\n");
2064 }
2065 break;
2066 case AURORA_8X20_SIZE:
2067 if(does_sync)
2068 {
2069 bptr->b_type = BD_8520P;
2070 bptr->b_nchips = 1;
2071 bptr->b_nports = 8;
2072 bptr->b_flags = BD_SYNC;
2073 bptr->b_cimbase = NULL;
2074 bptr->board_number = BD8520Pcounter;
2075 ++BD8520Pcounter;
2076 printk(KERN_ALERT "auraXX20n: Found Saturn 8520P.\n");
2077 }
2078 else
2079 {
2080 bptr->b_type = BD_8020P;
2081 bptr->b_nchips = 1;
2082 bptr->b_nports = 8;
2083 bptr->b_flags = 0x0;
2084 bptr->b_cimbase = NULL;
2085 bptr->board_number = BD8020Pcounter;
2086 ++BD8020Pcounter;
2087 printk(KERN_ALERT "auraXX20n: Found Apollo 8020P.\n");
2088 }
2089 break;
2090 case AURORA_2X20_SIZE:
2091 if(does_sync)
2092 {
2093 if(use_1port)
2094 {
2095 bptr->b_type = BD_1520P;
2096 printk(KERN_ALERT "auraXX20n: Found Saturn 1520P.\n");
2097 bptr->b_nchips = 1;
2098 bptr->b_nports = 1;
2099 bptr->b_flags = BD_SYNC;
2100 bptr->b_cimbase = NULL;
2101 bptr->board_number = BD1520Pcounter;
2102 ++BD1520Pcounter;
2103 printk(KERN_ALERT "auraXX20n: Found Saturn 1520P.\n");
2104 }
2105 else
2106 {
2107 bptr->b_type = BD_2520P;
2108 bptr->b_nchips = 1;
2109 bptr->b_nports = 2;
2110 bptr->b_flags = BD_SYNC;
2111 bptr->b_cimbase = NULL;
2112 bptr->board_number = BD2520Pcounter;
2113 ++BD2520Pcounter;
2114 printk(KERN_ALERT "auraXX20n: Found Saturn 2520P.\n");
2115 }
2116 }
2117 else
2118 {
2119 if(use_1port)
2120 {
2121 bptr->b_type = BD_1020P;
2122 bptr->b_nchips = 1;
2123 bptr->b_nports = 1;
2124 bptr->b_flags = 0x0;
2125 bptr->b_cimbase = NULL;
2126 bptr->board_number = BD1020Pcounter;
2127 ++BD1020Pcounter;
2128 printk(KERN_ALERT "auraXX20n: Found Apollo 1020P.\n");
2129 }
2130 else
2131 {
2132 bptr->b_type = BD_2020P;
2133 bptr->b_nchips = 1;
2134 bptr->b_nports = 2;
2135 bptr->b_flags = 0x0;
2136 bptr->b_cimbase = NULL;
2137 bptr->board_number = BD2020Pcounter;
2138 ++BD2020Pcounter;
2139 printk(KERN_ALERT "auraXX20n: Found Apollo 2020P.\n");
2140 }
2141 }
2142 break;
2143 default:
2144 printk(KERN_ALERT "Error: Board could not be identified\n");
2145 iounmap((void*)bptr->virtbaseaddress0);
2146 bptr->virtbaseaddress0 = 0;
2147 iounmap((void*)bptr->virtbaseaddress2);
2148 bptr->virtbaseaddress2 = 0;
2149
2150 goto MULTIPORTRESTART;
2151 }
2152 /* Let's get the clockrate right -- ugh!*/
2153
2154 bptr->b_clkspeed = bptr->b_eprom[AURORA_MULTI_EPROM_CLKLSW/2];
2155
2156 if(bptr->b_clkspeed == -1) /* misprogrammed -- ugh. */
2157 {
2158 switch(bptr->b_type)
2159 {
2160 case BD_8520P:
2161 case BD_8020P:
2162 bptr->b_clkspeed = AURORA_MULTI_CLKSPEED/4;
2163 break;
2164 default:
2165 bptr->b_clkspeed = AURORA_MULTI_CLKSPEED;
2166 break;
2167
2168 }
2169 printk(KERN_ALERT "auraXX20n: UNKNOWN CLOCKSPEED -- ASSUMING %ld.\n", bptr->b_clkspeed);
2170
2171 plx9050_eprom_cmd(&((PLX9050*)(bptr->virtbaseaddress0))->ctrl,
2172 NM93_WENCMD, NM93_WENADDR, 0);
2173 plx9050_eprom_cmd(&((PLX9050*)(bptr->virtbaseaddress0))->ctrl,
2174 NM93_WRITECMD,
2175 54, (unsigned short) bptr->b_clkspeed);
2176 plx9050_eprom_cmd(&((PLX9050*)(bptr->virtbaseaddress0))->ctrl,
2177 NM93_WRITECMD,
2178 55, (bptr->b_clkspeed >> 16));
2179 plx9050_eprom_cmd(&((PLX9050*)(bptr->virtbaseaddress0))->ctrl,
2180 NM93_WDSCMD, NM93_WDSADDR, 0);
2181 }
2182
2183 return bptr;
2184 }
2185
2186 #if LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 0)
2187 #ifdef MODULE
init_module(void)2188 int init_module(void) /* all OS */
2189 #else
2190 int auraXX20_probe(struct net_device *devp) /* passed default device structure */
2191 #endif
2192 #else
2193 static int __init auraXX20_probe(void) /* legacy device initialization 2.4.* */
2194 #endif
2195 {
2196 SAB_BOARD *boardptr;
2197 SAB_PORT *portptr;
2198 struct net_device *dev;
2199 unsigned int result;
2200 unsigned int namelength;
2201 unsigned int portno;
2202 int intr_val;
2203
2204 int mp_probe_count = 0; /* multiport count */
2205 int cp_probe_count = 0; /* compact pci count */
2206 int wm_probe_count = 0; /* wan multiserver count */
2207
2208 printk(KERN_ALERT "aurora interea miseris mortalibus almam extulerat lucem\n");
2209 printk(KERN_ALERT " referens opera atque labores\n");
2210
2211 memset(AuraBoardESCC8IrqRoot, 0, sizeof(AuraBoardESCC8IrqRoot));
2212 memset(AuraBoardESCC2IrqRoot, 0, sizeof(AuraBoardESCC2IrqRoot));
2213 memset(AuraBoardMCSIrqRoot, 0, sizeof(AuraBoardMCSIrqRoot));
2214
2215 #if !defined(MODULE) && (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 0))
2216 if(do_probe == 0)
2217 return -1; /* only allow to be called one 2.2.* */
2218 do_probe = 0;
2219 #endif
2220
2221 fn_init_crc_table(); /* used in faking ethernet packets for */
2222 /* the network driver -- crcs are currently */
2223 /* not being checked by this software */
2224 /* but is good to have them in case a frame */
2225 /* passes through a WAN LAN bridge */
2226
2227 sab8253x_setup_ttydriver(); /* add synchronous tty and synchronous network
2228 driver initialization */
2229
2230 AuraBoardRoot = NULL; /* basic lists */
2231 AuraChipRoot = NULL;
2232 AuraPortRoot = NULL;
2233 NumSab8253xPorts = 0;
2234
2235 AuraXX20DriverParams.debug = auraXX20n_debug;
2236 AuraXX20DriverParams.listsize = sab8253xn_listsize;
2237
2238 if(auraXX20n_name != 0)
2239 {
2240 #if LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 0)
2241 auraXX20n_prototype.name = auraXX20n_name;
2242 #else
2243 strcpy(auraXX20n_prototype.name, auraXX20n_name);
2244 #endif
2245 }
2246
2247 /* find all multiport cards */
2248 XX20lastpdev = NULL;
2249 while(1)
2250 {
2251 boardptr = find_ati_multiport_card();
2252 if(boardptr == NULL)
2253 {
2254 printk(KERN_ALERT
2255 "auraXX20n: found %d AURAXX20 multiport device%s.\n",
2256 mp_probe_count, ((mp_probe_count == 1) ? "" : "s"));
2257 break;
2258 }
2259 boardptr->nextboard = AuraBoardRoot;
2260 AuraBoardRoot = boardptr;
2261 printk(KERN_ALERT "auraXX20n: found AURAXX20 multiport device #%d.\n",
2262 mp_probe_count);
2263 ++mp_probe_count;
2264 }
2265
2266 /* find all cpci cards */
2267 XX20lastpdev = NULL;
2268 while(1)
2269 {
2270 boardptr = find_ati_cpci_card();
2271 if(boardptr == NULL)
2272 {
2273 printk(KERN_ALERT
2274 "auraXX20n: found %d AURAXX20 CPCI device%s.\n",
2275 cp_probe_count, ((cp_probe_count == 1) ? "" : "s"));
2276 break;
2277 }
2278 boardptr->nextboard = AuraBoardRoot;
2279 AuraBoardRoot = boardptr;
2280 printk(KERN_ALERT "auraXX20n: found AURAXX20 CPCI device #%d.\n",
2281 cp_probe_count);
2282 ++cp_probe_count;
2283 }
2284 /* find all WAN MS cards */
2285 XX20lastpdev = NULL;
2286 while(1)
2287 {
2288 boardptr = find_ati_wanms_card();
2289 if(boardptr == NULL)
2290 {
2291 printk(KERN_ALERT
2292 "auraXX20n: found %d AURAXX20 WANMS device%s.\n",
2293 wm_probe_count, ((wm_probe_count == 1) ? "" : "s"));
2294 break;
2295 }
2296 boardptr->nextboard = AuraBoardRoot;
2297 AuraBoardRoot = boardptr;
2298 printk(KERN_ALERT "auraXX20n: found AURAXX20 WANMS device #%d.\n",
2299 wm_probe_count);
2300 ++wm_probe_count;
2301 }
2302
2303 /* Now do the chips! */
2304
2305 for(boardptr = AuraBoardRoot; boardptr != NULL; boardptr = boardptr->nextboard)
2306 {
2307 SetupAllChips(boardptr); /* sets up the ports on the chips */
2308 }
2309
2310 /* set up global driver structures
2311 * for async tty, call out device
2312 * for sync tty and for network device
2313 */
2314
2315 /* NOW TURN ON THE PLX INTS */
2316 /* note all port ints (only receive right now)
2317 * are off */
2318
2319 /* interrupts cannot be turned on by port
2320 this seems to be the only sensible place
2321 to do it*/
2322
2323 /* only at this point is the number of
2324 * ttys to be created known. */
2325
2326 if(finish_sab8253x_setup_ttydriver() == -1) /* only as many termios are allocated */
2327 /* as needed */
2328 {
2329 return 0;
2330 }
2331 for(portno = 0, portptr = AuraPortRoot; portptr != NULL; ++portno, portptr = portptr->next)
2332 {
2333 portptr->line = portno; /* set up the line number == minor dev associated with port */
2334 portptr->sigmode = sab8253x_default_sp502_mode;
2335 /* if we have SP502s let getty work with RS232 by default */
2336 /* unless overridden in module setup. */
2337 }
2338 /* Now lets set up the network devices */
2339 for(portno = 0, portptr = AuraPortRoot; portptr != NULL; ++portno, portptr = portptr->next)
2340 {
2341
2342 dev = kmalloc(sizeof(struct net_device), GFP_KERNEL);
2343 if(!dev)
2344 {
2345 break;
2346 }
2347 memset(dev, 0, sizeof(struct net_device));
2348 *dev = auraXX20n_prototype;
2349 #if LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 0)
2350 dev->name = kmalloc(IFNAMSIZ+1, GFP_KERNEL);
2351 if(!dev->name)
2352 {
2353 kfree(dev);
2354 break;
2355 }
2356 #endif
2357 namelength = MIN(strlen(auraXX20n_prototype.name), IFNAMSIZ);
2358 strcpy(dev->name, auraXX20n_prototype.name);
2359 sprintf(&dev->name[namelength-1], "%3.3d", portno);
2360
2361 #if 1
2362 current_sab_port = portptr;
2363 #else
2364 dev->priv = portptr;
2365 #endif
2366 result = register_netdev(dev);
2367 if(result)
2368 { /* if we run into some internal kernel limit */
2369 break;
2370 }
2371 printk(KERN_ALERT "sab8253xn: found sab8253x network device #%d.\n",
2372 portno);
2373 }
2374 printk(KERN_ALERT
2375 "sab8253xn: found %d sab8253x network device%s.\n",
2376 portno, ((portno == 1) ? "" : "s"));
2377
2378 /* Now lets set up the character device */
2379
2380 if(sab8253xc_name)
2381 {
2382 result = register_chrdev(sab8253xc_major, sab8253xc_name, &sab8253xc_fops);
2383 if(result < 0)
2384 {
2385 sab8253xc_major = result;
2386 printk(KERN_ALERT "Could not install sab8253xc device.\n");
2387 }
2388 else if(result > 0)
2389 {
2390 sab8253xc_major = result;
2391 }
2392 }
2393
2394 for(boardptr = AuraBoardRoot; boardptr != NULL; boardptr = boardptr->nextboard)
2395 { /* let's set up port interrupt lists */
2396 intr_val = boardptr->b_irq;
2397 if((intr_val < 0) || (intr_val >= NUMINTS))
2398 {
2399 printk(KERN_ALERT "sab8253xn: bad interrupt %i board %p.\n", intr_val, boardptr);
2400 continue;
2401 }
2402 switch(boardptr->b_type)
2403 {
2404 case BD_WANMCS:
2405 boardptr->next_on_interrupt = AuraBoardMCSIrqRoot[intr_val];
2406 AuraBoardMCSIrqRoot[intr_val] = boardptr;
2407 break;
2408 case BD_8520P:
2409 case BD_8520CP:
2410 boardptr->next_on_interrupt = AuraBoardESCC8IrqRoot[intr_val];
2411 AuraBoardESCC8IrqRoot[intr_val] = boardptr;
2412 break;
2413 default:
2414 boardptr->next_on_interrupt = AuraBoardESCC2IrqRoot[intr_val];
2415 AuraBoardESCC2IrqRoot[intr_val] = boardptr;
2416 break;
2417 }
2418 }
2419
2420 for(intr_val = 0; intr_val < NUMINTS; ++intr_val) /* trying to install as few int handlers as possible */
2421 { /* one for each group of boards on a given irq */
2422 if((AuraBoardESCC2IrqRoot[intr_val] != NULL) || (AuraBoardESCC8IrqRoot[intr_val] != NULL) ||
2423 (AuraBoardMCSIrqRoot[intr_val] != NULL))
2424 {
2425 if (request_irq(intr_val, sab8253x_interrupt, SA_SHIRQ,
2426 "sab8253x", &AuraBoardESCC2IrqRoot[intr_val]) == 0)
2427 /* interrupts on perboard basis
2428 * cycle through chips and then
2429 * ports */
2430 /* NOTE PLX INTS ARE OFF -- so turn them on */
2431 {
2432 for(boardptr = AuraBoardESCC2IrqRoot[intr_val]; boardptr != NULL;
2433 boardptr = boardptr->next_on_interrupt)
2434 {
2435 writel(PLX_INT_ON, &(boardptr->b_bridge->intr));
2436 }
2437 for(boardptr = AuraBoardESCC8IrqRoot[intr_val]; boardptr != NULL;
2438 boardptr = boardptr->next_on_interrupt)
2439 {
2440 writel(PLX_INT_ON, &(boardptr->b_bridge->intr));
2441 }
2442 for(boardptr = AuraBoardMCSIrqRoot[intr_val]; boardptr != NULL;
2443 boardptr = boardptr->next_on_interrupt)
2444 {
2445 /* write to the MIC csr to reset the PCI interrupt */
2446 writeb(0, (unsigned char*)(boardptr->MICCMD_REG + MICCMD_MICCSR));
2447
2448 /* now, write to the CIM interrupt ena to re-enable interrupt generation */
2449 writeb(0, (unsigned char*)(boardptr->CIMCMD_REG + CIMCMD_WRINTENA));
2450
2451 /* now, activate PCI interrupts */
2452 writel(AMCC_AOINTPINENA, (unsigned int*)(boardptr->AMCC_REG + AMCC_INTCSR));
2453 }
2454 }
2455 else
2456 {
2457 printk(KERN_ALERT "Unable to get interrupt, board set up not complete %i.\n", intr_val);
2458 }
2459 }
2460 }
2461
2462 /* all done! a lot of work */
2463
2464 #if !defined(MODULE) && (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 0))
2465 return -1; /* otherwise 2.2 probe uses up
2466 * a default device structure*/
2467 #else
2468 return 0;
2469 #endif
2470 }
2471
2472 #if LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 0)
2473 #ifdef MODULE
2474 /* cleanup module/free up virtual memory */
2475 /* space*/
cleanup_module(void)2476 void cleanup_module(void)
2477 #endif
2478 #else
2479 void auraXX20_cleanup(void)
2480 #endif
2481 {
2482 SAB_BOARD *boardptr;
2483 SAB_CHIP *chipptr;
2484 SAB_PORT *portptr;
2485 AURA_CIM *cimptr;
2486 int intr_val;
2487 extern void sab8253x_cleanup_ttydriver(void);
2488
2489 printk(KERN_ALERT "auraXX20n: unloading AURAXX20 driver.\n");
2490
2491 sab8253x_cleanup_ttydriver(); /* clean up tty */
2492
2493 /* unallocate and turn off ints */
2494 for(intr_val = 0; intr_val < NUMINTS; ++intr_val)
2495 {
2496 if((AuraBoardESCC2IrqRoot[intr_val] != NULL) || (AuraBoardESCC8IrqRoot[intr_val] != NULL) ||
2497 (AuraBoardMCSIrqRoot[intr_val] != NULL))
2498 {
2499 for(boardptr = AuraBoardESCC2IrqRoot[intr_val]; boardptr != NULL;
2500 boardptr = boardptr->next_on_interrupt)
2501 {
2502 writel(PLX_INT_OFF, &(boardptr->b_bridge->intr));
2503 }
2504 for(boardptr = AuraBoardESCC8IrqRoot[intr_val]; boardptr != NULL;
2505 boardptr = boardptr->next_on_interrupt)
2506 {
2507 writel(PLX_INT_OFF, &(boardptr->b_bridge->intr));
2508 }
2509 for(boardptr = AuraBoardMCSIrqRoot[intr_val]; boardptr != NULL;
2510 boardptr = boardptr->next_on_interrupt)
2511 {
2512 writel(AMCC_INT_OFF, (unsigned int*)(boardptr->AMCC_REG + AMCC_INTCSR));
2513 (void) wanmcs_reset(boardptr);
2514 writel(AMCC_INT_OFF, (unsigned int*)(boardptr->AMCC_REG + AMCC_INTCSR));
2515 }
2516
2517 free_irq(intr_val, &AuraBoardESCC2IrqRoot[intr_val]); /* free up board int
2518 * note that if two boards
2519 * share an int, two int
2520 * handlers were registered
2521 *
2522 */
2523 }
2524 }
2525
2526 /* disable chips and free board memory*/
2527 while(AuraBoardRoot)
2528 {
2529 boardptr = AuraBoardRoot;
2530 for(chipptr = boardptr->board_chipbase; chipptr != NULL; chipptr = chipptr->next_by_board)
2531 {
2532 (*chipptr->int_disable)(chipptr); /* make sure no ints can come int */
2533 }
2534 AuraBoardRoot = boardptr->nextboard;
2535 if(boardptr->b_type == BD_WANMCS)
2536 {
2537 if(boardptr->virtbaseaddress0 != 0)
2538 {
2539 DEBUGPRINT((KERN_ALERT "auraXX20n: unmapping virtual address %p.\n",
2540 (void*)boardptr->virtbaseaddress0));
2541 iounmap((void*)boardptr->virtbaseaddress0);
2542 boardptr->virtbaseaddress0 = 0;
2543 }
2544
2545 if(boardptr->virtbaseaddress1 != 0)
2546 {
2547 DEBUGPRINT((KERN_ALERT "auraXX20n: unmapping virtual address %p.\n",
2548 (void*)boardptr->virtbaseaddress1));
2549 iounmap((void*)boardptr->virtbaseaddress1);
2550 boardptr->virtbaseaddress1 = 0;
2551 }
2552
2553 if(boardptr->virtbaseaddress2 != 0)
2554 {
2555 DEBUGPRINT((KERN_ALERT "auraXX20n: unmapping virtual address %p.\n",
2556 (void*)boardptr->virtbaseaddress2));
2557 iounmap((void*)boardptr->virtbaseaddress2);
2558 boardptr->virtbaseaddress2 = 0;
2559 }
2560
2561 if(boardptr->virtbaseaddress3 != 0)
2562 {
2563 DEBUGPRINT((KERN_ALERT "auraXX20n: unmapping virtual address %p.\n",
2564 (void*)boardptr->virtbaseaddress3));
2565 iounmap((void*)boardptr->virtbaseaddress3);
2566 boardptr->virtbaseaddress3 = 0;
2567 }
2568
2569 }
2570 else /* everything but wan multichannel servers */
2571 {
2572 if(boardptr->virtbaseaddress0)
2573 {
2574 DEBUGPRINT((KERN_ALERT
2575 "auraXX20n: unmapping virtual address %p.\n",
2576 (void*)boardptr->virtbaseaddress0));
2577 iounmap((void*)boardptr->virtbaseaddress0);
2578 boardptr->virtbaseaddress0 = 0;
2579 }
2580 if(boardptr->virtbaseaddress2)
2581 {
2582 DEBUGPRINT((KERN_ALERT
2583 "auraXX20n: unmapping virtual address %p.\n",
2584 (void*)boardptr->virtbaseaddress2));
2585 iounmap((void*)boardptr->virtbaseaddress2);
2586 boardptr->virtbaseaddress2 = 0;
2587 }
2588 }
2589 kfree(boardptr);
2590 }
2591
2592 while(AuraCimRoot)
2593 {
2594 cimptr = AuraCimRoot;
2595 AuraCimRoot = cimptr->next;
2596 kfree(cimptr);
2597 }
2598
2599
2600 while(AuraChipRoot) /* free chip memory */
2601 {
2602 chipptr = AuraChipRoot;
2603 AuraChipRoot = chipptr->next;
2604 kfree(chipptr);
2605 }
2606
2607 if(sab8253xc_name && (sab8253xc_major > 0)) /* unregister the chr device */
2608 {
2609 unregister_chrdev(sab8253xc_major, sab8253xc_name);
2610 }
2611
2612 while(Sab8253xRoot) /* free up network stuff */
2613 {
2614 SAB_PORT *priv;
2615 priv = (SAB_PORT *)Sab8253xRoot->priv;
2616 unregister_netdev(Sab8253xRoot);
2617 #if LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 0)
2618 kfree(Sab8253xRoot.name);
2619 #endif
2620 kfree(Sab8253xRoot);
2621 Sab8253xRoot = priv->next_dev;
2622 }
2623
2624 while(AuraPortRoot) /* free up port memory */
2625 {
2626 portptr = AuraPortRoot;
2627 AuraPortRoot = portptr->next;
2628 if(portptr->dcontrol2.receive)
2629 {
2630 kfree(portptr->dcontrol2.receive);
2631 }
2632 if(portptr->dcontrol2.transmit)
2633 {
2634 kfree(portptr->dcontrol2.transmit);
2635 }
2636 kfree(portptr);
2637 }
2638 }
2639
2640 /*
2641 * Hardware dependent read and write functions.
2642 * We have functions to write/read a byte, write/read
2643 * a word and read and write the FIFO
2644 */
2645
2646
2647 /***************************************************************************
2648 * aura_readb: Function to read a byte on a 4X20P, 8X20P or Sun serial
2649 *
2650 *
2651 * Parameters :
2652 * port: The port being accessed
2653 * reg: The address of the register
2654 *
2655 * Return value : The value of the register.
2656 *
2657 * Prerequisite : The port must have been opened
2658 *
2659 * Remark :
2660 *
2661 * Author : fw
2662 *
2663 * Revision : Oct 10 2000, creation
2664 ***************************************************************************/
2665
aura_readb(struct sab_port * port,unsigned char * reg)2666 static unsigned char aura_readb(struct sab_port *port, unsigned char *reg)
2667 {
2668 return readb(reg);
2669 }
2670
2671 /***************************************************************************
2672 * aura_writeb: Function to write a byte on a 4X20P, 8X20P or Sun serial
2673 *
2674 *
2675 * Parameters :
2676 * port: The port being accessed
2677 * reg: The address of the register
2678 * val: The value to put into the register
2679 *
2680 * Return value : None
2681 *
2682 * Prerequisite : The port must have been opened
2683 *
2684 * Remark :
2685 *
2686 * Author : fw
2687 *
2688 * Revision : Oct 10 2000, creation
2689 ***************************************************************************/
2690
aura_writeb(struct sab_port * port,unsigned char * reg,unsigned char val)2691 static void aura_writeb(struct sab_port *port, unsigned char *reg,unsigned char val)
2692 {
2693 writeb(val,reg);
2694 }
2695
2696 /***************************************************************************
2697 * aura_readw: Function to read a word on a 4X20P, 8X20P or Sun serial
2698 *
2699 *
2700 * Parameters :
2701 * port: The port being accessed
2702 * reg: The address of the hw memory to access
2703 *
2704 * Return value : The value of the memory area.
2705 *
2706 * Prerequisite : The port must have been opened
2707 *
2708 * Remark :
2709 *
2710 * Author : fw
2711 *
2712 * Revision : Oct 10 2000, creation
2713 ***************************************************************************/
aura_readw(struct sab_port * port,unsigned short * reg)2714 static unsigned short aura_readw(struct sab_port *port, unsigned short *reg)
2715 {
2716 return readw(reg);
2717 }
2718
2719 /***************************************************************************
2720 * aura_writew: Function to write a word on a 4X20P, 8X20P or Sun serial
2721 *
2722 *
2723 * Parameters :
2724 * port: The port being accessed
2725 * reg: The address of the hw memory to access
2726 * val: The value to put into the register
2727 *
2728 * Return value : The value of the memory area.
2729 *
2730 * Prerequisite : The port must have been opened
2731 *
2732 * Remark :
2733 *
2734 * Author : fw
2735 *
2736 * Revision : Oct 10 2000, creation
2737 ***************************************************************************/
2738
aura_writew(struct sab_port * port,unsigned short * reg,unsigned short val)2739 static void aura_writew(struct sab_port *port, unsigned short *reg,unsigned short val)
2740 {
2741 writew(val,reg);
2742 }
2743
2744 /***************************************************************************
2745 * aura_readfifo: Function to read the FIFO on a 4X20P, 8X20P or Sun serial
2746 *
2747 *
2748 * Parameters :
2749 * port: The port being accessed
2750 * buf: The address of a buffer where we should put
2751 * what we read
2752 * nbytes: How many chars to read.
2753 *
2754 * Return value : none
2755 *
2756 * Prerequisite : The port must have been opened
2757 *
2758 * Remark :
2759 *
2760 * Author : fw
2761 *
2762 * Revision : Oct 13 2000, creation
2763 ***************************************************************************/
aura_readfifo(struct sab_port * port,unsigned char * buf,unsigned int nbytes)2764 static void aura_readfifo(struct sab_port *port, unsigned char *buf, unsigned int nbytes)
2765 {
2766 int i;
2767 unsigned short *wptr = (unsigned short*) buf;
2768 int nwords = ((nbytes+1)/2);
2769 for(i = 0; i < nwords; i ++)
2770 {
2771 wptr[i] = readw(((unsigned short *)port->regs));
2772 }
2773 }
2774
2775 /***************************************************************************
2776 * aura_writefifo: Function to write the FIFO on a 4X20P, 8X20P or Sun serial
2777 *
2778 *
2779 * Parameters :
2780 * port: The port being accessed
2781 *
2782 * Return value : none
2783 *
2784 * Prerequisite : The port must have been opened
2785 *
2786 * Remark :
2787 *
2788 * Author : fw
2789 *
2790 * Revision : Oct 13 2000, creation
2791 ***************************************************************************/
aura_writefifo(struct sab_port * port)2792 static void aura_writefifo(struct sab_port *port)
2793 {
2794 int i,max,maxw;
2795 unsigned short *wptr;
2796 unsigned char buffer[32];
2797
2798 if(port->xmit_cnt <= 0)
2799 {
2800 return;
2801 }
2802 max= (port->xmit_fifo_size < port->xmit_cnt) ? port->xmit_fifo_size : port->xmit_cnt;
2803
2804 for (i = 0; i < max; i++)
2805 {
2806 buffer[i] = port->xmit_buf[port->xmit_tail++];
2807 port->xmit_tail &= (SAB8253X_XMIT_SIZE - 1);
2808 port->icount.tx++;
2809 port->xmit_cnt--;
2810 }
2811
2812 maxw = max/2;
2813 wptr = (unsigned short*) buffer;
2814
2815 for(i = 0; i < maxw; ++i)
2816 {
2817 writew(wptr[i], (unsigned short *)port->regs);
2818 }
2819
2820 if(max & 1)
2821 {
2822 writeb(buffer[max-1], (unsigned char*)port->regs);
2823 }
2824 }
2825
2826 /***************************************************************************
2827 * wmsaura_readb: Function to read a byte on a LMS, WMS
2828 *
2829 *
2830 * Parameters :
2831 * port: The port being accessed
2832 * reg: The address of the register
2833 *
2834 * Return value : The value of the register.
2835 *
2836 * Prerequisite : The port must have been opened
2837 *
2838 * Remark : TO BE IMPLEMENTED
2839 *
2840 * Author : fw
2841 *
2842 * Revision : Oct 10 2000, creation
2843 ***************************************************************************/
2844
wmsaura_readb(struct sab_port * port,unsigned char * reg)2845 static unsigned char wmsaura_readb(struct sab_port *port, unsigned char *reg)
2846 {
2847 return readb((unsigned char*) (((unsigned int) reg) + CIMCMD_RDREGB));
2848 }
2849
2850 /***************************************************************************
2851 * wmsaura_writeb: Function to write a byte on a LMS, WMS
2852 *
2853 *
2854 * Parameters :
2855 * port: The port being accessed
2856 * reg: The address of the register
2857 * val: The value to put into the register
2858 *
2859 * Return value : None
2860 *
2861 * Prerequisite : The port must have been opened
2862 *
2863 * Remark : TO BE IMPLEMENTED
2864 *
2865 * Author : fw
2866 *
2867 * Revision : Oct 10 2000, creation
2868 ***************************************************************************/
2869
wmsaura_writeb(struct sab_port * port,unsigned char * reg,unsigned char val)2870 static void wmsaura_writeb(struct sab_port *port, unsigned char *reg,unsigned char val)
2871 {
2872 writeb(val, (unsigned char*) (((unsigned int) reg) + CIMCMD_WRREGB));
2873 }
2874
2875 /***************************************************************************
2876 * wmsaura_readw: Function to read a word on a LMS, WMS
2877 *
2878 *
2879 * Parameters :
2880 * port: The port being accessed
2881 * reg: The address of the hw memory to access
2882 *
2883 * Return value : The value of the memory area.
2884 *
2885 * Prerequisite : The port must have been opened
2886 *
2887 * Remark : TO BE IMPLEMENTED
2888 *
2889 * Author : fw
2890 *
2891 * Revision : Oct 10 2000, creation
2892 ***************************************************************************/
wmsaura_readw(struct sab_port * port,unsigned short * reg)2893 static unsigned short wmsaura_readw(struct sab_port *port, unsigned short *reg)
2894 {
2895 unsigned short readval;
2896 unsigned int address;
2897 address = (unsigned int) reg;
2898
2899 readval = readb((unsigned char*) (address + CIMCMD_RDREGB));
2900 ++address;
2901 return (readval | (readb((unsigned char*) (address + CIMCMD_RDREGB)) << 8));
2902 }
2903
2904 /***************************************************************************
2905 * wmsaura_writew: Function to write a word on a LMS, WMS
2906 *
2907 *
2908 * Parameters :
2909 * port: The port being accessed
2910 * reg: The address of the hw memory to access
2911 * val: The value to put into the register
2912 *
2913 * Return value : The value of the memory area.
2914 *
2915 * Prerequisite : The port must have been opened
2916 *
2917 * Remark : TO BE IMPLEMENTED
2918 *
2919 * Author : fw
2920 *
2921 * Revision : Oct 10 2000, creation
2922 ***************************************************************************/
2923
wmsaura_writew(struct sab_port * port,unsigned short * reg,unsigned short val)2924 static void wmsaura_writew(struct sab_port *port, unsigned short *reg, unsigned short val)
2925 {
2926 unsigned char vallow;
2927 unsigned char valhigh;
2928 unsigned int address;
2929
2930 address = (unsigned int) reg;
2931
2932 vallow = (unsigned char) val;
2933 valhigh = (unsigned char) (val >> 8);
2934
2935 writeb(vallow, (unsigned char*) (address + CIMCMD_WRREGB));
2936 ++address;
2937 writeb(valhigh, (unsigned char*) (address + CIMCMD_WRREGB));
2938 }
2939
wmsaura_readfifo(struct sab_port * port,unsigned char * buf,unsigned int nbytes)2940 static void wmsaura_readfifo(struct sab_port *port, unsigned char *buf, unsigned int nbytes)
2941 {
2942 #ifdef FIFO_DIRECT
2943 unsigned short fifo[32/2]; /* this array is word aligned
2944 * buf may not be word aligned*/
2945 unsigned int nwords;
2946 int i;
2947 int wcount;
2948 unsigned int address;
2949
2950 if (nbytes == 0)
2951 {
2952 return;
2953 }
2954
2955 wcount = ((nbytes + 1) >> 1);
2956 /* Read the thing into the local FIFO and copy it out. */
2957 address = (unsigned int) port->regs;
2958
2959 for(i = 0; i < wcount; ++i)
2960 {
2961 fifo[i] = readw((unsigned short*)(address + CIMCMD_RDFIFOW));
2962 }
2963
2964 memcpy((unsigned char*) buf, (unsigned char*) &(fifo[0]), (unsigned int) nbytes);
2965
2966 #else /* FIFO_DIRECT */
2967 unsigned short fifo[32/2];
2968 int i;
2969 int wcount;
2970 SAB_BOARD *bptr;
2971 unsigned int channel;
2972
2973 if (nbytes == 0)
2974 {
2975 return;
2976 }
2977
2978 bptr = port->board;
2979 wcount = ((nbytes + 1) >> 1);
2980 channel = (((unsigned char*) port->regs) - bptr->CIMCMD_REG); /* should be properly shifted */
2981
2982 /*
2983 * Trigger a cache read by writing the nwords - 1 to the
2984 * magic place.
2985 */
2986
2987 writeb((unsigned char) wcount, bptr->MICCMD_REG + (MICCMD_CACHETRIG + channel));
2988
2989 /*
2990 * Now, read out the contents.
2991 */
2992
2993 channel >>= 1;
2994
2995 for(i = 0; i < wcount; ++i)
2996 {
2997 fifo[i] = readw((unsigned short*)(bptr->FIFOCACHE_REG + (channel + (i << 1))));
2998 }
2999
3000 memcpy((unsigned char*) buf, (unsigned char*) &(fifo[0]), (unsigned int) nbytes);
3001 #endif /* !FIFO_DIRECT */
3002 }
3003
wmsaura_writefifo(struct sab_port * port)3004 static void wmsaura_writefifo(struct sab_port *port)
3005 {
3006 unsigned short fifo[32/2];
3007 unsigned char* fifob = (unsigned char*) fifo;
3008 int i,max;
3009 int wcount;
3010 unsigned int address;
3011
3012 if(port->xmit_cnt <= 0)
3013 {
3014 return;
3015 }
3016 max = (port->xmit_fifo_size < port->xmit_cnt) ? port->xmit_fifo_size:port->xmit_cnt;
3017 for (i = 0; i < max; i++)
3018 {
3019 fifob[i] = port->xmit_buf[port->xmit_tail++];
3020 port->xmit_tail &= (SAB8253X_XMIT_SIZE - 1);
3021 port->icount.tx++;
3022 port->xmit_cnt--;
3023 }
3024
3025 wcount = (max >> 1);
3026 /* Copy from the linear local FIFO into the hardware fifo. */
3027 address = (unsigned int) port->regs;
3028
3029 for(i = 0; i < wcount; ++i)
3030 {
3031 writew(fifo[i], (unsigned short*)(address + CIMCMD_WRFIFOW));
3032 }
3033 if(max & 1) /* odd byte */
3034 {
3035 --max;
3036 writeb(fifob[max], (unsigned short*)(address + CIMCMD_WRFIFOB));
3037 }
3038 }
3039
3040 module_init(auraXX20_probe);
3041 module_exit(auraXX20_cleanup);
3042 MODULE_DESCRIPTION("Aurora Multiport Multiprotocol Serial Driver");
3043 MODULE_AUTHOR("Joachim Martillo <martillo@telfordtools.com>");
3044 MODULE_LICENSE("GPL");
3045