1 /*
2 * x86 SMP booting functions
3 *
4 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
5 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
6 *
7 * Much of the core SMP work is based on previous work by Thomas Radke, to
8 * whom a great many thanks are extended.
9 *
10 * Thanks to Intel for making available several different Pentium,
11 * Pentium Pro and Pentium-II/Xeon MP machines.
12 * Original development of Linux SMP code supported by Caldera.
13 *
14 * This code is released under the GNU General Public License version 2 or
15 * later.
16 *
17 * Fixes
18 * Felix Koop : NR_CPUS used properly
19 * Jose Renau : Handle single CPU case.
20 * Alan Cox : By repeated request 8) - Total BogoMIP report.
21 * Greg Wright : Fix for kernel stacks panic.
22 * Erich Boleyn : MP v1.4 and additional changes.
23 * Matthias Sattler : Changes for 2.1 kernel map.
24 * Michel Lespinasse : Changes for 2.1 kernel map.
25 * Michael Chastain : Change trampoline.S to gnu as.
26 * Alan Cox : Dumb bug: 'B' step PPro's are fine
27 * Ingo Molnar : Added APIC timers, based on code
28 * from Jose Renau
29 * Ingo Molnar : various cleanups and rewrites
30 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
31 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
32 * Martin J. Bligh : Added support for multi-quad systems
33 */
34
35 #include <linux/config.h>
36 #include <linux/init.h>
37
38 #include <linux/mm.h>
39 #include <linux/kernel_stat.h>
40 #include <linux/smp_lock.h>
41 #include <linux/irq.h>
42 #include <linux/bootmem.h>
43
44 #include <linux/delay.h>
45 #include <linux/mc146818rtc.h>
46 #include <asm/mtrr.h>
47 #include <asm/pgalloc.h>
48 #include <asm/smpboot.h>
49
50 /* Set if we find a B stepping CPU */
51 static int smp_b_stepping;
52
53 /* Setup configured maximum number of CPUs to activate */
54 unsigned int max_cpus = NR_CPUS;
55
56 /* Total count of live CPUs */
57 int smp_num_cpus = 1;
58
59 /* Number of siblings per CPU package */
60 int smp_num_siblings = 1;
61 int __initdata phys_proc_id[NR_CPUS]; /* Package ID of each logical CPU */
62
63 /* Bitmask of currently online CPUs */
64 unsigned long cpu_online_map;
65
66 static volatile unsigned long cpu_callin_map;
67 static volatile unsigned long cpu_callout_map;
68
69 /* Per CPU bogomips and other parameters */
70 struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned;
71
72 /* Set when the idlers are all forked */
73 int smp_threads_ready;
74
75 /*
76 * Setup routine for controlling SMP activation
77 *
78 * Command-line option of "nosmp" or "maxcpus=0" will disable SMP
79 * activation entirely (the MPS table probe still happens, though).
80 */
81
nosmp(char * str)82 static int __init nosmp(char *str)
83 {
84 max_cpus = 0;
85 return 1;
86 }
87
88 __setup("nosmp", nosmp);
89
90 /*
91 * Trampoline 80x86 program as an array.
92 */
93
94 extern unsigned char trampoline_data [];
95 extern unsigned char trampoline_end [];
96 static unsigned char *trampoline_base;
97
98 /*
99 * Currently trivial. Write the real->protected mode
100 * bootstrap into the page concerned. The caller
101 * has made sure it's suitably aligned.
102 */
103
setup_trampoline(void)104 static unsigned long __init setup_trampoline(void)
105 {
106 memcpy(trampoline_base, trampoline_data, trampoline_end - trampoline_data);
107 return virt_to_phys(trampoline_base);
108 }
109
110 /*
111 * We are called very early to get the low memory for the
112 * SMP bootup trampoline page.
113 */
smp_alloc_memory(void)114 void __init smp_alloc_memory(void)
115 {
116 trampoline_base = (void *) alloc_bootmem_low_pages(PAGE_SIZE);
117 /*
118 * Has to be in very low memory so we can execute
119 * real-mode AP code.
120 */
121 if (__pa(trampoline_base) >= 0x9F000)
122 BUG();
123 }
124
125 /*
126 * The bootstrap kernel entry code has set these up. Save them for
127 * a given CPU
128 */
129
smp_store_cpu_info(int id)130 void __init smp_store_cpu_info(int id)
131 {
132 struct cpuinfo_x86 *c = cpu_data + id;
133
134 *c = boot_cpu_data;
135 c->pte_quick = 0;
136 c->pmd_quick = 0;
137 c->pgd_quick = 0;
138 c->pgtable_cache_sz = 0;
139 identify_cpu(c);
140 /*
141 * Mask B, Pentium, but not Pentium MMX
142 */
143 if (c->x86_vendor == X86_VENDOR_INTEL &&
144 c->x86 == 5 &&
145 c->x86_mask >= 1 && c->x86_mask <= 4 &&
146 c->x86_model <= 3)
147 /*
148 * Remember we have B step Pentia with bugs
149 */
150 smp_b_stepping = 1;
151 }
152
153 /*
154 * Architecture specific routine called by the kernel just before init is
155 * fired off. This allows the BP to have everything in order [we hope].
156 * At the end of this all the APs will hit the system scheduling and off
157 * we go. Each AP will load the system gdt's and jump through the kernel
158 * init into idle(). At this point the scheduler will one day take over
159 * and give them jobs to do. smp_callin is a standard routine
160 * we use to track CPUs as they power up.
161 */
162
163 static atomic_t smp_commenced = ATOMIC_INIT(0);
164
smp_commence(void)165 void __init smp_commence(void)
166 {
167 /*
168 * Lets the callins below out of their loop.
169 */
170 Dprintk("Setting commenced=1, go go go\n");
171
172 wmb();
173 atomic_set(&smp_commenced,1);
174 }
175
176 /*
177 * TSC synchronization.
178 *
179 * We first check wether all CPUs have their TSC's synchronized,
180 * then we print a warning if not, and always resync.
181 */
182
183 static atomic_t tsc_start_flag = ATOMIC_INIT(0);
184 static atomic_t tsc_count_start = ATOMIC_INIT(0);
185 static atomic_t tsc_count_stop = ATOMIC_INIT(0);
186 static unsigned long long tsc_values[NR_CPUS];
187
188 #define NR_LOOPS 5
189
190 extern unsigned long fast_gettimeoffset_quotient;
191
192 /*
193 * accurate 64-bit/32-bit division, expanded to 32-bit divisions and 64-bit
194 * multiplication. Not terribly optimized but we need it at boot time only
195 * anyway.
196 *
197 * result == a / b
198 * == (a1 + a2*(2^32)) / b
199 * == a1/b + a2*(2^32/b)
200 * == a1/b + a2*((2^32-1)/b) + a2/b + (a2*((2^32-1) % b))/b
201 * ^---- (this multiplication can overflow)
202 */
203
div64(unsigned long long a,unsigned long b0)204 static unsigned long long __init div64 (unsigned long long a, unsigned long b0)
205 {
206 unsigned int a1, a2;
207 unsigned long long res;
208
209 a1 = ((unsigned int*)&a)[0];
210 a2 = ((unsigned int*)&a)[1];
211
212 res = a1/b0 +
213 (unsigned long long)a2 * (unsigned long long)(0xffffffff/b0) +
214 a2 / b0 +
215 (a2 * (0xffffffff % b0)) / b0;
216
217 return res;
218 }
219
synchronize_tsc_bp(void)220 static void __init synchronize_tsc_bp (void)
221 {
222 int i;
223 unsigned long long t0;
224 unsigned long long sum, avg;
225 long long delta;
226 unsigned long one_usec;
227 int buggy = 0;
228
229 printk("checking TSC synchronization across CPUs: ");
230
231 one_usec = ((1<<30)/fast_gettimeoffset_quotient)*(1<<2);
232
233 atomic_set(&tsc_start_flag, 1);
234 wmb();
235
236 /*
237 * We loop a few times to get a primed instruction cache,
238 * then the last pass is more or less synchronized and
239 * the BP and APs set their cycle counters to zero all at
240 * once. This reduces the chance of having random offsets
241 * between the processors, and guarantees that the maximum
242 * delay between the cycle counters is never bigger than
243 * the latency of information-passing (cachelines) between
244 * two CPUs.
245 */
246 for (i = 0; i < NR_LOOPS; i++) {
247 /*
248 * all APs synchronize but they loop on '== num_cpus'
249 */
250 while (atomic_read(&tsc_count_start) != smp_num_cpus-1) mb();
251 atomic_set(&tsc_count_stop, 0);
252 wmb();
253 /*
254 * this lets the APs save their current TSC:
255 */
256 atomic_inc(&tsc_count_start);
257
258 rdtscll(tsc_values[smp_processor_id()]);
259 /*
260 * We clear the TSC in the last loop:
261 */
262 if (i == NR_LOOPS-1)
263 write_tsc(0, 0);
264
265 /*
266 * Wait for all APs to leave the synchronization point:
267 */
268 while (atomic_read(&tsc_count_stop) != smp_num_cpus-1) mb();
269 atomic_set(&tsc_count_start, 0);
270 wmb();
271 atomic_inc(&tsc_count_stop);
272 }
273
274 sum = 0;
275 for (i = 0; i < smp_num_cpus; i++) {
276 t0 = tsc_values[i];
277 sum += t0;
278 }
279 avg = div64(sum, smp_num_cpus);
280
281 sum = 0;
282 for (i = 0; i < smp_num_cpus; i++) {
283 delta = tsc_values[i] - avg;
284 if (delta < 0)
285 delta = -delta;
286 /*
287 * We report bigger than 2 microseconds clock differences.
288 */
289 if (delta > 2*one_usec) {
290 long realdelta;
291 if (!buggy) {
292 buggy = 1;
293 printk("\n");
294 }
295 realdelta = div64(delta, one_usec);
296 if (tsc_values[i] < avg)
297 realdelta = -realdelta;
298
299 printk("BIOS BUG: CPU#%d improperly initialized, has %ld usecs TSC skew! FIXED.\n",
300 i, realdelta);
301 }
302
303 sum += delta;
304 }
305 if (!buggy)
306 printk("passed.\n");
307 }
308
synchronize_tsc_ap(void)309 static void __init synchronize_tsc_ap (void)
310 {
311 int i;
312
313 /*
314 * smp_num_cpus is not necessarily known at the time
315 * this gets called, so we first wait for the BP to
316 * finish SMP initialization:
317 */
318 while (!atomic_read(&tsc_start_flag)) mb();
319
320 for (i = 0; i < NR_LOOPS; i++) {
321 atomic_inc(&tsc_count_start);
322 while (atomic_read(&tsc_count_start) != smp_num_cpus) mb();
323
324 rdtscll(tsc_values[smp_processor_id()]);
325 if (i == NR_LOOPS-1)
326 write_tsc(0, 0);
327
328 atomic_inc(&tsc_count_stop);
329 while (atomic_read(&tsc_count_stop) != smp_num_cpus) mb();
330 }
331 }
332 #undef NR_LOOPS
333
334 extern void calibrate_delay(void);
335
336 static atomic_t init_deasserted;
337
smp_callin(void)338 void __init smp_callin(void)
339 {
340 int cpuid, phys_id;
341 unsigned long timeout;
342
343 /*
344 * If waken up by an INIT in an 82489DX configuration
345 * we may get here before an INIT-deassert IPI reaches
346 * our local APIC. We have to wait for the IPI or we'll
347 * lock up on an APIC access.
348 */
349 if (!clustered_apic_mode)
350 while (!atomic_read(&init_deasserted));
351
352 /*
353 * (This works even if the APIC is not enabled.)
354 */
355 phys_id = GET_APIC_ID(apic_read(APIC_ID));
356 cpuid = current->processor;
357 if (test_and_set_bit(cpuid, &cpu_online_map)) {
358 printk("huh, phys CPU#%d, CPU#%d already present??\n",
359 phys_id, cpuid);
360 BUG();
361 }
362 Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
363
364 /*
365 * STARTUP IPIs are fragile beasts as they might sometimes
366 * trigger some glue motherboard logic. Complete APIC bus
367 * silence for 1 second, this overestimates the time the
368 * boot CPU is spending to send the up to 2 STARTUP IPIs
369 * by a factor of two. This should be enough.
370 */
371
372 /*
373 * Waiting 2s total for startup (udelay is not yet working)
374 */
375 timeout = jiffies + 2*HZ;
376 while (time_before(jiffies, timeout)) {
377 /*
378 * Has the boot CPU finished it's STARTUP sequence?
379 */
380 if (test_bit(cpuid, &cpu_callout_map))
381 break;
382 rep_nop();
383 }
384
385 if (!time_before(jiffies, timeout)) {
386 printk("BUG: CPU%d started up but did not get a callout!\n",
387 cpuid);
388 BUG();
389 }
390
391 /*
392 * the boot CPU has finished the init stage and is spinning
393 * on callin_map until we finish. We are free to set up this
394 * CPU, first the APIC. (this is probably redundant on most
395 * boards)
396 */
397
398 Dprintk("CALLIN, before setup_local_APIC().\n");
399 /*
400 * Because we use NMIs rather than the INIT-STARTUP sequence to
401 * bootstrap the CPUs, the APIC may be in a weird state. Kick it.
402 */
403 if (clustered_apic_mode)
404 clear_local_APIC();
405 setup_local_APIC();
406
407 __sti();
408
409 #ifdef CONFIG_MTRR
410 /*
411 * Must be done before calibration delay is computed
412 */
413 mtrr_init_secondary_cpu ();
414 #endif
415 /*
416 * Get our bogomips.
417 */
418 calibrate_delay();
419 Dprintk("Stack at about %p\n",&cpuid);
420
421 /*
422 * Save our processor parameters
423 */
424 smp_store_cpu_info(cpuid);
425
426 /*
427 * Allow the master to continue.
428 */
429 set_bit(cpuid, &cpu_callin_map);
430
431 /*
432 * Synchronize the TSC with the BP
433 */
434 if (cpu_has_tsc)
435 synchronize_tsc_ap();
436 }
437
438 int cpucount;
439
440 extern int cpu_idle(void);
441
442 /*
443 * Activate a secondary processor.
444 */
start_secondary(void * unused)445 int __init start_secondary(void *unused)
446 {
447 /*
448 * Dont put anything before smp_callin(), SMP
449 * booting is too fragile that we want to limit the
450 * things done here to the most necessary things.
451 */
452 cpu_init();
453 smp_callin();
454 while (!atomic_read(&smp_commenced))
455 rep_nop();
456 /*
457 * low-memory mappings have been cleared, flush them from
458 * the local TLBs too.
459 */
460 local_flush_tlb();
461
462 return cpu_idle();
463 }
464
465 /*
466 * Everything has been set up for the secondary
467 * CPUs - they just need to reload everything
468 * from the task structure
469 * This function must not return.
470 */
initialize_secondary(void)471 void __init initialize_secondary(void)
472 {
473 /*
474 * We don't actually need to load the full TSS,
475 * basically just the stack pointer and the eip.
476 */
477
478 asm volatile(
479 "movl %0,%%esp\n\t"
480 "jmp *%1"
481 :
482 :"r" (current->thread.esp),"r" (current->thread.eip));
483 }
484
485 extern struct {
486 void * esp;
487 unsigned short ss;
488 } stack_start;
489
fork_by_hand(void)490 static int __init fork_by_hand(void)
491 {
492 struct pt_regs regs;
493 /*
494 * don't care about the eip and regs settings since
495 * we'll never reschedule the forked task.
496 */
497 return do_fork(CLONE_VM|CLONE_PID, 0, ®s, 0);
498 }
499
500 /* which physical APIC ID maps to which logical CPU number */
501 volatile int physical_apicid_2_cpu[MAX_APICID];
502 /* which logical CPU number maps to which physical APIC ID */
503 volatile int cpu_2_physical_apicid[NR_CPUS];
504
505 /* which logical APIC ID maps to which logical CPU number */
506 volatile int logical_apicid_2_cpu[MAX_APICID];
507 /* which logical CPU number maps to which logical APIC ID */
508 volatile int cpu_2_logical_apicid[NR_CPUS];
509
init_cpu_to_apicid(void)510 static inline void init_cpu_to_apicid(void)
511 /* Initialize all maps between cpu number and apicids */
512 {
513 int apicid, cpu;
514
515 for (apicid = 0; apicid < MAX_APICID; apicid++) {
516 physical_apicid_2_cpu[apicid] = BAD_APICID;
517 logical_apicid_2_cpu[apicid] = BAD_APICID;
518 }
519 for (cpu = 0; cpu < NR_CPUS; cpu++) {
520 cpu_2_physical_apicid[cpu] = BAD_APICID;
521 cpu_2_logical_apicid[cpu] = BAD_APICID;
522 }
523 }
524
map_cpu_to_boot_apicid(int cpu,int apicid)525 static inline void map_cpu_to_boot_apicid(int cpu, int apicid)
526 /*
527 * set up a mapping between cpu and apicid. Uses logical apicids for multiquad,
528 * else physical apic ids
529 */
530 {
531 if (clustered_apic_mode == CLUSTERED_APIC_NUMAQ) {
532 logical_apicid_2_cpu[apicid] = cpu;
533 cpu_2_logical_apicid[cpu] = apicid;
534 } else {
535 physical_apicid_2_cpu[apicid] = cpu;
536 cpu_2_physical_apicid[cpu] = apicid;
537 }
538 }
539
unmap_cpu_to_boot_apicid(int cpu,int apicid)540 static inline void unmap_cpu_to_boot_apicid(int cpu, int apicid)
541 /*
542 * undo a mapping between cpu and apicid. Uses logical apicids for multiquad,
543 * else physical apic ids
544 */
545 {
546 if (clustered_apic_mode == CLUSTERED_APIC_NUMAQ) {
547 logical_apicid_2_cpu[apicid] = BAD_APICID;
548 cpu_2_logical_apicid[cpu] = BAD_APICID;
549 } else {
550 physical_apicid_2_cpu[apicid] = BAD_APICID;
551 cpu_2_physical_apicid[cpu] = BAD_APICID;
552 }
553 }
554
555 #if APIC_DEBUG
inquire_remote_apic(int apicid)556 static inline void inquire_remote_apic(int apicid)
557 {
558 int i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
559 char *names[] = { "ID", "VERSION", "SPIV" };
560 int timeout, status;
561
562 printk("Inquiring remote APIC #%d...\n", apicid);
563
564 for (i = 0; i < sizeof(regs) / sizeof(*regs); i++) {
565 printk("... APIC #%d %s: ", apicid, names[i]);
566
567 /*
568 * Wait for idle.
569 */
570 apic_wait_icr_idle();
571
572 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
573 apic_write_around(APIC_ICR, APIC_DM_REMRD | regs[i]);
574
575 timeout = 0;
576 do {
577 udelay(100);
578 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
579 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
580
581 switch (status) {
582 case APIC_ICR_RR_VALID:
583 status = apic_read(APIC_RRR);
584 printk("%08x\n", status);
585 break;
586 default:
587 printk("failed\n");
588 }
589 }
590 }
591 #endif
592
wakeup_secondary_via_NMI(int logical_apicid)593 static int wakeup_secondary_via_NMI(int logical_apicid)
594 /*
595 * Poke the other CPU in the eye to wake it up. Remember that the normal
596 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
597 * won't ... remember to clear down the APIC, etc later.
598 */
599 {
600 unsigned long send_status = 0, accept_status = 0;
601 int timeout, maxlvt;
602
603 /* Target chip */
604 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(logical_apicid));
605
606 /* Boot on the stack */
607 /* Kick the second */
608 apic_write_around(APIC_ICR, APIC_DM_NMI | APIC_DEST_LOGICAL);
609
610 Dprintk("Waiting for send to finish...\n");
611 timeout = 0;
612 do {
613 Dprintk("+");
614 udelay(100);
615 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
616 } while (send_status && (timeout++ < 1000));
617
618 /*
619 * Give the other CPU some time to accept the IPI.
620 */
621 udelay(200);
622 /*
623 * Due to the Pentium erratum 3AP.
624 */
625 maxlvt = get_maxlvt();
626 if (maxlvt > 3) {
627 apic_read_around(APIC_SPIV);
628 apic_write(APIC_ESR, 0);
629 }
630 accept_status = (apic_read(APIC_ESR) & 0xEF);
631 Dprintk("NMI sent.\n");
632
633 if (send_status)
634 printk("APIC never delivered???\n");
635 if (accept_status)
636 printk("APIC delivery error (%lx).\n", accept_status);
637
638 return (send_status | accept_status);
639 }
640
wakeup_secondary_via_INIT(int phys_apicid,unsigned long start_eip)641 static int wakeup_secondary_via_INIT(int phys_apicid, unsigned long start_eip)
642 {
643 unsigned long send_status = 0, accept_status = 0;
644 int maxlvt, timeout, num_starts, j;
645
646 Dprintk("Asserting INIT.\n");
647
648 /*
649 * Turn INIT on target chip
650 */
651 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
652
653 /*
654 * Send IPI
655 */
656 apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT
657 | APIC_DM_INIT);
658
659 Dprintk("Waiting for send to finish...\n");
660 timeout = 0;
661 do {
662 Dprintk("+");
663 udelay(100);
664 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
665 } while (send_status && (timeout++ < 1000));
666
667 mdelay(10);
668
669 Dprintk("Deasserting INIT.\n");
670
671 /* Target chip */
672 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
673
674 /* Send IPI */
675 apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
676
677 Dprintk("Waiting for send to finish...\n");
678 timeout = 0;
679 do {
680 Dprintk("+");
681 udelay(100);
682 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
683 } while (send_status && (timeout++ < 1000));
684
685 atomic_set(&init_deasserted, 1);
686
687 /*
688 * Should we send STARTUP IPIs ?
689 *
690 * Determine this based on the APIC version.
691 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
692 */
693 if (APIC_INTEGRATED(apic_version[phys_apicid]))
694 num_starts = 2;
695 else
696 num_starts = 0;
697
698 /*
699 * Run STARTUP IPI loop.
700 */
701 Dprintk("#startup loops: %d.\n", num_starts);
702
703 maxlvt = get_maxlvt();
704
705 for (j = 1; j <= num_starts; j++) {
706 Dprintk("Sending STARTUP #%d.\n",j);
707 apic_read_around(APIC_SPIV);
708 apic_write(APIC_ESR, 0);
709 apic_read(APIC_ESR);
710 Dprintk("After apic_write.\n");
711
712 /*
713 * STARTUP IPI
714 */
715
716 /* Target chip */
717 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
718
719 /* Boot on the stack */
720 /* Kick the second */
721 apic_write_around(APIC_ICR, APIC_DM_STARTUP
722 | (start_eip >> 12));
723
724 /*
725 * Give the other CPU some time to accept the IPI.
726 */
727 udelay(300);
728
729 Dprintk("Startup point 1.\n");
730
731 Dprintk("Waiting for send to finish...\n");
732 timeout = 0;
733 do {
734 Dprintk("+");
735 udelay(100);
736 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
737 } while (send_status && (timeout++ < 1000));
738
739 /*
740 * Give the other CPU some time to accept the IPI.
741 */
742 udelay(200);
743 /*
744 * Due to the Pentium erratum 3AP.
745 */
746 if (maxlvt > 3) {
747 apic_read_around(APIC_SPIV);
748 apic_write(APIC_ESR, 0);
749 }
750 accept_status = (apic_read(APIC_ESR) & 0xEF);
751 if (send_status || accept_status)
752 break;
753 }
754 Dprintk("After Startup.\n");
755
756 if (send_status)
757 printk("APIC never delivered???\n");
758 if (accept_status)
759 printk("APIC delivery error (%lx).\n", accept_status);
760
761 return (send_status | accept_status);
762 }
763
764 extern unsigned long cpu_initialized;
765
do_boot_cpu(int apicid)766 static void __init do_boot_cpu (int apicid)
767 /*
768 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
769 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
770 */
771 {
772 struct task_struct *idle;
773 unsigned long boot_error = 0;
774 int timeout, cpu;
775 unsigned long start_eip;
776 unsigned short nmi_high = 0, nmi_low = 0;
777
778 cpu = ++cpucount;
779 /*
780 * We can't use kernel_thread since we must avoid to
781 * reschedule the child.
782 */
783 if (fork_by_hand() < 0)
784 panic("failed fork for CPU %d", cpu);
785
786 /*
787 * We remove it from the pidhash and the runqueue
788 * once we got the process:
789 */
790 idle = init_task.prev_task;
791 if (!idle)
792 panic("No idle process for CPU %d", cpu);
793
794 idle->processor = cpu;
795 idle->cpus_runnable = 1 << cpu; /* we schedule the first task manually */
796
797 map_cpu_to_boot_apicid(cpu, apicid);
798
799 idle->thread.eip = (unsigned long) start_secondary;
800
801 del_from_runqueue(idle);
802 unhash_process(idle);
803 init_tasks[cpu] = idle;
804
805 /* start_eip had better be page-aligned! */
806 start_eip = setup_trampoline();
807
808 /* So we see what's up */
809 printk("Booting processor %d/%d eip %lx\n", cpu, apicid, start_eip);
810 stack_start.esp = (void *) (1024 + PAGE_SIZE + (char *)idle);
811
812 /*
813 * This grunge runs the startup process for
814 * the targeted processor.
815 */
816
817 atomic_set(&init_deasserted, 0);
818
819 Dprintk("Setting warm reset code and vector.\n");
820
821 if (clustered_apic_mode == CLUSTERED_APIC_NUMAQ) {
822 /* stash the current NMI vector, so we can put things back */
823 nmi_high = *((volatile unsigned short *) TRAMPOLINE_HIGH);
824 nmi_low = *((volatile unsigned short *) TRAMPOLINE_LOW);
825 }
826
827 CMOS_WRITE(0xa, 0xf);
828 local_flush_tlb();
829 Dprintk("1.\n");
830 *((volatile unsigned short *) TRAMPOLINE_HIGH) = start_eip >> 4;
831 Dprintk("2.\n");
832 *((volatile unsigned short *) TRAMPOLINE_LOW) = start_eip & 0xf;
833 Dprintk("3.\n");
834
835 /*
836 * Be paranoid about clearing APIC errors.
837 */
838 if (!clustered_apic_mode && APIC_INTEGRATED(apic_version[apicid])) {
839 apic_read_around(APIC_SPIV);
840 apic_write(APIC_ESR, 0);
841 apic_read(APIC_ESR);
842 }
843
844 /*
845 * Status is now clean
846 */
847 boot_error = 0;
848
849 /*
850 * Starting actual IPI sequence...
851 */
852
853 if (clustered_apic_mode == CLUSTERED_APIC_NUMAQ)
854 boot_error = wakeup_secondary_via_NMI(apicid);
855 else
856 boot_error = wakeup_secondary_via_INIT(apicid, start_eip);
857
858 if (!boot_error) {
859 /*
860 * allow APs to start initializing.
861 */
862 Dprintk("Before Callout %d.\n", cpu);
863 set_bit(cpu, &cpu_callout_map);
864 Dprintk("After Callout %d.\n", cpu);
865
866 /*
867 * Wait 5s total for a response
868 */
869 for (timeout = 0; timeout < 50000; timeout++) {
870 if (test_bit(cpu, &cpu_callin_map))
871 break; /* It has booted */
872 udelay(100);
873 }
874
875 if (test_bit(cpu, &cpu_callin_map)) {
876 /* number CPUs logically, starting from 1 (BSP is 0) */
877 Dprintk("OK.\n");
878 printk("CPU%d: ", cpu);
879 print_cpu_info(&cpu_data[cpu]);
880 Dprintk("CPU has booted.\n");
881 } else {
882 boot_error= 1;
883 if (*((volatile unsigned char *)phys_to_virt(8192))
884 == 0xA5)
885 /* trampoline started but...? */
886 printk("Stuck ??\n");
887 else
888 /* trampoline code not run */
889 printk("Not responding.\n");
890 #if APIC_DEBUG
891 if (!clustered_apic_mode)
892 inquire_remote_apic(apicid);
893 #endif
894 }
895 }
896 if (boot_error) {
897 /* Try to put things back the way they were before ... */
898 unmap_cpu_to_boot_apicid(cpu, apicid);
899 clear_bit(cpu, &cpu_callout_map); /* was set here (do_boot_cpu()) */
900 clear_bit(cpu, &cpu_initialized); /* was set by cpu_init() */
901 clear_bit(cpu, &cpu_online_map); /* was set in smp_callin() */
902 cpucount--;
903 }
904
905 /* mark "stuck" area as not stuck */
906 *((volatile unsigned long *)phys_to_virt(8192)) = 0;
907
908 if(clustered_apic_mode == CLUSTERED_APIC_NUMAQ) {
909 printk("Restoring NMI vector\n");
910 *((volatile unsigned short *) TRAMPOLINE_HIGH) = nmi_high;
911 *((volatile unsigned short *) TRAMPOLINE_LOW) = nmi_low;
912 }
913 }
914
915 cycles_t cacheflush_time;
916
smp_tune_scheduling(void)917 static void smp_tune_scheduling (void)
918 {
919 unsigned long cachesize; /* kB */
920 unsigned long bandwidth = 350; /* MB/s */
921 /*
922 * Rough estimation for SMP scheduling, this is the number of
923 * cycles it takes for a fully memory-limited process to flush
924 * the SMP-local cache.
925 *
926 * (For a P5 this pretty much means we will choose another idle
927 * CPU almost always at wakeup time (this is due to the small
928 * L1 cache), on PIIs it's around 50-100 usecs, depending on
929 * the cache size)
930 */
931
932 if (!cpu_khz) {
933 /*
934 * this basically disables processor-affinity
935 * scheduling on SMP without a TSC.
936 */
937 cacheflush_time = 0;
938 return;
939 } else {
940 cachesize = boot_cpu_data.x86_cache_size;
941 if (cachesize == -1) {
942 cachesize = 16; /* Pentiums, 2x8kB cache */
943 bandwidth = 100;
944 }
945
946 cacheflush_time = (cpu_khz>>10) * (cachesize<<10) / bandwidth;
947 }
948
949 printk("per-CPU timeslice cutoff: %ld.%02ld usecs.\n",
950 (long)cacheflush_time/(cpu_khz/1000),
951 ((long)cacheflush_time*100/(cpu_khz/1000)) % 100);
952 }
953
954 /*
955 * Cycle through the processors sending APIC IPIs to boot each.
956 */
957
958 extern int prof_multiplier[NR_CPUS];
959 extern int prof_old_multiplier[NR_CPUS];
960 extern int prof_counter[NR_CPUS];
961
962 static int boot_cpu_logical_apicid;
963 /* Where the IO area was mapped on multiquad, always 0 otherwise */
964 void *xquad_portio;
965
966 int cpu_sibling_map[NR_CPUS] __cacheline_aligned;
967
smp_boot_cpus(void)968 void __init smp_boot_cpus(void)
969 {
970 int apicid, cpu, bit;
971
972 if ((clustered_apic_mode == CLUSTERED_APIC_NUMAQ) && (numnodes > 1)) {
973 printk("Remapping cross-quad port I/O for %d quads\n",
974 numnodes);
975 printk("xquad_portio vaddr 0x%08lx, len %08lx\n",
976 (u_long) xquad_portio,
977 (u_long) numnodes * XQUAD_PORTIO_LEN);
978 xquad_portio = ioremap (XQUAD_PORTIO_BASE,
979 numnodes * XQUAD_PORTIO_LEN);
980 }
981
982 #ifdef CONFIG_MTRR
983 /* Must be done before other processors booted */
984 mtrr_init_boot_cpu ();
985 #endif
986 /*
987 * Initialize the logical to physical CPU number mapping
988 * and the per-CPU profiling counter/multiplier
989 */
990
991 for (cpu = 0; cpu < NR_CPUS; cpu++) {
992 prof_counter[cpu] = 1;
993 prof_old_multiplier[cpu] = 1;
994 prof_multiplier[cpu] = 1;
995 }
996
997 init_cpu_to_apicid();
998
999 /*
1000 * Setup boot CPU information
1001 */
1002 smp_store_cpu_info(0); /* Final full version of the data */
1003 printk("CPU%d: ", 0);
1004 print_cpu_info(&cpu_data[0]);
1005
1006 /*
1007 * We have the boot CPU online for sure.
1008 */
1009 set_bit(0, &cpu_online_map);
1010 if (clustered_apic_mode == CLUSTERED_APIC_XAPIC)
1011 boot_cpu_logical_apicid = physical_to_logical_apicid(boot_cpu_physical_apicid);
1012 else
1013 boot_cpu_logical_apicid = logical_smp_processor_id();
1014 map_cpu_to_boot_apicid(0, boot_cpu_apicid);
1015
1016 global_irq_holder = 0;
1017 current->processor = 0;
1018 init_idle();
1019 smp_tune_scheduling();
1020
1021 /*
1022 * If we couldnt find an SMP configuration at boot time,
1023 * get out of here now!
1024 */
1025 if (!smp_found_config && !acpi_lapic) {
1026 printk(KERN_NOTICE "SMP motherboard not detected.\n");
1027 #ifndef CONFIG_VISWS
1028 io_apic_irqs = 0;
1029 #endif
1030 cpu_online_map = phys_cpu_present_map = 1;
1031 smp_num_cpus = 1;
1032 if (APIC_init_uniprocessor())
1033 printk(KERN_NOTICE "Local APIC not detected."
1034 " Using dummy APIC emulation.\n");
1035 goto smp_done;
1036 }
1037
1038 /*
1039 * Should not be necessary because the MP table should list the boot
1040 * CPU too, but we do it for the sake of robustness anyway.
1041 * Makes no sense to do this check in clustered apic mode, so skip it
1042 */
1043 if (!clustered_apic_mode &&
1044 !test_bit(boot_cpu_physical_apicid, &phys_cpu_present_map)) {
1045 printk("weird, boot CPU (#%d) not listed by the BIOS.\n",
1046 boot_cpu_physical_apicid);
1047 phys_cpu_present_map |= (1 << hard_smp_processor_id());
1048 }
1049
1050 /*
1051 * If we couldn't find a local APIC, then get out of here now!
1052 */
1053 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
1054 !test_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability)) {
1055 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
1056 boot_cpu_physical_apicid);
1057 printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n");
1058 #ifndef CONFIG_VISWS
1059 io_apic_irqs = 0;
1060 #endif
1061 cpu_online_map = phys_cpu_present_map = 1;
1062 smp_num_cpus = 1;
1063 goto smp_done;
1064 }
1065
1066 verify_local_APIC();
1067
1068 /*
1069 * If SMP should be disabled, then really disable it!
1070 */
1071 if (!max_cpus) {
1072 smp_found_config = 0;
1073 printk(KERN_INFO "SMP mode deactivated, forcing use of dummy APIC emulation.\n");
1074 #ifndef CONFIG_VISWS
1075 io_apic_irqs = 0;
1076 #endif
1077 cpu_online_map = phys_cpu_present_map = 1;
1078 smp_num_cpus = 1;
1079 goto smp_done;
1080 }
1081
1082 connect_bsp_APIC();
1083 setup_local_APIC();
1084
1085 if (GET_APIC_ID(apic_read(APIC_ID)) != boot_cpu_physical_apicid)
1086 BUG();
1087
1088 /*
1089 * Scan the CPU present map and fire up the other CPUs via do_boot_cpu
1090 *
1091 * In clustered apic mode, phys_cpu_present_map is a constructed thus:
1092 * bits 0-3 are quad0, 4-7 are quad1, etc. A perverse twist on the
1093 * clustered apic ID.
1094 */
1095 Dprintk("CPU present map: %lx\n", phys_cpu_present_map);
1096
1097 for (bit = 0; bit < BITS_PER_LONG; bit++) {
1098 apicid = cpu_present_to_apicid(bit);
1099
1100 /* don't try to boot BAD_APICID */
1101 if (apicid == BAD_APICID)
1102 continue;
1103 /*
1104 * Don't even attempt to start the boot CPU!
1105 */
1106 if (apicid == boot_cpu_apicid)
1107 continue;
1108
1109 if (!(phys_cpu_present_map & apicid_to_phys_cpu_present(apicid)))
1110 continue;
1111
1112 do_boot_cpu(apicid);
1113
1114 /*
1115 * Make sure we unmap all failed CPUs
1116 */
1117 if ((boot_apicid_to_cpu(apicid) == -1) &&
1118 (phys_cpu_present_map &
1119 apicid_to_phys_cpu_present(apicid)))
1120 printk("CPU #%d/0x%02x not responding - cannot use it.\n",
1121 bit, apicid);
1122 }
1123
1124 /*
1125 * Cleanup possible dangling ends...
1126 */
1127 #ifndef CONFIG_VISWS
1128 {
1129 /*
1130 * Install writable page 0 entry to set BIOS data area.
1131 */
1132 local_flush_tlb();
1133
1134 /*
1135 * Paranoid: Set warm reset code and vector here back
1136 * to default values.
1137 */
1138 CMOS_WRITE(0, 0xf);
1139
1140 *((volatile long *) phys_to_virt(0x467)) = 0;
1141 }
1142 #endif
1143
1144 /*
1145 * Allow the user to impress friends.
1146 */
1147
1148 Dprintk("Before bogomips.\n");
1149 {
1150 unsigned long bogosum = 0;
1151 for (cpu = 0; cpu < NR_CPUS; cpu++)
1152 if (cpu_online_map & (1<<cpu))
1153 bogosum += cpu_data[cpu].loops_per_jiffy;
1154 printk(KERN_INFO "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
1155 cpucount+1,
1156 bogosum/(500000/HZ),
1157 (bogosum/(5000/HZ))%100);
1158 Dprintk("Before bogocount - setting activated=1.\n");
1159 }
1160 smp_num_cpus = cpucount + 1;
1161
1162 if (smp_b_stepping)
1163 printk(KERN_WARNING "WARNING: SMP operation may be unreliable with B stepping processors.\n");
1164 Dprintk("Boot done.\n");
1165
1166 /*
1167 * If Hyper-Threading is avaialble, construct cpu_sibling_map[], so
1168 * that we can tell the sibling CPU efficiently.
1169 */
1170 if (test_bit(X86_FEATURE_HT, boot_cpu_data.x86_capability)
1171 && smp_num_siblings > 1) {
1172 for (cpu = 0; cpu < NR_CPUS; cpu++)
1173 cpu_sibling_map[cpu] = NO_PROC_ID;
1174
1175 for (cpu = 0; cpu < smp_num_cpus; cpu++) {
1176 int i;
1177
1178 for (i = 0; i < smp_num_cpus; i++) {
1179 if (i == cpu)
1180 continue;
1181 if (phys_proc_id[cpu] == phys_proc_id[i]) {
1182 cpu_sibling_map[cpu] = i;
1183 printk("cpu_sibling_map[%d] = %d\n", cpu, cpu_sibling_map[cpu]);
1184 break;
1185 }
1186 }
1187 if (cpu_sibling_map[cpu] == NO_PROC_ID) {
1188 smp_num_siblings = 1;
1189 printk(KERN_WARNING "WARNING: No sibling found for CPU %d.\n", cpu);
1190 }
1191 }
1192 }
1193
1194 #ifndef CONFIG_VISWS
1195 /*
1196 * Here we can be sure that there is an IO-APIC in the system. Let's
1197 * go and set it up:
1198 */
1199 if (!skip_ioapic_setup && nr_ioapics)
1200 setup_IO_APIC();
1201 #endif
1202
1203 /*
1204 * Set up all local APIC timers in the system:
1205 */
1206 setup_APIC_clocks();
1207
1208 /*
1209 * Synchronize the TSC with the AP
1210 */
1211 if (cpu_has_tsc && cpucount)
1212 synchronize_tsc_bp();
1213
1214 smp_done:
1215 zap_low_mappings();
1216 }
1217