1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * xHCI host controller driver
4  *
5  * Copyright (C) 2008 Intel Corp.
6  *
7  * Author: Sarah Sharp
8  * Some code borrowed from the Linux EHCI driver.
9  */
10 
11 
12 #include <linux/slab.h>
13 #include <asm/unaligned.h>
14 #include <linux/bitfield.h>
15 
16 #include "xhci.h"
17 #include "xhci-trace.h"
18 
19 #define	PORT_WAKE_BITS	(PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
20 #define	PORT_RWC_BITS	(PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
21 			 PORT_RC | PORT_PLC | PORT_PE)
22 
23 /* Default sublink speed attribute of each lane */
24 static u32 ssp_cap_default_ssa[] = {
25 	0x00050034, /* USB 3.0 SS Gen1x1 id:4 symmetric rx 5Gbps */
26 	0x000500b4, /* USB 3.0 SS Gen1x1 id:4 symmetric tx 5Gbps */
27 	0x000a4035, /* USB 3.1 SSP Gen2x1 id:5 symmetric rx 10Gbps */
28 	0x000a40b5, /* USB 3.1 SSP Gen2x1 id:5 symmetric tx 10Gbps */
29 	0x00054036, /* USB 3.2 SSP Gen1x2 id:6 symmetric rx 5Gbps */
30 	0x000540b6, /* USB 3.2 SSP Gen1x2 id:6 symmetric tx 5Gbps */
31 	0x000a4037, /* USB 3.2 SSP Gen2x2 id:7 symmetric rx 10Gbps */
32 	0x000a40b7, /* USB 3.2 SSP Gen2x2 id:7 symmetric tx 10Gbps */
33 };
34 
xhci_create_usb3x_bos_desc(struct xhci_hcd * xhci,char * buf,u16 wLength)35 static int xhci_create_usb3x_bos_desc(struct xhci_hcd *xhci, char *buf,
36 				      u16 wLength)
37 {
38 	struct usb_bos_descriptor	*bos;
39 	struct usb_ss_cap_descriptor	*ss_cap;
40 	struct usb_ssp_cap_descriptor	*ssp_cap;
41 	struct xhci_port_cap		*port_cap = NULL;
42 	u16				bcdUSB;
43 	u32				reg;
44 	u32				min_rate = 0;
45 	u8				min_ssid;
46 	u8				ssac;
47 	u8				ssic;
48 	int				offset;
49 	int				i;
50 
51 	/* BOS descriptor */
52 	bos = (struct usb_bos_descriptor *)buf;
53 	bos->bLength = USB_DT_BOS_SIZE;
54 	bos->bDescriptorType = USB_DT_BOS;
55 	bos->wTotalLength = cpu_to_le16(USB_DT_BOS_SIZE +
56 					USB_DT_USB_SS_CAP_SIZE);
57 	bos->bNumDeviceCaps = 1;
58 
59 	/* Create the descriptor for port with the highest revision */
60 	for (i = 0; i < xhci->num_port_caps; i++) {
61 		u8 major = xhci->port_caps[i].maj_rev;
62 		u8 minor = xhci->port_caps[i].min_rev;
63 		u16 rev = (major << 8) | minor;
64 
65 		if (i == 0 || bcdUSB < rev) {
66 			bcdUSB = rev;
67 			port_cap = &xhci->port_caps[i];
68 		}
69 	}
70 
71 	if (bcdUSB >= 0x0310) {
72 		if (port_cap->psi_count) {
73 			u8 num_sym_ssa = 0;
74 
75 			for (i = 0; i < port_cap->psi_count; i++) {
76 				if ((port_cap->psi[i] & PLT_MASK) == PLT_SYM)
77 					num_sym_ssa++;
78 			}
79 
80 			ssac = port_cap->psi_count + num_sym_ssa - 1;
81 			ssic = port_cap->psi_uid_count - 1;
82 		} else {
83 			if (bcdUSB >= 0x0320)
84 				ssac = 7;
85 			else
86 				ssac = 3;
87 
88 			ssic = (ssac + 1) / 2 - 1;
89 		}
90 
91 		bos->bNumDeviceCaps++;
92 		bos->wTotalLength = cpu_to_le16(USB_DT_BOS_SIZE +
93 						USB_DT_USB_SS_CAP_SIZE +
94 						USB_DT_USB_SSP_CAP_SIZE(ssac));
95 	}
96 
97 	if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE)
98 		return wLength;
99 
100 	/* SuperSpeed USB Device Capability */
101 	ss_cap = (struct usb_ss_cap_descriptor *)&buf[USB_DT_BOS_SIZE];
102 	ss_cap->bLength = USB_DT_USB_SS_CAP_SIZE;
103 	ss_cap->bDescriptorType = USB_DT_DEVICE_CAPABILITY;
104 	ss_cap->bDevCapabilityType = USB_SS_CAP_TYPE;
105 	ss_cap->bmAttributes = 0; /* set later */
106 	ss_cap->wSpeedSupported = cpu_to_le16(USB_5GBPS_OPERATION);
107 	ss_cap->bFunctionalitySupport = USB_LOW_SPEED_OPERATION;
108 	ss_cap->bU1devExitLat = 0; /* set later */
109 	ss_cap->bU2DevExitLat = 0; /* set later */
110 
111 	reg = readl(&xhci->cap_regs->hcc_params);
112 	if (HCC_LTC(reg))
113 		ss_cap->bmAttributes |= USB_LTM_SUPPORT;
114 
115 	if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
116 		reg = readl(&xhci->cap_regs->hcs_params3);
117 		ss_cap->bU1devExitLat = HCS_U1_LATENCY(reg);
118 		ss_cap->bU2DevExitLat = cpu_to_le16(HCS_U2_LATENCY(reg));
119 	}
120 
121 	if (wLength < le16_to_cpu(bos->wTotalLength))
122 		return wLength;
123 
124 	if (bcdUSB < 0x0310)
125 		return le16_to_cpu(bos->wTotalLength);
126 
127 	ssp_cap = (struct usb_ssp_cap_descriptor *)&buf[USB_DT_BOS_SIZE +
128 		USB_DT_USB_SS_CAP_SIZE];
129 	ssp_cap->bLength = USB_DT_USB_SSP_CAP_SIZE(ssac);
130 	ssp_cap->bDescriptorType = USB_DT_DEVICE_CAPABILITY;
131 	ssp_cap->bDevCapabilityType = USB_SSP_CAP_TYPE;
132 	ssp_cap->bReserved = 0;
133 	ssp_cap->wReserved = 0;
134 	ssp_cap->bmAttributes =
135 		cpu_to_le32(FIELD_PREP(USB_SSP_SUBLINK_SPEED_ATTRIBS, ssac) |
136 			    FIELD_PREP(USB_SSP_SUBLINK_SPEED_IDS, ssic));
137 
138 	if (!port_cap->psi_count) {
139 		for (i = 0; i < ssac + 1; i++)
140 			ssp_cap->bmSublinkSpeedAttr[i] =
141 				cpu_to_le32(ssp_cap_default_ssa[i]);
142 
143 		min_ssid = 4;
144 		goto out;
145 	}
146 
147 	offset = 0;
148 	for (i = 0; i < port_cap->psi_count; i++) {
149 		u32 psi;
150 		u32 attr;
151 		u8 ssid;
152 		u8 lp;
153 		u8 lse;
154 		u8 psie;
155 		u16 lane_mantissa;
156 		u16 psim;
157 		u16 plt;
158 
159 		psi = port_cap->psi[i];
160 		ssid = XHCI_EXT_PORT_PSIV(psi);
161 		lp = XHCI_EXT_PORT_LP(psi);
162 		psie = XHCI_EXT_PORT_PSIE(psi);
163 		psim = XHCI_EXT_PORT_PSIM(psi);
164 		plt = psi & PLT_MASK;
165 
166 		lse = psie;
167 		lane_mantissa = psim;
168 
169 		/* Shift to Gbps and set SSP Link Protocol if 10Gpbs */
170 		for (; psie < USB_SSP_SUBLINK_SPEED_LSE_GBPS; psie++)
171 			psim /= 1000;
172 
173 		if (!min_rate || psim < min_rate) {
174 			min_ssid = ssid;
175 			min_rate = psim;
176 		}
177 
178 		/* Some host controllers don't set the link protocol for SSP */
179 		if (psim >= 10)
180 			lp = USB_SSP_SUBLINK_SPEED_LP_SSP;
181 
182 		/*
183 		 * PSIM and PSIE represent the total speed of PSI. The BOS
184 		 * descriptor SSP sublink speed attribute lane mantissa
185 		 * describes the lane speed. E.g. PSIM and PSIE for gen2x2
186 		 * is 20Gbps, but the BOS descriptor lane speed mantissa is
187 		 * 10Gbps. Check and modify the mantissa value to match the
188 		 * lane speed.
189 		 */
190 		if (bcdUSB == 0x0320 && plt == PLT_SYM) {
191 			/*
192 			 * The PSI dword for gen1x2 and gen2x1 share the same
193 			 * values. But the lane speed for gen1x2 is 5Gbps while
194 			 * gen2x1 is 10Gbps. If the previous PSI dword SSID is
195 			 * 5 and the PSIE and PSIM match with SSID 6, let's
196 			 * assume that the controller follows the default speed
197 			 * id with SSID 6 for gen1x2.
198 			 */
199 			if (ssid == 6 && psie == 3 && psim == 10 && i) {
200 				u32 prev = port_cap->psi[i - 1];
201 
202 				if ((prev & PLT_MASK) == PLT_SYM &&
203 				    XHCI_EXT_PORT_PSIV(prev) == 5 &&
204 				    XHCI_EXT_PORT_PSIE(prev) == 3 &&
205 				    XHCI_EXT_PORT_PSIM(prev) == 10) {
206 					lse = USB_SSP_SUBLINK_SPEED_LSE_GBPS;
207 					lane_mantissa = 5;
208 				}
209 			}
210 
211 			if (psie == 3 && psim > 10) {
212 				lse = USB_SSP_SUBLINK_SPEED_LSE_GBPS;
213 				lane_mantissa = 10;
214 			}
215 		}
216 
217 		attr = (FIELD_PREP(USB_SSP_SUBLINK_SPEED_SSID, ssid) |
218 			FIELD_PREP(USB_SSP_SUBLINK_SPEED_LP, lp) |
219 			FIELD_PREP(USB_SSP_SUBLINK_SPEED_LSE, lse) |
220 			FIELD_PREP(USB_SSP_SUBLINK_SPEED_LSM, lane_mantissa));
221 
222 		switch (plt) {
223 		case PLT_SYM:
224 			attr |= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST,
225 					   USB_SSP_SUBLINK_SPEED_ST_SYM_RX);
226 			ssp_cap->bmSublinkSpeedAttr[offset++] = cpu_to_le32(attr);
227 
228 			attr &= ~USB_SSP_SUBLINK_SPEED_ST;
229 			attr |= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST,
230 					   USB_SSP_SUBLINK_SPEED_ST_SYM_TX);
231 			ssp_cap->bmSublinkSpeedAttr[offset++] = cpu_to_le32(attr);
232 			break;
233 		case PLT_ASYM_RX:
234 			attr |= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST,
235 					   USB_SSP_SUBLINK_SPEED_ST_ASYM_RX);
236 			ssp_cap->bmSublinkSpeedAttr[offset++] = cpu_to_le32(attr);
237 			break;
238 		case PLT_ASYM_TX:
239 			attr |= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST,
240 					   USB_SSP_SUBLINK_SPEED_ST_ASYM_TX);
241 			ssp_cap->bmSublinkSpeedAttr[offset++] = cpu_to_le32(attr);
242 			break;
243 		}
244 	}
245 out:
246 	ssp_cap->wFunctionalitySupport =
247 		cpu_to_le16(FIELD_PREP(USB_SSP_MIN_SUBLINK_SPEED_ATTRIBUTE_ID,
248 				       min_ssid) |
249 			    FIELD_PREP(USB_SSP_MIN_RX_LANE_COUNT, 1) |
250 			    FIELD_PREP(USB_SSP_MIN_TX_LANE_COUNT, 1));
251 
252 	return le16_to_cpu(bos->wTotalLength);
253 }
254 
xhci_common_hub_descriptor(struct xhci_hcd * xhci,struct usb_hub_descriptor * desc,int ports)255 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
256 		struct usb_hub_descriptor *desc, int ports)
257 {
258 	u16 temp;
259 
260 	desc->bHubContrCurrent = 0;
261 
262 	desc->bNbrPorts = ports;
263 	temp = 0;
264 	/* Bits 1:0 - support per-port power switching, or power always on */
265 	if (HCC_PPC(xhci->hcc_params))
266 		temp |= HUB_CHAR_INDV_PORT_LPSM;
267 	else
268 		temp |= HUB_CHAR_NO_LPSM;
269 	/* Bit  2 - root hubs are not part of a compound device */
270 	/* Bits 4:3 - individual port over current protection */
271 	temp |= HUB_CHAR_INDV_PORT_OCPM;
272 	/* Bits 6:5 - no TTs in root ports */
273 	/* Bit  7 - no port indicators */
274 	desc->wHubCharacteristics = cpu_to_le16(temp);
275 }
276 
277 /* Fill in the USB 2.0 roothub descriptor */
xhci_usb2_hub_descriptor(struct usb_hcd * hcd,struct xhci_hcd * xhci,struct usb_hub_descriptor * desc)278 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
279 		struct usb_hub_descriptor *desc)
280 {
281 	int ports;
282 	u16 temp;
283 	__u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
284 	u32 portsc;
285 	unsigned int i;
286 	struct xhci_hub *rhub;
287 
288 	rhub = &xhci->usb2_rhub;
289 	ports = rhub->num_ports;
290 	xhci_common_hub_descriptor(xhci, desc, ports);
291 	desc->bDescriptorType = USB_DT_HUB;
292 	temp = 1 + (ports / 8);
293 	desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
294 	desc->bPwrOn2PwrGood = 10;	/* xhci section 5.4.8 says 20ms */
295 
296 	/* The Device Removable bits are reported on a byte granularity.
297 	 * If the port doesn't exist within that byte, the bit is set to 0.
298 	 */
299 	memset(port_removable, 0, sizeof(port_removable));
300 	for (i = 0; i < ports; i++) {
301 		portsc = readl(rhub->ports[i]->addr);
302 		/* If a device is removable, PORTSC reports a 0, same as in the
303 		 * hub descriptor DeviceRemovable bits.
304 		 */
305 		if (portsc & PORT_DEV_REMOVE)
306 			/* This math is hairy because bit 0 of DeviceRemovable
307 			 * is reserved, and bit 1 is for port 1, etc.
308 			 */
309 			port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
310 	}
311 
312 	/* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
313 	 * ports on it.  The USB 2.0 specification says that there are two
314 	 * variable length fields at the end of the hub descriptor:
315 	 * DeviceRemovable and PortPwrCtrlMask.  But since we can have less than
316 	 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
317 	 * to set PortPwrCtrlMask bits.  PortPwrCtrlMask must always be set to
318 	 * 0xFF, so we initialize the both arrays (DeviceRemovable and
319 	 * PortPwrCtrlMask) to 0xFF.  Then we set the DeviceRemovable for each
320 	 * set of ports that actually exist.
321 	 */
322 	memset(desc->u.hs.DeviceRemovable, 0xff,
323 			sizeof(desc->u.hs.DeviceRemovable));
324 	memset(desc->u.hs.PortPwrCtrlMask, 0xff,
325 			sizeof(desc->u.hs.PortPwrCtrlMask));
326 
327 	for (i = 0; i < (ports + 1 + 7) / 8; i++)
328 		memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
329 				sizeof(__u8));
330 }
331 
332 /* Fill in the USB 3.0 roothub descriptor */
xhci_usb3_hub_descriptor(struct usb_hcd * hcd,struct xhci_hcd * xhci,struct usb_hub_descriptor * desc)333 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
334 		struct usb_hub_descriptor *desc)
335 {
336 	int ports;
337 	u16 port_removable;
338 	u32 portsc;
339 	unsigned int i;
340 	struct xhci_hub *rhub;
341 
342 	rhub = &xhci->usb3_rhub;
343 	ports = rhub->num_ports;
344 	xhci_common_hub_descriptor(xhci, desc, ports);
345 	desc->bDescriptorType = USB_DT_SS_HUB;
346 	desc->bDescLength = USB_DT_SS_HUB_SIZE;
347 	desc->bPwrOn2PwrGood = 50;	/* usb 3.1 may fail if less than 100ms */
348 
349 	/* header decode latency should be zero for roothubs,
350 	 * see section 4.23.5.2.
351 	 */
352 	desc->u.ss.bHubHdrDecLat = 0;
353 	desc->u.ss.wHubDelay = 0;
354 
355 	port_removable = 0;
356 	/* bit 0 is reserved, bit 1 is for port 1, etc. */
357 	for (i = 0; i < ports; i++) {
358 		portsc = readl(rhub->ports[i]->addr);
359 		if (portsc & PORT_DEV_REMOVE)
360 			port_removable |= 1 << (i + 1);
361 	}
362 
363 	desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
364 }
365 
xhci_hub_descriptor(struct usb_hcd * hcd,struct xhci_hcd * xhci,struct usb_hub_descriptor * desc)366 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
367 		struct usb_hub_descriptor *desc)
368 {
369 
370 	if (hcd->speed >= HCD_USB3)
371 		xhci_usb3_hub_descriptor(hcd, xhci, desc);
372 	else
373 		xhci_usb2_hub_descriptor(hcd, xhci, desc);
374 
375 }
376 
xhci_port_speed(unsigned int port_status)377 static unsigned int xhci_port_speed(unsigned int port_status)
378 {
379 	if (DEV_LOWSPEED(port_status))
380 		return USB_PORT_STAT_LOW_SPEED;
381 	if (DEV_HIGHSPEED(port_status))
382 		return USB_PORT_STAT_HIGH_SPEED;
383 	/*
384 	 * FIXME: Yes, we should check for full speed, but the core uses that as
385 	 * a default in portspeed() in usb/core/hub.c (which is the only place
386 	 * USB_PORT_STAT_*_SPEED is used).
387 	 */
388 	return 0;
389 }
390 
391 /*
392  * These bits are Read Only (RO) and should be saved and written to the
393  * registers: 0, 3, 10:13, 30
394  * connect status, over-current status, port speed, and device removable.
395  * connect status and port speed are also sticky - meaning they're in
396  * the AUX well and they aren't changed by a hot, warm, or cold reset.
397  */
398 #define	XHCI_PORT_RO	((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
399 /*
400  * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
401  * bits 5:8, 9, 14:15, 25:27
402  * link state, port power, port indicator state, "wake on" enable state
403  */
404 #define XHCI_PORT_RWS	((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
405 /*
406  * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
407  * bit 4 (port reset)
408  */
409 #define	XHCI_PORT_RW1S	((1<<4))
410 /*
411  * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
412  * bits 1, 17, 18, 19, 20, 21, 22, 23
413  * port enable/disable, and
414  * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
415  * over-current, reset, link state, and L1 change
416  */
417 #define XHCI_PORT_RW1CS	((1<<1) | (0x7f<<17))
418 /*
419  * Bit 16 is RW, and writing a '1' to it causes the link state control to be
420  * latched in
421  */
422 #define	XHCI_PORT_RW	((1<<16))
423 /*
424  * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
425  * bits 2, 24, 28:31
426  */
427 #define	XHCI_PORT_RZ	((1<<2) | (1<<24) | (0xf<<28))
428 
429 /*
430  * Given a port state, this function returns a value that would result in the
431  * port being in the same state, if the value was written to the port status
432  * control register.
433  * Save Read Only (RO) bits and save read/write bits where
434  * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
435  * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
436  */
xhci_port_state_to_neutral(u32 state)437 u32 xhci_port_state_to_neutral(u32 state)
438 {
439 	/* Save read-only status and port state */
440 	return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
441 }
442 
443 /*
444  * find slot id based on port number.
445  * @port: The one-based port number from one of the two split roothubs.
446  */
xhci_find_slot_id_by_port(struct usb_hcd * hcd,struct xhci_hcd * xhci,u16 port)447 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
448 		u16 port)
449 {
450 	int slot_id;
451 	int i;
452 	enum usb_device_speed speed;
453 
454 	slot_id = 0;
455 	for (i = 0; i < MAX_HC_SLOTS; i++) {
456 		if (!xhci->devs[i] || !xhci->devs[i]->udev)
457 			continue;
458 		speed = xhci->devs[i]->udev->speed;
459 		if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3))
460 				&& xhci->devs[i]->fake_port == port) {
461 			slot_id = i;
462 			break;
463 		}
464 	}
465 
466 	return slot_id;
467 }
468 
469 /*
470  * Stop device
471  * It issues stop endpoint command for EP 0 to 30. And wait the last command
472  * to complete.
473  * suspend will set to 1, if suspend bit need to set in command.
474  */
xhci_stop_device(struct xhci_hcd * xhci,int slot_id,int suspend)475 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
476 {
477 	struct xhci_virt_device *virt_dev;
478 	struct xhci_command *cmd;
479 	unsigned long flags;
480 	int ret;
481 	int i;
482 
483 	ret = 0;
484 	virt_dev = xhci->devs[slot_id];
485 	if (!virt_dev)
486 		return -ENODEV;
487 
488 	trace_xhci_stop_device(virt_dev);
489 
490 	cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
491 	if (!cmd)
492 		return -ENOMEM;
493 
494 	spin_lock_irqsave(&xhci->lock, flags);
495 	for (i = LAST_EP_INDEX; i > 0; i--) {
496 		if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
497 			struct xhci_ep_ctx *ep_ctx;
498 			struct xhci_command *command;
499 
500 			ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, i);
501 
502 			/* Check ep is running, required by AMD SNPS 3.1 xHC */
503 			if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_RUNNING)
504 				continue;
505 
506 			command = xhci_alloc_command(xhci, false, GFP_NOWAIT);
507 			if (!command) {
508 				spin_unlock_irqrestore(&xhci->lock, flags);
509 				ret = -ENOMEM;
510 				goto cmd_cleanup;
511 			}
512 
513 			ret = xhci_queue_stop_endpoint(xhci, command, slot_id,
514 						       i, suspend);
515 			if (ret) {
516 				spin_unlock_irqrestore(&xhci->lock, flags);
517 				xhci_free_command(xhci, command);
518 				goto cmd_cleanup;
519 			}
520 		}
521 	}
522 	ret = xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
523 	if (ret) {
524 		spin_unlock_irqrestore(&xhci->lock, flags);
525 		goto cmd_cleanup;
526 	}
527 
528 	xhci_ring_cmd_db(xhci);
529 	spin_unlock_irqrestore(&xhci->lock, flags);
530 
531 	/* Wait for last stop endpoint command to finish */
532 	wait_for_completion(cmd->completion);
533 
534 	if (cmd->status == COMP_COMMAND_ABORTED ||
535 	    cmd->status == COMP_COMMAND_RING_STOPPED) {
536 		xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
537 		ret = -ETIME;
538 	}
539 
540 cmd_cleanup:
541 	xhci_free_command(xhci, cmd);
542 	return ret;
543 }
544 
545 /*
546  * Ring device, it rings the all doorbells unconditionally.
547  */
xhci_ring_device(struct xhci_hcd * xhci,int slot_id)548 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
549 {
550 	int i, s;
551 	struct xhci_virt_ep *ep;
552 
553 	for (i = 0; i < LAST_EP_INDEX + 1; i++) {
554 		ep = &xhci->devs[slot_id]->eps[i];
555 
556 		if (ep->ep_state & EP_HAS_STREAMS) {
557 			for (s = 1; s < ep->stream_info->num_streams; s++)
558 				xhci_ring_ep_doorbell(xhci, slot_id, i, s);
559 		} else if (ep->ring && ep->ring->dequeue) {
560 			xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
561 		}
562 	}
563 
564 	return;
565 }
566 
xhci_disable_port(struct usb_hcd * hcd,struct xhci_hcd * xhci,u16 wIndex,__le32 __iomem * addr,u32 port_status)567 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
568 		u16 wIndex, __le32 __iomem *addr, u32 port_status)
569 {
570 	/* Don't allow the USB core to disable SuperSpeed ports. */
571 	if (hcd->speed >= HCD_USB3) {
572 		xhci_dbg(xhci, "Ignoring request to disable "
573 				"SuperSpeed port.\n");
574 		return;
575 	}
576 
577 	if (xhci->quirks & XHCI_BROKEN_PORT_PED) {
578 		xhci_dbg(xhci,
579 			 "Broken Port Enabled/Disabled, ignoring port disable request.\n");
580 		return;
581 	}
582 
583 	/* Write 1 to disable the port */
584 	writel(port_status | PORT_PE, addr);
585 	port_status = readl(addr);
586 	xhci_dbg(xhci, "disable port %d-%d, portsc: 0x%x\n",
587 		 hcd->self.busnum, wIndex + 1, port_status);
588 }
589 
xhci_clear_port_change_bit(struct xhci_hcd * xhci,u16 wValue,u16 wIndex,__le32 __iomem * addr,u32 port_status)590 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
591 		u16 wIndex, __le32 __iomem *addr, u32 port_status)
592 {
593 	char *port_change_bit;
594 	u32 status;
595 
596 	switch (wValue) {
597 	case USB_PORT_FEAT_C_RESET:
598 		status = PORT_RC;
599 		port_change_bit = "reset";
600 		break;
601 	case USB_PORT_FEAT_C_BH_PORT_RESET:
602 		status = PORT_WRC;
603 		port_change_bit = "warm(BH) reset";
604 		break;
605 	case USB_PORT_FEAT_C_CONNECTION:
606 		status = PORT_CSC;
607 		port_change_bit = "connect";
608 		break;
609 	case USB_PORT_FEAT_C_OVER_CURRENT:
610 		status = PORT_OCC;
611 		port_change_bit = "over-current";
612 		break;
613 	case USB_PORT_FEAT_C_ENABLE:
614 		status = PORT_PEC;
615 		port_change_bit = "enable/disable";
616 		break;
617 	case USB_PORT_FEAT_C_SUSPEND:
618 		status = PORT_PLC;
619 		port_change_bit = "suspend/resume";
620 		break;
621 	case USB_PORT_FEAT_C_PORT_LINK_STATE:
622 		status = PORT_PLC;
623 		port_change_bit = "link state";
624 		break;
625 	case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
626 		status = PORT_CEC;
627 		port_change_bit = "config error";
628 		break;
629 	default:
630 		/* Should never happen */
631 		return;
632 	}
633 	/* Change bits are all write 1 to clear */
634 	writel(port_status | status, addr);
635 	port_status = readl(addr);
636 
637 	xhci_dbg(xhci, "clear port%d %s change, portsc: 0x%x\n",
638 		 wIndex + 1, port_change_bit, port_status);
639 }
640 
xhci_get_rhub(struct usb_hcd * hcd)641 struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd)
642 {
643 	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
644 
645 	if (hcd->speed >= HCD_USB3)
646 		return &xhci->usb3_rhub;
647 	return &xhci->usb2_rhub;
648 }
649 
650 /*
651  * xhci_set_port_power() must be called with xhci->lock held.
652  * It will release and re-aquire the lock while calling ACPI
653  * method.
654  */
xhci_set_port_power(struct xhci_hcd * xhci,struct usb_hcd * hcd,u16 index,bool on,unsigned long * flags)655 static void xhci_set_port_power(struct xhci_hcd *xhci, struct usb_hcd *hcd,
656 				u16 index, bool on, unsigned long *flags)
657 	__must_hold(&xhci->lock)
658 {
659 	struct xhci_hub *rhub;
660 	struct xhci_port *port;
661 	u32 temp;
662 
663 	rhub = xhci_get_rhub(hcd);
664 	port = rhub->ports[index];
665 	temp = readl(port->addr);
666 
667 	xhci_dbg(xhci, "set port power %d-%d %s, portsc: 0x%x\n",
668 		 hcd->self.busnum, index + 1, on ? "ON" : "OFF", temp);
669 
670 	temp = xhci_port_state_to_neutral(temp);
671 
672 	if (on) {
673 		/* Power on */
674 		writel(temp | PORT_POWER, port->addr);
675 		readl(port->addr);
676 	} else {
677 		/* Power off */
678 		writel(temp & ~PORT_POWER, port->addr);
679 	}
680 
681 	spin_unlock_irqrestore(&xhci->lock, *flags);
682 	temp = usb_acpi_power_manageable(hcd->self.root_hub,
683 					index);
684 	if (temp)
685 		usb_acpi_set_power_state(hcd->self.root_hub,
686 			index, on);
687 	spin_lock_irqsave(&xhci->lock, *flags);
688 }
689 
xhci_port_set_test_mode(struct xhci_hcd * xhci,u16 test_mode,u16 wIndex)690 static void xhci_port_set_test_mode(struct xhci_hcd *xhci,
691 	u16 test_mode, u16 wIndex)
692 {
693 	u32 temp;
694 	struct xhci_port *port;
695 
696 	/* xhci only supports test mode for usb2 ports */
697 	port = xhci->usb2_rhub.ports[wIndex];
698 	temp = readl(port->addr + PORTPMSC);
699 	temp |= test_mode << PORT_TEST_MODE_SHIFT;
700 	writel(temp, port->addr + PORTPMSC);
701 	xhci->test_mode = test_mode;
702 	if (test_mode == USB_TEST_FORCE_ENABLE)
703 		xhci_start(xhci);
704 }
705 
xhci_enter_test_mode(struct xhci_hcd * xhci,u16 test_mode,u16 wIndex,unsigned long * flags)706 static int xhci_enter_test_mode(struct xhci_hcd *xhci,
707 				u16 test_mode, u16 wIndex, unsigned long *flags)
708 	__must_hold(&xhci->lock)
709 {
710 	struct usb_hcd *usb3_hcd = xhci_get_usb3_hcd(xhci);
711 	int i, retval;
712 
713 	/* Disable all Device Slots */
714 	xhci_dbg(xhci, "Disable all slots\n");
715 	spin_unlock_irqrestore(&xhci->lock, *flags);
716 	for (i = 1; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
717 		if (!xhci->devs[i])
718 			continue;
719 
720 		retval = xhci_disable_slot(xhci, i);
721 		xhci_free_virt_device(xhci, i);
722 		if (retval)
723 			xhci_err(xhci, "Failed to disable slot %d, %d. Enter test mode anyway\n",
724 				 i, retval);
725 	}
726 	spin_lock_irqsave(&xhci->lock, *flags);
727 	/* Put all ports to the Disable state by clear PP */
728 	xhci_dbg(xhci, "Disable all port (PP = 0)\n");
729 	/* Power off USB3 ports*/
730 	for (i = 0; i < xhci->usb3_rhub.num_ports; i++)
731 		xhci_set_port_power(xhci, usb3_hcd, i, false, flags);
732 	/* Power off USB2 ports*/
733 	for (i = 0; i < xhci->usb2_rhub.num_ports; i++)
734 		xhci_set_port_power(xhci, xhci->main_hcd, i, false, flags);
735 	/* Stop the controller */
736 	xhci_dbg(xhci, "Stop controller\n");
737 	retval = xhci_halt(xhci);
738 	if (retval)
739 		return retval;
740 	/* Disable runtime PM for test mode */
741 	pm_runtime_forbid(xhci_to_hcd(xhci)->self.controller);
742 	/* Set PORTPMSC.PTC field to enter selected test mode */
743 	/* Port is selected by wIndex. port_id = wIndex + 1 */
744 	xhci_dbg(xhci, "Enter Test Mode: %d, Port_id=%d\n",
745 					test_mode, wIndex + 1);
746 	xhci_port_set_test_mode(xhci, test_mode, wIndex);
747 	return retval;
748 }
749 
xhci_exit_test_mode(struct xhci_hcd * xhci)750 static int xhci_exit_test_mode(struct xhci_hcd *xhci)
751 {
752 	int retval;
753 
754 	if (!xhci->test_mode) {
755 		xhci_err(xhci, "Not in test mode, do nothing.\n");
756 		return 0;
757 	}
758 	if (xhci->test_mode == USB_TEST_FORCE_ENABLE &&
759 		!(xhci->xhc_state & XHCI_STATE_HALTED)) {
760 		retval = xhci_halt(xhci);
761 		if (retval)
762 			return retval;
763 	}
764 	pm_runtime_allow(xhci_to_hcd(xhci)->self.controller);
765 	xhci->test_mode = 0;
766 	return xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
767 }
768 
xhci_set_link_state(struct xhci_hcd * xhci,struct xhci_port * port,u32 link_state)769 void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
770 			 u32 link_state)
771 {
772 	u32 temp;
773 	u32 portsc;
774 
775 	portsc = readl(port->addr);
776 	temp = xhci_port_state_to_neutral(portsc);
777 	temp &= ~PORT_PLS_MASK;
778 	temp |= PORT_LINK_STROBE | link_state;
779 	writel(temp, port->addr);
780 
781 	xhci_dbg(xhci, "Set port %d-%d link state, portsc: 0x%x, write 0x%x",
782 		 port->rhub->hcd->self.busnum, port->hcd_portnum + 1,
783 		 portsc, temp);
784 }
785 
xhci_set_remote_wake_mask(struct xhci_hcd * xhci,struct xhci_port * port,u16 wake_mask)786 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
787 				      struct xhci_port *port, u16 wake_mask)
788 {
789 	u32 temp;
790 
791 	temp = readl(port->addr);
792 	temp = xhci_port_state_to_neutral(temp);
793 
794 	if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
795 		temp |= PORT_WKCONN_E;
796 	else
797 		temp &= ~PORT_WKCONN_E;
798 
799 	if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
800 		temp |= PORT_WKDISC_E;
801 	else
802 		temp &= ~PORT_WKDISC_E;
803 
804 	if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
805 		temp |= PORT_WKOC_E;
806 	else
807 		temp &= ~PORT_WKOC_E;
808 
809 	writel(temp, port->addr);
810 }
811 
812 /* Test and clear port RWC bit */
xhci_test_and_clear_bit(struct xhci_hcd * xhci,struct xhci_port * port,u32 port_bit)813 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port,
814 			     u32 port_bit)
815 {
816 	u32 temp;
817 
818 	temp = readl(port->addr);
819 	if (temp & port_bit) {
820 		temp = xhci_port_state_to_neutral(temp);
821 		temp |= port_bit;
822 		writel(temp, port->addr);
823 	}
824 }
825 
826 /* Updates Link Status for super Speed port */
xhci_hub_report_usb3_link_state(struct xhci_hcd * xhci,u32 * status,u32 status_reg)827 static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
828 		u32 *status, u32 status_reg)
829 {
830 	u32 pls = status_reg & PORT_PLS_MASK;
831 
832 	/* When the CAS bit is set then warm reset
833 	 * should be performed on port
834 	 */
835 	if (status_reg & PORT_CAS) {
836 		/* The CAS bit can be set while the port is
837 		 * in any link state.
838 		 * Only roothubs have CAS bit, so we
839 		 * pretend to be in compliance mode
840 		 * unless we're already in compliance
841 		 * or the inactive state.
842 		 */
843 		if (pls != USB_SS_PORT_LS_COMP_MOD &&
844 		    pls != USB_SS_PORT_LS_SS_INACTIVE) {
845 			pls = USB_SS_PORT_LS_COMP_MOD;
846 		}
847 		/* Return also connection bit -
848 		 * hub state machine resets port
849 		 * when this bit is set.
850 		 */
851 		pls |= USB_PORT_STAT_CONNECTION;
852 	} else {
853 		/*
854 		 * Resume state is an xHCI internal state.  Do not report it to
855 		 * usb core, instead, pretend to be U3, thus usb core knows
856 		 * it's not ready for transfer.
857 		 */
858 		if (pls == XDEV_RESUME) {
859 			*status |= USB_SS_PORT_LS_U3;
860 			return;
861 		}
862 
863 		/*
864 		 * If CAS bit isn't set but the Port is already at
865 		 * Compliance Mode, fake a connection so the USB core
866 		 * notices the Compliance state and resets the port.
867 		 * This resolves an issue generated by the SN65LVPE502CP
868 		 * in which sometimes the port enters compliance mode
869 		 * caused by a delay on the host-device negotiation.
870 		 */
871 		if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
872 				(pls == USB_SS_PORT_LS_COMP_MOD))
873 			pls |= USB_PORT_STAT_CONNECTION;
874 	}
875 
876 	/* update status field */
877 	*status |= pls;
878 }
879 
880 /*
881  * Function for Compliance Mode Quirk.
882  *
883  * This Function verifies if all xhc USB3 ports have entered U0, if so,
884  * the compliance mode timer is deleted. A port won't enter
885  * compliance mode if it has previously entered U0.
886  */
xhci_del_comp_mod_timer(struct xhci_hcd * xhci,u32 status,u16 wIndex)887 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
888 				    u16 wIndex)
889 {
890 	u32 all_ports_seen_u0 = ((1 << xhci->usb3_rhub.num_ports) - 1);
891 	bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
892 
893 	if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
894 		return;
895 
896 	if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
897 		xhci->port_status_u0 |= 1 << wIndex;
898 		if (xhci->port_status_u0 == all_ports_seen_u0) {
899 			del_timer_sync(&xhci->comp_mode_recovery_timer);
900 			xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
901 				"All USB3 ports have entered U0 already!");
902 			xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
903 				"Compliance Mode Recovery Timer Deleted.");
904 		}
905 	}
906 }
907 
xhci_handle_usb2_port_link_resume(struct xhci_port * port,u32 * status,u32 portsc,unsigned long * flags)908 static int xhci_handle_usb2_port_link_resume(struct xhci_port *port,
909 					     u32 *status, u32 portsc,
910 					     unsigned long *flags)
911 {
912 	struct xhci_bus_state *bus_state;
913 	struct xhci_hcd	*xhci;
914 	struct usb_hcd *hcd;
915 	int slot_id;
916 	u32 wIndex;
917 
918 	hcd = port->rhub->hcd;
919 	bus_state = &port->rhub->bus_state;
920 	xhci = hcd_to_xhci(hcd);
921 	wIndex = port->hcd_portnum;
922 
923 	if ((portsc & PORT_RESET) || !(portsc & PORT_PE)) {
924 		*status = 0xffffffff;
925 		return -EINVAL;
926 	}
927 	/* did port event handler already start resume timing? */
928 	if (!bus_state->resume_done[wIndex]) {
929 		/* If not, maybe we are in a host initated resume? */
930 		if (test_bit(wIndex, &bus_state->resuming_ports)) {
931 			/* Host initated resume doesn't time the resume
932 			 * signalling using resume_done[].
933 			 * It manually sets RESUME state, sleeps 20ms
934 			 * and sets U0 state. This should probably be
935 			 * changed, but not right now.
936 			 */
937 		} else {
938 			/* port resume was discovered now and here,
939 			 * start resume timing
940 			 */
941 			unsigned long timeout = jiffies +
942 				msecs_to_jiffies(USB_RESUME_TIMEOUT);
943 
944 			set_bit(wIndex, &bus_state->resuming_ports);
945 			bus_state->resume_done[wIndex] = timeout;
946 			mod_timer(&hcd->rh_timer, timeout);
947 			usb_hcd_start_port_resume(&hcd->self, wIndex);
948 		}
949 	/* Has resume been signalled for USB_RESUME_TIME yet? */
950 	} else if (time_after_eq(jiffies, bus_state->resume_done[wIndex])) {
951 		int time_left;
952 
953 		xhci_dbg(xhci, "resume USB2 port %d-%d\n",
954 			 hcd->self.busnum, wIndex + 1);
955 
956 		bus_state->resume_done[wIndex] = 0;
957 		clear_bit(wIndex, &bus_state->resuming_ports);
958 
959 		set_bit(wIndex, &bus_state->rexit_ports);
960 
961 		xhci_test_and_clear_bit(xhci, port, PORT_PLC);
962 		xhci_set_link_state(xhci, port, XDEV_U0);
963 
964 		spin_unlock_irqrestore(&xhci->lock, *flags);
965 		time_left = wait_for_completion_timeout(
966 			&bus_state->rexit_done[wIndex],
967 			msecs_to_jiffies(XHCI_MAX_REXIT_TIMEOUT_MS));
968 		spin_lock_irqsave(&xhci->lock, *flags);
969 
970 		if (time_left) {
971 			slot_id = xhci_find_slot_id_by_port(hcd, xhci,
972 							    wIndex + 1);
973 			if (!slot_id) {
974 				xhci_dbg(xhci, "slot_id is zero\n");
975 				*status = 0xffffffff;
976 				return -ENODEV;
977 			}
978 			xhci_ring_device(xhci, slot_id);
979 		} else {
980 			int port_status = readl(port->addr);
981 
982 			xhci_warn(xhci, "Port resume timed out, port %d-%d: 0x%x\n",
983 				  hcd->self.busnum, wIndex + 1, port_status);
984 			*status |= USB_PORT_STAT_SUSPEND;
985 			clear_bit(wIndex, &bus_state->rexit_ports);
986 		}
987 
988 		usb_hcd_end_port_resume(&hcd->self, wIndex);
989 		bus_state->port_c_suspend |= 1 << wIndex;
990 		bus_state->suspended_ports &= ~(1 << wIndex);
991 	} else {
992 		/*
993 		 * The resume has been signaling for less than
994 		 * USB_RESUME_TIME. Report the port status as SUSPEND,
995 		 * let the usbcore check port status again and clear
996 		 * resume signaling later.
997 		 */
998 		*status |= USB_PORT_STAT_SUSPEND;
999 	}
1000 	return 0;
1001 }
1002 
xhci_get_ext_port_status(u32 raw_port_status,u32 port_li)1003 static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li)
1004 {
1005 	u32 ext_stat = 0;
1006 	int speed_id;
1007 
1008 	/* only support rx and tx lane counts of 1 in usb3.1 spec */
1009 	speed_id = DEV_PORT_SPEED(raw_port_status);
1010 	ext_stat |= speed_id;		/* bits 3:0, RX speed id */
1011 	ext_stat |= speed_id << 4;	/* bits 7:4, TX speed id */
1012 
1013 	ext_stat |= PORT_RX_LANES(port_li) << 8;  /* bits 11:8 Rx lane count */
1014 	ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */
1015 
1016 	return ext_stat;
1017 }
1018 
xhci_get_usb3_port_status(struct xhci_port * port,u32 * status,u32 portsc)1019 static void xhci_get_usb3_port_status(struct xhci_port *port, u32 *status,
1020 				      u32 portsc)
1021 {
1022 	struct xhci_bus_state *bus_state;
1023 	struct xhci_hcd	*xhci;
1024 	struct usb_hcd *hcd;
1025 	u32 link_state;
1026 	u32 portnum;
1027 
1028 	bus_state = &port->rhub->bus_state;
1029 	xhci = hcd_to_xhci(port->rhub->hcd);
1030 	hcd = port->rhub->hcd;
1031 	link_state = portsc & PORT_PLS_MASK;
1032 	portnum = port->hcd_portnum;
1033 
1034 	/* USB3 specific wPortChange bits
1035 	 *
1036 	 * Port link change with port in resume state should not be
1037 	 * reported to usbcore, as this is an internal state to be
1038 	 * handled by xhci driver. Reporting PLC to usbcore may
1039 	 * cause usbcore clearing PLC first and port change event
1040 	 * irq won't be generated.
1041 	 */
1042 
1043 	if (portsc & PORT_PLC && (link_state != XDEV_RESUME))
1044 		*status |= USB_PORT_STAT_C_LINK_STATE << 16;
1045 	if (portsc & PORT_WRC)
1046 		*status |= USB_PORT_STAT_C_BH_RESET << 16;
1047 	if (portsc & PORT_CEC)
1048 		*status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
1049 
1050 	/* USB3 specific wPortStatus bits */
1051 	if (portsc & PORT_POWER) {
1052 		*status |= USB_SS_PORT_STAT_POWER;
1053 		/* link state handling */
1054 		if (link_state == XDEV_U0)
1055 			bus_state->suspended_ports &= ~(1 << portnum);
1056 	}
1057 
1058 	/* remote wake resume signaling complete */
1059 	if (bus_state->port_remote_wakeup & (1 << portnum) &&
1060 	    link_state != XDEV_RESUME &&
1061 	    link_state != XDEV_RECOVERY) {
1062 		bus_state->port_remote_wakeup &= ~(1 << portnum);
1063 		usb_hcd_end_port_resume(&hcd->self, portnum);
1064 	}
1065 
1066 	xhci_hub_report_usb3_link_state(xhci, status, portsc);
1067 	xhci_del_comp_mod_timer(xhci, portsc, portnum);
1068 }
1069 
xhci_get_usb2_port_status(struct xhci_port * port,u32 * status,u32 portsc,unsigned long * flags)1070 static void xhci_get_usb2_port_status(struct xhci_port *port, u32 *status,
1071 				      u32 portsc, unsigned long *flags)
1072 {
1073 	struct xhci_bus_state *bus_state;
1074 	u32 link_state;
1075 	u32 portnum;
1076 	int ret;
1077 
1078 	bus_state = &port->rhub->bus_state;
1079 	link_state = portsc & PORT_PLS_MASK;
1080 	portnum = port->hcd_portnum;
1081 
1082 	/* USB2 wPortStatus bits */
1083 	if (portsc & PORT_POWER) {
1084 		*status |= USB_PORT_STAT_POWER;
1085 
1086 		/* link state is only valid if port is powered */
1087 		if (link_state == XDEV_U3)
1088 			*status |= USB_PORT_STAT_SUSPEND;
1089 		if (link_state == XDEV_U2)
1090 			*status |= USB_PORT_STAT_L1;
1091 		if (link_state == XDEV_U0) {
1092 			if (bus_state->resume_done[portnum])
1093 				usb_hcd_end_port_resume(&port->rhub->hcd->self,
1094 							portnum);
1095 			bus_state->resume_done[portnum] = 0;
1096 			clear_bit(portnum, &bus_state->resuming_ports);
1097 			if (bus_state->suspended_ports & (1 << portnum)) {
1098 				bus_state->suspended_ports &= ~(1 << portnum);
1099 				bus_state->port_c_suspend |= 1 << portnum;
1100 			}
1101 		}
1102 		if (link_state == XDEV_RESUME) {
1103 			ret = xhci_handle_usb2_port_link_resume(port, status,
1104 								portsc, flags);
1105 			if (ret)
1106 				return;
1107 		}
1108 	}
1109 }
1110 
1111 /*
1112  * Converts a raw xHCI port status into the format that external USB 2.0 or USB
1113  * 3.0 hubs use.
1114  *
1115  * Possible side effects:
1116  *  - Mark a port as being done with device resume,
1117  *    and ring the endpoint doorbells.
1118  *  - Stop the Synopsys redriver Compliance Mode polling.
1119  *  - Drop and reacquire the xHCI lock, in order to wait for port resume.
1120  */
xhci_get_port_status(struct usb_hcd * hcd,struct xhci_bus_state * bus_state,u16 wIndex,u32 raw_port_status,unsigned long * flags)1121 static u32 xhci_get_port_status(struct usb_hcd *hcd,
1122 		struct xhci_bus_state *bus_state,
1123 	u16 wIndex, u32 raw_port_status,
1124 		unsigned long *flags)
1125 	__releases(&xhci->lock)
1126 	__acquires(&xhci->lock)
1127 {
1128 	u32 status = 0;
1129 	struct xhci_hub *rhub;
1130 	struct xhci_port *port;
1131 
1132 	rhub = xhci_get_rhub(hcd);
1133 	port = rhub->ports[wIndex];
1134 
1135 	/* common wPortChange bits */
1136 	if (raw_port_status & PORT_CSC)
1137 		status |= USB_PORT_STAT_C_CONNECTION << 16;
1138 	if (raw_port_status & PORT_PEC)
1139 		status |= USB_PORT_STAT_C_ENABLE << 16;
1140 	if ((raw_port_status & PORT_OCC))
1141 		status |= USB_PORT_STAT_C_OVERCURRENT << 16;
1142 	if ((raw_port_status & PORT_RC))
1143 		status |= USB_PORT_STAT_C_RESET << 16;
1144 
1145 	/* common wPortStatus bits */
1146 	if (raw_port_status & PORT_CONNECT) {
1147 		status |= USB_PORT_STAT_CONNECTION;
1148 		status |= xhci_port_speed(raw_port_status);
1149 	}
1150 	if (raw_port_status & PORT_PE)
1151 		status |= USB_PORT_STAT_ENABLE;
1152 	if (raw_port_status & PORT_OC)
1153 		status |= USB_PORT_STAT_OVERCURRENT;
1154 	if (raw_port_status & PORT_RESET)
1155 		status |= USB_PORT_STAT_RESET;
1156 
1157 	/* USB2 and USB3 specific bits, including Port Link State */
1158 	if (hcd->speed >= HCD_USB3)
1159 		xhci_get_usb3_port_status(port, &status, raw_port_status);
1160 	else
1161 		xhci_get_usb2_port_status(port, &status, raw_port_status,
1162 					  flags);
1163 	/*
1164 	 * Clear stale usb2 resume signalling variables in case port changed
1165 	 * state during resume signalling. For example on error
1166 	 */
1167 	if ((bus_state->resume_done[wIndex] ||
1168 	     test_bit(wIndex, &bus_state->resuming_ports)) &&
1169 	    (raw_port_status & PORT_PLS_MASK) != XDEV_U3 &&
1170 	    (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) {
1171 		bus_state->resume_done[wIndex] = 0;
1172 		clear_bit(wIndex, &bus_state->resuming_ports);
1173 		usb_hcd_end_port_resume(&hcd->self, wIndex);
1174 	}
1175 
1176 	if (bus_state->port_c_suspend & (1 << wIndex))
1177 		status |= USB_PORT_STAT_C_SUSPEND << 16;
1178 
1179 	return status;
1180 }
1181 
xhci_hub_control(struct usb_hcd * hcd,u16 typeReq,u16 wValue,u16 wIndex,char * buf,u16 wLength)1182 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
1183 		u16 wIndex, char *buf, u16 wLength)
1184 {
1185 	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
1186 	int max_ports;
1187 	unsigned long flags;
1188 	u32 temp, status;
1189 	int retval = 0;
1190 	int slot_id;
1191 	struct xhci_bus_state *bus_state;
1192 	u16 link_state = 0;
1193 	u16 wake_mask = 0;
1194 	u16 timeout = 0;
1195 	u16 test_mode = 0;
1196 	struct xhci_hub *rhub;
1197 	struct xhci_port **ports;
1198 
1199 	rhub = xhci_get_rhub(hcd);
1200 	ports = rhub->ports;
1201 	max_ports = rhub->num_ports;
1202 	bus_state = &rhub->bus_state;
1203 
1204 	spin_lock_irqsave(&xhci->lock, flags);
1205 	switch (typeReq) {
1206 	case GetHubStatus:
1207 		/* No power source, over-current reported per port */
1208 		memset(buf, 0, 4);
1209 		break;
1210 	case GetHubDescriptor:
1211 		/* Check to make sure userspace is asking for the USB 3.0 hub
1212 		 * descriptor for the USB 3.0 roothub.  If not, we stall the
1213 		 * endpoint, like external hubs do.
1214 		 */
1215 		if (hcd->speed >= HCD_USB3 &&
1216 				(wLength < USB_DT_SS_HUB_SIZE ||
1217 				 wValue != (USB_DT_SS_HUB << 8))) {
1218 			xhci_dbg(xhci, "Wrong hub descriptor type for "
1219 					"USB 3.0 roothub.\n");
1220 			goto error;
1221 		}
1222 		xhci_hub_descriptor(hcd, xhci,
1223 				(struct usb_hub_descriptor *) buf);
1224 		break;
1225 	case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
1226 		if ((wValue & 0xff00) != (USB_DT_BOS << 8))
1227 			goto error;
1228 
1229 		if (hcd->speed < HCD_USB3)
1230 			goto error;
1231 
1232 		retval = xhci_create_usb3x_bos_desc(xhci, buf, wLength);
1233 		spin_unlock_irqrestore(&xhci->lock, flags);
1234 		return retval;
1235 	case GetPortStatus:
1236 		if (!wIndex || wIndex > max_ports)
1237 			goto error;
1238 		wIndex--;
1239 		temp = readl(ports[wIndex]->addr);
1240 		if (temp == ~(u32)0) {
1241 			xhci_hc_died(xhci);
1242 			retval = -ENODEV;
1243 			break;
1244 		}
1245 		trace_xhci_get_port_status(wIndex, temp);
1246 		status = xhci_get_port_status(hcd, bus_state, wIndex, temp,
1247 					      &flags);
1248 		if (status == 0xffffffff)
1249 			goto error;
1250 
1251 		xhci_dbg(xhci, "Get port status %d-%d read: 0x%x, return 0x%x",
1252 			 hcd->self.busnum, wIndex + 1, temp, status);
1253 
1254 		put_unaligned(cpu_to_le32(status), (__le32 *) buf);
1255 		/* if USB 3.1 extended port status return additional 4 bytes */
1256 		if (wValue == 0x02) {
1257 			u32 port_li;
1258 
1259 			if (hcd->speed < HCD_USB31 || wLength != 8) {
1260 				xhci_err(xhci, "get ext port status invalid parameter\n");
1261 				retval = -EINVAL;
1262 				break;
1263 			}
1264 			port_li = readl(ports[wIndex]->addr + PORTLI);
1265 			status = xhci_get_ext_port_status(temp, port_li);
1266 			put_unaligned_le32(status, &buf[4]);
1267 		}
1268 		break;
1269 	case SetPortFeature:
1270 		if (wValue == USB_PORT_FEAT_LINK_STATE)
1271 			link_state = (wIndex & 0xff00) >> 3;
1272 		if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
1273 			wake_mask = wIndex & 0xff00;
1274 		if (wValue == USB_PORT_FEAT_TEST)
1275 			test_mode = (wIndex & 0xff00) >> 8;
1276 		/* The MSB of wIndex is the U1/U2 timeout */
1277 		timeout = (wIndex & 0xff00) >> 8;
1278 		wIndex &= 0xff;
1279 		if (!wIndex || wIndex > max_ports)
1280 			goto error;
1281 		wIndex--;
1282 		temp = readl(ports[wIndex]->addr);
1283 		if (temp == ~(u32)0) {
1284 			xhci_hc_died(xhci);
1285 			retval = -ENODEV;
1286 			break;
1287 		}
1288 		temp = xhci_port_state_to_neutral(temp);
1289 		/* FIXME: What new port features do we need to support? */
1290 		switch (wValue) {
1291 		case USB_PORT_FEAT_SUSPEND:
1292 			temp = readl(ports[wIndex]->addr);
1293 			if ((temp & PORT_PLS_MASK) != XDEV_U0) {
1294 				/* Resume the port to U0 first */
1295 				xhci_set_link_state(xhci, ports[wIndex],
1296 							XDEV_U0);
1297 				spin_unlock_irqrestore(&xhci->lock, flags);
1298 				msleep(10);
1299 				spin_lock_irqsave(&xhci->lock, flags);
1300 			}
1301 			/* In spec software should not attempt to suspend
1302 			 * a port unless the port reports that it is in the
1303 			 * enabled (PED = ‘1’,PLS < ‘3’) state.
1304 			 */
1305 			temp = readl(ports[wIndex]->addr);
1306 			if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
1307 				|| (temp & PORT_PLS_MASK) >= XDEV_U3) {
1308 				xhci_warn(xhci, "USB core suspending port %d-%d not in U0/U1/U2\n",
1309 					  hcd->self.busnum, wIndex + 1);
1310 				goto error;
1311 			}
1312 
1313 			slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1314 					wIndex + 1);
1315 			if (!slot_id) {
1316 				xhci_warn(xhci, "slot_id is zero\n");
1317 				goto error;
1318 			}
1319 			/* unlock to execute stop endpoint commands */
1320 			spin_unlock_irqrestore(&xhci->lock, flags);
1321 			xhci_stop_device(xhci, slot_id, 1);
1322 			spin_lock_irqsave(&xhci->lock, flags);
1323 
1324 			xhci_set_link_state(xhci, ports[wIndex], XDEV_U3);
1325 
1326 			spin_unlock_irqrestore(&xhci->lock, flags);
1327 			msleep(10); /* wait device to enter */
1328 			spin_lock_irqsave(&xhci->lock, flags);
1329 
1330 			temp = readl(ports[wIndex]->addr);
1331 			bus_state->suspended_ports |= 1 << wIndex;
1332 			break;
1333 		case USB_PORT_FEAT_LINK_STATE:
1334 			temp = readl(ports[wIndex]->addr);
1335 			/* Disable port */
1336 			if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
1337 				xhci_dbg(xhci, "Disable port %d-%d\n",
1338 					 hcd->self.busnum, wIndex + 1);
1339 				temp = xhci_port_state_to_neutral(temp);
1340 				/*
1341 				 * Clear all change bits, so that we get a new
1342 				 * connection event.
1343 				 */
1344 				temp |= PORT_CSC | PORT_PEC | PORT_WRC |
1345 					PORT_OCC | PORT_RC | PORT_PLC |
1346 					PORT_CEC;
1347 				writel(temp | PORT_PE, ports[wIndex]->addr);
1348 				temp = readl(ports[wIndex]->addr);
1349 				break;
1350 			}
1351 
1352 			/* Put link in RxDetect (enable port) */
1353 			if (link_state == USB_SS_PORT_LS_RX_DETECT) {
1354 				xhci_dbg(xhci, "Enable port %d-%d\n",
1355 					 hcd->self.busnum, wIndex + 1);
1356 				xhci_set_link_state(xhci, ports[wIndex],
1357 							link_state);
1358 				temp = readl(ports[wIndex]->addr);
1359 				break;
1360 			}
1361 
1362 			/*
1363 			 * For xHCI 1.1 according to section 4.19.1.2.4.1 a
1364 			 * root hub port's transition to compliance mode upon
1365 			 * detecting LFPS timeout may be controlled by an
1366 			 * Compliance Transition Enabled (CTE) flag (not
1367 			 * software visible). This flag is set by writing 0xA
1368 			 * to PORTSC PLS field which will allow transition to
1369 			 * compliance mode the next time LFPS timeout is
1370 			 * encountered. A warm reset will clear it.
1371 			 *
1372 			 * The CTE flag is only supported if the HCCPARAMS2 CTC
1373 			 * flag is set, otherwise, the compliance substate is
1374 			 * automatically entered as on 1.0 and prior.
1375 			 */
1376 			if (link_state == USB_SS_PORT_LS_COMP_MOD) {
1377 				if (!HCC2_CTC(xhci->hcc_params2)) {
1378 					xhci_dbg(xhci, "CTC flag is 0, port already supports entering compliance mode\n");
1379 					break;
1380 				}
1381 
1382 				if ((temp & PORT_CONNECT)) {
1383 					xhci_warn(xhci, "Can't set compliance mode when port is connected\n");
1384 					goto error;
1385 				}
1386 
1387 				xhci_dbg(xhci, "Enable compliance mode transition for port %d-%d\n",
1388 					 hcd->self.busnum, wIndex + 1);
1389 				xhci_set_link_state(xhci, ports[wIndex],
1390 						link_state);
1391 
1392 				temp = readl(ports[wIndex]->addr);
1393 				break;
1394 			}
1395 			/* Port must be enabled */
1396 			if (!(temp & PORT_PE)) {
1397 				retval = -ENODEV;
1398 				break;
1399 			}
1400 			/* Can't set port link state above '3' (U3) */
1401 			if (link_state > USB_SS_PORT_LS_U3) {
1402 				xhci_warn(xhci, "Cannot set port %d-%d link state %d\n",
1403 					  hcd->self.busnum, wIndex + 1,
1404 					  link_state);
1405 				goto error;
1406 			}
1407 
1408 			/*
1409 			 * set link to U0, steps depend on current link state.
1410 			 * U3: set link to U0 and wait for u3exit completion.
1411 			 * U1/U2:  no PLC complete event, only set link to U0.
1412 			 * Resume/Recovery: device initiated U0, only wait for
1413 			 * completion
1414 			 */
1415 			if (link_state == USB_SS_PORT_LS_U0) {
1416 				u32 pls = temp & PORT_PLS_MASK;
1417 				bool wait_u0 = false;
1418 
1419 				/* already in U0 */
1420 				if (pls == XDEV_U0)
1421 					break;
1422 				if (pls == XDEV_U3 ||
1423 				    pls == XDEV_RESUME ||
1424 				    pls == XDEV_RECOVERY) {
1425 					wait_u0 = true;
1426 					reinit_completion(&bus_state->u3exit_done[wIndex]);
1427 				}
1428 				if (pls <= XDEV_U3) /* U1, U2, U3 */
1429 					xhci_set_link_state(xhci, ports[wIndex],
1430 							    USB_SS_PORT_LS_U0);
1431 				if (!wait_u0) {
1432 					if (pls > XDEV_U3)
1433 						goto error;
1434 					break;
1435 				}
1436 				spin_unlock_irqrestore(&xhci->lock, flags);
1437 				if (!wait_for_completion_timeout(&bus_state->u3exit_done[wIndex],
1438 								 msecs_to_jiffies(500)))
1439 					xhci_dbg(xhci, "missing U0 port change event for port %d-%d\n",
1440 						 hcd->self.busnum, wIndex + 1);
1441 				spin_lock_irqsave(&xhci->lock, flags);
1442 				temp = readl(ports[wIndex]->addr);
1443 				break;
1444 			}
1445 
1446 			if (link_state == USB_SS_PORT_LS_U3) {
1447 				int retries = 16;
1448 				slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1449 						wIndex + 1);
1450 				if (slot_id) {
1451 					/* unlock to execute stop endpoint
1452 					 * commands */
1453 					spin_unlock_irqrestore(&xhci->lock,
1454 								flags);
1455 					xhci_stop_device(xhci, slot_id, 1);
1456 					spin_lock_irqsave(&xhci->lock, flags);
1457 				}
1458 				xhci_set_link_state(xhci, ports[wIndex], USB_SS_PORT_LS_U3);
1459 				spin_unlock_irqrestore(&xhci->lock, flags);
1460 				while (retries--) {
1461 					usleep_range(4000, 8000);
1462 					temp = readl(ports[wIndex]->addr);
1463 					if ((temp & PORT_PLS_MASK) == XDEV_U3)
1464 						break;
1465 				}
1466 				spin_lock_irqsave(&xhci->lock, flags);
1467 				temp = readl(ports[wIndex]->addr);
1468 				bus_state->suspended_ports |= 1 << wIndex;
1469 			}
1470 			break;
1471 		case USB_PORT_FEAT_POWER:
1472 			/*
1473 			 * Turn on ports, even if there isn't per-port switching.
1474 			 * HC will report connect events even before this is set.
1475 			 * However, hub_wq will ignore the roothub events until
1476 			 * the roothub is registered.
1477 			 */
1478 			xhci_set_port_power(xhci, hcd, wIndex, true, &flags);
1479 			break;
1480 		case USB_PORT_FEAT_RESET:
1481 			temp = (temp | PORT_RESET);
1482 			writel(temp, ports[wIndex]->addr);
1483 
1484 			temp = readl(ports[wIndex]->addr);
1485 			xhci_dbg(xhci, "set port reset, actual port %d-%d status  = 0x%x\n",
1486 				 hcd->self.busnum, wIndex + 1, temp);
1487 			break;
1488 		case USB_PORT_FEAT_REMOTE_WAKE_MASK:
1489 			xhci_set_remote_wake_mask(xhci, ports[wIndex],
1490 						  wake_mask);
1491 			temp = readl(ports[wIndex]->addr);
1492 			xhci_dbg(xhci, "set port remote wake mask, actual port %d-%d status  = 0x%x\n",
1493 				 hcd->self.busnum, wIndex + 1, temp);
1494 			break;
1495 		case USB_PORT_FEAT_BH_PORT_RESET:
1496 			temp |= PORT_WR;
1497 			writel(temp, ports[wIndex]->addr);
1498 			temp = readl(ports[wIndex]->addr);
1499 			break;
1500 		case USB_PORT_FEAT_U1_TIMEOUT:
1501 			if (hcd->speed < HCD_USB3)
1502 				goto error;
1503 			temp = readl(ports[wIndex]->addr + PORTPMSC);
1504 			temp &= ~PORT_U1_TIMEOUT_MASK;
1505 			temp |= PORT_U1_TIMEOUT(timeout);
1506 			writel(temp, ports[wIndex]->addr + PORTPMSC);
1507 			break;
1508 		case USB_PORT_FEAT_U2_TIMEOUT:
1509 			if (hcd->speed < HCD_USB3)
1510 				goto error;
1511 			temp = readl(ports[wIndex]->addr + PORTPMSC);
1512 			temp &= ~PORT_U2_TIMEOUT_MASK;
1513 			temp |= PORT_U2_TIMEOUT(timeout);
1514 			writel(temp, ports[wIndex]->addr + PORTPMSC);
1515 			break;
1516 		case USB_PORT_FEAT_TEST:
1517 			/* 4.19.6 Port Test Modes (USB2 Test Mode) */
1518 			if (hcd->speed != HCD_USB2)
1519 				goto error;
1520 			if (test_mode > USB_TEST_FORCE_ENABLE ||
1521 			    test_mode < USB_TEST_J)
1522 				goto error;
1523 			retval = xhci_enter_test_mode(xhci, test_mode, wIndex,
1524 						      &flags);
1525 			break;
1526 		default:
1527 			goto error;
1528 		}
1529 		/* unblock any posted writes */
1530 		temp = readl(ports[wIndex]->addr);
1531 		break;
1532 	case ClearPortFeature:
1533 		if (!wIndex || wIndex > max_ports)
1534 			goto error;
1535 		wIndex--;
1536 		temp = readl(ports[wIndex]->addr);
1537 		if (temp == ~(u32)0) {
1538 			xhci_hc_died(xhci);
1539 			retval = -ENODEV;
1540 			break;
1541 		}
1542 		/* FIXME: What new port features do we need to support? */
1543 		temp = xhci_port_state_to_neutral(temp);
1544 		switch (wValue) {
1545 		case USB_PORT_FEAT_SUSPEND:
1546 			temp = readl(ports[wIndex]->addr);
1547 			xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
1548 			xhci_dbg(xhci, "PORTSC %04x\n", temp);
1549 			if (temp & PORT_RESET)
1550 				goto error;
1551 			if ((temp & PORT_PLS_MASK) == XDEV_U3) {
1552 				if ((temp & PORT_PE) == 0)
1553 					goto error;
1554 
1555 				set_bit(wIndex, &bus_state->resuming_ports);
1556 				usb_hcd_start_port_resume(&hcd->self, wIndex);
1557 				xhci_set_link_state(xhci, ports[wIndex],
1558 						    XDEV_RESUME);
1559 				spin_unlock_irqrestore(&xhci->lock, flags);
1560 				msleep(USB_RESUME_TIMEOUT);
1561 				spin_lock_irqsave(&xhci->lock, flags);
1562 				xhci_set_link_state(xhci, ports[wIndex],
1563 							XDEV_U0);
1564 				clear_bit(wIndex, &bus_state->resuming_ports);
1565 				usb_hcd_end_port_resume(&hcd->self, wIndex);
1566 			}
1567 			bus_state->port_c_suspend |= 1 << wIndex;
1568 
1569 			slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1570 					wIndex + 1);
1571 			if (!slot_id) {
1572 				xhci_dbg(xhci, "slot_id is zero\n");
1573 				goto error;
1574 			}
1575 			xhci_ring_device(xhci, slot_id);
1576 			break;
1577 		case USB_PORT_FEAT_C_SUSPEND:
1578 			bus_state->port_c_suspend &= ~(1 << wIndex);
1579 			fallthrough;
1580 		case USB_PORT_FEAT_C_RESET:
1581 		case USB_PORT_FEAT_C_BH_PORT_RESET:
1582 		case USB_PORT_FEAT_C_CONNECTION:
1583 		case USB_PORT_FEAT_C_OVER_CURRENT:
1584 		case USB_PORT_FEAT_C_ENABLE:
1585 		case USB_PORT_FEAT_C_PORT_LINK_STATE:
1586 		case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
1587 			xhci_clear_port_change_bit(xhci, wValue, wIndex,
1588 					ports[wIndex]->addr, temp);
1589 			break;
1590 		case USB_PORT_FEAT_ENABLE:
1591 			xhci_disable_port(hcd, xhci, wIndex,
1592 					ports[wIndex]->addr, temp);
1593 			break;
1594 		case USB_PORT_FEAT_POWER:
1595 			xhci_set_port_power(xhci, hcd, wIndex, false, &flags);
1596 			break;
1597 		case USB_PORT_FEAT_TEST:
1598 			retval = xhci_exit_test_mode(xhci);
1599 			break;
1600 		default:
1601 			goto error;
1602 		}
1603 		break;
1604 	default:
1605 error:
1606 		/* "stall" on error */
1607 		retval = -EPIPE;
1608 	}
1609 	spin_unlock_irqrestore(&xhci->lock, flags);
1610 	return retval;
1611 }
1612 
1613 /*
1614  * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1615  * Ports are 0-indexed from the HCD point of view,
1616  * and 1-indexed from the USB core pointer of view.
1617  *
1618  * Note that the status change bits will be cleared as soon as a port status
1619  * change event is generated, so we use the saved status from that event.
1620  */
xhci_hub_status_data(struct usb_hcd * hcd,char * buf)1621 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1622 {
1623 	unsigned long flags;
1624 	u32 temp, status;
1625 	u32 mask;
1626 	int i, retval;
1627 	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
1628 	int max_ports;
1629 	struct xhci_bus_state *bus_state;
1630 	bool reset_change = false;
1631 	struct xhci_hub *rhub;
1632 	struct xhci_port **ports;
1633 
1634 	rhub = xhci_get_rhub(hcd);
1635 	ports = rhub->ports;
1636 	max_ports = rhub->num_ports;
1637 	bus_state = &rhub->bus_state;
1638 
1639 	/* Initial status is no changes */
1640 	retval = (max_ports + 8) / 8;
1641 	memset(buf, 0, retval);
1642 
1643 	/*
1644 	 * Inform the usbcore about resume-in-progress by returning
1645 	 * a non-zero value even if there are no status changes.
1646 	 */
1647 	spin_lock_irqsave(&xhci->lock, flags);
1648 
1649 	status = bus_state->resuming_ports;
1650 
1651 	/*
1652 	 * SS devices are only visible to roothub after link training completes.
1653 	 * Keep polling roothubs for a grace period after xHC start
1654 	 */
1655 	if (xhci->run_graceperiod) {
1656 		if (time_before(jiffies, xhci->run_graceperiod))
1657 			status = 1;
1658 		else
1659 			xhci->run_graceperiod = 0;
1660 	}
1661 
1662 	mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC;
1663 
1664 	/* For each port, did anything change?  If so, set that bit in buf. */
1665 	for (i = 0; i < max_ports; i++) {
1666 		temp = readl(ports[i]->addr);
1667 		if (temp == ~(u32)0) {
1668 			xhci_hc_died(xhci);
1669 			retval = -ENODEV;
1670 			break;
1671 		}
1672 		trace_xhci_hub_status_data(i, temp);
1673 
1674 		if ((temp & mask) != 0 ||
1675 			(bus_state->port_c_suspend & 1 << i) ||
1676 			(bus_state->resume_done[i] && time_after_eq(
1677 			    jiffies, bus_state->resume_done[i]))) {
1678 			buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1679 			status = 1;
1680 		}
1681 		if ((temp & PORT_RC))
1682 			reset_change = true;
1683 		if (temp & PORT_OC)
1684 			status = 1;
1685 	}
1686 	if (!status && !reset_change) {
1687 		xhci_dbg(xhci, "%s: stopping usb%d port polling\n",
1688 			 __func__, hcd->self.busnum);
1689 		clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1690 	}
1691 	spin_unlock_irqrestore(&xhci->lock, flags);
1692 	return status ? retval : 0;
1693 }
1694 
1695 #ifdef CONFIG_PM
1696 
xhci_bus_suspend(struct usb_hcd * hcd)1697 int xhci_bus_suspend(struct usb_hcd *hcd)
1698 {
1699 	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
1700 	int max_ports, port_index;
1701 	struct xhci_bus_state *bus_state;
1702 	unsigned long flags;
1703 	struct xhci_hub *rhub;
1704 	struct xhci_port **ports;
1705 	u32 portsc_buf[USB_MAXCHILDREN];
1706 	bool wake_enabled;
1707 
1708 	rhub = xhci_get_rhub(hcd);
1709 	ports = rhub->ports;
1710 	max_ports = rhub->num_ports;
1711 	bus_state = &rhub->bus_state;
1712 	wake_enabled = hcd->self.root_hub->do_remote_wakeup;
1713 
1714 	spin_lock_irqsave(&xhci->lock, flags);
1715 
1716 	if (wake_enabled) {
1717 		if (bus_state->resuming_ports ||	/* USB2 */
1718 		    bus_state->port_remote_wakeup) {	/* USB3 */
1719 			spin_unlock_irqrestore(&xhci->lock, flags);
1720 			xhci_dbg(xhci, "usb%d bus suspend to fail because a port is resuming\n",
1721 				 hcd->self.busnum);
1722 			return -EBUSY;
1723 		}
1724 	}
1725 	/*
1726 	 * Prepare ports for suspend, but don't write anything before all ports
1727 	 * are checked and we know bus suspend can proceed
1728 	 */
1729 	bus_state->bus_suspended = 0;
1730 	port_index = max_ports;
1731 	while (port_index--) {
1732 		u32 t1, t2;
1733 		int retries = 10;
1734 retry:
1735 		t1 = readl(ports[port_index]->addr);
1736 		t2 = xhci_port_state_to_neutral(t1);
1737 		portsc_buf[port_index] = 0;
1738 
1739 		/*
1740 		 * Give a USB3 port in link training time to finish, but don't
1741 		 * prevent suspend as port might be stuck
1742 		 */
1743 		if ((hcd->speed >= HCD_USB3) && retries-- &&
1744 		    (t1 & PORT_PLS_MASK) == XDEV_POLLING) {
1745 			spin_unlock_irqrestore(&xhci->lock, flags);
1746 			msleep(XHCI_PORT_POLLING_LFPS_TIME);
1747 			spin_lock_irqsave(&xhci->lock, flags);
1748 			xhci_dbg(xhci, "port %d-%d polling in bus suspend, waiting\n",
1749 				 hcd->self.busnum, port_index + 1);
1750 			goto retry;
1751 		}
1752 		/* bail out if port detected a over-current condition */
1753 		if (t1 & PORT_OC) {
1754 			bus_state->bus_suspended = 0;
1755 			spin_unlock_irqrestore(&xhci->lock, flags);
1756 			xhci_dbg(xhci, "Bus suspend bailout, port over-current detected\n");
1757 			return -EBUSY;
1758 		}
1759 		/* suspend ports in U0, or bail out for new connect changes */
1760 		if ((t1 & PORT_PE) && (t1 & PORT_PLS_MASK) == XDEV_U0) {
1761 			if ((t1 & PORT_CSC) && wake_enabled) {
1762 				bus_state->bus_suspended = 0;
1763 				spin_unlock_irqrestore(&xhci->lock, flags);
1764 				xhci_dbg(xhci, "Bus suspend bailout, port connect change\n");
1765 				return -EBUSY;
1766 			}
1767 			xhci_dbg(xhci, "port %d-%d not suspended\n",
1768 				 hcd->self.busnum, port_index + 1);
1769 			t2 &= ~PORT_PLS_MASK;
1770 			t2 |= PORT_LINK_STROBE | XDEV_U3;
1771 			set_bit(port_index, &bus_state->bus_suspended);
1772 		}
1773 		/* USB core sets remote wake mask for USB 3.0 hubs,
1774 		 * including the USB 3.0 roothub, but only if CONFIG_PM
1775 		 * is enabled, so also enable remote wake here.
1776 		 */
1777 		if (wake_enabled) {
1778 			if (t1 & PORT_CONNECT) {
1779 				t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1780 				t2 &= ~PORT_WKCONN_E;
1781 			} else {
1782 				t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1783 				t2 &= ~PORT_WKDISC_E;
1784 			}
1785 
1786 			if ((xhci->quirks & XHCI_U2_DISABLE_WAKE) &&
1787 			    (hcd->speed < HCD_USB3)) {
1788 				if (usb_amd_pt_check_port(hcd->self.controller,
1789 							  port_index))
1790 					t2 &= ~PORT_WAKE_BITS;
1791 			}
1792 		} else
1793 			t2 &= ~PORT_WAKE_BITS;
1794 
1795 		t1 = xhci_port_state_to_neutral(t1);
1796 		if (t1 != t2)
1797 			portsc_buf[port_index] = t2;
1798 	}
1799 
1800 	/* write port settings, stopping and suspending ports if needed */
1801 	port_index = max_ports;
1802 	while (port_index--) {
1803 		if (!portsc_buf[port_index])
1804 			continue;
1805 		if (test_bit(port_index, &bus_state->bus_suspended)) {
1806 			int slot_id;
1807 
1808 			slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1809 							    port_index + 1);
1810 			if (slot_id) {
1811 				spin_unlock_irqrestore(&xhci->lock, flags);
1812 				xhci_stop_device(xhci, slot_id, 1);
1813 				spin_lock_irqsave(&xhci->lock, flags);
1814 			}
1815 		}
1816 		writel(portsc_buf[port_index], ports[port_index]->addr);
1817 	}
1818 	hcd->state = HC_STATE_SUSPENDED;
1819 	bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1820 	spin_unlock_irqrestore(&xhci->lock, flags);
1821 
1822 	if (bus_state->bus_suspended)
1823 		usleep_range(5000, 10000);
1824 
1825 	return 0;
1826 }
1827 
1828 /*
1829  * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3.
1830  * warm reset a USB3 device stuck in polling or compliance mode after resume.
1831  * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8
1832  */
xhci_port_missing_cas_quirk(struct xhci_port * port)1833 static bool xhci_port_missing_cas_quirk(struct xhci_port *port)
1834 {
1835 	u32 portsc;
1836 
1837 	portsc = readl(port->addr);
1838 
1839 	/* if any of these are set we are not stuck */
1840 	if (portsc & (PORT_CONNECT | PORT_CAS))
1841 		return false;
1842 
1843 	if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) &&
1844 	    ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE))
1845 		return false;
1846 
1847 	/* clear wakeup/change bits, and do a warm port reset */
1848 	portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1849 	portsc |= PORT_WR;
1850 	writel(portsc, port->addr);
1851 	/* flush write */
1852 	readl(port->addr);
1853 	return true;
1854 }
1855 
xhci_bus_resume(struct usb_hcd * hcd)1856 int xhci_bus_resume(struct usb_hcd *hcd)
1857 {
1858 	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
1859 	struct xhci_bus_state *bus_state;
1860 	unsigned long flags;
1861 	int max_ports, port_index;
1862 	int slot_id;
1863 	int sret;
1864 	u32 next_state;
1865 	u32 temp, portsc;
1866 	struct xhci_hub *rhub;
1867 	struct xhci_port **ports;
1868 
1869 	rhub = xhci_get_rhub(hcd);
1870 	ports = rhub->ports;
1871 	max_ports = rhub->num_ports;
1872 	bus_state = &rhub->bus_state;
1873 
1874 	if (time_before(jiffies, bus_state->next_statechange))
1875 		msleep(5);
1876 
1877 	spin_lock_irqsave(&xhci->lock, flags);
1878 	if (!HCD_HW_ACCESSIBLE(hcd)) {
1879 		spin_unlock_irqrestore(&xhci->lock, flags);
1880 		return -ESHUTDOWN;
1881 	}
1882 
1883 	/* delay the irqs */
1884 	temp = readl(&xhci->op_regs->command);
1885 	temp &= ~CMD_EIE;
1886 	writel(temp, &xhci->op_regs->command);
1887 
1888 	/* bus specific resume for ports we suspended at bus_suspend */
1889 	if (hcd->speed >= HCD_USB3)
1890 		next_state = XDEV_U0;
1891 	else
1892 		next_state = XDEV_RESUME;
1893 
1894 	port_index = max_ports;
1895 	while (port_index--) {
1896 		portsc = readl(ports[port_index]->addr);
1897 
1898 		/* warm reset CAS limited ports stuck in polling/compliance */
1899 		if ((xhci->quirks & XHCI_MISSING_CAS) &&
1900 		    (hcd->speed >= HCD_USB3) &&
1901 		    xhci_port_missing_cas_quirk(ports[port_index])) {
1902 			xhci_dbg(xhci, "reset stuck port %d-%d\n",
1903 				 hcd->self.busnum, port_index + 1);
1904 			clear_bit(port_index, &bus_state->bus_suspended);
1905 			continue;
1906 		}
1907 		/* resume if we suspended the link, and it is still suspended */
1908 		if (test_bit(port_index, &bus_state->bus_suspended))
1909 			switch (portsc & PORT_PLS_MASK) {
1910 			case XDEV_U3:
1911 				portsc = xhci_port_state_to_neutral(portsc);
1912 				portsc &= ~PORT_PLS_MASK;
1913 				portsc |= PORT_LINK_STROBE | next_state;
1914 				break;
1915 			case XDEV_RESUME:
1916 				/* resume already initiated */
1917 				break;
1918 			default:
1919 				/* not in a resumeable state, ignore it */
1920 				clear_bit(port_index,
1921 					  &bus_state->bus_suspended);
1922 				break;
1923 			}
1924 		/* disable wake for all ports, write new link state if needed */
1925 		portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1926 		writel(portsc, ports[port_index]->addr);
1927 	}
1928 
1929 	/* USB2 specific resume signaling delay and U0 link state transition */
1930 	if (hcd->speed < HCD_USB3) {
1931 		if (bus_state->bus_suspended) {
1932 			spin_unlock_irqrestore(&xhci->lock, flags);
1933 			msleep(USB_RESUME_TIMEOUT);
1934 			spin_lock_irqsave(&xhci->lock, flags);
1935 		}
1936 		for_each_set_bit(port_index, &bus_state->bus_suspended,
1937 				 BITS_PER_LONG) {
1938 			/* Clear PLC to poll it later for U0 transition */
1939 			xhci_test_and_clear_bit(xhci, ports[port_index],
1940 						PORT_PLC);
1941 			xhci_set_link_state(xhci, ports[port_index], XDEV_U0);
1942 		}
1943 	}
1944 
1945 	/* poll for U0 link state complete, both USB2 and USB3 */
1946 	for_each_set_bit(port_index, &bus_state->bus_suspended, BITS_PER_LONG) {
1947 		sret = xhci_handshake(ports[port_index]->addr, PORT_PLC,
1948 				      PORT_PLC, 10 * 1000);
1949 		if (sret) {
1950 			xhci_warn(xhci, "port %d-%d resume PLC timeout\n",
1951 				  hcd->self.busnum, port_index + 1);
1952 			continue;
1953 		}
1954 		xhci_test_and_clear_bit(xhci, ports[port_index], PORT_PLC);
1955 		slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1);
1956 		if (slot_id)
1957 			xhci_ring_device(xhci, slot_id);
1958 	}
1959 	(void) readl(&xhci->op_regs->command);
1960 
1961 	bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1962 	/* re-enable irqs */
1963 	temp = readl(&xhci->op_regs->command);
1964 	temp |= CMD_EIE;
1965 	writel(temp, &xhci->op_regs->command);
1966 	temp = readl(&xhci->op_regs->command);
1967 
1968 	spin_unlock_irqrestore(&xhci->lock, flags);
1969 	return 0;
1970 }
1971 
xhci_get_resuming_ports(struct usb_hcd * hcd)1972 unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd)
1973 {
1974 	struct xhci_hub *rhub = xhci_get_rhub(hcd);
1975 
1976 	/* USB3 port wakeups are reported via usb_wakeup_notification() */
1977 	return rhub->bus_state.resuming_ports;	/* USB2 ports only */
1978 }
1979 
1980 #endif	/* CONFIG_PM */
1981