1 /*
2 * AMD 10Gb Ethernet driver
3 *
4 * This file is available to you under your choice of the following two
5 * licenses:
6 *
7 * License 1: GPLv2
8 *
9 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
10 *
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 *
24 * This file incorporates work covered by the following copyright and
25 * permission notice:
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
29 * and you.
30 *
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
40 *
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
43 *
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
55 *
56 *
57 * License 2: Modified BSD
58 *
59 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
60 * All rights reserved.
61 *
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
72 *
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
83 *
84 * This file incorporates work covered by the following copyright and
85 * permission notice:
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
89 * and you.
90 *
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
100 *
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
103 *
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
115 */
116
117 #include <linux/module.h>
118 #include <linux/spinlock.h>
119 #include <linux/tcp.h>
120 #include <linux/if_vlan.h>
121 #include <linux/interrupt.h>
122 #include <linux/clk.h>
123 #include <linux/if_ether.h>
124 #include <linux/net_tstamp.h>
125 #include <linux/phy.h>
126 #include <net/vxlan.h>
127
128 #include "xgbe.h"
129 #include "xgbe-common.h"
130
131 static unsigned int ecc_sec_info_threshold = 10;
132 static unsigned int ecc_sec_warn_threshold = 10000;
133 static unsigned int ecc_sec_period = 600;
134 static unsigned int ecc_ded_threshold = 2;
135 static unsigned int ecc_ded_period = 600;
136
137 #ifdef CONFIG_AMD_XGBE_HAVE_ECC
138 /* Only expose the ECC parameters if supported */
139 module_param(ecc_sec_info_threshold, uint, 0644);
140 MODULE_PARM_DESC(ecc_sec_info_threshold,
141 " ECC corrected error informational threshold setting");
142
143 module_param(ecc_sec_warn_threshold, uint, 0644);
144 MODULE_PARM_DESC(ecc_sec_warn_threshold,
145 " ECC corrected error warning threshold setting");
146
147 module_param(ecc_sec_period, uint, 0644);
148 MODULE_PARM_DESC(ecc_sec_period, " ECC corrected error period (in seconds)");
149
150 module_param(ecc_ded_threshold, uint, 0644);
151 MODULE_PARM_DESC(ecc_ded_threshold, " ECC detected error threshold setting");
152
153 module_param(ecc_ded_period, uint, 0644);
154 MODULE_PARM_DESC(ecc_ded_period, " ECC detected error period (in seconds)");
155 #endif
156
157 static int xgbe_one_poll(struct napi_struct *, int);
158 static int xgbe_all_poll(struct napi_struct *, int);
159 static void xgbe_stop(struct xgbe_prv_data *);
160
xgbe_alloc_node(size_t size,int node)161 static void *xgbe_alloc_node(size_t size, int node)
162 {
163 void *mem;
164
165 mem = kzalloc_node(size, GFP_KERNEL, node);
166 if (!mem)
167 mem = kzalloc(size, GFP_KERNEL);
168
169 return mem;
170 }
171
xgbe_free_channels(struct xgbe_prv_data * pdata)172 static void xgbe_free_channels(struct xgbe_prv_data *pdata)
173 {
174 unsigned int i;
175
176 for (i = 0; i < ARRAY_SIZE(pdata->channel); i++) {
177 if (!pdata->channel[i])
178 continue;
179
180 kfree(pdata->channel[i]->rx_ring);
181 kfree(pdata->channel[i]->tx_ring);
182 kfree(pdata->channel[i]);
183
184 pdata->channel[i] = NULL;
185 }
186
187 pdata->channel_count = 0;
188 }
189
xgbe_alloc_channels(struct xgbe_prv_data * pdata)190 static int xgbe_alloc_channels(struct xgbe_prv_data *pdata)
191 {
192 struct xgbe_channel *channel;
193 struct xgbe_ring *ring;
194 unsigned int count, i;
195 unsigned int cpu;
196 int node;
197
198 count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count);
199 for (i = 0; i < count; i++) {
200 /* Attempt to use a CPU on the node the device is on */
201 cpu = cpumask_local_spread(i, dev_to_node(pdata->dev));
202
203 /* Set the allocation node based on the returned CPU */
204 node = cpu_to_node(cpu);
205
206 channel = xgbe_alloc_node(sizeof(*channel), node);
207 if (!channel)
208 goto err_mem;
209 pdata->channel[i] = channel;
210
211 snprintf(channel->name, sizeof(channel->name), "channel-%u", i);
212 channel->pdata = pdata;
213 channel->queue_index = i;
214 channel->dma_regs = pdata->xgmac_regs + DMA_CH_BASE +
215 (DMA_CH_INC * i);
216 channel->node = node;
217 cpumask_set_cpu(cpu, &channel->affinity_mask);
218
219 if (pdata->per_channel_irq)
220 channel->dma_irq = pdata->channel_irq[i];
221
222 if (i < pdata->tx_ring_count) {
223 ring = xgbe_alloc_node(sizeof(*ring), node);
224 if (!ring)
225 goto err_mem;
226
227 spin_lock_init(&ring->lock);
228 ring->node = node;
229
230 channel->tx_ring = ring;
231 }
232
233 if (i < pdata->rx_ring_count) {
234 ring = xgbe_alloc_node(sizeof(*ring), node);
235 if (!ring)
236 goto err_mem;
237
238 spin_lock_init(&ring->lock);
239 ring->node = node;
240
241 channel->rx_ring = ring;
242 }
243
244 netif_dbg(pdata, drv, pdata->netdev,
245 "%s: cpu=%u, node=%d\n", channel->name, cpu, node);
246
247 netif_dbg(pdata, drv, pdata->netdev,
248 "%s: dma_regs=%p, dma_irq=%d, tx=%p, rx=%p\n",
249 channel->name, channel->dma_regs, channel->dma_irq,
250 channel->tx_ring, channel->rx_ring);
251 }
252
253 pdata->channel_count = count;
254
255 return 0;
256
257 err_mem:
258 xgbe_free_channels(pdata);
259
260 return -ENOMEM;
261 }
262
xgbe_tx_avail_desc(struct xgbe_ring * ring)263 static inline unsigned int xgbe_tx_avail_desc(struct xgbe_ring *ring)
264 {
265 return (ring->rdesc_count - (ring->cur - ring->dirty));
266 }
267
xgbe_rx_dirty_desc(struct xgbe_ring * ring)268 static inline unsigned int xgbe_rx_dirty_desc(struct xgbe_ring *ring)
269 {
270 return (ring->cur - ring->dirty);
271 }
272
xgbe_maybe_stop_tx_queue(struct xgbe_channel * channel,struct xgbe_ring * ring,unsigned int count)273 static int xgbe_maybe_stop_tx_queue(struct xgbe_channel *channel,
274 struct xgbe_ring *ring, unsigned int count)
275 {
276 struct xgbe_prv_data *pdata = channel->pdata;
277
278 if (count > xgbe_tx_avail_desc(ring)) {
279 netif_info(pdata, drv, pdata->netdev,
280 "Tx queue stopped, not enough descriptors available\n");
281 netif_stop_subqueue(pdata->netdev, channel->queue_index);
282 ring->tx.queue_stopped = 1;
283
284 /* If we haven't notified the hardware because of xmit_more
285 * support, tell it now
286 */
287 if (ring->tx.xmit_more)
288 pdata->hw_if.tx_start_xmit(channel, ring);
289
290 return NETDEV_TX_BUSY;
291 }
292
293 return 0;
294 }
295
xgbe_calc_rx_buf_size(struct net_device * netdev,unsigned int mtu)296 static int xgbe_calc_rx_buf_size(struct net_device *netdev, unsigned int mtu)
297 {
298 unsigned int rx_buf_size;
299
300 rx_buf_size = mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
301 rx_buf_size = clamp_val(rx_buf_size, XGBE_RX_MIN_BUF_SIZE, PAGE_SIZE);
302
303 rx_buf_size = (rx_buf_size + XGBE_RX_BUF_ALIGN - 1) &
304 ~(XGBE_RX_BUF_ALIGN - 1);
305
306 return rx_buf_size;
307 }
308
xgbe_enable_rx_tx_int(struct xgbe_prv_data * pdata,struct xgbe_channel * channel)309 static void xgbe_enable_rx_tx_int(struct xgbe_prv_data *pdata,
310 struct xgbe_channel *channel)
311 {
312 struct xgbe_hw_if *hw_if = &pdata->hw_if;
313 enum xgbe_int int_id;
314
315 if (channel->tx_ring && channel->rx_ring)
316 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
317 else if (channel->tx_ring)
318 int_id = XGMAC_INT_DMA_CH_SR_TI;
319 else if (channel->rx_ring)
320 int_id = XGMAC_INT_DMA_CH_SR_RI;
321 else
322 return;
323
324 hw_if->enable_int(channel, int_id);
325 }
326
xgbe_enable_rx_tx_ints(struct xgbe_prv_data * pdata)327 static void xgbe_enable_rx_tx_ints(struct xgbe_prv_data *pdata)
328 {
329 unsigned int i;
330
331 for (i = 0; i < pdata->channel_count; i++)
332 xgbe_enable_rx_tx_int(pdata, pdata->channel[i]);
333 }
334
xgbe_disable_rx_tx_int(struct xgbe_prv_data * pdata,struct xgbe_channel * channel)335 static void xgbe_disable_rx_tx_int(struct xgbe_prv_data *pdata,
336 struct xgbe_channel *channel)
337 {
338 struct xgbe_hw_if *hw_if = &pdata->hw_if;
339 enum xgbe_int int_id;
340
341 if (channel->tx_ring && channel->rx_ring)
342 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
343 else if (channel->tx_ring)
344 int_id = XGMAC_INT_DMA_CH_SR_TI;
345 else if (channel->rx_ring)
346 int_id = XGMAC_INT_DMA_CH_SR_RI;
347 else
348 return;
349
350 hw_if->disable_int(channel, int_id);
351 }
352
xgbe_disable_rx_tx_ints(struct xgbe_prv_data * pdata)353 static void xgbe_disable_rx_tx_ints(struct xgbe_prv_data *pdata)
354 {
355 unsigned int i;
356
357 for (i = 0; i < pdata->channel_count; i++)
358 xgbe_disable_rx_tx_int(pdata, pdata->channel[i]);
359 }
360
xgbe_ecc_sec(struct xgbe_prv_data * pdata,unsigned long * period,unsigned int * count,const char * area)361 static bool xgbe_ecc_sec(struct xgbe_prv_data *pdata, unsigned long *period,
362 unsigned int *count, const char *area)
363 {
364 if (time_before(jiffies, *period)) {
365 (*count)++;
366 } else {
367 *period = jiffies + (ecc_sec_period * HZ);
368 *count = 1;
369 }
370
371 if (*count > ecc_sec_info_threshold)
372 dev_warn_once(pdata->dev,
373 "%s ECC corrected errors exceed informational threshold\n",
374 area);
375
376 if (*count > ecc_sec_warn_threshold) {
377 dev_warn_once(pdata->dev,
378 "%s ECC corrected errors exceed warning threshold\n",
379 area);
380 return true;
381 }
382
383 return false;
384 }
385
xgbe_ecc_ded(struct xgbe_prv_data * pdata,unsigned long * period,unsigned int * count,const char * area)386 static bool xgbe_ecc_ded(struct xgbe_prv_data *pdata, unsigned long *period,
387 unsigned int *count, const char *area)
388 {
389 if (time_before(jiffies, *period)) {
390 (*count)++;
391 } else {
392 *period = jiffies + (ecc_ded_period * HZ);
393 *count = 1;
394 }
395
396 if (*count > ecc_ded_threshold) {
397 netdev_alert(pdata->netdev,
398 "%s ECC detected errors exceed threshold\n",
399 area);
400 return true;
401 }
402
403 return false;
404 }
405
xgbe_ecc_isr_task(struct tasklet_struct * t)406 static void xgbe_ecc_isr_task(struct tasklet_struct *t)
407 {
408 struct xgbe_prv_data *pdata = from_tasklet(pdata, t, tasklet_ecc);
409 unsigned int ecc_isr;
410 bool stop = false;
411
412 /* Mask status with only the interrupts we care about */
413 ecc_isr = XP_IOREAD(pdata, XP_ECC_ISR);
414 ecc_isr &= XP_IOREAD(pdata, XP_ECC_IER);
415 netif_dbg(pdata, intr, pdata->netdev, "ECC_ISR=%#010x\n", ecc_isr);
416
417 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, TX_DED)) {
418 stop |= xgbe_ecc_ded(pdata, &pdata->tx_ded_period,
419 &pdata->tx_ded_count, "TX fifo");
420 }
421
422 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, RX_DED)) {
423 stop |= xgbe_ecc_ded(pdata, &pdata->rx_ded_period,
424 &pdata->rx_ded_count, "RX fifo");
425 }
426
427 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, DESC_DED)) {
428 stop |= xgbe_ecc_ded(pdata, &pdata->desc_ded_period,
429 &pdata->desc_ded_count,
430 "descriptor cache");
431 }
432
433 if (stop) {
434 pdata->hw_if.disable_ecc_ded(pdata);
435 schedule_work(&pdata->stopdev_work);
436 goto out;
437 }
438
439 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, TX_SEC)) {
440 if (xgbe_ecc_sec(pdata, &pdata->tx_sec_period,
441 &pdata->tx_sec_count, "TX fifo"))
442 pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_TX);
443 }
444
445 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, RX_SEC))
446 if (xgbe_ecc_sec(pdata, &pdata->rx_sec_period,
447 &pdata->rx_sec_count, "RX fifo"))
448 pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_RX);
449
450 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, DESC_SEC))
451 if (xgbe_ecc_sec(pdata, &pdata->desc_sec_period,
452 &pdata->desc_sec_count, "descriptor cache"))
453 pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_DESC);
454
455 out:
456 /* Clear all ECC interrupts */
457 XP_IOWRITE(pdata, XP_ECC_ISR, ecc_isr);
458
459 /* Reissue interrupt if status is not clear */
460 if (pdata->vdata->irq_reissue_support)
461 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 1);
462 }
463
xgbe_ecc_isr(int irq,void * data)464 static irqreturn_t xgbe_ecc_isr(int irq, void *data)
465 {
466 struct xgbe_prv_data *pdata = data;
467
468 if (pdata->isr_as_tasklet)
469 tasklet_schedule(&pdata->tasklet_ecc);
470 else
471 xgbe_ecc_isr_task(&pdata->tasklet_ecc);
472
473 return IRQ_HANDLED;
474 }
475
xgbe_isr_task(struct tasklet_struct * t)476 static void xgbe_isr_task(struct tasklet_struct *t)
477 {
478 struct xgbe_prv_data *pdata = from_tasklet(pdata, t, tasklet_dev);
479 struct xgbe_hw_if *hw_if = &pdata->hw_if;
480 struct xgbe_channel *channel;
481 unsigned int dma_isr, dma_ch_isr;
482 unsigned int mac_isr, mac_tssr, mac_mdioisr;
483 unsigned int i;
484
485 /* The DMA interrupt status register also reports MAC and MTL
486 * interrupts. So for polling mode, we just need to check for
487 * this register to be non-zero
488 */
489 dma_isr = XGMAC_IOREAD(pdata, DMA_ISR);
490 if (!dma_isr)
491 goto isr_done;
492
493 netif_dbg(pdata, intr, pdata->netdev, "DMA_ISR=%#010x\n", dma_isr);
494
495 for (i = 0; i < pdata->channel_count; i++) {
496 if (!(dma_isr & (1 << i)))
497 continue;
498
499 channel = pdata->channel[i];
500
501 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
502 netif_dbg(pdata, intr, pdata->netdev, "DMA_CH%u_ISR=%#010x\n",
503 i, dma_ch_isr);
504
505 /* The TI or RI interrupt bits may still be set even if using
506 * per channel DMA interrupts. Check to be sure those are not
507 * enabled before using the private data napi structure.
508 */
509 if (!pdata->per_channel_irq &&
510 (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) ||
511 XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI))) {
512 if (napi_schedule_prep(&pdata->napi)) {
513 /* Disable Tx and Rx interrupts */
514 xgbe_disable_rx_tx_ints(pdata);
515
516 /* Turn on polling */
517 __napi_schedule(&pdata->napi);
518 }
519 } else {
520 /* Don't clear Rx/Tx status if doing per channel DMA
521 * interrupts, these will be cleared by the ISR for
522 * per channel DMA interrupts.
523 */
524 XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, TI, 0);
525 XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, RI, 0);
526 }
527
528 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RBU))
529 pdata->ext_stats.rx_buffer_unavailable++;
530
531 /* Restart the device on a Fatal Bus Error */
532 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, FBE))
533 schedule_work(&pdata->restart_work);
534
535 /* Clear interrupt signals */
536 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
537 }
538
539 if (XGMAC_GET_BITS(dma_isr, DMA_ISR, MACIS)) {
540 mac_isr = XGMAC_IOREAD(pdata, MAC_ISR);
541
542 netif_dbg(pdata, intr, pdata->netdev, "MAC_ISR=%#010x\n",
543 mac_isr);
544
545 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCTXIS))
546 hw_if->tx_mmc_int(pdata);
547
548 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCRXIS))
549 hw_if->rx_mmc_int(pdata);
550
551 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, TSIS)) {
552 mac_tssr = XGMAC_IOREAD(pdata, MAC_TSSR);
553
554 netif_dbg(pdata, intr, pdata->netdev,
555 "MAC_TSSR=%#010x\n", mac_tssr);
556
557 if (XGMAC_GET_BITS(mac_tssr, MAC_TSSR, TXTSC)) {
558 /* Read Tx Timestamp to clear interrupt */
559 pdata->tx_tstamp =
560 hw_if->get_tx_tstamp(pdata);
561 queue_work(pdata->dev_workqueue,
562 &pdata->tx_tstamp_work);
563 }
564 }
565
566 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, SMI)) {
567 mac_mdioisr = XGMAC_IOREAD(pdata, MAC_MDIOISR);
568
569 netif_dbg(pdata, intr, pdata->netdev,
570 "MAC_MDIOISR=%#010x\n", mac_mdioisr);
571
572 if (XGMAC_GET_BITS(mac_mdioisr, MAC_MDIOISR,
573 SNGLCOMPINT))
574 complete(&pdata->mdio_complete);
575 }
576 }
577
578 isr_done:
579 /* If there is not a separate AN irq, handle it here */
580 if (pdata->dev_irq == pdata->an_irq)
581 pdata->phy_if.an_isr(pdata);
582
583 /* If there is not a separate ECC irq, handle it here */
584 if (pdata->vdata->ecc_support && (pdata->dev_irq == pdata->ecc_irq))
585 xgbe_ecc_isr_task(&pdata->tasklet_ecc);
586
587 /* If there is not a separate I2C irq, handle it here */
588 if (pdata->vdata->i2c_support && (pdata->dev_irq == pdata->i2c_irq))
589 pdata->i2c_if.i2c_isr(pdata);
590
591 /* Reissue interrupt if status is not clear */
592 if (pdata->vdata->irq_reissue_support) {
593 unsigned int reissue_mask;
594
595 reissue_mask = 1 << 0;
596 if (!pdata->per_channel_irq)
597 reissue_mask |= 0xffff << 4;
598
599 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, reissue_mask);
600 }
601 }
602
xgbe_isr(int irq,void * data)603 static irqreturn_t xgbe_isr(int irq, void *data)
604 {
605 struct xgbe_prv_data *pdata = data;
606
607 if (pdata->isr_as_tasklet)
608 tasklet_schedule(&pdata->tasklet_dev);
609 else
610 xgbe_isr_task(&pdata->tasklet_dev);
611
612 return IRQ_HANDLED;
613 }
614
xgbe_dma_isr(int irq,void * data)615 static irqreturn_t xgbe_dma_isr(int irq, void *data)
616 {
617 struct xgbe_channel *channel = data;
618 struct xgbe_prv_data *pdata = channel->pdata;
619 unsigned int dma_status;
620
621 /* Per channel DMA interrupts are enabled, so we use the per
622 * channel napi structure and not the private data napi structure
623 */
624 if (napi_schedule_prep(&channel->napi)) {
625 /* Disable Tx and Rx interrupts */
626 if (pdata->channel_irq_mode)
627 xgbe_disable_rx_tx_int(pdata, channel);
628 else
629 disable_irq_nosync(channel->dma_irq);
630
631 /* Turn on polling */
632 __napi_schedule_irqoff(&channel->napi);
633 }
634
635 /* Clear Tx/Rx signals */
636 dma_status = 0;
637 XGMAC_SET_BITS(dma_status, DMA_CH_SR, TI, 1);
638 XGMAC_SET_BITS(dma_status, DMA_CH_SR, RI, 1);
639 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_status);
640
641 return IRQ_HANDLED;
642 }
643
xgbe_tx_timer(struct timer_list * t)644 static void xgbe_tx_timer(struct timer_list *t)
645 {
646 struct xgbe_channel *channel = from_timer(channel, t, tx_timer);
647 struct xgbe_prv_data *pdata = channel->pdata;
648 struct napi_struct *napi;
649
650 DBGPR("-->xgbe_tx_timer\n");
651
652 napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi;
653
654 if (napi_schedule_prep(napi)) {
655 /* Disable Tx and Rx interrupts */
656 if (pdata->per_channel_irq)
657 if (pdata->channel_irq_mode)
658 xgbe_disable_rx_tx_int(pdata, channel);
659 else
660 disable_irq_nosync(channel->dma_irq);
661 else
662 xgbe_disable_rx_tx_ints(pdata);
663
664 /* Turn on polling */
665 __napi_schedule(napi);
666 }
667
668 channel->tx_timer_active = 0;
669
670 DBGPR("<--xgbe_tx_timer\n");
671 }
672
xgbe_service(struct work_struct * work)673 static void xgbe_service(struct work_struct *work)
674 {
675 struct xgbe_prv_data *pdata = container_of(work,
676 struct xgbe_prv_data,
677 service_work);
678
679 pdata->phy_if.phy_status(pdata);
680 }
681
xgbe_service_timer(struct timer_list * t)682 static void xgbe_service_timer(struct timer_list *t)
683 {
684 struct xgbe_prv_data *pdata = from_timer(pdata, t, service_timer);
685
686 queue_work(pdata->dev_workqueue, &pdata->service_work);
687
688 mod_timer(&pdata->service_timer, jiffies + HZ);
689 }
690
xgbe_init_timers(struct xgbe_prv_data * pdata)691 static void xgbe_init_timers(struct xgbe_prv_data *pdata)
692 {
693 struct xgbe_channel *channel;
694 unsigned int i;
695
696 timer_setup(&pdata->service_timer, xgbe_service_timer, 0);
697
698 for (i = 0; i < pdata->channel_count; i++) {
699 channel = pdata->channel[i];
700 if (!channel->tx_ring)
701 break;
702
703 timer_setup(&channel->tx_timer, xgbe_tx_timer, 0);
704 }
705 }
706
xgbe_start_timers(struct xgbe_prv_data * pdata)707 static void xgbe_start_timers(struct xgbe_prv_data *pdata)
708 {
709 mod_timer(&pdata->service_timer, jiffies + HZ);
710 }
711
xgbe_stop_timers(struct xgbe_prv_data * pdata)712 static void xgbe_stop_timers(struct xgbe_prv_data *pdata)
713 {
714 struct xgbe_channel *channel;
715 unsigned int i;
716
717 del_timer_sync(&pdata->service_timer);
718
719 for (i = 0; i < pdata->channel_count; i++) {
720 channel = pdata->channel[i];
721 if (!channel->tx_ring)
722 break;
723
724 /* Deactivate the Tx timer */
725 del_timer_sync(&channel->tx_timer);
726 channel->tx_timer_active = 0;
727 }
728 }
729
xgbe_get_all_hw_features(struct xgbe_prv_data * pdata)730 void xgbe_get_all_hw_features(struct xgbe_prv_data *pdata)
731 {
732 unsigned int mac_hfr0, mac_hfr1, mac_hfr2;
733 struct xgbe_hw_features *hw_feat = &pdata->hw_feat;
734
735 mac_hfr0 = XGMAC_IOREAD(pdata, MAC_HWF0R);
736 mac_hfr1 = XGMAC_IOREAD(pdata, MAC_HWF1R);
737 mac_hfr2 = XGMAC_IOREAD(pdata, MAC_HWF2R);
738
739 memset(hw_feat, 0, sizeof(*hw_feat));
740
741 hw_feat->version = XGMAC_IOREAD(pdata, MAC_VR);
742
743 /* Hardware feature register 0 */
744 hw_feat->gmii = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL);
745 hw_feat->vlhash = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH);
746 hw_feat->sma = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL);
747 hw_feat->rwk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL);
748 hw_feat->mgk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL);
749 hw_feat->mmc = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL);
750 hw_feat->aoe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL);
751 hw_feat->ts = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL);
752 hw_feat->eee = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL);
753 hw_feat->tx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL);
754 hw_feat->rx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL);
755 hw_feat->addn_mac = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R,
756 ADDMACADRSEL);
757 hw_feat->ts_src = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL);
758 hw_feat->sa_vlan_ins = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS);
759 hw_feat->vxn = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VXN);
760
761 /* Hardware feature register 1 */
762 hw_feat->rx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
763 RXFIFOSIZE);
764 hw_feat->tx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
765 TXFIFOSIZE);
766 hw_feat->adv_ts_hi = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADVTHWORD);
767 hw_feat->dma_width = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64);
768 hw_feat->dcb = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN);
769 hw_feat->sph = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN);
770 hw_feat->tso = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN);
771 hw_feat->dma_debug = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA);
772 hw_feat->rss = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN);
773 hw_feat->tc_cnt = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC);
774 hw_feat->hash_table_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
775 HASHTBLSZ);
776 hw_feat->l3l4_filter_num = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
777 L3L4FNUM);
778
779 /* Hardware feature register 2 */
780 hw_feat->rx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT);
781 hw_feat->tx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT);
782 hw_feat->rx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT);
783 hw_feat->tx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT);
784 hw_feat->pps_out_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM);
785 hw_feat->aux_snap_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, AUXSNAPNUM);
786
787 /* Translate the Hash Table size into actual number */
788 switch (hw_feat->hash_table_size) {
789 case 0:
790 break;
791 case 1:
792 hw_feat->hash_table_size = 64;
793 break;
794 case 2:
795 hw_feat->hash_table_size = 128;
796 break;
797 case 3:
798 hw_feat->hash_table_size = 256;
799 break;
800 }
801
802 /* Translate the address width setting into actual number */
803 switch (hw_feat->dma_width) {
804 case 0:
805 hw_feat->dma_width = 32;
806 break;
807 case 1:
808 hw_feat->dma_width = 40;
809 break;
810 case 2:
811 hw_feat->dma_width = 48;
812 break;
813 default:
814 hw_feat->dma_width = 32;
815 }
816
817 /* The Queue, Channel and TC counts are zero based so increment them
818 * to get the actual number
819 */
820 hw_feat->rx_q_cnt++;
821 hw_feat->tx_q_cnt++;
822 hw_feat->rx_ch_cnt++;
823 hw_feat->tx_ch_cnt++;
824 hw_feat->tc_cnt++;
825
826 /* Translate the fifo sizes into actual numbers */
827 hw_feat->rx_fifo_size = 1 << (hw_feat->rx_fifo_size + 7);
828 hw_feat->tx_fifo_size = 1 << (hw_feat->tx_fifo_size + 7);
829
830 if (netif_msg_probe(pdata)) {
831 dev_dbg(pdata->dev, "Hardware features:\n");
832
833 /* Hardware feature register 0 */
834 dev_dbg(pdata->dev, " 1GbE support : %s\n",
835 hw_feat->gmii ? "yes" : "no");
836 dev_dbg(pdata->dev, " VLAN hash filter : %s\n",
837 hw_feat->vlhash ? "yes" : "no");
838 dev_dbg(pdata->dev, " MDIO interface : %s\n",
839 hw_feat->sma ? "yes" : "no");
840 dev_dbg(pdata->dev, " Wake-up packet support : %s\n",
841 hw_feat->rwk ? "yes" : "no");
842 dev_dbg(pdata->dev, " Magic packet support : %s\n",
843 hw_feat->mgk ? "yes" : "no");
844 dev_dbg(pdata->dev, " Management counters : %s\n",
845 hw_feat->mmc ? "yes" : "no");
846 dev_dbg(pdata->dev, " ARP offload : %s\n",
847 hw_feat->aoe ? "yes" : "no");
848 dev_dbg(pdata->dev, " IEEE 1588-2008 Timestamp : %s\n",
849 hw_feat->ts ? "yes" : "no");
850 dev_dbg(pdata->dev, " Energy Efficient Ethernet : %s\n",
851 hw_feat->eee ? "yes" : "no");
852 dev_dbg(pdata->dev, " TX checksum offload : %s\n",
853 hw_feat->tx_coe ? "yes" : "no");
854 dev_dbg(pdata->dev, " RX checksum offload : %s\n",
855 hw_feat->rx_coe ? "yes" : "no");
856 dev_dbg(pdata->dev, " Additional MAC addresses : %u\n",
857 hw_feat->addn_mac);
858 dev_dbg(pdata->dev, " Timestamp source : %s\n",
859 (hw_feat->ts_src == 1) ? "internal" :
860 (hw_feat->ts_src == 2) ? "external" :
861 (hw_feat->ts_src == 3) ? "internal/external" : "n/a");
862 dev_dbg(pdata->dev, " SA/VLAN insertion : %s\n",
863 hw_feat->sa_vlan_ins ? "yes" : "no");
864 dev_dbg(pdata->dev, " VXLAN/NVGRE support : %s\n",
865 hw_feat->vxn ? "yes" : "no");
866
867 /* Hardware feature register 1 */
868 dev_dbg(pdata->dev, " RX fifo size : %u\n",
869 hw_feat->rx_fifo_size);
870 dev_dbg(pdata->dev, " TX fifo size : %u\n",
871 hw_feat->tx_fifo_size);
872 dev_dbg(pdata->dev, " IEEE 1588 high word : %s\n",
873 hw_feat->adv_ts_hi ? "yes" : "no");
874 dev_dbg(pdata->dev, " DMA width : %u\n",
875 hw_feat->dma_width);
876 dev_dbg(pdata->dev, " Data Center Bridging : %s\n",
877 hw_feat->dcb ? "yes" : "no");
878 dev_dbg(pdata->dev, " Split header : %s\n",
879 hw_feat->sph ? "yes" : "no");
880 dev_dbg(pdata->dev, " TCP Segmentation Offload : %s\n",
881 hw_feat->tso ? "yes" : "no");
882 dev_dbg(pdata->dev, " Debug memory interface : %s\n",
883 hw_feat->dma_debug ? "yes" : "no");
884 dev_dbg(pdata->dev, " Receive Side Scaling : %s\n",
885 hw_feat->rss ? "yes" : "no");
886 dev_dbg(pdata->dev, " Traffic Class count : %u\n",
887 hw_feat->tc_cnt);
888 dev_dbg(pdata->dev, " Hash table size : %u\n",
889 hw_feat->hash_table_size);
890 dev_dbg(pdata->dev, " L3/L4 Filters : %u\n",
891 hw_feat->l3l4_filter_num);
892
893 /* Hardware feature register 2 */
894 dev_dbg(pdata->dev, " RX queue count : %u\n",
895 hw_feat->rx_q_cnt);
896 dev_dbg(pdata->dev, " TX queue count : %u\n",
897 hw_feat->tx_q_cnt);
898 dev_dbg(pdata->dev, " RX DMA channel count : %u\n",
899 hw_feat->rx_ch_cnt);
900 dev_dbg(pdata->dev, " TX DMA channel count : %u\n",
901 hw_feat->rx_ch_cnt);
902 dev_dbg(pdata->dev, " PPS outputs : %u\n",
903 hw_feat->pps_out_num);
904 dev_dbg(pdata->dev, " Auxiliary snapshot inputs : %u\n",
905 hw_feat->aux_snap_num);
906 }
907 }
908
xgbe_vxlan_set_port(struct net_device * netdev,unsigned int table,unsigned int entry,struct udp_tunnel_info * ti)909 static int xgbe_vxlan_set_port(struct net_device *netdev, unsigned int table,
910 unsigned int entry, struct udp_tunnel_info *ti)
911 {
912 struct xgbe_prv_data *pdata = netdev_priv(netdev);
913
914 pdata->vxlan_port = be16_to_cpu(ti->port);
915 pdata->hw_if.enable_vxlan(pdata);
916
917 return 0;
918 }
919
xgbe_vxlan_unset_port(struct net_device * netdev,unsigned int table,unsigned int entry,struct udp_tunnel_info * ti)920 static int xgbe_vxlan_unset_port(struct net_device *netdev, unsigned int table,
921 unsigned int entry, struct udp_tunnel_info *ti)
922 {
923 struct xgbe_prv_data *pdata = netdev_priv(netdev);
924
925 pdata->hw_if.disable_vxlan(pdata);
926 pdata->vxlan_port = 0;
927
928 return 0;
929 }
930
931 static const struct udp_tunnel_nic_info xgbe_udp_tunnels = {
932 .set_port = xgbe_vxlan_set_port,
933 .unset_port = xgbe_vxlan_unset_port,
934 .flags = UDP_TUNNEL_NIC_INFO_OPEN_ONLY,
935 .tables = {
936 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, },
937 },
938 };
939
xgbe_get_udp_tunnel_info(void)940 const struct udp_tunnel_nic_info *xgbe_get_udp_tunnel_info(void)
941 {
942 return &xgbe_udp_tunnels;
943 }
944
xgbe_napi_enable(struct xgbe_prv_data * pdata,unsigned int add)945 static void xgbe_napi_enable(struct xgbe_prv_data *pdata, unsigned int add)
946 {
947 struct xgbe_channel *channel;
948 unsigned int i;
949
950 if (pdata->per_channel_irq) {
951 for (i = 0; i < pdata->channel_count; i++) {
952 channel = pdata->channel[i];
953 if (add)
954 netif_napi_add(pdata->netdev, &channel->napi,
955 xgbe_one_poll, NAPI_POLL_WEIGHT);
956
957 napi_enable(&channel->napi);
958 }
959 } else {
960 if (add)
961 netif_napi_add(pdata->netdev, &pdata->napi,
962 xgbe_all_poll, NAPI_POLL_WEIGHT);
963
964 napi_enable(&pdata->napi);
965 }
966 }
967
xgbe_napi_disable(struct xgbe_prv_data * pdata,unsigned int del)968 static void xgbe_napi_disable(struct xgbe_prv_data *pdata, unsigned int del)
969 {
970 struct xgbe_channel *channel;
971 unsigned int i;
972
973 if (pdata->per_channel_irq) {
974 for (i = 0; i < pdata->channel_count; i++) {
975 channel = pdata->channel[i];
976 napi_disable(&channel->napi);
977
978 if (del)
979 netif_napi_del(&channel->napi);
980 }
981 } else {
982 napi_disable(&pdata->napi);
983
984 if (del)
985 netif_napi_del(&pdata->napi);
986 }
987 }
988
xgbe_request_irqs(struct xgbe_prv_data * pdata)989 static int xgbe_request_irqs(struct xgbe_prv_data *pdata)
990 {
991 struct xgbe_channel *channel;
992 struct net_device *netdev = pdata->netdev;
993 unsigned int i;
994 int ret;
995
996 tasklet_setup(&pdata->tasklet_dev, xgbe_isr_task);
997 tasklet_setup(&pdata->tasklet_ecc, xgbe_ecc_isr_task);
998
999 ret = devm_request_irq(pdata->dev, pdata->dev_irq, xgbe_isr, 0,
1000 netdev_name(netdev), pdata);
1001 if (ret) {
1002 netdev_alert(netdev, "error requesting irq %d\n",
1003 pdata->dev_irq);
1004 return ret;
1005 }
1006
1007 if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq)) {
1008 ret = devm_request_irq(pdata->dev, pdata->ecc_irq, xgbe_ecc_isr,
1009 0, pdata->ecc_name, pdata);
1010 if (ret) {
1011 netdev_alert(netdev, "error requesting ecc irq %d\n",
1012 pdata->ecc_irq);
1013 goto err_dev_irq;
1014 }
1015 }
1016
1017 if (!pdata->per_channel_irq)
1018 return 0;
1019
1020 for (i = 0; i < pdata->channel_count; i++) {
1021 channel = pdata->channel[i];
1022 snprintf(channel->dma_irq_name,
1023 sizeof(channel->dma_irq_name) - 1,
1024 "%s-TxRx-%u", netdev_name(netdev),
1025 channel->queue_index);
1026
1027 ret = devm_request_irq(pdata->dev, channel->dma_irq,
1028 xgbe_dma_isr, 0,
1029 channel->dma_irq_name, channel);
1030 if (ret) {
1031 netdev_alert(netdev, "error requesting irq %d\n",
1032 channel->dma_irq);
1033 goto err_dma_irq;
1034 }
1035
1036 irq_set_affinity_hint(channel->dma_irq,
1037 &channel->affinity_mask);
1038 }
1039
1040 return 0;
1041
1042 err_dma_irq:
1043 /* Using an unsigned int, 'i' will go to UINT_MAX and exit */
1044 for (i--; i < pdata->channel_count; i--) {
1045 channel = pdata->channel[i];
1046
1047 irq_set_affinity_hint(channel->dma_irq, NULL);
1048 devm_free_irq(pdata->dev, channel->dma_irq, channel);
1049 }
1050
1051 if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq))
1052 devm_free_irq(pdata->dev, pdata->ecc_irq, pdata);
1053
1054 err_dev_irq:
1055 devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
1056
1057 return ret;
1058 }
1059
xgbe_free_irqs(struct xgbe_prv_data * pdata)1060 static void xgbe_free_irqs(struct xgbe_prv_data *pdata)
1061 {
1062 struct xgbe_channel *channel;
1063 unsigned int i;
1064
1065 devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
1066
1067 if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq))
1068 devm_free_irq(pdata->dev, pdata->ecc_irq, pdata);
1069
1070 if (!pdata->per_channel_irq)
1071 return;
1072
1073 for (i = 0; i < pdata->channel_count; i++) {
1074 channel = pdata->channel[i];
1075
1076 irq_set_affinity_hint(channel->dma_irq, NULL);
1077 devm_free_irq(pdata->dev, channel->dma_irq, channel);
1078 }
1079 }
1080
xgbe_init_tx_coalesce(struct xgbe_prv_data * pdata)1081 void xgbe_init_tx_coalesce(struct xgbe_prv_data *pdata)
1082 {
1083 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1084
1085 DBGPR("-->xgbe_init_tx_coalesce\n");
1086
1087 pdata->tx_usecs = XGMAC_INIT_DMA_TX_USECS;
1088 pdata->tx_frames = XGMAC_INIT_DMA_TX_FRAMES;
1089
1090 hw_if->config_tx_coalesce(pdata);
1091
1092 DBGPR("<--xgbe_init_tx_coalesce\n");
1093 }
1094
xgbe_init_rx_coalesce(struct xgbe_prv_data * pdata)1095 void xgbe_init_rx_coalesce(struct xgbe_prv_data *pdata)
1096 {
1097 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1098
1099 DBGPR("-->xgbe_init_rx_coalesce\n");
1100
1101 pdata->rx_riwt = hw_if->usec_to_riwt(pdata, XGMAC_INIT_DMA_RX_USECS);
1102 pdata->rx_usecs = XGMAC_INIT_DMA_RX_USECS;
1103 pdata->rx_frames = XGMAC_INIT_DMA_RX_FRAMES;
1104
1105 hw_if->config_rx_coalesce(pdata);
1106
1107 DBGPR("<--xgbe_init_rx_coalesce\n");
1108 }
1109
xgbe_free_tx_data(struct xgbe_prv_data * pdata)1110 static void xgbe_free_tx_data(struct xgbe_prv_data *pdata)
1111 {
1112 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1113 struct xgbe_ring *ring;
1114 struct xgbe_ring_data *rdata;
1115 unsigned int i, j;
1116
1117 DBGPR("-->xgbe_free_tx_data\n");
1118
1119 for (i = 0; i < pdata->channel_count; i++) {
1120 ring = pdata->channel[i]->tx_ring;
1121 if (!ring)
1122 break;
1123
1124 for (j = 0; j < ring->rdesc_count; j++) {
1125 rdata = XGBE_GET_DESC_DATA(ring, j);
1126 desc_if->unmap_rdata(pdata, rdata);
1127 }
1128 }
1129
1130 DBGPR("<--xgbe_free_tx_data\n");
1131 }
1132
xgbe_free_rx_data(struct xgbe_prv_data * pdata)1133 static void xgbe_free_rx_data(struct xgbe_prv_data *pdata)
1134 {
1135 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1136 struct xgbe_ring *ring;
1137 struct xgbe_ring_data *rdata;
1138 unsigned int i, j;
1139
1140 DBGPR("-->xgbe_free_rx_data\n");
1141
1142 for (i = 0; i < pdata->channel_count; i++) {
1143 ring = pdata->channel[i]->rx_ring;
1144 if (!ring)
1145 break;
1146
1147 for (j = 0; j < ring->rdesc_count; j++) {
1148 rdata = XGBE_GET_DESC_DATA(ring, j);
1149 desc_if->unmap_rdata(pdata, rdata);
1150 }
1151 }
1152
1153 DBGPR("<--xgbe_free_rx_data\n");
1154 }
1155
xgbe_phy_reset(struct xgbe_prv_data * pdata)1156 static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
1157 {
1158 pdata->phy_link = -1;
1159 pdata->phy_speed = SPEED_UNKNOWN;
1160
1161 return pdata->phy_if.phy_reset(pdata);
1162 }
1163
xgbe_powerdown(struct net_device * netdev,unsigned int caller)1164 int xgbe_powerdown(struct net_device *netdev, unsigned int caller)
1165 {
1166 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1167 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1168 unsigned long flags;
1169
1170 DBGPR("-->xgbe_powerdown\n");
1171
1172 if (!netif_running(netdev) ||
1173 (caller == XGMAC_IOCTL_CONTEXT && pdata->power_down)) {
1174 netdev_alert(netdev, "Device is already powered down\n");
1175 DBGPR("<--xgbe_powerdown\n");
1176 return -EINVAL;
1177 }
1178
1179 spin_lock_irqsave(&pdata->lock, flags);
1180
1181 if (caller == XGMAC_DRIVER_CONTEXT)
1182 netif_device_detach(netdev);
1183
1184 netif_tx_stop_all_queues(netdev);
1185
1186 xgbe_stop_timers(pdata);
1187 flush_workqueue(pdata->dev_workqueue);
1188
1189 hw_if->powerdown_tx(pdata);
1190 hw_if->powerdown_rx(pdata);
1191
1192 xgbe_napi_disable(pdata, 0);
1193
1194 pdata->power_down = 1;
1195
1196 spin_unlock_irqrestore(&pdata->lock, flags);
1197
1198 DBGPR("<--xgbe_powerdown\n");
1199
1200 return 0;
1201 }
1202
xgbe_powerup(struct net_device * netdev,unsigned int caller)1203 int xgbe_powerup(struct net_device *netdev, unsigned int caller)
1204 {
1205 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1206 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1207 unsigned long flags;
1208
1209 DBGPR("-->xgbe_powerup\n");
1210
1211 if (!netif_running(netdev) ||
1212 (caller == XGMAC_IOCTL_CONTEXT && !pdata->power_down)) {
1213 netdev_alert(netdev, "Device is already powered up\n");
1214 DBGPR("<--xgbe_powerup\n");
1215 return -EINVAL;
1216 }
1217
1218 spin_lock_irqsave(&pdata->lock, flags);
1219
1220 pdata->power_down = 0;
1221
1222 xgbe_napi_enable(pdata, 0);
1223
1224 hw_if->powerup_tx(pdata);
1225 hw_if->powerup_rx(pdata);
1226
1227 if (caller == XGMAC_DRIVER_CONTEXT)
1228 netif_device_attach(netdev);
1229
1230 netif_tx_start_all_queues(netdev);
1231
1232 xgbe_start_timers(pdata);
1233
1234 spin_unlock_irqrestore(&pdata->lock, flags);
1235
1236 DBGPR("<--xgbe_powerup\n");
1237
1238 return 0;
1239 }
1240
xgbe_free_memory(struct xgbe_prv_data * pdata)1241 static void xgbe_free_memory(struct xgbe_prv_data *pdata)
1242 {
1243 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1244
1245 /* Free the ring descriptors and buffers */
1246 desc_if->free_ring_resources(pdata);
1247
1248 /* Free the channel and ring structures */
1249 xgbe_free_channels(pdata);
1250 }
1251
xgbe_alloc_memory(struct xgbe_prv_data * pdata)1252 static int xgbe_alloc_memory(struct xgbe_prv_data *pdata)
1253 {
1254 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1255 struct net_device *netdev = pdata->netdev;
1256 int ret;
1257
1258 if (pdata->new_tx_ring_count) {
1259 pdata->tx_ring_count = pdata->new_tx_ring_count;
1260 pdata->tx_q_count = pdata->tx_ring_count;
1261 pdata->new_tx_ring_count = 0;
1262 }
1263
1264 if (pdata->new_rx_ring_count) {
1265 pdata->rx_ring_count = pdata->new_rx_ring_count;
1266 pdata->new_rx_ring_count = 0;
1267 }
1268
1269 /* Calculate the Rx buffer size before allocating rings */
1270 pdata->rx_buf_size = xgbe_calc_rx_buf_size(netdev, netdev->mtu);
1271
1272 /* Allocate the channel and ring structures */
1273 ret = xgbe_alloc_channels(pdata);
1274 if (ret)
1275 return ret;
1276
1277 /* Allocate the ring descriptors and buffers */
1278 ret = desc_if->alloc_ring_resources(pdata);
1279 if (ret)
1280 goto err_channels;
1281
1282 /* Initialize the service and Tx timers */
1283 xgbe_init_timers(pdata);
1284
1285 return 0;
1286
1287 err_channels:
1288 xgbe_free_memory(pdata);
1289
1290 return ret;
1291 }
1292
xgbe_start(struct xgbe_prv_data * pdata)1293 static int xgbe_start(struct xgbe_prv_data *pdata)
1294 {
1295 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1296 struct xgbe_phy_if *phy_if = &pdata->phy_if;
1297 struct net_device *netdev = pdata->netdev;
1298 unsigned int i;
1299 int ret;
1300
1301 /* Set the number of queues */
1302 ret = netif_set_real_num_tx_queues(netdev, pdata->tx_ring_count);
1303 if (ret) {
1304 netdev_err(netdev, "error setting real tx queue count\n");
1305 return ret;
1306 }
1307
1308 ret = netif_set_real_num_rx_queues(netdev, pdata->rx_ring_count);
1309 if (ret) {
1310 netdev_err(netdev, "error setting real rx queue count\n");
1311 return ret;
1312 }
1313
1314 /* Set RSS lookup table data for programming */
1315 for (i = 0; i < XGBE_RSS_MAX_TABLE_SIZE; i++)
1316 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH,
1317 i % pdata->rx_ring_count);
1318
1319 ret = hw_if->init(pdata);
1320 if (ret)
1321 return ret;
1322
1323 xgbe_napi_enable(pdata, 1);
1324
1325 ret = xgbe_request_irqs(pdata);
1326 if (ret)
1327 goto err_napi;
1328
1329 ret = phy_if->phy_start(pdata);
1330 if (ret)
1331 goto err_irqs;
1332
1333 hw_if->enable_tx(pdata);
1334 hw_if->enable_rx(pdata);
1335
1336 udp_tunnel_nic_reset_ntf(netdev);
1337
1338 netif_tx_start_all_queues(netdev);
1339
1340 xgbe_start_timers(pdata);
1341 queue_work(pdata->dev_workqueue, &pdata->service_work);
1342
1343 clear_bit(XGBE_STOPPED, &pdata->dev_state);
1344
1345 return 0;
1346
1347 err_irqs:
1348 xgbe_free_irqs(pdata);
1349
1350 err_napi:
1351 xgbe_napi_disable(pdata, 1);
1352
1353 hw_if->exit(pdata);
1354
1355 return ret;
1356 }
1357
xgbe_stop(struct xgbe_prv_data * pdata)1358 static void xgbe_stop(struct xgbe_prv_data *pdata)
1359 {
1360 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1361 struct xgbe_phy_if *phy_if = &pdata->phy_if;
1362 struct xgbe_channel *channel;
1363 struct net_device *netdev = pdata->netdev;
1364 struct netdev_queue *txq;
1365 unsigned int i;
1366
1367 DBGPR("-->xgbe_stop\n");
1368
1369 if (test_bit(XGBE_STOPPED, &pdata->dev_state))
1370 return;
1371
1372 netif_tx_stop_all_queues(netdev);
1373 netif_carrier_off(pdata->netdev);
1374
1375 xgbe_stop_timers(pdata);
1376 flush_workqueue(pdata->dev_workqueue);
1377
1378 xgbe_vxlan_unset_port(netdev, 0, 0, NULL);
1379
1380 hw_if->disable_tx(pdata);
1381 hw_if->disable_rx(pdata);
1382
1383 phy_if->phy_stop(pdata);
1384
1385 xgbe_free_irqs(pdata);
1386
1387 xgbe_napi_disable(pdata, 1);
1388
1389 hw_if->exit(pdata);
1390
1391 for (i = 0; i < pdata->channel_count; i++) {
1392 channel = pdata->channel[i];
1393 if (!channel->tx_ring)
1394 continue;
1395
1396 txq = netdev_get_tx_queue(netdev, channel->queue_index);
1397 netdev_tx_reset_queue(txq);
1398 }
1399
1400 set_bit(XGBE_STOPPED, &pdata->dev_state);
1401
1402 DBGPR("<--xgbe_stop\n");
1403 }
1404
xgbe_stopdev(struct work_struct * work)1405 static void xgbe_stopdev(struct work_struct *work)
1406 {
1407 struct xgbe_prv_data *pdata = container_of(work,
1408 struct xgbe_prv_data,
1409 stopdev_work);
1410
1411 rtnl_lock();
1412
1413 xgbe_stop(pdata);
1414
1415 xgbe_free_tx_data(pdata);
1416 xgbe_free_rx_data(pdata);
1417
1418 rtnl_unlock();
1419
1420 netdev_alert(pdata->netdev, "device stopped\n");
1421 }
1422
xgbe_full_restart_dev(struct xgbe_prv_data * pdata)1423 void xgbe_full_restart_dev(struct xgbe_prv_data *pdata)
1424 {
1425 /* If not running, "restart" will happen on open */
1426 if (!netif_running(pdata->netdev))
1427 return;
1428
1429 xgbe_stop(pdata);
1430
1431 xgbe_free_memory(pdata);
1432 xgbe_alloc_memory(pdata);
1433
1434 xgbe_start(pdata);
1435 }
1436
xgbe_restart_dev(struct xgbe_prv_data * pdata)1437 void xgbe_restart_dev(struct xgbe_prv_data *pdata)
1438 {
1439 /* If not running, "restart" will happen on open */
1440 if (!netif_running(pdata->netdev))
1441 return;
1442
1443 xgbe_stop(pdata);
1444
1445 xgbe_free_tx_data(pdata);
1446 xgbe_free_rx_data(pdata);
1447
1448 xgbe_start(pdata);
1449 }
1450
xgbe_restart(struct work_struct * work)1451 static void xgbe_restart(struct work_struct *work)
1452 {
1453 struct xgbe_prv_data *pdata = container_of(work,
1454 struct xgbe_prv_data,
1455 restart_work);
1456
1457 rtnl_lock();
1458
1459 xgbe_restart_dev(pdata);
1460
1461 rtnl_unlock();
1462 }
1463
xgbe_tx_tstamp(struct work_struct * work)1464 static void xgbe_tx_tstamp(struct work_struct *work)
1465 {
1466 struct xgbe_prv_data *pdata = container_of(work,
1467 struct xgbe_prv_data,
1468 tx_tstamp_work);
1469 struct skb_shared_hwtstamps hwtstamps;
1470 u64 nsec;
1471 unsigned long flags;
1472
1473 spin_lock_irqsave(&pdata->tstamp_lock, flags);
1474 if (!pdata->tx_tstamp_skb)
1475 goto unlock;
1476
1477 if (pdata->tx_tstamp) {
1478 nsec = timecounter_cyc2time(&pdata->tstamp_tc,
1479 pdata->tx_tstamp);
1480
1481 memset(&hwtstamps, 0, sizeof(hwtstamps));
1482 hwtstamps.hwtstamp = ns_to_ktime(nsec);
1483 skb_tstamp_tx(pdata->tx_tstamp_skb, &hwtstamps);
1484 }
1485
1486 dev_kfree_skb_any(pdata->tx_tstamp_skb);
1487
1488 pdata->tx_tstamp_skb = NULL;
1489
1490 unlock:
1491 spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
1492 }
1493
xgbe_get_hwtstamp_settings(struct xgbe_prv_data * pdata,struct ifreq * ifreq)1494 static int xgbe_get_hwtstamp_settings(struct xgbe_prv_data *pdata,
1495 struct ifreq *ifreq)
1496 {
1497 if (copy_to_user(ifreq->ifr_data, &pdata->tstamp_config,
1498 sizeof(pdata->tstamp_config)))
1499 return -EFAULT;
1500
1501 return 0;
1502 }
1503
xgbe_set_hwtstamp_settings(struct xgbe_prv_data * pdata,struct ifreq * ifreq)1504 static int xgbe_set_hwtstamp_settings(struct xgbe_prv_data *pdata,
1505 struct ifreq *ifreq)
1506 {
1507 struct hwtstamp_config config;
1508 unsigned int mac_tscr;
1509
1510 if (copy_from_user(&config, ifreq->ifr_data, sizeof(config)))
1511 return -EFAULT;
1512
1513 mac_tscr = 0;
1514
1515 switch (config.tx_type) {
1516 case HWTSTAMP_TX_OFF:
1517 break;
1518
1519 case HWTSTAMP_TX_ON:
1520 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1521 break;
1522
1523 default:
1524 return -ERANGE;
1525 }
1526
1527 switch (config.rx_filter) {
1528 case HWTSTAMP_FILTER_NONE:
1529 break;
1530
1531 case HWTSTAMP_FILTER_NTP_ALL:
1532 case HWTSTAMP_FILTER_ALL:
1533 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1);
1534 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1535 break;
1536
1537 /* PTP v2, UDP, any kind of event packet */
1538 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1539 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1540 fallthrough; /* to PTP v1, UDP, any kind of event packet */
1541 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1542 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1543 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1544 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1545 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1546 break;
1547
1548 /* PTP v2, UDP, Sync packet */
1549 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1550 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1551 fallthrough; /* to PTP v1, UDP, Sync packet */
1552 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1553 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1554 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1555 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1556 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1557 break;
1558
1559 /* PTP v2, UDP, Delay_req packet */
1560 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1561 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1562 fallthrough; /* to PTP v1, UDP, Delay_req packet */
1563 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1564 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1565 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1566 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1567 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1568 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1569 break;
1570
1571 /* 802.AS1, Ethernet, any kind of event packet */
1572 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1573 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1574 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1575 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1576 break;
1577
1578 /* 802.AS1, Ethernet, Sync packet */
1579 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1580 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1581 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1582 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1583 break;
1584
1585 /* 802.AS1, Ethernet, Delay_req packet */
1586 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1587 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1588 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1589 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1590 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1591 break;
1592
1593 /* PTP v2/802.AS1, any layer, any kind of event packet */
1594 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1595 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1596 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1597 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1598 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1599 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1600 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1601 break;
1602
1603 /* PTP v2/802.AS1, any layer, Sync packet */
1604 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1605 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1606 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1607 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1608 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1609 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1610 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1611 break;
1612
1613 /* PTP v2/802.AS1, any layer, Delay_req packet */
1614 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1615 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1616 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1617 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1618 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1619 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1620 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1621 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1622 break;
1623
1624 default:
1625 return -ERANGE;
1626 }
1627
1628 pdata->hw_if.config_tstamp(pdata, mac_tscr);
1629
1630 memcpy(&pdata->tstamp_config, &config, sizeof(config));
1631
1632 return 0;
1633 }
1634
xgbe_prep_tx_tstamp(struct xgbe_prv_data * pdata,struct sk_buff * skb,struct xgbe_packet_data * packet)1635 static void xgbe_prep_tx_tstamp(struct xgbe_prv_data *pdata,
1636 struct sk_buff *skb,
1637 struct xgbe_packet_data *packet)
1638 {
1639 unsigned long flags;
1640
1641 if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) {
1642 spin_lock_irqsave(&pdata->tstamp_lock, flags);
1643 if (pdata->tx_tstamp_skb) {
1644 /* Another timestamp in progress, ignore this one */
1645 XGMAC_SET_BITS(packet->attributes,
1646 TX_PACKET_ATTRIBUTES, PTP, 0);
1647 } else {
1648 pdata->tx_tstamp_skb = skb_get(skb);
1649 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1650 }
1651 spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
1652 }
1653
1654 skb_tx_timestamp(skb);
1655 }
1656
xgbe_prep_vlan(struct sk_buff * skb,struct xgbe_packet_data * packet)1657 static void xgbe_prep_vlan(struct sk_buff *skb, struct xgbe_packet_data *packet)
1658 {
1659 if (skb_vlan_tag_present(skb))
1660 packet->vlan_ctag = skb_vlan_tag_get(skb);
1661 }
1662
xgbe_prep_tso(struct sk_buff * skb,struct xgbe_packet_data * packet)1663 static int xgbe_prep_tso(struct sk_buff *skb, struct xgbe_packet_data *packet)
1664 {
1665 int ret;
1666
1667 if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1668 TSO_ENABLE))
1669 return 0;
1670
1671 ret = skb_cow_head(skb, 0);
1672 if (ret)
1673 return ret;
1674
1675 if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, VXLAN)) {
1676 packet->header_len = skb_inner_transport_offset(skb) +
1677 inner_tcp_hdrlen(skb);
1678 packet->tcp_header_len = inner_tcp_hdrlen(skb);
1679 } else {
1680 packet->header_len = skb_transport_offset(skb) +
1681 tcp_hdrlen(skb);
1682 packet->tcp_header_len = tcp_hdrlen(skb);
1683 }
1684 packet->tcp_payload_len = skb->len - packet->header_len;
1685 packet->mss = skb_shinfo(skb)->gso_size;
1686
1687 DBGPR(" packet->header_len=%u\n", packet->header_len);
1688 DBGPR(" packet->tcp_header_len=%u, packet->tcp_payload_len=%u\n",
1689 packet->tcp_header_len, packet->tcp_payload_len);
1690 DBGPR(" packet->mss=%u\n", packet->mss);
1691
1692 /* Update the number of packets that will ultimately be transmitted
1693 * along with the extra bytes for each extra packet
1694 */
1695 packet->tx_packets = skb_shinfo(skb)->gso_segs;
1696 packet->tx_bytes += (packet->tx_packets - 1) * packet->header_len;
1697
1698 return 0;
1699 }
1700
xgbe_is_vxlan(struct sk_buff * skb)1701 static bool xgbe_is_vxlan(struct sk_buff *skb)
1702 {
1703 if (!skb->encapsulation)
1704 return false;
1705
1706 if (skb->ip_summed != CHECKSUM_PARTIAL)
1707 return false;
1708
1709 switch (skb->protocol) {
1710 case htons(ETH_P_IP):
1711 if (ip_hdr(skb)->protocol != IPPROTO_UDP)
1712 return false;
1713 break;
1714
1715 case htons(ETH_P_IPV6):
1716 if (ipv6_hdr(skb)->nexthdr != IPPROTO_UDP)
1717 return false;
1718 break;
1719
1720 default:
1721 return false;
1722 }
1723
1724 if (skb->inner_protocol_type != ENCAP_TYPE_ETHER ||
1725 skb->inner_protocol != htons(ETH_P_TEB) ||
1726 (skb_inner_mac_header(skb) - skb_transport_header(skb) !=
1727 sizeof(struct udphdr) + sizeof(struct vxlanhdr)))
1728 return false;
1729
1730 return true;
1731 }
1732
xgbe_is_tso(struct sk_buff * skb)1733 static int xgbe_is_tso(struct sk_buff *skb)
1734 {
1735 if (skb->ip_summed != CHECKSUM_PARTIAL)
1736 return 0;
1737
1738 if (!skb_is_gso(skb))
1739 return 0;
1740
1741 DBGPR(" TSO packet to be processed\n");
1742
1743 return 1;
1744 }
1745
xgbe_packet_info(struct xgbe_prv_data * pdata,struct xgbe_ring * ring,struct sk_buff * skb,struct xgbe_packet_data * packet)1746 static void xgbe_packet_info(struct xgbe_prv_data *pdata,
1747 struct xgbe_ring *ring, struct sk_buff *skb,
1748 struct xgbe_packet_data *packet)
1749 {
1750 skb_frag_t *frag;
1751 unsigned int context_desc;
1752 unsigned int len;
1753 unsigned int i;
1754
1755 packet->skb = skb;
1756
1757 context_desc = 0;
1758 packet->rdesc_count = 0;
1759
1760 packet->tx_packets = 1;
1761 packet->tx_bytes = skb->len;
1762
1763 if (xgbe_is_tso(skb)) {
1764 /* TSO requires an extra descriptor if mss is different */
1765 if (skb_shinfo(skb)->gso_size != ring->tx.cur_mss) {
1766 context_desc = 1;
1767 packet->rdesc_count++;
1768 }
1769
1770 /* TSO requires an extra descriptor for TSO header */
1771 packet->rdesc_count++;
1772
1773 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1774 TSO_ENABLE, 1);
1775 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1776 CSUM_ENABLE, 1);
1777 } else if (skb->ip_summed == CHECKSUM_PARTIAL)
1778 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1779 CSUM_ENABLE, 1);
1780
1781 if (xgbe_is_vxlan(skb))
1782 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1783 VXLAN, 1);
1784
1785 if (skb_vlan_tag_present(skb)) {
1786 /* VLAN requires an extra descriptor if tag is different */
1787 if (skb_vlan_tag_get(skb) != ring->tx.cur_vlan_ctag)
1788 /* We can share with the TSO context descriptor */
1789 if (!context_desc) {
1790 context_desc = 1;
1791 packet->rdesc_count++;
1792 }
1793
1794 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1795 VLAN_CTAG, 1);
1796 }
1797
1798 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1799 (pdata->tstamp_config.tx_type == HWTSTAMP_TX_ON))
1800 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1801 PTP, 1);
1802
1803 for (len = skb_headlen(skb); len;) {
1804 packet->rdesc_count++;
1805 len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE);
1806 }
1807
1808 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1809 frag = &skb_shinfo(skb)->frags[i];
1810 for (len = skb_frag_size(frag); len; ) {
1811 packet->rdesc_count++;
1812 len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE);
1813 }
1814 }
1815 }
1816
xgbe_open(struct net_device * netdev)1817 static int xgbe_open(struct net_device *netdev)
1818 {
1819 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1820 int ret;
1821
1822 /* Create the various names based on netdev name */
1823 snprintf(pdata->an_name, sizeof(pdata->an_name) - 1, "%s-pcs",
1824 netdev_name(netdev));
1825
1826 snprintf(pdata->ecc_name, sizeof(pdata->ecc_name) - 1, "%s-ecc",
1827 netdev_name(netdev));
1828
1829 snprintf(pdata->i2c_name, sizeof(pdata->i2c_name) - 1, "%s-i2c",
1830 netdev_name(netdev));
1831
1832 /* Create workqueues */
1833 pdata->dev_workqueue =
1834 create_singlethread_workqueue(netdev_name(netdev));
1835 if (!pdata->dev_workqueue) {
1836 netdev_err(netdev, "device workqueue creation failed\n");
1837 return -ENOMEM;
1838 }
1839
1840 pdata->an_workqueue =
1841 create_singlethread_workqueue(pdata->an_name);
1842 if (!pdata->an_workqueue) {
1843 netdev_err(netdev, "phy workqueue creation failed\n");
1844 ret = -ENOMEM;
1845 goto err_dev_wq;
1846 }
1847
1848 /* Reset the phy settings */
1849 ret = xgbe_phy_reset(pdata);
1850 if (ret)
1851 goto err_an_wq;
1852
1853 /* Enable the clocks */
1854 ret = clk_prepare_enable(pdata->sysclk);
1855 if (ret) {
1856 netdev_alert(netdev, "dma clk_prepare_enable failed\n");
1857 goto err_an_wq;
1858 }
1859
1860 ret = clk_prepare_enable(pdata->ptpclk);
1861 if (ret) {
1862 netdev_alert(netdev, "ptp clk_prepare_enable failed\n");
1863 goto err_sysclk;
1864 }
1865
1866 INIT_WORK(&pdata->service_work, xgbe_service);
1867 INIT_WORK(&pdata->restart_work, xgbe_restart);
1868 INIT_WORK(&pdata->stopdev_work, xgbe_stopdev);
1869 INIT_WORK(&pdata->tx_tstamp_work, xgbe_tx_tstamp);
1870
1871 ret = xgbe_alloc_memory(pdata);
1872 if (ret)
1873 goto err_ptpclk;
1874
1875 ret = xgbe_start(pdata);
1876 if (ret)
1877 goto err_mem;
1878
1879 clear_bit(XGBE_DOWN, &pdata->dev_state);
1880
1881 return 0;
1882
1883 err_mem:
1884 xgbe_free_memory(pdata);
1885
1886 err_ptpclk:
1887 clk_disable_unprepare(pdata->ptpclk);
1888
1889 err_sysclk:
1890 clk_disable_unprepare(pdata->sysclk);
1891
1892 err_an_wq:
1893 destroy_workqueue(pdata->an_workqueue);
1894
1895 err_dev_wq:
1896 destroy_workqueue(pdata->dev_workqueue);
1897
1898 return ret;
1899 }
1900
xgbe_close(struct net_device * netdev)1901 static int xgbe_close(struct net_device *netdev)
1902 {
1903 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1904
1905 /* Stop the device */
1906 xgbe_stop(pdata);
1907
1908 xgbe_free_memory(pdata);
1909
1910 /* Disable the clocks */
1911 clk_disable_unprepare(pdata->ptpclk);
1912 clk_disable_unprepare(pdata->sysclk);
1913
1914 destroy_workqueue(pdata->an_workqueue);
1915
1916 destroy_workqueue(pdata->dev_workqueue);
1917
1918 set_bit(XGBE_DOWN, &pdata->dev_state);
1919
1920 return 0;
1921 }
1922
xgbe_xmit(struct sk_buff * skb,struct net_device * netdev)1923 static netdev_tx_t xgbe_xmit(struct sk_buff *skb, struct net_device *netdev)
1924 {
1925 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1926 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1927 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1928 struct xgbe_channel *channel;
1929 struct xgbe_ring *ring;
1930 struct xgbe_packet_data *packet;
1931 struct netdev_queue *txq;
1932 netdev_tx_t ret;
1933
1934 DBGPR("-->xgbe_xmit: skb->len = %d\n", skb->len);
1935
1936 channel = pdata->channel[skb->queue_mapping];
1937 txq = netdev_get_tx_queue(netdev, channel->queue_index);
1938 ring = channel->tx_ring;
1939 packet = &ring->packet_data;
1940
1941 ret = NETDEV_TX_OK;
1942
1943 if (skb->len == 0) {
1944 netif_err(pdata, tx_err, netdev,
1945 "empty skb received from stack\n");
1946 dev_kfree_skb_any(skb);
1947 goto tx_netdev_return;
1948 }
1949
1950 /* Calculate preliminary packet info */
1951 memset(packet, 0, sizeof(*packet));
1952 xgbe_packet_info(pdata, ring, skb, packet);
1953
1954 /* Check that there are enough descriptors available */
1955 ret = xgbe_maybe_stop_tx_queue(channel, ring, packet->rdesc_count);
1956 if (ret)
1957 goto tx_netdev_return;
1958
1959 ret = xgbe_prep_tso(skb, packet);
1960 if (ret) {
1961 netif_err(pdata, tx_err, netdev,
1962 "error processing TSO packet\n");
1963 dev_kfree_skb_any(skb);
1964 goto tx_netdev_return;
1965 }
1966 xgbe_prep_vlan(skb, packet);
1967
1968 if (!desc_if->map_tx_skb(channel, skb)) {
1969 dev_kfree_skb_any(skb);
1970 goto tx_netdev_return;
1971 }
1972
1973 xgbe_prep_tx_tstamp(pdata, skb, packet);
1974
1975 /* Report on the actual number of bytes (to be) sent */
1976 netdev_tx_sent_queue(txq, packet->tx_bytes);
1977
1978 /* Configure required descriptor fields for transmission */
1979 hw_if->dev_xmit(channel);
1980
1981 if (netif_msg_pktdata(pdata))
1982 xgbe_print_pkt(netdev, skb, true);
1983
1984 /* Stop the queue in advance if there may not be enough descriptors */
1985 xgbe_maybe_stop_tx_queue(channel, ring, XGBE_TX_MAX_DESCS);
1986
1987 ret = NETDEV_TX_OK;
1988
1989 tx_netdev_return:
1990 return ret;
1991 }
1992
xgbe_set_rx_mode(struct net_device * netdev)1993 static void xgbe_set_rx_mode(struct net_device *netdev)
1994 {
1995 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1996 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1997
1998 DBGPR("-->xgbe_set_rx_mode\n");
1999
2000 hw_if->config_rx_mode(pdata);
2001
2002 DBGPR("<--xgbe_set_rx_mode\n");
2003 }
2004
xgbe_set_mac_address(struct net_device * netdev,void * addr)2005 static int xgbe_set_mac_address(struct net_device *netdev, void *addr)
2006 {
2007 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2008 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2009 struct sockaddr *saddr = addr;
2010
2011 DBGPR("-->xgbe_set_mac_address\n");
2012
2013 if (!is_valid_ether_addr(saddr->sa_data))
2014 return -EADDRNOTAVAIL;
2015
2016 eth_hw_addr_set(netdev, saddr->sa_data);
2017
2018 hw_if->set_mac_address(pdata, netdev->dev_addr);
2019
2020 DBGPR("<--xgbe_set_mac_address\n");
2021
2022 return 0;
2023 }
2024
xgbe_ioctl(struct net_device * netdev,struct ifreq * ifreq,int cmd)2025 static int xgbe_ioctl(struct net_device *netdev, struct ifreq *ifreq, int cmd)
2026 {
2027 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2028 int ret;
2029
2030 switch (cmd) {
2031 case SIOCGHWTSTAMP:
2032 ret = xgbe_get_hwtstamp_settings(pdata, ifreq);
2033 break;
2034
2035 case SIOCSHWTSTAMP:
2036 ret = xgbe_set_hwtstamp_settings(pdata, ifreq);
2037 break;
2038
2039 default:
2040 ret = -EOPNOTSUPP;
2041 }
2042
2043 return ret;
2044 }
2045
xgbe_change_mtu(struct net_device * netdev,int mtu)2046 static int xgbe_change_mtu(struct net_device *netdev, int mtu)
2047 {
2048 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2049 int ret;
2050
2051 DBGPR("-->xgbe_change_mtu\n");
2052
2053 ret = xgbe_calc_rx_buf_size(netdev, mtu);
2054 if (ret < 0)
2055 return ret;
2056
2057 pdata->rx_buf_size = ret;
2058 netdev->mtu = mtu;
2059
2060 xgbe_restart_dev(pdata);
2061
2062 DBGPR("<--xgbe_change_mtu\n");
2063
2064 return 0;
2065 }
2066
xgbe_tx_timeout(struct net_device * netdev,unsigned int txqueue)2067 static void xgbe_tx_timeout(struct net_device *netdev, unsigned int txqueue)
2068 {
2069 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2070
2071 netdev_warn(netdev, "tx timeout, device restarting\n");
2072 schedule_work(&pdata->restart_work);
2073 }
2074
xgbe_get_stats64(struct net_device * netdev,struct rtnl_link_stats64 * s)2075 static void xgbe_get_stats64(struct net_device *netdev,
2076 struct rtnl_link_stats64 *s)
2077 {
2078 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2079 struct xgbe_mmc_stats *pstats = &pdata->mmc_stats;
2080
2081 DBGPR("-->%s\n", __func__);
2082
2083 pdata->hw_if.read_mmc_stats(pdata);
2084
2085 s->rx_packets = pstats->rxframecount_gb;
2086 s->rx_bytes = pstats->rxoctetcount_gb;
2087 s->rx_errors = pstats->rxframecount_gb -
2088 pstats->rxbroadcastframes_g -
2089 pstats->rxmulticastframes_g -
2090 pstats->rxunicastframes_g;
2091 s->multicast = pstats->rxmulticastframes_g;
2092 s->rx_length_errors = pstats->rxlengtherror;
2093 s->rx_crc_errors = pstats->rxcrcerror;
2094 s->rx_fifo_errors = pstats->rxfifooverflow;
2095
2096 s->tx_packets = pstats->txframecount_gb;
2097 s->tx_bytes = pstats->txoctetcount_gb;
2098 s->tx_errors = pstats->txframecount_gb - pstats->txframecount_g;
2099 s->tx_dropped = netdev->stats.tx_dropped;
2100
2101 DBGPR("<--%s\n", __func__);
2102 }
2103
xgbe_vlan_rx_add_vid(struct net_device * netdev,__be16 proto,u16 vid)2104 static int xgbe_vlan_rx_add_vid(struct net_device *netdev, __be16 proto,
2105 u16 vid)
2106 {
2107 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2108 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2109
2110 DBGPR("-->%s\n", __func__);
2111
2112 set_bit(vid, pdata->active_vlans);
2113 hw_if->update_vlan_hash_table(pdata);
2114
2115 DBGPR("<--%s\n", __func__);
2116
2117 return 0;
2118 }
2119
xgbe_vlan_rx_kill_vid(struct net_device * netdev,__be16 proto,u16 vid)2120 static int xgbe_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto,
2121 u16 vid)
2122 {
2123 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2124 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2125
2126 DBGPR("-->%s\n", __func__);
2127
2128 clear_bit(vid, pdata->active_vlans);
2129 hw_if->update_vlan_hash_table(pdata);
2130
2131 DBGPR("<--%s\n", __func__);
2132
2133 return 0;
2134 }
2135
2136 #ifdef CONFIG_NET_POLL_CONTROLLER
xgbe_poll_controller(struct net_device * netdev)2137 static void xgbe_poll_controller(struct net_device *netdev)
2138 {
2139 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2140 struct xgbe_channel *channel;
2141 unsigned int i;
2142
2143 DBGPR("-->xgbe_poll_controller\n");
2144
2145 if (pdata->per_channel_irq) {
2146 for (i = 0; i < pdata->channel_count; i++) {
2147 channel = pdata->channel[i];
2148 xgbe_dma_isr(channel->dma_irq, channel);
2149 }
2150 } else {
2151 disable_irq(pdata->dev_irq);
2152 xgbe_isr(pdata->dev_irq, pdata);
2153 enable_irq(pdata->dev_irq);
2154 }
2155
2156 DBGPR("<--xgbe_poll_controller\n");
2157 }
2158 #endif /* End CONFIG_NET_POLL_CONTROLLER */
2159
xgbe_setup_tc(struct net_device * netdev,enum tc_setup_type type,void * type_data)2160 static int xgbe_setup_tc(struct net_device *netdev, enum tc_setup_type type,
2161 void *type_data)
2162 {
2163 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2164 struct tc_mqprio_qopt *mqprio = type_data;
2165 u8 tc;
2166
2167 if (type != TC_SETUP_QDISC_MQPRIO)
2168 return -EOPNOTSUPP;
2169
2170 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
2171 tc = mqprio->num_tc;
2172
2173 if (tc > pdata->hw_feat.tc_cnt)
2174 return -EINVAL;
2175
2176 pdata->num_tcs = tc;
2177 pdata->hw_if.config_tc(pdata);
2178
2179 return 0;
2180 }
2181
xgbe_fix_features(struct net_device * netdev,netdev_features_t features)2182 static netdev_features_t xgbe_fix_features(struct net_device *netdev,
2183 netdev_features_t features)
2184 {
2185 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2186 netdev_features_t vxlan_base;
2187
2188 vxlan_base = NETIF_F_GSO_UDP_TUNNEL | NETIF_F_RX_UDP_TUNNEL_PORT;
2189
2190 if (!pdata->hw_feat.vxn)
2191 return features;
2192
2193 /* VXLAN CSUM requires VXLAN base */
2194 if ((features & NETIF_F_GSO_UDP_TUNNEL_CSUM) &&
2195 !(features & NETIF_F_GSO_UDP_TUNNEL)) {
2196 netdev_notice(netdev,
2197 "forcing tx udp tunnel support\n");
2198 features |= NETIF_F_GSO_UDP_TUNNEL;
2199 }
2200
2201 /* Can't do one without doing the other */
2202 if ((features & vxlan_base) != vxlan_base) {
2203 netdev_notice(netdev,
2204 "forcing both tx and rx udp tunnel support\n");
2205 features |= vxlan_base;
2206 }
2207
2208 if (features & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)) {
2209 if (!(features & NETIF_F_GSO_UDP_TUNNEL_CSUM)) {
2210 netdev_notice(netdev,
2211 "forcing tx udp tunnel checksumming on\n");
2212 features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
2213 }
2214 } else {
2215 if (features & NETIF_F_GSO_UDP_TUNNEL_CSUM) {
2216 netdev_notice(netdev,
2217 "forcing tx udp tunnel checksumming off\n");
2218 features &= ~NETIF_F_GSO_UDP_TUNNEL_CSUM;
2219 }
2220 }
2221
2222 return features;
2223 }
2224
xgbe_set_features(struct net_device * netdev,netdev_features_t features)2225 static int xgbe_set_features(struct net_device *netdev,
2226 netdev_features_t features)
2227 {
2228 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2229 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2230 netdev_features_t rxhash, rxcsum, rxvlan, rxvlan_filter;
2231 int ret = 0;
2232
2233 rxhash = pdata->netdev_features & NETIF_F_RXHASH;
2234 rxcsum = pdata->netdev_features & NETIF_F_RXCSUM;
2235 rxvlan = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_RX;
2236 rxvlan_filter = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_FILTER;
2237
2238 if ((features & NETIF_F_RXHASH) && !rxhash)
2239 ret = hw_if->enable_rss(pdata);
2240 else if (!(features & NETIF_F_RXHASH) && rxhash)
2241 ret = hw_if->disable_rss(pdata);
2242 if (ret)
2243 return ret;
2244
2245 if ((features & NETIF_F_RXCSUM) && !rxcsum)
2246 hw_if->enable_rx_csum(pdata);
2247 else if (!(features & NETIF_F_RXCSUM) && rxcsum)
2248 hw_if->disable_rx_csum(pdata);
2249
2250 if ((features & NETIF_F_HW_VLAN_CTAG_RX) && !rxvlan)
2251 hw_if->enable_rx_vlan_stripping(pdata);
2252 else if (!(features & NETIF_F_HW_VLAN_CTAG_RX) && rxvlan)
2253 hw_if->disable_rx_vlan_stripping(pdata);
2254
2255 if ((features & NETIF_F_HW_VLAN_CTAG_FILTER) && !rxvlan_filter)
2256 hw_if->enable_rx_vlan_filtering(pdata);
2257 else if (!(features & NETIF_F_HW_VLAN_CTAG_FILTER) && rxvlan_filter)
2258 hw_if->disable_rx_vlan_filtering(pdata);
2259
2260 pdata->netdev_features = features;
2261
2262 DBGPR("<--xgbe_set_features\n");
2263
2264 return 0;
2265 }
2266
xgbe_features_check(struct sk_buff * skb,struct net_device * netdev,netdev_features_t features)2267 static netdev_features_t xgbe_features_check(struct sk_buff *skb,
2268 struct net_device *netdev,
2269 netdev_features_t features)
2270 {
2271 features = vlan_features_check(skb, features);
2272 features = vxlan_features_check(skb, features);
2273
2274 return features;
2275 }
2276
2277 static const struct net_device_ops xgbe_netdev_ops = {
2278 .ndo_open = xgbe_open,
2279 .ndo_stop = xgbe_close,
2280 .ndo_start_xmit = xgbe_xmit,
2281 .ndo_set_rx_mode = xgbe_set_rx_mode,
2282 .ndo_set_mac_address = xgbe_set_mac_address,
2283 .ndo_validate_addr = eth_validate_addr,
2284 .ndo_eth_ioctl = xgbe_ioctl,
2285 .ndo_change_mtu = xgbe_change_mtu,
2286 .ndo_tx_timeout = xgbe_tx_timeout,
2287 .ndo_get_stats64 = xgbe_get_stats64,
2288 .ndo_vlan_rx_add_vid = xgbe_vlan_rx_add_vid,
2289 .ndo_vlan_rx_kill_vid = xgbe_vlan_rx_kill_vid,
2290 #ifdef CONFIG_NET_POLL_CONTROLLER
2291 .ndo_poll_controller = xgbe_poll_controller,
2292 #endif
2293 .ndo_setup_tc = xgbe_setup_tc,
2294 .ndo_fix_features = xgbe_fix_features,
2295 .ndo_set_features = xgbe_set_features,
2296 .ndo_features_check = xgbe_features_check,
2297 };
2298
xgbe_get_netdev_ops(void)2299 const struct net_device_ops *xgbe_get_netdev_ops(void)
2300 {
2301 return &xgbe_netdev_ops;
2302 }
2303
xgbe_rx_refresh(struct xgbe_channel * channel)2304 static void xgbe_rx_refresh(struct xgbe_channel *channel)
2305 {
2306 struct xgbe_prv_data *pdata = channel->pdata;
2307 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2308 struct xgbe_desc_if *desc_if = &pdata->desc_if;
2309 struct xgbe_ring *ring = channel->rx_ring;
2310 struct xgbe_ring_data *rdata;
2311
2312 while (ring->dirty != ring->cur) {
2313 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
2314
2315 /* Reset rdata values */
2316 desc_if->unmap_rdata(pdata, rdata);
2317
2318 if (desc_if->map_rx_buffer(pdata, ring, rdata))
2319 break;
2320
2321 hw_if->rx_desc_reset(pdata, rdata, ring->dirty);
2322
2323 ring->dirty++;
2324 }
2325
2326 /* Make sure everything is written before the register write */
2327 wmb();
2328
2329 /* Update the Rx Tail Pointer Register with address of
2330 * the last cleaned entry */
2331 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty - 1);
2332 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO,
2333 lower_32_bits(rdata->rdesc_dma));
2334 }
2335
xgbe_create_skb(struct xgbe_prv_data * pdata,struct napi_struct * napi,struct xgbe_ring_data * rdata,unsigned int len)2336 static struct sk_buff *xgbe_create_skb(struct xgbe_prv_data *pdata,
2337 struct napi_struct *napi,
2338 struct xgbe_ring_data *rdata,
2339 unsigned int len)
2340 {
2341 struct sk_buff *skb;
2342 u8 *packet;
2343
2344 skb = napi_alloc_skb(napi, rdata->rx.hdr.dma_len);
2345 if (!skb)
2346 return NULL;
2347
2348 /* Pull in the header buffer which may contain just the header
2349 * or the header plus data
2350 */
2351 dma_sync_single_range_for_cpu(pdata->dev, rdata->rx.hdr.dma_base,
2352 rdata->rx.hdr.dma_off,
2353 rdata->rx.hdr.dma_len, DMA_FROM_DEVICE);
2354
2355 packet = page_address(rdata->rx.hdr.pa.pages) +
2356 rdata->rx.hdr.pa.pages_offset;
2357 skb_copy_to_linear_data(skb, packet, len);
2358 skb_put(skb, len);
2359
2360 return skb;
2361 }
2362
xgbe_rx_buf1_len(struct xgbe_ring_data * rdata,struct xgbe_packet_data * packet)2363 static unsigned int xgbe_rx_buf1_len(struct xgbe_ring_data *rdata,
2364 struct xgbe_packet_data *packet)
2365 {
2366 /* Always zero if not the first descriptor */
2367 if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, FIRST))
2368 return 0;
2369
2370 /* First descriptor with split header, return header length */
2371 if (rdata->rx.hdr_len)
2372 return rdata->rx.hdr_len;
2373
2374 /* First descriptor but not the last descriptor and no split header,
2375 * so the full buffer was used
2376 */
2377 if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, LAST))
2378 return rdata->rx.hdr.dma_len;
2379
2380 /* First descriptor and last descriptor and no split header, so
2381 * calculate how much of the buffer was used
2382 */
2383 return min_t(unsigned int, rdata->rx.hdr.dma_len, rdata->rx.len);
2384 }
2385
xgbe_rx_buf2_len(struct xgbe_ring_data * rdata,struct xgbe_packet_data * packet,unsigned int len)2386 static unsigned int xgbe_rx_buf2_len(struct xgbe_ring_data *rdata,
2387 struct xgbe_packet_data *packet,
2388 unsigned int len)
2389 {
2390 /* Always the full buffer if not the last descriptor */
2391 if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, LAST))
2392 return rdata->rx.buf.dma_len;
2393
2394 /* Last descriptor so calculate how much of the buffer was used
2395 * for the last bit of data
2396 */
2397 return rdata->rx.len - len;
2398 }
2399
xgbe_tx_poll(struct xgbe_channel * channel)2400 static int xgbe_tx_poll(struct xgbe_channel *channel)
2401 {
2402 struct xgbe_prv_data *pdata = channel->pdata;
2403 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2404 struct xgbe_desc_if *desc_if = &pdata->desc_if;
2405 struct xgbe_ring *ring = channel->tx_ring;
2406 struct xgbe_ring_data *rdata;
2407 struct xgbe_ring_desc *rdesc;
2408 struct net_device *netdev = pdata->netdev;
2409 struct netdev_queue *txq;
2410 int processed = 0;
2411 unsigned int tx_packets = 0, tx_bytes = 0;
2412 unsigned int cur;
2413
2414 DBGPR("-->xgbe_tx_poll\n");
2415
2416 /* Nothing to do if there isn't a Tx ring for this channel */
2417 if (!ring)
2418 return 0;
2419
2420 cur = ring->cur;
2421
2422 /* Be sure we get ring->cur before accessing descriptor data */
2423 smp_rmb();
2424
2425 txq = netdev_get_tx_queue(netdev, channel->queue_index);
2426
2427 while ((processed < XGBE_TX_DESC_MAX_PROC) &&
2428 (ring->dirty != cur)) {
2429 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
2430 rdesc = rdata->rdesc;
2431
2432 if (!hw_if->tx_complete(rdesc))
2433 break;
2434
2435 /* Make sure descriptor fields are read after reading the OWN
2436 * bit */
2437 dma_rmb();
2438
2439 if (netif_msg_tx_done(pdata))
2440 xgbe_dump_tx_desc(pdata, ring, ring->dirty, 1, 0);
2441
2442 if (hw_if->is_last_desc(rdesc)) {
2443 tx_packets += rdata->tx.packets;
2444 tx_bytes += rdata->tx.bytes;
2445 }
2446
2447 /* Free the SKB and reset the descriptor for re-use */
2448 desc_if->unmap_rdata(pdata, rdata);
2449 hw_if->tx_desc_reset(rdata);
2450
2451 processed++;
2452 ring->dirty++;
2453 }
2454
2455 if (!processed)
2456 return 0;
2457
2458 netdev_tx_completed_queue(txq, tx_packets, tx_bytes);
2459
2460 if ((ring->tx.queue_stopped == 1) &&
2461 (xgbe_tx_avail_desc(ring) > XGBE_TX_DESC_MIN_FREE)) {
2462 ring->tx.queue_stopped = 0;
2463 netif_tx_wake_queue(txq);
2464 }
2465
2466 DBGPR("<--xgbe_tx_poll: processed=%d\n", processed);
2467
2468 return processed;
2469 }
2470
xgbe_rx_poll(struct xgbe_channel * channel,int budget)2471 static int xgbe_rx_poll(struct xgbe_channel *channel, int budget)
2472 {
2473 struct xgbe_prv_data *pdata = channel->pdata;
2474 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2475 struct xgbe_ring *ring = channel->rx_ring;
2476 struct xgbe_ring_data *rdata;
2477 struct xgbe_packet_data *packet;
2478 struct net_device *netdev = pdata->netdev;
2479 struct napi_struct *napi;
2480 struct sk_buff *skb;
2481 struct skb_shared_hwtstamps *hwtstamps;
2482 unsigned int last, error, context_next, context;
2483 unsigned int len, buf1_len, buf2_len, max_len;
2484 unsigned int received = 0;
2485 int packet_count = 0;
2486
2487 DBGPR("-->xgbe_rx_poll: budget=%d\n", budget);
2488
2489 /* Nothing to do if there isn't a Rx ring for this channel */
2490 if (!ring)
2491 return 0;
2492
2493 last = 0;
2494 context_next = 0;
2495
2496 napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi;
2497
2498 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
2499 packet = &ring->packet_data;
2500 while (packet_count < budget) {
2501 DBGPR(" cur = %d\n", ring->cur);
2502
2503 /* First time in loop see if we need to restore state */
2504 if (!received && rdata->state_saved) {
2505 skb = rdata->state.skb;
2506 error = rdata->state.error;
2507 len = rdata->state.len;
2508 } else {
2509 memset(packet, 0, sizeof(*packet));
2510 skb = NULL;
2511 error = 0;
2512 len = 0;
2513 }
2514
2515 read_again:
2516 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
2517
2518 if (xgbe_rx_dirty_desc(ring) > (XGBE_RX_DESC_CNT >> 3))
2519 xgbe_rx_refresh(channel);
2520
2521 if (hw_if->dev_read(channel))
2522 break;
2523
2524 received++;
2525 ring->cur++;
2526
2527 last = XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
2528 LAST);
2529 context_next = XGMAC_GET_BITS(packet->attributes,
2530 RX_PACKET_ATTRIBUTES,
2531 CONTEXT_NEXT);
2532 context = XGMAC_GET_BITS(packet->attributes,
2533 RX_PACKET_ATTRIBUTES,
2534 CONTEXT);
2535
2536 /* Earlier error, just drain the remaining data */
2537 if ((!last || context_next) && error)
2538 goto read_again;
2539
2540 if (error || packet->errors) {
2541 if (packet->errors)
2542 netif_err(pdata, rx_err, netdev,
2543 "error in received packet\n");
2544 dev_kfree_skb(skb);
2545 goto next_packet;
2546 }
2547
2548 if (!context) {
2549 /* Get the data length in the descriptor buffers */
2550 buf1_len = xgbe_rx_buf1_len(rdata, packet);
2551 len += buf1_len;
2552 buf2_len = xgbe_rx_buf2_len(rdata, packet, len);
2553 len += buf2_len;
2554
2555 if (buf2_len > rdata->rx.buf.dma_len) {
2556 /* Hardware inconsistency within the descriptors
2557 * that has resulted in a length underflow.
2558 */
2559 error = 1;
2560 goto skip_data;
2561 }
2562
2563 if (!skb) {
2564 skb = xgbe_create_skb(pdata, napi, rdata,
2565 buf1_len);
2566 if (!skb) {
2567 error = 1;
2568 goto skip_data;
2569 }
2570 }
2571
2572 if (buf2_len) {
2573 dma_sync_single_range_for_cpu(pdata->dev,
2574 rdata->rx.buf.dma_base,
2575 rdata->rx.buf.dma_off,
2576 rdata->rx.buf.dma_len,
2577 DMA_FROM_DEVICE);
2578
2579 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
2580 rdata->rx.buf.pa.pages,
2581 rdata->rx.buf.pa.pages_offset,
2582 buf2_len,
2583 rdata->rx.buf.dma_len);
2584 rdata->rx.buf.pa.pages = NULL;
2585 }
2586 }
2587
2588 skip_data:
2589 if (!last || context_next)
2590 goto read_again;
2591
2592 if (!skb || error) {
2593 dev_kfree_skb(skb);
2594 goto next_packet;
2595 }
2596
2597 /* Be sure we don't exceed the configured MTU */
2598 max_len = netdev->mtu + ETH_HLEN;
2599 if (!(netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
2600 (skb->protocol == htons(ETH_P_8021Q)))
2601 max_len += VLAN_HLEN;
2602
2603 if (skb->len > max_len) {
2604 netif_err(pdata, rx_err, netdev,
2605 "packet length exceeds configured MTU\n");
2606 dev_kfree_skb(skb);
2607 goto next_packet;
2608 }
2609
2610 if (netif_msg_pktdata(pdata))
2611 xgbe_print_pkt(netdev, skb, false);
2612
2613 skb_checksum_none_assert(skb);
2614 if (XGMAC_GET_BITS(packet->attributes,
2615 RX_PACKET_ATTRIBUTES, CSUM_DONE))
2616 skb->ip_summed = CHECKSUM_UNNECESSARY;
2617
2618 if (XGMAC_GET_BITS(packet->attributes,
2619 RX_PACKET_ATTRIBUTES, TNP)) {
2620 skb->encapsulation = 1;
2621
2622 if (XGMAC_GET_BITS(packet->attributes,
2623 RX_PACKET_ATTRIBUTES, TNPCSUM_DONE))
2624 skb->csum_level = 1;
2625 }
2626
2627 if (XGMAC_GET_BITS(packet->attributes,
2628 RX_PACKET_ATTRIBUTES, VLAN_CTAG))
2629 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2630 packet->vlan_ctag);
2631
2632 if (XGMAC_GET_BITS(packet->attributes,
2633 RX_PACKET_ATTRIBUTES, RX_TSTAMP)) {
2634 u64 nsec;
2635
2636 nsec = timecounter_cyc2time(&pdata->tstamp_tc,
2637 packet->rx_tstamp);
2638 hwtstamps = skb_hwtstamps(skb);
2639 hwtstamps->hwtstamp = ns_to_ktime(nsec);
2640 }
2641
2642 if (XGMAC_GET_BITS(packet->attributes,
2643 RX_PACKET_ATTRIBUTES, RSS_HASH))
2644 skb_set_hash(skb, packet->rss_hash,
2645 packet->rss_hash_type);
2646
2647 skb->dev = netdev;
2648 skb->protocol = eth_type_trans(skb, netdev);
2649 skb_record_rx_queue(skb, channel->queue_index);
2650
2651 napi_gro_receive(napi, skb);
2652
2653 next_packet:
2654 packet_count++;
2655 }
2656
2657 /* Check if we need to save state before leaving */
2658 if (received && (!last || context_next)) {
2659 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
2660 rdata->state_saved = 1;
2661 rdata->state.skb = skb;
2662 rdata->state.len = len;
2663 rdata->state.error = error;
2664 }
2665
2666 DBGPR("<--xgbe_rx_poll: packet_count = %d\n", packet_count);
2667
2668 return packet_count;
2669 }
2670
xgbe_one_poll(struct napi_struct * napi,int budget)2671 static int xgbe_one_poll(struct napi_struct *napi, int budget)
2672 {
2673 struct xgbe_channel *channel = container_of(napi, struct xgbe_channel,
2674 napi);
2675 struct xgbe_prv_data *pdata = channel->pdata;
2676 int processed = 0;
2677
2678 DBGPR("-->xgbe_one_poll: budget=%d\n", budget);
2679
2680 /* Cleanup Tx ring first */
2681 xgbe_tx_poll(channel);
2682
2683 /* Process Rx ring next */
2684 processed = xgbe_rx_poll(channel, budget);
2685
2686 /* If we processed everything, we are done */
2687 if ((processed < budget) && napi_complete_done(napi, processed)) {
2688 /* Enable Tx and Rx interrupts */
2689 if (pdata->channel_irq_mode)
2690 xgbe_enable_rx_tx_int(pdata, channel);
2691 else
2692 enable_irq(channel->dma_irq);
2693 }
2694
2695 DBGPR("<--xgbe_one_poll: received = %d\n", processed);
2696
2697 return processed;
2698 }
2699
xgbe_all_poll(struct napi_struct * napi,int budget)2700 static int xgbe_all_poll(struct napi_struct *napi, int budget)
2701 {
2702 struct xgbe_prv_data *pdata = container_of(napi, struct xgbe_prv_data,
2703 napi);
2704 struct xgbe_channel *channel;
2705 int ring_budget;
2706 int processed, last_processed;
2707 unsigned int i;
2708
2709 DBGPR("-->xgbe_all_poll: budget=%d\n", budget);
2710
2711 processed = 0;
2712 ring_budget = budget / pdata->rx_ring_count;
2713 do {
2714 last_processed = processed;
2715
2716 for (i = 0; i < pdata->channel_count; i++) {
2717 channel = pdata->channel[i];
2718
2719 /* Cleanup Tx ring first */
2720 xgbe_tx_poll(channel);
2721
2722 /* Process Rx ring next */
2723 if (ring_budget > (budget - processed))
2724 ring_budget = budget - processed;
2725 processed += xgbe_rx_poll(channel, ring_budget);
2726 }
2727 } while ((processed < budget) && (processed != last_processed));
2728
2729 /* If we processed everything, we are done */
2730 if ((processed < budget) && napi_complete_done(napi, processed)) {
2731 /* Enable Tx and Rx interrupts */
2732 xgbe_enable_rx_tx_ints(pdata);
2733 }
2734
2735 DBGPR("<--xgbe_all_poll: received = %d\n", processed);
2736
2737 return processed;
2738 }
2739
xgbe_dump_tx_desc(struct xgbe_prv_data * pdata,struct xgbe_ring * ring,unsigned int idx,unsigned int count,unsigned int flag)2740 void xgbe_dump_tx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring,
2741 unsigned int idx, unsigned int count, unsigned int flag)
2742 {
2743 struct xgbe_ring_data *rdata;
2744 struct xgbe_ring_desc *rdesc;
2745
2746 while (count--) {
2747 rdata = XGBE_GET_DESC_DATA(ring, idx);
2748 rdesc = rdata->rdesc;
2749 netdev_dbg(pdata->netdev,
2750 "TX_NORMAL_DESC[%d %s] = %08x:%08x:%08x:%08x\n", idx,
2751 (flag == 1) ? "QUEUED FOR TX" : "TX BY DEVICE",
2752 le32_to_cpu(rdesc->desc0),
2753 le32_to_cpu(rdesc->desc1),
2754 le32_to_cpu(rdesc->desc2),
2755 le32_to_cpu(rdesc->desc3));
2756 idx++;
2757 }
2758 }
2759
xgbe_dump_rx_desc(struct xgbe_prv_data * pdata,struct xgbe_ring * ring,unsigned int idx)2760 void xgbe_dump_rx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring,
2761 unsigned int idx)
2762 {
2763 struct xgbe_ring_data *rdata;
2764 struct xgbe_ring_desc *rdesc;
2765
2766 rdata = XGBE_GET_DESC_DATA(ring, idx);
2767 rdesc = rdata->rdesc;
2768 netdev_dbg(pdata->netdev,
2769 "RX_NORMAL_DESC[%d RX BY DEVICE] = %08x:%08x:%08x:%08x\n",
2770 idx, le32_to_cpu(rdesc->desc0), le32_to_cpu(rdesc->desc1),
2771 le32_to_cpu(rdesc->desc2), le32_to_cpu(rdesc->desc3));
2772 }
2773
xgbe_print_pkt(struct net_device * netdev,struct sk_buff * skb,bool tx_rx)2774 void xgbe_print_pkt(struct net_device *netdev, struct sk_buff *skb, bool tx_rx)
2775 {
2776 struct ethhdr *eth = (struct ethhdr *)skb->data;
2777 unsigned char buffer[128];
2778 unsigned int i;
2779
2780 netdev_dbg(netdev, "\n************** SKB dump ****************\n");
2781
2782 netdev_dbg(netdev, "%s packet of %d bytes\n",
2783 (tx_rx ? "TX" : "RX"), skb->len);
2784
2785 netdev_dbg(netdev, "Dst MAC addr: %pM\n", eth->h_dest);
2786 netdev_dbg(netdev, "Src MAC addr: %pM\n", eth->h_source);
2787 netdev_dbg(netdev, "Protocol: %#06x\n", ntohs(eth->h_proto));
2788
2789 for (i = 0; i < skb->len; i += 32) {
2790 unsigned int len = min(skb->len - i, 32U);
2791
2792 hex_dump_to_buffer(&skb->data[i], len, 32, 1,
2793 buffer, sizeof(buffer), false);
2794 netdev_dbg(netdev, " %#06x: %s\n", i, buffer);
2795 }
2796
2797 netdev_dbg(netdev, "\n************** SKB dump ****************\n");
2798 }
2799