1 #ifndef _PPC64_PACA_H 2 #define _PPC64_PACA_H 3 4 /*============================================================================ 5 * Header File Id 6 * Name______________: paca.h 7 * 8 * Description_______: 9 * 10 * This control block defines the PACA which defines the processor 11 * specific data for each logical processor on the system. 12 * There are some pointers defined that are utilized by PLIC. 13 * 14 * C 2001 PPC 64 Team, IBM Corp 15 * 16 * This program is free software; you can redistribute it and/or 17 * modify it under the terms of the GNU General Public License 18 * as published by the Free Software Foundation; either version 19 * 2 of the License, or (at your option) any later version. 20 */ 21 #include <asm/types.h> 22 23 #define N_EXC_STACK 2 24 25 /*----------------------------------------------------------------------------- 26 * Other Includes 27 *----------------------------------------------------------------------------- 28 */ 29 #include <asm/iSeries/ItLpPaca.h> 30 #include <asm/iSeries/ItLpRegSave.h> 31 #include <asm/iSeries/ItLpQueue.h> 32 #include <asm/rtas.h> 33 #include <asm/mmu.h> 34 #include <asm/processor.h> 35 36 /* A paca entry is required for each logical processor. On systems 37 * that support hardware multi-threading, this is equal to twice the 38 * number of physical processors. On LPAR systems, we are required 39 * to have space for the maximum number of logical processors we 40 * could ever possibly have. Currently, we are limited to allocating 41 * 24 processors to a partition which gives 48 logical processors on 42 * an HMT box. Therefore, we reserve this many paca entries. 43 */ 44 #define MAX_PROCESSORS 24 45 #define MAX_PACAS MAX_PROCESSORS * 2 46 47 extern struct paca_struct paca[]; 48 register struct paca_struct *local_paca asm("r13"); 49 #define get_paca() local_paca 50 51 /*============================================================================ 52 * Name_______: paca 53 * 54 * Description: 55 * 56 * Defines the layout of the paca. 57 * 58 * This structure is not directly accessed by PLIC or the SP except 59 * for the first two pointers that point to the ItLpPaca area and the 60 * ItLpRegSave area for this processor. Both the ItLpPaca and 61 * ItLpRegSave objects are currently contained within the 62 * PACA but they do not need to be. 63 * 64 *============================================================================ 65 */ 66 struct paca_struct { 67 /*===================================================================================== 68 * CACHE_LINE_1 0x0000 - 0x007F 69 *===================================================================================== 70 */ 71 struct ItLpPaca *xLpPacaPtr; /* Pointer to LpPaca for PLIC 0x00 */ 72 struct ItLpRegSave *xLpRegSavePtr; /* Pointer to LpRegSave for PLIC 0x08 */ 73 u64 xCurrent; /* Pointer to current 0x10 */ 74 u16 xPacaIndex; /* Logical processor number 0x18 */ 75 u16 xHwProcNum; /* Actual Hardware Processor Number 0x1a */ 76 u32 default_decr; /* Default decrementer value 0x1c */ 77 u64 xHrdIntStack; /* Stack for hardware interrupts 0x20 */ 78 u64 xKsave; /* Saved Kernel stack addr or zero 0x28 */ 79 u64 pvr; /* Processor version register 0x30 */ 80 u8 *exception_sp; /* 0x38 */ 81 82 struct ItLpQueue *lpQueuePtr; /* LpQueue handled by this processor 0x40 */ 83 u64 xTOC; /* Kernel TOC address 0x48 */ 84 STAB xStab_data; /* Segment table information 0x50,0x58,0x60 */ 85 u8 xSegments[STAB_CACHE_SIZE]; /* Cache of used stab entries 0x68,0x70 */ 86 u8 xProcEnabled; /* 1=soft enabled 0x78 */ 87 u8 xHrdIntCount; /* Count of active hardware interrupts 0x79 */ 88 u8 active; /* Is this cpu active? 0x1a */ 89 u8 available; /* Is this cpu available? 0x1b */ 90 u8 resv1[4]; /* 0x7B-0x7F */ 91 92 /*===================================================================================== 93 * CACHE_LINE_2 0x0080 - 0x00FF 94 *===================================================================================== 95 */ 96 u64 *pgd_cache; /* 0x00 */ 97 u64 *pmd_cache; /* 0x08 */ 98 u64 *pte_cache; /* 0x10 */ 99 u64 pgtable_cache_sz; /* 0x18 */ 100 u64 next_jiffy_update_tb; /* TB value for next jiffy update 0x20 */ 101 u32 lpEvent_count; /* lpEvents processed 0x28 */ 102 u8 yielded; /* 0 = this processor is running 0x2c */ 103 /* 1 = this processor is yielded */ 104 u8 rsvd2[128-5*8-1*4-1]; /* 0x68 */ 105 106 /*===================================================================================== 107 * CACHE_LINE_3 0x0100 - 0x017F 108 *===================================================================================== 109 */ 110 u8 xProcStart; /* At startup, processor spins until 0x100 */ 111 /* xProcStart becomes non-zero. */ 112 u8 rsvd3[127]; 113 114 /*===================================================================================== 115 * CACHE_LINE_4-8 0x0180 - 0x03FF Contains ItLpPaca 116 *===================================================================================== 117 */ 118 struct ItLpPaca xLpPaca; /* Space for ItLpPaca */ 119 120 /*===================================================================================== 121 * CACHE_LINE_9-16 0x0400 - 0x07FF Contains ItLpRegSave 122 *===================================================================================== 123 */ 124 struct ItLpRegSave xRegSav; /* Register save for proc */ 125 126 /*===================================================================================== 127 * CACHE_LINE_17-18 0x0800 - 0x0EFF Reserved 128 *===================================================================================== 129 */ 130 struct rtas_args xRtas; /* Per processor RTAS struct */ 131 u64 xR1; /* r1 save for RTAS calls */ 132 u64 xSavedMsr; /* Old msr saved here by HvCall */ 133 u8 rsvd5[256-16-sizeof(struct rtas_args)]; 134 135 /*===================================================================================== 136 * CACHE_LINE_19 - 20 Profile Data 137 *===================================================================================== 138 */ 139 u64 pmc[12]; /* Default pmc value */ 140 u64 pmcc[8]; /* Cumulative pmc counts */ 141 142 u32 prof_multiplier; /* */ 143 u32 prof_shift; /* iSeries shift for profile bucket size */ 144 u32 *prof_buffer; /* iSeries profiling buffer */ 145 u32 *prof_stext; /* iSeries start of kernel text */ 146 u32 *prof_etext; /* iSeries start of kernel text */ 147 u32 prof_len; /* iSeries length of profile buffer -1 */ 148 u8 prof_mode; /* */ 149 u8 rsvv5b[3]; 150 u64 prof_counter; /* */ 151 u8 rsvd5c[256-8*26]; 152 153 /*===================================================================================== 154 * CACHE_LINE_20-30 155 *===================================================================================== 156 */ 157 u64 slb_shadow[0x20]; 158 u64 dispatch_log; 159 u8 rsvd6[0x400 - 0x8]; 160 161 /*===================================================================================== 162 * CACHE_LINE_31 0x0F00 - 0x0F7F Exception stack 163 *===================================================================================== 164 */ 165 u8 exception_stack[N_EXC_STACK*EXC_FRAME_SIZE]; 166 167 /*===================================================================================== 168 * CACHE_LINE_32 0x0F80 - 0x0FFF Reserved 169 *===================================================================================== 170 */ 171 u8 rsvd7[0x80]; /* Give the stack some rope ... */ 172 173 /*===================================================================================== 174 * Page 2 Reserved for guard page. Also used as a stack early in SMP boots before 175 * relocation is enabled. 176 *===================================================================================== 177 */ 178 u8 guard[0x1000]; /* ... and then hang 'em */ 179 }; 180 181 #define get_hard_smp_processor_id(CPU) (paca[(CPU)].xHwProcNum) 182 183 #endif /* _PPC64_PACA_H */ 184