1 /*
2  * Performance events x86 architecture code
3  *
4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6  *  Copyright (C) 2009 Jaswinder Singh Rajput
7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
11  *
12  *  For licencing details see kernel-base/COPYING
13  */
14 
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/export.h>
21 #include <linux/init.h>
22 #include <linux/kdebug.h>
23 #include <linux/sched/mm.h>
24 #include <linux/sched/clock.h>
25 #include <linux/uaccess.h>
26 #include <linux/slab.h>
27 #include <linux/cpu.h>
28 #include <linux/bitops.h>
29 #include <linux/device.h>
30 #include <linux/nospec.h>
31 #include <linux/static_call.h>
32 
33 #include <asm/apic.h>
34 #include <asm/stacktrace.h>
35 #include <asm/nmi.h>
36 #include <asm/smp.h>
37 #include <asm/alternative.h>
38 #include <asm/mmu_context.h>
39 #include <asm/tlbflush.h>
40 #include <asm/timer.h>
41 #include <asm/desc.h>
42 #include <asm/ldt.h>
43 #include <asm/unwind.h>
44 
45 #include "perf_event.h"
46 
47 struct x86_pmu x86_pmu __read_mostly;
48 static struct pmu pmu;
49 
50 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
51 	.enabled = 1,
52 	.pmu = &pmu,
53 };
54 
55 DEFINE_STATIC_KEY_FALSE(rdpmc_never_available_key);
56 DEFINE_STATIC_KEY_FALSE(rdpmc_always_available_key);
57 DEFINE_STATIC_KEY_FALSE(perf_is_hybrid);
58 
59 /*
60  * This here uses DEFINE_STATIC_CALL_NULL() to get a static_call defined
61  * from just a typename, as opposed to an actual function.
62  */
63 DEFINE_STATIC_CALL_NULL(x86_pmu_handle_irq,  *x86_pmu.handle_irq);
64 DEFINE_STATIC_CALL_NULL(x86_pmu_disable_all, *x86_pmu.disable_all);
65 DEFINE_STATIC_CALL_NULL(x86_pmu_enable_all,  *x86_pmu.enable_all);
66 DEFINE_STATIC_CALL_NULL(x86_pmu_enable,	     *x86_pmu.enable);
67 DEFINE_STATIC_CALL_NULL(x86_pmu_disable,     *x86_pmu.disable);
68 
69 DEFINE_STATIC_CALL_NULL(x86_pmu_assign, *x86_pmu.assign);
70 
71 DEFINE_STATIC_CALL_NULL(x86_pmu_add,  *x86_pmu.add);
72 DEFINE_STATIC_CALL_NULL(x86_pmu_del,  *x86_pmu.del);
73 DEFINE_STATIC_CALL_NULL(x86_pmu_read, *x86_pmu.read);
74 
75 DEFINE_STATIC_CALL_NULL(x86_pmu_set_period,   *x86_pmu.set_period);
76 DEFINE_STATIC_CALL_NULL(x86_pmu_update,       *x86_pmu.update);
77 DEFINE_STATIC_CALL_NULL(x86_pmu_limit_period, *x86_pmu.limit_period);
78 
79 DEFINE_STATIC_CALL_NULL(x86_pmu_schedule_events,       *x86_pmu.schedule_events);
80 DEFINE_STATIC_CALL_NULL(x86_pmu_get_event_constraints, *x86_pmu.get_event_constraints);
81 DEFINE_STATIC_CALL_NULL(x86_pmu_put_event_constraints, *x86_pmu.put_event_constraints);
82 
83 DEFINE_STATIC_CALL_NULL(x86_pmu_start_scheduling,  *x86_pmu.start_scheduling);
84 DEFINE_STATIC_CALL_NULL(x86_pmu_commit_scheduling, *x86_pmu.commit_scheduling);
85 DEFINE_STATIC_CALL_NULL(x86_pmu_stop_scheduling,   *x86_pmu.stop_scheduling);
86 
87 DEFINE_STATIC_CALL_NULL(x86_pmu_sched_task,    *x86_pmu.sched_task);
88 DEFINE_STATIC_CALL_NULL(x86_pmu_swap_task_ctx, *x86_pmu.swap_task_ctx);
89 
90 DEFINE_STATIC_CALL_NULL(x86_pmu_drain_pebs,   *x86_pmu.drain_pebs);
91 DEFINE_STATIC_CALL_NULL(x86_pmu_pebs_aliases, *x86_pmu.pebs_aliases);
92 
93 DEFINE_STATIC_CALL_NULL(x86_pmu_filter, *x86_pmu.filter);
94 
95 /*
96  * This one is magic, it will get called even when PMU init fails (because
97  * there is no PMU), in which case it should simply return NULL.
98  */
99 DEFINE_STATIC_CALL_RET0(x86_pmu_guest_get_msrs, *x86_pmu.guest_get_msrs);
100 
101 u64 __read_mostly hw_cache_event_ids
102 				[PERF_COUNT_HW_CACHE_MAX]
103 				[PERF_COUNT_HW_CACHE_OP_MAX]
104 				[PERF_COUNT_HW_CACHE_RESULT_MAX];
105 u64 __read_mostly hw_cache_extra_regs
106 				[PERF_COUNT_HW_CACHE_MAX]
107 				[PERF_COUNT_HW_CACHE_OP_MAX]
108 				[PERF_COUNT_HW_CACHE_RESULT_MAX];
109 
110 /*
111  * Propagate event elapsed time into the generic event.
112  * Can only be executed on the CPU where the event is active.
113  * Returns the delta events processed.
114  */
x86_perf_event_update(struct perf_event * event)115 u64 x86_perf_event_update(struct perf_event *event)
116 {
117 	struct hw_perf_event *hwc = &event->hw;
118 	int shift = 64 - x86_pmu.cntval_bits;
119 	u64 prev_raw_count, new_raw_count;
120 	u64 delta;
121 
122 	if (unlikely(!hwc->event_base))
123 		return 0;
124 
125 	/*
126 	 * Careful: an NMI might modify the previous event value.
127 	 *
128 	 * Our tactic to handle this is to first atomically read and
129 	 * exchange a new raw count - then add that new-prev delta
130 	 * count to the generic event atomically:
131 	 */
132 	prev_raw_count = local64_read(&hwc->prev_count);
133 	do {
134 		rdpmcl(hwc->event_base_rdpmc, new_raw_count);
135 	} while (!local64_try_cmpxchg(&hwc->prev_count,
136 				      &prev_raw_count, new_raw_count));
137 
138 	/*
139 	 * Now we have the new raw value and have updated the prev
140 	 * timestamp already. We can now calculate the elapsed delta
141 	 * (event-)time and add that to the generic event.
142 	 *
143 	 * Careful, not all hw sign-extends above the physical width
144 	 * of the count.
145 	 */
146 	delta = (new_raw_count << shift) - (prev_raw_count << shift);
147 	delta >>= shift;
148 
149 	local64_add(delta, &event->count);
150 	local64_sub(delta, &hwc->period_left);
151 
152 	return new_raw_count;
153 }
154 
155 /*
156  * Find and validate any extra registers to set up.
157  */
x86_pmu_extra_regs(u64 config,struct perf_event * event)158 static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
159 {
160 	struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs);
161 	struct hw_perf_event_extra *reg;
162 	struct extra_reg *er;
163 
164 	reg = &event->hw.extra_reg;
165 
166 	if (!extra_regs)
167 		return 0;
168 
169 	for (er = extra_regs; er->msr; er++) {
170 		if (er->event != (config & er->config_mask))
171 			continue;
172 		if (event->attr.config1 & ~er->valid_mask)
173 			return -EINVAL;
174 		/* Check if the extra msrs can be safely accessed*/
175 		if (!er->extra_msr_access)
176 			return -ENXIO;
177 
178 		reg->idx = er->idx;
179 		reg->config = event->attr.config1;
180 		reg->reg = er->msr;
181 		break;
182 	}
183 	return 0;
184 }
185 
186 static atomic_t active_events;
187 static atomic_t pmc_refcount;
188 static DEFINE_MUTEX(pmc_reserve_mutex);
189 
190 #ifdef CONFIG_X86_LOCAL_APIC
191 
get_possible_num_counters(void)192 static inline int get_possible_num_counters(void)
193 {
194 	int i, num_counters = x86_pmu.num_counters;
195 
196 	if (!is_hybrid())
197 		return num_counters;
198 
199 	for (i = 0; i < x86_pmu.num_hybrid_pmus; i++)
200 		num_counters = max_t(int, num_counters, x86_pmu.hybrid_pmu[i].num_counters);
201 
202 	return num_counters;
203 }
204 
reserve_pmc_hardware(void)205 static bool reserve_pmc_hardware(void)
206 {
207 	int i, num_counters = get_possible_num_counters();
208 
209 	for (i = 0; i < num_counters; i++) {
210 		if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
211 			goto perfctr_fail;
212 	}
213 
214 	for (i = 0; i < num_counters; i++) {
215 		if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
216 			goto eventsel_fail;
217 	}
218 
219 	return true;
220 
221 eventsel_fail:
222 	for (i--; i >= 0; i--)
223 		release_evntsel_nmi(x86_pmu_config_addr(i));
224 
225 	i = num_counters;
226 
227 perfctr_fail:
228 	for (i--; i >= 0; i--)
229 		release_perfctr_nmi(x86_pmu_event_addr(i));
230 
231 	return false;
232 }
233 
release_pmc_hardware(void)234 static void release_pmc_hardware(void)
235 {
236 	int i, num_counters = get_possible_num_counters();
237 
238 	for (i = 0; i < num_counters; i++) {
239 		release_perfctr_nmi(x86_pmu_event_addr(i));
240 		release_evntsel_nmi(x86_pmu_config_addr(i));
241 	}
242 }
243 
244 #else
245 
reserve_pmc_hardware(void)246 static bool reserve_pmc_hardware(void) { return true; }
release_pmc_hardware(void)247 static void release_pmc_hardware(void) {}
248 
249 #endif
250 
check_hw_exists(struct pmu * pmu,int num_counters,int num_counters_fixed)251 bool check_hw_exists(struct pmu *pmu, int num_counters, int num_counters_fixed)
252 {
253 	u64 val, val_fail = -1, val_new= ~0;
254 	int i, reg, reg_fail = -1, ret = 0;
255 	int bios_fail = 0;
256 	int reg_safe = -1;
257 
258 	/*
259 	 * Check to see if the BIOS enabled any of the counters, if so
260 	 * complain and bail.
261 	 */
262 	for (i = 0; i < num_counters; i++) {
263 		reg = x86_pmu_config_addr(i);
264 		ret = rdmsrl_safe(reg, &val);
265 		if (ret)
266 			goto msr_fail;
267 		if (val & ARCH_PERFMON_EVENTSEL_ENABLE) {
268 			bios_fail = 1;
269 			val_fail = val;
270 			reg_fail = reg;
271 		} else {
272 			reg_safe = i;
273 		}
274 	}
275 
276 	if (num_counters_fixed) {
277 		reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
278 		ret = rdmsrl_safe(reg, &val);
279 		if (ret)
280 			goto msr_fail;
281 		for (i = 0; i < num_counters_fixed; i++) {
282 			if (fixed_counter_disabled(i, pmu))
283 				continue;
284 			if (val & (0x03ULL << i*4)) {
285 				bios_fail = 1;
286 				val_fail = val;
287 				reg_fail = reg;
288 			}
289 		}
290 	}
291 
292 	/*
293 	 * If all the counters are enabled, the below test will always
294 	 * fail.  The tools will also become useless in this scenario.
295 	 * Just fail and disable the hardware counters.
296 	 */
297 
298 	if (reg_safe == -1) {
299 		reg = reg_safe;
300 		goto msr_fail;
301 	}
302 
303 	/*
304 	 * Read the current value, change it and read it back to see if it
305 	 * matches, this is needed to detect certain hardware emulators
306 	 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
307 	 */
308 	reg = x86_pmu_event_addr(reg_safe);
309 	if (rdmsrl_safe(reg, &val))
310 		goto msr_fail;
311 	val ^= 0xffffUL;
312 	ret = wrmsrl_safe(reg, val);
313 	ret |= rdmsrl_safe(reg, &val_new);
314 	if (ret || val != val_new)
315 		goto msr_fail;
316 
317 	/*
318 	 * We still allow the PMU driver to operate:
319 	 */
320 	if (bios_fail) {
321 		pr_cont("Broken BIOS detected, complain to your hardware vendor.\n");
322 		pr_err(FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n",
323 			      reg_fail, val_fail);
324 	}
325 
326 	return true;
327 
328 msr_fail:
329 	if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
330 		pr_cont("PMU not available due to virtualization, using software events only.\n");
331 	} else {
332 		pr_cont("Broken PMU hardware detected, using software events only.\n");
333 		pr_err("Failed to access perfctr msr (MSR %x is %Lx)\n",
334 		       reg, val_new);
335 	}
336 
337 	return false;
338 }
339 
hw_perf_event_destroy(struct perf_event * event)340 static void hw_perf_event_destroy(struct perf_event *event)
341 {
342 	x86_release_hardware();
343 	atomic_dec(&active_events);
344 }
345 
hw_perf_lbr_event_destroy(struct perf_event * event)346 void hw_perf_lbr_event_destroy(struct perf_event *event)
347 {
348 	hw_perf_event_destroy(event);
349 
350 	/* undo the lbr/bts event accounting */
351 	x86_del_exclusive(x86_lbr_exclusive_lbr);
352 }
353 
x86_pmu_initialized(void)354 static inline int x86_pmu_initialized(void)
355 {
356 	return x86_pmu.handle_irq != NULL;
357 }
358 
359 static inline int
set_ext_hw_attr(struct hw_perf_event * hwc,struct perf_event * event)360 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
361 {
362 	struct perf_event_attr *attr = &event->attr;
363 	unsigned int cache_type, cache_op, cache_result;
364 	u64 config, val;
365 
366 	config = attr->config;
367 
368 	cache_type = (config >> 0) & 0xff;
369 	if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
370 		return -EINVAL;
371 	cache_type = array_index_nospec(cache_type, PERF_COUNT_HW_CACHE_MAX);
372 
373 	cache_op = (config >>  8) & 0xff;
374 	if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
375 		return -EINVAL;
376 	cache_op = array_index_nospec(cache_op, PERF_COUNT_HW_CACHE_OP_MAX);
377 
378 	cache_result = (config >> 16) & 0xff;
379 	if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
380 		return -EINVAL;
381 	cache_result = array_index_nospec(cache_result, PERF_COUNT_HW_CACHE_RESULT_MAX);
382 
383 	val = hybrid_var(event->pmu, hw_cache_event_ids)[cache_type][cache_op][cache_result];
384 	if (val == 0)
385 		return -ENOENT;
386 
387 	if (val == -1)
388 		return -EINVAL;
389 
390 	hwc->config |= val;
391 	attr->config1 = hybrid_var(event->pmu, hw_cache_extra_regs)[cache_type][cache_op][cache_result];
392 	return x86_pmu_extra_regs(val, event);
393 }
394 
x86_reserve_hardware(void)395 int x86_reserve_hardware(void)
396 {
397 	int err = 0;
398 
399 	if (!atomic_inc_not_zero(&pmc_refcount)) {
400 		mutex_lock(&pmc_reserve_mutex);
401 		if (atomic_read(&pmc_refcount) == 0) {
402 			if (!reserve_pmc_hardware()) {
403 				err = -EBUSY;
404 			} else {
405 				reserve_ds_buffers();
406 				reserve_lbr_buffers();
407 			}
408 		}
409 		if (!err)
410 			atomic_inc(&pmc_refcount);
411 		mutex_unlock(&pmc_reserve_mutex);
412 	}
413 
414 	return err;
415 }
416 
x86_release_hardware(void)417 void x86_release_hardware(void)
418 {
419 	if (atomic_dec_and_mutex_lock(&pmc_refcount, &pmc_reserve_mutex)) {
420 		release_pmc_hardware();
421 		release_ds_buffers();
422 		release_lbr_buffers();
423 		mutex_unlock(&pmc_reserve_mutex);
424 	}
425 }
426 
427 /*
428  * Check if we can create event of a certain type (that no conflicting events
429  * are present).
430  */
x86_add_exclusive(unsigned int what)431 int x86_add_exclusive(unsigned int what)
432 {
433 	int i;
434 
435 	/*
436 	 * When lbr_pt_coexist we allow PT to coexist with either LBR or BTS.
437 	 * LBR and BTS are still mutually exclusive.
438 	 */
439 	if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
440 		goto out;
441 
442 	if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) {
443 		mutex_lock(&pmc_reserve_mutex);
444 		for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++) {
445 			if (i != what && atomic_read(&x86_pmu.lbr_exclusive[i]))
446 				goto fail_unlock;
447 		}
448 		atomic_inc(&x86_pmu.lbr_exclusive[what]);
449 		mutex_unlock(&pmc_reserve_mutex);
450 	}
451 
452 out:
453 	atomic_inc(&active_events);
454 	return 0;
455 
456 fail_unlock:
457 	mutex_unlock(&pmc_reserve_mutex);
458 	return -EBUSY;
459 }
460 
x86_del_exclusive(unsigned int what)461 void x86_del_exclusive(unsigned int what)
462 {
463 	atomic_dec(&active_events);
464 
465 	/*
466 	 * See the comment in x86_add_exclusive().
467 	 */
468 	if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
469 		return;
470 
471 	atomic_dec(&x86_pmu.lbr_exclusive[what]);
472 }
473 
x86_setup_perfctr(struct perf_event * event)474 int x86_setup_perfctr(struct perf_event *event)
475 {
476 	struct perf_event_attr *attr = &event->attr;
477 	struct hw_perf_event *hwc = &event->hw;
478 	u64 config;
479 
480 	if (!is_sampling_event(event)) {
481 		hwc->sample_period = x86_pmu.max_period;
482 		hwc->last_period = hwc->sample_period;
483 		local64_set(&hwc->period_left, hwc->sample_period);
484 	}
485 
486 	if (attr->type == event->pmu->type)
487 		return x86_pmu_extra_regs(event->attr.config, event);
488 
489 	if (attr->type == PERF_TYPE_HW_CACHE)
490 		return set_ext_hw_attr(hwc, event);
491 
492 	if (attr->config >= x86_pmu.max_events)
493 		return -EINVAL;
494 
495 	attr->config = array_index_nospec((unsigned long)attr->config, x86_pmu.max_events);
496 
497 	/*
498 	 * The generic map:
499 	 */
500 	config = x86_pmu.event_map(attr->config);
501 
502 	if (config == 0)
503 		return -ENOENT;
504 
505 	if (config == -1LL)
506 		return -EINVAL;
507 
508 	hwc->config |= config;
509 
510 	return 0;
511 }
512 
513 /*
514  * check that branch_sample_type is compatible with
515  * settings needed for precise_ip > 1 which implies
516  * using the LBR to capture ALL taken branches at the
517  * priv levels of the measurement
518  */
precise_br_compat(struct perf_event * event)519 static inline int precise_br_compat(struct perf_event *event)
520 {
521 	u64 m = event->attr.branch_sample_type;
522 	u64 b = 0;
523 
524 	/* must capture all branches */
525 	if (!(m & PERF_SAMPLE_BRANCH_ANY))
526 		return 0;
527 
528 	m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER;
529 
530 	if (!event->attr.exclude_user)
531 		b |= PERF_SAMPLE_BRANCH_USER;
532 
533 	if (!event->attr.exclude_kernel)
534 		b |= PERF_SAMPLE_BRANCH_KERNEL;
535 
536 	/*
537 	 * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
538 	 */
539 
540 	return m == b;
541 }
542 
x86_pmu_max_precise(void)543 int x86_pmu_max_precise(void)
544 {
545 	int precise = 0;
546 
547 	/* Support for constant skid */
548 	if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
549 		precise++;
550 
551 		/* Support for IP fixup */
552 		if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2)
553 			precise++;
554 
555 		if (x86_pmu.pebs_prec_dist)
556 			precise++;
557 	}
558 	return precise;
559 }
560 
x86_pmu_hw_config(struct perf_event * event)561 int x86_pmu_hw_config(struct perf_event *event)
562 {
563 	if (event->attr.precise_ip) {
564 		int precise = x86_pmu_max_precise();
565 
566 		if (event->attr.precise_ip > precise)
567 			return -EOPNOTSUPP;
568 
569 		/* There's no sense in having PEBS for non sampling events: */
570 		if (!is_sampling_event(event))
571 			return -EINVAL;
572 	}
573 	/*
574 	 * check that PEBS LBR correction does not conflict with
575 	 * whatever the user is asking with attr->branch_sample_type
576 	 */
577 	if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format < 2) {
578 		u64 *br_type = &event->attr.branch_sample_type;
579 
580 		if (has_branch_stack(event)) {
581 			if (!precise_br_compat(event))
582 				return -EOPNOTSUPP;
583 
584 			/* branch_sample_type is compatible */
585 
586 		} else {
587 			/*
588 			 * user did not specify  branch_sample_type
589 			 *
590 			 * For PEBS fixups, we capture all
591 			 * the branches at the priv level of the
592 			 * event.
593 			 */
594 			*br_type = PERF_SAMPLE_BRANCH_ANY;
595 
596 			if (!event->attr.exclude_user)
597 				*br_type |= PERF_SAMPLE_BRANCH_USER;
598 
599 			if (!event->attr.exclude_kernel)
600 				*br_type |= PERF_SAMPLE_BRANCH_KERNEL;
601 		}
602 	}
603 
604 	if (event->attr.branch_sample_type & PERF_SAMPLE_BRANCH_CALL_STACK)
605 		event->attach_state |= PERF_ATTACH_TASK_DATA;
606 
607 	/*
608 	 * Generate PMC IRQs:
609 	 * (keep 'enabled' bit clear for now)
610 	 */
611 	event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
612 
613 	/*
614 	 * Count user and OS events unless requested not to
615 	 */
616 	if (!event->attr.exclude_user)
617 		event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
618 	if (!event->attr.exclude_kernel)
619 		event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
620 
621 	if (event->attr.type == event->pmu->type)
622 		event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
623 
624 	if (event->attr.sample_period && x86_pmu.limit_period) {
625 		s64 left = event->attr.sample_period;
626 		x86_pmu.limit_period(event, &left);
627 		if (left > event->attr.sample_period)
628 			return -EINVAL;
629 	}
630 
631 	/* sample_regs_user never support XMM registers */
632 	if (unlikely(event->attr.sample_regs_user & PERF_REG_EXTENDED_MASK))
633 		return -EINVAL;
634 	/*
635 	 * Besides the general purpose registers, XMM registers may
636 	 * be collected in PEBS on some platforms, e.g. Icelake
637 	 */
638 	if (unlikely(event->attr.sample_regs_intr & PERF_REG_EXTENDED_MASK)) {
639 		if (!(event->pmu->capabilities & PERF_PMU_CAP_EXTENDED_REGS))
640 			return -EINVAL;
641 
642 		if (!event->attr.precise_ip)
643 			return -EINVAL;
644 	}
645 
646 	return x86_setup_perfctr(event);
647 }
648 
649 /*
650  * Setup the hardware configuration for a given attr_type
651  */
__x86_pmu_event_init(struct perf_event * event)652 static int __x86_pmu_event_init(struct perf_event *event)
653 {
654 	int err;
655 
656 	if (!x86_pmu_initialized())
657 		return -ENODEV;
658 
659 	err = x86_reserve_hardware();
660 	if (err)
661 		return err;
662 
663 	atomic_inc(&active_events);
664 	event->destroy = hw_perf_event_destroy;
665 
666 	event->hw.idx = -1;
667 	event->hw.last_cpu = -1;
668 	event->hw.last_tag = ~0ULL;
669 
670 	/* mark unused */
671 	event->hw.extra_reg.idx = EXTRA_REG_NONE;
672 	event->hw.branch_reg.idx = EXTRA_REG_NONE;
673 
674 	return x86_pmu.hw_config(event);
675 }
676 
x86_pmu_disable_all(void)677 void x86_pmu_disable_all(void)
678 {
679 	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
680 	int idx;
681 
682 	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
683 		struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
684 		u64 val;
685 
686 		if (!test_bit(idx, cpuc->active_mask))
687 			continue;
688 		rdmsrl(x86_pmu_config_addr(idx), val);
689 		if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
690 			continue;
691 		val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
692 		wrmsrl(x86_pmu_config_addr(idx), val);
693 		if (is_counter_pair(hwc))
694 			wrmsrl(x86_pmu_config_addr(idx + 1), 0);
695 	}
696 }
697 
perf_guest_get_msrs(int * nr,void * data)698 struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, void *data)
699 {
700 	return static_call(x86_pmu_guest_get_msrs)(nr, data);
701 }
702 EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
703 
704 /*
705  * There may be PMI landing after enabled=0. The PMI hitting could be before or
706  * after disable_all.
707  *
708  * If PMI hits before disable_all, the PMU will be disabled in the NMI handler.
709  * It will not be re-enabled in the NMI handler again, because enabled=0. After
710  * handling the NMI, disable_all will be called, which will not change the
711  * state either. If PMI hits after disable_all, the PMU is already disabled
712  * before entering NMI handler. The NMI handler will not change the state
713  * either.
714  *
715  * So either situation is harmless.
716  */
x86_pmu_disable(struct pmu * pmu)717 static void x86_pmu_disable(struct pmu *pmu)
718 {
719 	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
720 
721 	if (!x86_pmu_initialized())
722 		return;
723 
724 	if (!cpuc->enabled)
725 		return;
726 
727 	cpuc->n_added = 0;
728 	cpuc->enabled = 0;
729 	barrier();
730 
731 	static_call(x86_pmu_disable_all)();
732 }
733 
x86_pmu_enable_all(int added)734 void x86_pmu_enable_all(int added)
735 {
736 	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
737 	int idx;
738 
739 	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
740 		struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
741 
742 		if (!test_bit(idx, cpuc->active_mask))
743 			continue;
744 
745 		__x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
746 	}
747 }
748 
is_x86_event(struct perf_event * event)749 static inline int is_x86_event(struct perf_event *event)
750 {
751 	int i;
752 
753 	if (!is_hybrid())
754 		return event->pmu == &pmu;
755 
756 	for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) {
757 		if (event->pmu == &x86_pmu.hybrid_pmu[i].pmu)
758 			return true;
759 	}
760 
761 	return false;
762 }
763 
x86_get_pmu(unsigned int cpu)764 struct pmu *x86_get_pmu(unsigned int cpu)
765 {
766 	struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
767 
768 	/*
769 	 * All CPUs of the hybrid type have been offline.
770 	 * The x86_get_pmu() should not be invoked.
771 	 */
772 	if (WARN_ON_ONCE(!cpuc->pmu))
773 		return &pmu;
774 
775 	return cpuc->pmu;
776 }
777 /*
778  * Event scheduler state:
779  *
780  * Assign events iterating over all events and counters, beginning
781  * with events with least weights first. Keep the current iterator
782  * state in struct sched_state.
783  */
784 struct sched_state {
785 	int	weight;
786 	int	event;		/* event index */
787 	int	counter;	/* counter index */
788 	int	unassigned;	/* number of events to be assigned left */
789 	int	nr_gp;		/* number of GP counters used */
790 	u64	used;
791 };
792 
793 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
794 #define	SCHED_STATES_MAX	2
795 
796 struct perf_sched {
797 	int			max_weight;
798 	int			max_events;
799 	int			max_gp;
800 	int			saved_states;
801 	struct event_constraint	**constraints;
802 	struct sched_state	state;
803 	struct sched_state	saved[SCHED_STATES_MAX];
804 };
805 
806 /*
807  * Initialize iterator that runs through all events and counters.
808  */
perf_sched_init(struct perf_sched * sched,struct event_constraint ** constraints,int num,int wmin,int wmax,int gpmax)809 static void perf_sched_init(struct perf_sched *sched, struct event_constraint **constraints,
810 			    int num, int wmin, int wmax, int gpmax)
811 {
812 	int idx;
813 
814 	memset(sched, 0, sizeof(*sched));
815 	sched->max_events	= num;
816 	sched->max_weight	= wmax;
817 	sched->max_gp		= gpmax;
818 	sched->constraints	= constraints;
819 
820 	for (idx = 0; idx < num; idx++) {
821 		if (constraints[idx]->weight == wmin)
822 			break;
823 	}
824 
825 	sched->state.event	= idx;		/* start with min weight */
826 	sched->state.weight	= wmin;
827 	sched->state.unassigned	= num;
828 }
829 
perf_sched_save_state(struct perf_sched * sched)830 static void perf_sched_save_state(struct perf_sched *sched)
831 {
832 	if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX))
833 		return;
834 
835 	sched->saved[sched->saved_states] = sched->state;
836 	sched->saved_states++;
837 }
838 
perf_sched_restore_state(struct perf_sched * sched)839 static bool perf_sched_restore_state(struct perf_sched *sched)
840 {
841 	if (!sched->saved_states)
842 		return false;
843 
844 	sched->saved_states--;
845 	sched->state = sched->saved[sched->saved_states];
846 
847 	/* this assignment didn't work out */
848 	/* XXX broken vs EVENT_PAIR */
849 	sched->state.used &= ~BIT_ULL(sched->state.counter);
850 
851 	/* try the next one */
852 	sched->state.counter++;
853 
854 	return true;
855 }
856 
857 /*
858  * Select a counter for the current event to schedule. Return true on
859  * success.
860  */
__perf_sched_find_counter(struct perf_sched * sched)861 static bool __perf_sched_find_counter(struct perf_sched *sched)
862 {
863 	struct event_constraint *c;
864 	int idx;
865 
866 	if (!sched->state.unassigned)
867 		return false;
868 
869 	if (sched->state.event >= sched->max_events)
870 		return false;
871 
872 	c = sched->constraints[sched->state.event];
873 	/* Prefer fixed purpose counters */
874 	if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
875 		idx = INTEL_PMC_IDX_FIXED;
876 		for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
877 			u64 mask = BIT_ULL(idx);
878 
879 			if (sched->state.used & mask)
880 				continue;
881 
882 			sched->state.used |= mask;
883 			goto done;
884 		}
885 	}
886 
887 	/* Grab the first unused counter starting with idx */
888 	idx = sched->state.counter;
889 	for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
890 		u64 mask = BIT_ULL(idx);
891 
892 		if (c->flags & PERF_X86_EVENT_PAIR)
893 			mask |= mask << 1;
894 
895 		if (sched->state.used & mask)
896 			continue;
897 
898 		if (sched->state.nr_gp++ >= sched->max_gp)
899 			return false;
900 
901 		sched->state.used |= mask;
902 		goto done;
903 	}
904 
905 	return false;
906 
907 done:
908 	sched->state.counter = idx;
909 
910 	if (c->overlap)
911 		perf_sched_save_state(sched);
912 
913 	return true;
914 }
915 
perf_sched_find_counter(struct perf_sched * sched)916 static bool perf_sched_find_counter(struct perf_sched *sched)
917 {
918 	while (!__perf_sched_find_counter(sched)) {
919 		if (!perf_sched_restore_state(sched))
920 			return false;
921 	}
922 
923 	return true;
924 }
925 
926 /*
927  * Go through all unassigned events and find the next one to schedule.
928  * Take events with the least weight first. Return true on success.
929  */
perf_sched_next_event(struct perf_sched * sched)930 static bool perf_sched_next_event(struct perf_sched *sched)
931 {
932 	struct event_constraint *c;
933 
934 	if (!sched->state.unassigned || !--sched->state.unassigned)
935 		return false;
936 
937 	do {
938 		/* next event */
939 		sched->state.event++;
940 		if (sched->state.event >= sched->max_events) {
941 			/* next weight */
942 			sched->state.event = 0;
943 			sched->state.weight++;
944 			if (sched->state.weight > sched->max_weight)
945 				return false;
946 		}
947 		c = sched->constraints[sched->state.event];
948 	} while (c->weight != sched->state.weight);
949 
950 	sched->state.counter = 0;	/* start with first counter */
951 
952 	return true;
953 }
954 
955 /*
956  * Assign a counter for each event.
957  */
perf_assign_events(struct event_constraint ** constraints,int n,int wmin,int wmax,int gpmax,int * assign)958 int perf_assign_events(struct event_constraint **constraints, int n,
959 			int wmin, int wmax, int gpmax, int *assign)
960 {
961 	struct perf_sched sched;
962 
963 	perf_sched_init(&sched, constraints, n, wmin, wmax, gpmax);
964 
965 	do {
966 		if (!perf_sched_find_counter(&sched))
967 			break;	/* failed */
968 		if (assign)
969 			assign[sched.state.event] = sched.state.counter;
970 	} while (perf_sched_next_event(&sched));
971 
972 	return sched.state.unassigned;
973 }
974 EXPORT_SYMBOL_GPL(perf_assign_events);
975 
x86_schedule_events(struct cpu_hw_events * cpuc,int n,int * assign)976 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
977 {
978 	int num_counters = hybrid(cpuc->pmu, num_counters);
979 	struct event_constraint *c;
980 	struct perf_event *e;
981 	int n0, i, wmin, wmax, unsched = 0;
982 	struct hw_perf_event *hwc;
983 	u64 used_mask = 0;
984 
985 	/*
986 	 * Compute the number of events already present; see x86_pmu_add(),
987 	 * validate_group() and x86_pmu_commit_txn(). For the former two
988 	 * cpuc->n_events hasn't been updated yet, while for the latter
989 	 * cpuc->n_txn contains the number of events added in the current
990 	 * transaction.
991 	 */
992 	n0 = cpuc->n_events;
993 	if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
994 		n0 -= cpuc->n_txn;
995 
996 	static_call_cond(x86_pmu_start_scheduling)(cpuc);
997 
998 	for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
999 		c = cpuc->event_constraint[i];
1000 
1001 		/*
1002 		 * Previously scheduled events should have a cached constraint,
1003 		 * while new events should not have one.
1004 		 */
1005 		WARN_ON_ONCE((c && i >= n0) || (!c && i < n0));
1006 
1007 		/*
1008 		 * Request constraints for new events; or for those events that
1009 		 * have a dynamic constraint -- for those the constraint can
1010 		 * change due to external factors (sibling state, allow_tfa).
1011 		 */
1012 		if (!c || (c->flags & PERF_X86_EVENT_DYNAMIC)) {
1013 			c = static_call(x86_pmu_get_event_constraints)(cpuc, i, cpuc->event_list[i]);
1014 			cpuc->event_constraint[i] = c;
1015 		}
1016 
1017 		wmin = min(wmin, c->weight);
1018 		wmax = max(wmax, c->weight);
1019 	}
1020 
1021 	/*
1022 	 * fastpath, try to reuse previous register
1023 	 */
1024 	for (i = 0; i < n; i++) {
1025 		u64 mask;
1026 
1027 		hwc = &cpuc->event_list[i]->hw;
1028 		c = cpuc->event_constraint[i];
1029 
1030 		/* never assigned */
1031 		if (hwc->idx == -1)
1032 			break;
1033 
1034 		/* constraint still honored */
1035 		if (!test_bit(hwc->idx, c->idxmsk))
1036 			break;
1037 
1038 		mask = BIT_ULL(hwc->idx);
1039 		if (is_counter_pair(hwc))
1040 			mask |= mask << 1;
1041 
1042 		/* not already used */
1043 		if (used_mask & mask)
1044 			break;
1045 
1046 		used_mask |= mask;
1047 
1048 		if (assign)
1049 			assign[i] = hwc->idx;
1050 	}
1051 
1052 	/* slow path */
1053 	if (i != n) {
1054 		int gpmax = num_counters;
1055 
1056 		/*
1057 		 * Do not allow scheduling of more than half the available
1058 		 * generic counters.
1059 		 *
1060 		 * This helps avoid counter starvation of sibling thread by
1061 		 * ensuring at most half the counters cannot be in exclusive
1062 		 * mode. There is no designated counters for the limits. Any
1063 		 * N/2 counters can be used. This helps with events with
1064 		 * specific counter constraints.
1065 		 */
1066 		if (is_ht_workaround_enabled() && !cpuc->is_fake &&
1067 		    READ_ONCE(cpuc->excl_cntrs->exclusive_present))
1068 			gpmax /= 2;
1069 
1070 		/*
1071 		 * Reduce the amount of available counters to allow fitting
1072 		 * the extra Merge events needed by large increment events.
1073 		 */
1074 		if (x86_pmu.flags & PMU_FL_PAIR) {
1075 			gpmax = num_counters - cpuc->n_pair;
1076 			WARN_ON(gpmax <= 0);
1077 		}
1078 
1079 		unsched = perf_assign_events(cpuc->event_constraint, n, wmin,
1080 					     wmax, gpmax, assign);
1081 	}
1082 
1083 	/*
1084 	 * In case of success (unsched = 0), mark events as committed,
1085 	 * so we do not put_constraint() in case new events are added
1086 	 * and fail to be scheduled
1087 	 *
1088 	 * We invoke the lower level commit callback to lock the resource
1089 	 *
1090 	 * We do not need to do all of this in case we are called to
1091 	 * validate an event group (assign == NULL)
1092 	 */
1093 	if (!unsched && assign) {
1094 		for (i = 0; i < n; i++)
1095 			static_call_cond(x86_pmu_commit_scheduling)(cpuc, i, assign[i]);
1096 	} else {
1097 		for (i = n0; i < n; i++) {
1098 			e = cpuc->event_list[i];
1099 
1100 			/*
1101 			 * release events that failed scheduling
1102 			 */
1103 			static_call_cond(x86_pmu_put_event_constraints)(cpuc, e);
1104 
1105 			cpuc->event_constraint[i] = NULL;
1106 		}
1107 	}
1108 
1109 	static_call_cond(x86_pmu_stop_scheduling)(cpuc);
1110 
1111 	return unsched ? -EINVAL : 0;
1112 }
1113 
add_nr_metric_event(struct cpu_hw_events * cpuc,struct perf_event * event)1114 static int add_nr_metric_event(struct cpu_hw_events *cpuc,
1115 			       struct perf_event *event)
1116 {
1117 	if (is_metric_event(event)) {
1118 		if (cpuc->n_metric == INTEL_TD_METRIC_NUM)
1119 			return -EINVAL;
1120 		cpuc->n_metric++;
1121 		cpuc->n_txn_metric++;
1122 	}
1123 
1124 	return 0;
1125 }
1126 
del_nr_metric_event(struct cpu_hw_events * cpuc,struct perf_event * event)1127 static void del_nr_metric_event(struct cpu_hw_events *cpuc,
1128 				struct perf_event *event)
1129 {
1130 	if (is_metric_event(event))
1131 		cpuc->n_metric--;
1132 }
1133 
collect_event(struct cpu_hw_events * cpuc,struct perf_event * event,int max_count,int n)1134 static int collect_event(struct cpu_hw_events *cpuc, struct perf_event *event,
1135 			 int max_count, int n)
1136 {
1137 	union perf_capabilities intel_cap = hybrid(cpuc->pmu, intel_cap);
1138 
1139 	if (intel_cap.perf_metrics && add_nr_metric_event(cpuc, event))
1140 		return -EINVAL;
1141 
1142 	if (n >= max_count + cpuc->n_metric)
1143 		return -EINVAL;
1144 
1145 	cpuc->event_list[n] = event;
1146 	if (is_counter_pair(&event->hw)) {
1147 		cpuc->n_pair++;
1148 		cpuc->n_txn_pair++;
1149 	}
1150 
1151 	return 0;
1152 }
1153 
1154 /*
1155  * dogrp: true if must collect siblings events (group)
1156  * returns total number of events and error code
1157  */
collect_events(struct cpu_hw_events * cpuc,struct perf_event * leader,bool dogrp)1158 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
1159 {
1160 	int num_counters = hybrid(cpuc->pmu, num_counters);
1161 	int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed);
1162 	struct perf_event *event;
1163 	int n, max_count;
1164 
1165 	max_count = num_counters + num_counters_fixed;
1166 
1167 	/* current number of events already accepted */
1168 	n = cpuc->n_events;
1169 	if (!cpuc->n_events)
1170 		cpuc->pebs_output = 0;
1171 
1172 	if (!cpuc->is_fake && leader->attr.precise_ip) {
1173 		/*
1174 		 * For PEBS->PT, if !aux_event, the group leader (PT) went
1175 		 * away, the group was broken down and this singleton event
1176 		 * can't schedule any more.
1177 		 */
1178 		if (is_pebs_pt(leader) && !leader->aux_event)
1179 			return -EINVAL;
1180 
1181 		/*
1182 		 * pebs_output: 0: no PEBS so far, 1: PT, 2: DS
1183 		 */
1184 		if (cpuc->pebs_output &&
1185 		    cpuc->pebs_output != is_pebs_pt(leader) + 1)
1186 			return -EINVAL;
1187 
1188 		cpuc->pebs_output = is_pebs_pt(leader) + 1;
1189 	}
1190 
1191 	if (is_x86_event(leader)) {
1192 		if (collect_event(cpuc, leader, max_count, n))
1193 			return -EINVAL;
1194 		n++;
1195 	}
1196 
1197 	if (!dogrp)
1198 		return n;
1199 
1200 	for_each_sibling_event(event, leader) {
1201 		if (!is_x86_event(event) || event->state <= PERF_EVENT_STATE_OFF)
1202 			continue;
1203 
1204 		if (collect_event(cpuc, event, max_count, n))
1205 			return -EINVAL;
1206 
1207 		n++;
1208 	}
1209 	return n;
1210 }
1211 
x86_assign_hw_event(struct perf_event * event,struct cpu_hw_events * cpuc,int i)1212 static inline void x86_assign_hw_event(struct perf_event *event,
1213 				struct cpu_hw_events *cpuc, int i)
1214 {
1215 	struct hw_perf_event *hwc = &event->hw;
1216 	int idx;
1217 
1218 	idx = hwc->idx = cpuc->assign[i];
1219 	hwc->last_cpu = smp_processor_id();
1220 	hwc->last_tag = ++cpuc->tags[i];
1221 
1222 	static_call_cond(x86_pmu_assign)(event, idx);
1223 
1224 	switch (hwc->idx) {
1225 	case INTEL_PMC_IDX_FIXED_BTS:
1226 	case INTEL_PMC_IDX_FIXED_VLBR:
1227 		hwc->config_base = 0;
1228 		hwc->event_base	= 0;
1229 		break;
1230 
1231 	case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
1232 		/* All the metric events are mapped onto the fixed counter 3. */
1233 		idx = INTEL_PMC_IDX_FIXED_SLOTS;
1234 		fallthrough;
1235 	case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS-1:
1236 		hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
1237 		hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 +
1238 				(idx - INTEL_PMC_IDX_FIXED);
1239 		hwc->event_base_rdpmc = (idx - INTEL_PMC_IDX_FIXED) |
1240 					INTEL_PMC_FIXED_RDPMC_BASE;
1241 		break;
1242 
1243 	default:
1244 		hwc->config_base = x86_pmu_config_addr(hwc->idx);
1245 		hwc->event_base  = x86_pmu_event_addr(hwc->idx);
1246 		hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx);
1247 		break;
1248 	}
1249 }
1250 
1251 /**
1252  * x86_perf_rdpmc_index - Return PMC counter used for event
1253  * @event: the perf_event to which the PMC counter was assigned
1254  *
1255  * The counter assigned to this performance event may change if interrupts
1256  * are enabled. This counter should thus never be used while interrupts are
1257  * enabled. Before this function is used to obtain the assigned counter the
1258  * event should be checked for validity using, for example,
1259  * perf_event_read_local(), within the same interrupt disabled section in
1260  * which this counter is planned to be used.
1261  *
1262  * Return: The index of the performance monitoring counter assigned to
1263  * @perf_event.
1264  */
x86_perf_rdpmc_index(struct perf_event * event)1265 int x86_perf_rdpmc_index(struct perf_event *event)
1266 {
1267 	lockdep_assert_irqs_disabled();
1268 
1269 	return event->hw.event_base_rdpmc;
1270 }
1271 
match_prev_assignment(struct hw_perf_event * hwc,struct cpu_hw_events * cpuc,int i)1272 static inline int match_prev_assignment(struct hw_perf_event *hwc,
1273 					struct cpu_hw_events *cpuc,
1274 					int i)
1275 {
1276 	return hwc->idx == cpuc->assign[i] &&
1277 		hwc->last_cpu == smp_processor_id() &&
1278 		hwc->last_tag == cpuc->tags[i];
1279 }
1280 
1281 static void x86_pmu_start(struct perf_event *event, int flags);
1282 
x86_pmu_enable(struct pmu * pmu)1283 static void x86_pmu_enable(struct pmu *pmu)
1284 {
1285 	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1286 	struct perf_event *event;
1287 	struct hw_perf_event *hwc;
1288 	int i, added = cpuc->n_added;
1289 
1290 	if (!x86_pmu_initialized())
1291 		return;
1292 
1293 	if (cpuc->enabled)
1294 		return;
1295 
1296 	if (cpuc->n_added) {
1297 		int n_running = cpuc->n_events - cpuc->n_added;
1298 		/*
1299 		 * apply assignment obtained either from
1300 		 * hw_perf_group_sched_in() or x86_pmu_enable()
1301 		 *
1302 		 * step1: save events moving to new counters
1303 		 */
1304 		for (i = 0; i < n_running; i++) {
1305 			event = cpuc->event_list[i];
1306 			hwc = &event->hw;
1307 
1308 			/*
1309 			 * we can avoid reprogramming counter if:
1310 			 * - assigned same counter as last time
1311 			 * - running on same CPU as last time
1312 			 * - no other event has used the counter since
1313 			 */
1314 			if (hwc->idx == -1 ||
1315 			    match_prev_assignment(hwc, cpuc, i))
1316 				continue;
1317 
1318 			/*
1319 			 * Ensure we don't accidentally enable a stopped
1320 			 * counter simply because we rescheduled.
1321 			 */
1322 			if (hwc->state & PERF_HES_STOPPED)
1323 				hwc->state |= PERF_HES_ARCH;
1324 
1325 			x86_pmu_stop(event, PERF_EF_UPDATE);
1326 		}
1327 
1328 		/*
1329 		 * step2: reprogram moved events into new counters
1330 		 */
1331 		for (i = 0; i < cpuc->n_events; i++) {
1332 			event = cpuc->event_list[i];
1333 			hwc = &event->hw;
1334 
1335 			if (!match_prev_assignment(hwc, cpuc, i))
1336 				x86_assign_hw_event(event, cpuc, i);
1337 			else if (i < n_running)
1338 				continue;
1339 
1340 			if (hwc->state & PERF_HES_ARCH)
1341 				continue;
1342 
1343 			/*
1344 			 * if cpuc->enabled = 0, then no wrmsr as
1345 			 * per x86_pmu_enable_event()
1346 			 */
1347 			x86_pmu_start(event, PERF_EF_RELOAD);
1348 		}
1349 		cpuc->n_added = 0;
1350 		perf_events_lapic_init();
1351 	}
1352 
1353 	cpuc->enabled = 1;
1354 	barrier();
1355 
1356 	static_call(x86_pmu_enable_all)(added);
1357 }
1358 
1359 DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
1360 
1361 /*
1362  * Set the next IRQ period, based on the hwc->period_left value.
1363  * To be called with the event disabled in hw:
1364  */
x86_perf_event_set_period(struct perf_event * event)1365 int x86_perf_event_set_period(struct perf_event *event)
1366 {
1367 	struct hw_perf_event *hwc = &event->hw;
1368 	s64 left = local64_read(&hwc->period_left);
1369 	s64 period = hwc->sample_period;
1370 	int ret = 0, idx = hwc->idx;
1371 
1372 	if (unlikely(!hwc->event_base))
1373 		return 0;
1374 
1375 	/*
1376 	 * If we are way outside a reasonable range then just skip forward:
1377 	 */
1378 	if (unlikely(left <= -period)) {
1379 		left = period;
1380 		local64_set(&hwc->period_left, left);
1381 		hwc->last_period = period;
1382 		ret = 1;
1383 	}
1384 
1385 	if (unlikely(left <= 0)) {
1386 		left += period;
1387 		local64_set(&hwc->period_left, left);
1388 		hwc->last_period = period;
1389 		ret = 1;
1390 	}
1391 	/*
1392 	 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1393 	 */
1394 	if (unlikely(left < 2))
1395 		left = 2;
1396 
1397 	if (left > x86_pmu.max_period)
1398 		left = x86_pmu.max_period;
1399 
1400 	static_call_cond(x86_pmu_limit_period)(event, &left);
1401 
1402 	this_cpu_write(pmc_prev_left[idx], left);
1403 
1404 	/*
1405 	 * The hw event starts counting from this event offset,
1406 	 * mark it to be able to extra future deltas:
1407 	 */
1408 	local64_set(&hwc->prev_count, (u64)-left);
1409 
1410 	wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
1411 
1412 	/*
1413 	 * Sign extend the Merge event counter's upper 16 bits since
1414 	 * we currently declare a 48-bit counter width
1415 	 */
1416 	if (is_counter_pair(hwc))
1417 		wrmsrl(x86_pmu_event_addr(idx + 1), 0xffff);
1418 
1419 	perf_event_update_userpage(event);
1420 
1421 	return ret;
1422 }
1423 
x86_pmu_enable_event(struct perf_event * event)1424 void x86_pmu_enable_event(struct perf_event *event)
1425 {
1426 	if (__this_cpu_read(cpu_hw_events.enabled))
1427 		__x86_pmu_enable_event(&event->hw,
1428 				       ARCH_PERFMON_EVENTSEL_ENABLE);
1429 }
1430 
1431 /*
1432  * Add a single event to the PMU.
1433  *
1434  * The event is added to the group of enabled events
1435  * but only if it can be scheduled with existing events.
1436  */
x86_pmu_add(struct perf_event * event,int flags)1437 static int x86_pmu_add(struct perf_event *event, int flags)
1438 {
1439 	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1440 	struct hw_perf_event *hwc;
1441 	int assign[X86_PMC_IDX_MAX];
1442 	int n, n0, ret;
1443 
1444 	hwc = &event->hw;
1445 
1446 	n0 = cpuc->n_events;
1447 	ret = n = collect_events(cpuc, event, false);
1448 	if (ret < 0)
1449 		goto out;
1450 
1451 	hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1452 	if (!(flags & PERF_EF_START))
1453 		hwc->state |= PERF_HES_ARCH;
1454 
1455 	/*
1456 	 * If group events scheduling transaction was started,
1457 	 * skip the schedulability test here, it will be performed
1458 	 * at commit time (->commit_txn) as a whole.
1459 	 *
1460 	 * If commit fails, we'll call ->del() on all events
1461 	 * for which ->add() was called.
1462 	 */
1463 	if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1464 		goto done_collect;
1465 
1466 	ret = static_call(x86_pmu_schedule_events)(cpuc, n, assign);
1467 	if (ret)
1468 		goto out;
1469 	/*
1470 	 * copy new assignment, now we know it is possible
1471 	 * will be used by hw_perf_enable()
1472 	 */
1473 	memcpy(cpuc->assign, assign, n*sizeof(int));
1474 
1475 done_collect:
1476 	/*
1477 	 * Commit the collect_events() state. See x86_pmu_del() and
1478 	 * x86_pmu_*_txn().
1479 	 */
1480 	cpuc->n_events = n;
1481 	cpuc->n_added += n - n0;
1482 	cpuc->n_txn += n - n0;
1483 
1484 	/*
1485 	 * This is before x86_pmu_enable() will call x86_pmu_start(),
1486 	 * so we enable LBRs before an event needs them etc..
1487 	 */
1488 	static_call_cond(x86_pmu_add)(event);
1489 
1490 	ret = 0;
1491 out:
1492 	return ret;
1493 }
1494 
x86_pmu_start(struct perf_event * event,int flags)1495 static void x86_pmu_start(struct perf_event *event, int flags)
1496 {
1497 	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1498 	int idx = event->hw.idx;
1499 
1500 	if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1501 		return;
1502 
1503 	if (WARN_ON_ONCE(idx == -1))
1504 		return;
1505 
1506 	if (flags & PERF_EF_RELOAD) {
1507 		WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1508 		static_call(x86_pmu_set_period)(event);
1509 	}
1510 
1511 	event->hw.state = 0;
1512 
1513 	cpuc->events[idx] = event;
1514 	__set_bit(idx, cpuc->active_mask);
1515 	static_call(x86_pmu_enable)(event);
1516 	perf_event_update_userpage(event);
1517 }
1518 
perf_event_print_debug(void)1519 void perf_event_print_debug(void)
1520 {
1521 	u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1522 	u64 pebs, debugctl;
1523 	int cpu = smp_processor_id();
1524 	struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1525 	int num_counters = hybrid(cpuc->pmu, num_counters);
1526 	int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed);
1527 	struct event_constraint *pebs_constraints = hybrid(cpuc->pmu, pebs_constraints);
1528 	unsigned long flags;
1529 	int idx;
1530 
1531 	if (!num_counters)
1532 		return;
1533 
1534 	local_irq_save(flags);
1535 
1536 	if (x86_pmu.version >= 2) {
1537 		rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1538 		rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1539 		rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1540 		rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1541 
1542 		pr_info("\n");
1543 		pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
1544 		pr_info("CPU#%d: status:     %016llx\n", cpu, status);
1545 		pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
1546 		pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1547 		if (pebs_constraints) {
1548 			rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1549 			pr_info("CPU#%d: pebs:       %016llx\n", cpu, pebs);
1550 		}
1551 		if (x86_pmu.lbr_nr) {
1552 			rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
1553 			pr_info("CPU#%d: debugctl:   %016llx\n", cpu, debugctl);
1554 		}
1555 	}
1556 	pr_info("CPU#%d: active:     %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1557 
1558 	for (idx = 0; idx < num_counters; idx++) {
1559 		rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
1560 		rdmsrl(x86_pmu_event_addr(idx), pmc_count);
1561 
1562 		prev_left = per_cpu(pmc_prev_left[idx], cpu);
1563 
1564 		pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
1565 			cpu, idx, pmc_ctrl);
1566 		pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
1567 			cpu, idx, pmc_count);
1568 		pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1569 			cpu, idx, prev_left);
1570 	}
1571 	for (idx = 0; idx < num_counters_fixed; idx++) {
1572 		if (fixed_counter_disabled(idx, cpuc->pmu))
1573 			continue;
1574 		rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1575 
1576 		pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1577 			cpu, idx, pmc_count);
1578 	}
1579 	local_irq_restore(flags);
1580 }
1581 
x86_pmu_stop(struct perf_event * event,int flags)1582 void x86_pmu_stop(struct perf_event *event, int flags)
1583 {
1584 	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1585 	struct hw_perf_event *hwc = &event->hw;
1586 
1587 	if (test_bit(hwc->idx, cpuc->active_mask)) {
1588 		static_call(x86_pmu_disable)(event);
1589 		__clear_bit(hwc->idx, cpuc->active_mask);
1590 		cpuc->events[hwc->idx] = NULL;
1591 		WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1592 		hwc->state |= PERF_HES_STOPPED;
1593 	}
1594 
1595 	if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1596 		/*
1597 		 * Drain the remaining delta count out of a event
1598 		 * that we are disabling:
1599 		 */
1600 		static_call(x86_pmu_update)(event);
1601 		hwc->state |= PERF_HES_UPTODATE;
1602 	}
1603 }
1604 
x86_pmu_del(struct perf_event * event,int flags)1605 static void x86_pmu_del(struct perf_event *event, int flags)
1606 {
1607 	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1608 	union perf_capabilities intel_cap = hybrid(cpuc->pmu, intel_cap);
1609 	int i;
1610 
1611 	/*
1612 	 * If we're called during a txn, we only need to undo x86_pmu.add.
1613 	 * The events never got scheduled and ->cancel_txn will truncate
1614 	 * the event_list.
1615 	 *
1616 	 * XXX assumes any ->del() called during a TXN will only be on
1617 	 * an event added during that same TXN.
1618 	 */
1619 	if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1620 		goto do_del;
1621 
1622 	__set_bit(event->hw.idx, cpuc->dirty);
1623 
1624 	/*
1625 	 * Not a TXN, therefore cleanup properly.
1626 	 */
1627 	x86_pmu_stop(event, PERF_EF_UPDATE);
1628 
1629 	for (i = 0; i < cpuc->n_events; i++) {
1630 		if (event == cpuc->event_list[i])
1631 			break;
1632 	}
1633 
1634 	if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */
1635 		return;
1636 
1637 	/* If we have a newly added event; make sure to decrease n_added. */
1638 	if (i >= cpuc->n_events - cpuc->n_added)
1639 		--cpuc->n_added;
1640 
1641 	static_call_cond(x86_pmu_put_event_constraints)(cpuc, event);
1642 
1643 	/* Delete the array entry. */
1644 	while (++i < cpuc->n_events) {
1645 		cpuc->event_list[i-1] = cpuc->event_list[i];
1646 		cpuc->event_constraint[i-1] = cpuc->event_constraint[i];
1647 	}
1648 	cpuc->event_constraint[i-1] = NULL;
1649 	--cpuc->n_events;
1650 	if (intel_cap.perf_metrics)
1651 		del_nr_metric_event(cpuc, event);
1652 
1653 	perf_event_update_userpage(event);
1654 
1655 do_del:
1656 
1657 	/*
1658 	 * This is after x86_pmu_stop(); so we disable LBRs after any
1659 	 * event can need them etc..
1660 	 */
1661 	static_call_cond(x86_pmu_del)(event);
1662 }
1663 
x86_pmu_handle_irq(struct pt_regs * regs)1664 int x86_pmu_handle_irq(struct pt_regs *regs)
1665 {
1666 	struct perf_sample_data data;
1667 	struct cpu_hw_events *cpuc;
1668 	struct perf_event *event;
1669 	int idx, handled = 0;
1670 	u64 val;
1671 
1672 	cpuc = this_cpu_ptr(&cpu_hw_events);
1673 
1674 	/*
1675 	 * Some chipsets need to unmask the LVTPC in a particular spot
1676 	 * inside the nmi handler.  As a result, the unmasking was pushed
1677 	 * into all the nmi handlers.
1678 	 *
1679 	 * This generic handler doesn't seem to have any issues where the
1680 	 * unmasking occurs so it was left at the top.
1681 	 */
1682 	apic_write(APIC_LVTPC, APIC_DM_NMI);
1683 
1684 	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1685 		if (!test_bit(idx, cpuc->active_mask))
1686 			continue;
1687 
1688 		event = cpuc->events[idx];
1689 
1690 		val = static_call(x86_pmu_update)(event);
1691 		if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1692 			continue;
1693 
1694 		/*
1695 		 * event overflow
1696 		 */
1697 		handled++;
1698 
1699 		if (!static_call(x86_pmu_set_period)(event))
1700 			continue;
1701 
1702 		perf_sample_data_init(&data, 0, event->hw.last_period);
1703 
1704 		if (has_branch_stack(event))
1705 			perf_sample_save_brstack(&data, event, &cpuc->lbr_stack);
1706 
1707 		if (perf_event_overflow(event, &data, regs))
1708 			x86_pmu_stop(event, 0);
1709 	}
1710 
1711 	if (handled)
1712 		inc_irq_stat(apic_perf_irqs);
1713 
1714 	return handled;
1715 }
1716 
perf_events_lapic_init(void)1717 void perf_events_lapic_init(void)
1718 {
1719 	if (!x86_pmu.apic || !x86_pmu_initialized())
1720 		return;
1721 
1722 	/*
1723 	 * Always use NMI for PMU
1724 	 */
1725 	apic_write(APIC_LVTPC, APIC_DM_NMI);
1726 }
1727 
1728 static int
perf_event_nmi_handler(unsigned int cmd,struct pt_regs * regs)1729 perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
1730 {
1731 	u64 start_clock;
1732 	u64 finish_clock;
1733 	int ret;
1734 
1735 	/*
1736 	 * All PMUs/events that share this PMI handler should make sure to
1737 	 * increment active_events for their events.
1738 	 */
1739 	if (!atomic_read(&active_events))
1740 		return NMI_DONE;
1741 
1742 	start_clock = sched_clock();
1743 	ret = static_call(x86_pmu_handle_irq)(regs);
1744 	finish_clock = sched_clock();
1745 
1746 	perf_sample_event_took(finish_clock - start_clock);
1747 
1748 	return ret;
1749 }
1750 NOKPROBE_SYMBOL(perf_event_nmi_handler);
1751 
1752 struct event_constraint emptyconstraint;
1753 struct event_constraint unconstrained;
1754 
x86_pmu_prepare_cpu(unsigned int cpu)1755 static int x86_pmu_prepare_cpu(unsigned int cpu)
1756 {
1757 	struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1758 	int i;
1759 
1760 	for (i = 0 ; i < X86_PERF_KFREE_MAX; i++)
1761 		cpuc->kfree_on_online[i] = NULL;
1762 	if (x86_pmu.cpu_prepare)
1763 		return x86_pmu.cpu_prepare(cpu);
1764 	return 0;
1765 }
1766 
x86_pmu_dead_cpu(unsigned int cpu)1767 static int x86_pmu_dead_cpu(unsigned int cpu)
1768 {
1769 	if (x86_pmu.cpu_dead)
1770 		x86_pmu.cpu_dead(cpu);
1771 	return 0;
1772 }
1773 
x86_pmu_online_cpu(unsigned int cpu)1774 static int x86_pmu_online_cpu(unsigned int cpu)
1775 {
1776 	struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1777 	int i;
1778 
1779 	for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) {
1780 		kfree(cpuc->kfree_on_online[i]);
1781 		cpuc->kfree_on_online[i] = NULL;
1782 	}
1783 	return 0;
1784 }
1785 
x86_pmu_starting_cpu(unsigned int cpu)1786 static int x86_pmu_starting_cpu(unsigned int cpu)
1787 {
1788 	if (x86_pmu.cpu_starting)
1789 		x86_pmu.cpu_starting(cpu);
1790 	return 0;
1791 }
1792 
x86_pmu_dying_cpu(unsigned int cpu)1793 static int x86_pmu_dying_cpu(unsigned int cpu)
1794 {
1795 	if (x86_pmu.cpu_dying)
1796 		x86_pmu.cpu_dying(cpu);
1797 	return 0;
1798 }
1799 
pmu_check_apic(void)1800 static void __init pmu_check_apic(void)
1801 {
1802 	if (boot_cpu_has(X86_FEATURE_APIC))
1803 		return;
1804 
1805 	x86_pmu.apic = 0;
1806 	pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1807 	pr_info("no hardware sampling interrupt available.\n");
1808 
1809 	/*
1810 	 * If we have a PMU initialized but no APIC
1811 	 * interrupts, we cannot sample hardware
1812 	 * events (user-space has to fall back and
1813 	 * sample via a hrtimer based software event):
1814 	 */
1815 	pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
1816 
1817 }
1818 
1819 static struct attribute_group x86_pmu_format_group __ro_after_init = {
1820 	.name = "format",
1821 	.attrs = NULL,
1822 };
1823 
events_sysfs_show(struct device * dev,struct device_attribute * attr,char * page)1824 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, char *page)
1825 {
1826 	struct perf_pmu_events_attr *pmu_attr =
1827 		container_of(attr, struct perf_pmu_events_attr, attr);
1828 	u64 config = 0;
1829 
1830 	if (pmu_attr->id < x86_pmu.max_events)
1831 		config = x86_pmu.event_map(pmu_attr->id);
1832 
1833 	/* string trumps id */
1834 	if (pmu_attr->event_str)
1835 		return sprintf(page, "%s\n", pmu_attr->event_str);
1836 
1837 	return x86_pmu.events_sysfs_show(page, config);
1838 }
1839 EXPORT_SYMBOL_GPL(events_sysfs_show);
1840 
events_ht_sysfs_show(struct device * dev,struct device_attribute * attr,char * page)1841 ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr,
1842 			  char *page)
1843 {
1844 	struct perf_pmu_events_ht_attr *pmu_attr =
1845 		container_of(attr, struct perf_pmu_events_ht_attr, attr);
1846 
1847 	/*
1848 	 * Report conditional events depending on Hyper-Threading.
1849 	 *
1850 	 * This is overly conservative as usually the HT special
1851 	 * handling is not needed if the other CPU thread is idle.
1852 	 *
1853 	 * Note this does not (and cannot) handle the case when thread
1854 	 * siblings are invisible, for example with virtualization
1855 	 * if they are owned by some other guest.  The user tool
1856 	 * has to re-read when a thread sibling gets onlined later.
1857 	 */
1858 	return sprintf(page, "%s",
1859 			topology_max_smt_threads() > 1 ?
1860 			pmu_attr->event_str_ht :
1861 			pmu_attr->event_str_noht);
1862 }
1863 
events_hybrid_sysfs_show(struct device * dev,struct device_attribute * attr,char * page)1864 ssize_t events_hybrid_sysfs_show(struct device *dev,
1865 				 struct device_attribute *attr,
1866 				 char *page)
1867 {
1868 	struct perf_pmu_events_hybrid_attr *pmu_attr =
1869 		container_of(attr, struct perf_pmu_events_hybrid_attr, attr);
1870 	struct x86_hybrid_pmu *pmu;
1871 	const char *str, *next_str;
1872 	int i;
1873 
1874 	if (hweight64(pmu_attr->pmu_type) == 1)
1875 		return sprintf(page, "%s", pmu_attr->event_str);
1876 
1877 	/*
1878 	 * Hybrid PMUs may support the same event name, but with different
1879 	 * event encoding, e.g., the mem-loads event on an Atom PMU has
1880 	 * different event encoding from a Core PMU.
1881 	 *
1882 	 * The event_str includes all event encodings. Each event encoding
1883 	 * is divided by ";". The order of the event encodings must follow
1884 	 * the order of the hybrid PMU index.
1885 	 */
1886 	pmu = container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
1887 
1888 	str = pmu_attr->event_str;
1889 	for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) {
1890 		if (!(x86_pmu.hybrid_pmu[i].cpu_type & pmu_attr->pmu_type))
1891 			continue;
1892 		if (x86_pmu.hybrid_pmu[i].cpu_type & pmu->cpu_type) {
1893 			next_str = strchr(str, ';');
1894 			if (next_str)
1895 				return snprintf(page, next_str - str + 1, "%s", str);
1896 			else
1897 				return sprintf(page, "%s", str);
1898 		}
1899 		str = strchr(str, ';');
1900 		str++;
1901 	}
1902 
1903 	return 0;
1904 }
1905 EXPORT_SYMBOL_GPL(events_hybrid_sysfs_show);
1906 
1907 EVENT_ATTR(cpu-cycles,			CPU_CYCLES		);
1908 EVENT_ATTR(instructions,		INSTRUCTIONS		);
1909 EVENT_ATTR(cache-references,		CACHE_REFERENCES	);
1910 EVENT_ATTR(cache-misses, 		CACHE_MISSES		);
1911 EVENT_ATTR(branch-instructions,		BRANCH_INSTRUCTIONS	);
1912 EVENT_ATTR(branch-misses,		BRANCH_MISSES		);
1913 EVENT_ATTR(bus-cycles,			BUS_CYCLES		);
1914 EVENT_ATTR(stalled-cycles-frontend,	STALLED_CYCLES_FRONTEND	);
1915 EVENT_ATTR(stalled-cycles-backend,	STALLED_CYCLES_BACKEND	);
1916 EVENT_ATTR(ref-cycles,			REF_CPU_CYCLES		);
1917 
1918 static struct attribute *empty_attrs;
1919 
1920 static struct attribute *events_attr[] = {
1921 	EVENT_PTR(CPU_CYCLES),
1922 	EVENT_PTR(INSTRUCTIONS),
1923 	EVENT_PTR(CACHE_REFERENCES),
1924 	EVENT_PTR(CACHE_MISSES),
1925 	EVENT_PTR(BRANCH_INSTRUCTIONS),
1926 	EVENT_PTR(BRANCH_MISSES),
1927 	EVENT_PTR(BUS_CYCLES),
1928 	EVENT_PTR(STALLED_CYCLES_FRONTEND),
1929 	EVENT_PTR(STALLED_CYCLES_BACKEND),
1930 	EVENT_PTR(REF_CPU_CYCLES),
1931 	NULL,
1932 };
1933 
1934 /*
1935  * Remove all undefined events (x86_pmu.event_map(id) == 0)
1936  * out of events_attr attributes.
1937  */
1938 static umode_t
is_visible(struct kobject * kobj,struct attribute * attr,int idx)1939 is_visible(struct kobject *kobj, struct attribute *attr, int idx)
1940 {
1941 	struct perf_pmu_events_attr *pmu_attr;
1942 
1943 	if (idx >= x86_pmu.max_events)
1944 		return 0;
1945 
1946 	pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr);
1947 	/* str trumps id */
1948 	return pmu_attr->event_str || x86_pmu.event_map(idx) ? attr->mode : 0;
1949 }
1950 
1951 static struct attribute_group x86_pmu_events_group __ro_after_init = {
1952 	.name = "events",
1953 	.attrs = events_attr,
1954 	.is_visible = is_visible,
1955 };
1956 
x86_event_sysfs_show(char * page,u64 config,u64 event)1957 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event)
1958 {
1959 	u64 umask  = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
1960 	u64 cmask  = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24;
1961 	bool edge  = (config & ARCH_PERFMON_EVENTSEL_EDGE);
1962 	bool pc    = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL);
1963 	bool any   = (config & ARCH_PERFMON_EVENTSEL_ANY);
1964 	bool inv   = (config & ARCH_PERFMON_EVENTSEL_INV);
1965 	ssize_t ret;
1966 
1967 	/*
1968 	* We have whole page size to spend and just little data
1969 	* to write, so we can safely use sprintf.
1970 	*/
1971 	ret = sprintf(page, "event=0x%02llx", event);
1972 
1973 	if (umask)
1974 		ret += sprintf(page + ret, ",umask=0x%02llx", umask);
1975 
1976 	if (edge)
1977 		ret += sprintf(page + ret, ",edge");
1978 
1979 	if (pc)
1980 		ret += sprintf(page + ret, ",pc");
1981 
1982 	if (any)
1983 		ret += sprintf(page + ret, ",any");
1984 
1985 	if (inv)
1986 		ret += sprintf(page + ret, ",inv");
1987 
1988 	if (cmask)
1989 		ret += sprintf(page + ret, ",cmask=0x%02llx", cmask);
1990 
1991 	ret += sprintf(page + ret, "\n");
1992 
1993 	return ret;
1994 }
1995 
1996 static struct attribute_group x86_pmu_attr_group;
1997 static struct attribute_group x86_pmu_caps_group;
1998 
x86_pmu_static_call_update(void)1999 static void x86_pmu_static_call_update(void)
2000 {
2001 	static_call_update(x86_pmu_handle_irq, x86_pmu.handle_irq);
2002 	static_call_update(x86_pmu_disable_all, x86_pmu.disable_all);
2003 	static_call_update(x86_pmu_enable_all, x86_pmu.enable_all);
2004 	static_call_update(x86_pmu_enable, x86_pmu.enable);
2005 	static_call_update(x86_pmu_disable, x86_pmu.disable);
2006 
2007 	static_call_update(x86_pmu_assign, x86_pmu.assign);
2008 
2009 	static_call_update(x86_pmu_add, x86_pmu.add);
2010 	static_call_update(x86_pmu_del, x86_pmu.del);
2011 	static_call_update(x86_pmu_read, x86_pmu.read);
2012 
2013 	static_call_update(x86_pmu_set_period, x86_pmu.set_period);
2014 	static_call_update(x86_pmu_update, x86_pmu.update);
2015 	static_call_update(x86_pmu_limit_period, x86_pmu.limit_period);
2016 
2017 	static_call_update(x86_pmu_schedule_events, x86_pmu.schedule_events);
2018 	static_call_update(x86_pmu_get_event_constraints, x86_pmu.get_event_constraints);
2019 	static_call_update(x86_pmu_put_event_constraints, x86_pmu.put_event_constraints);
2020 
2021 	static_call_update(x86_pmu_start_scheduling, x86_pmu.start_scheduling);
2022 	static_call_update(x86_pmu_commit_scheduling, x86_pmu.commit_scheduling);
2023 	static_call_update(x86_pmu_stop_scheduling, x86_pmu.stop_scheduling);
2024 
2025 	static_call_update(x86_pmu_sched_task, x86_pmu.sched_task);
2026 	static_call_update(x86_pmu_swap_task_ctx, x86_pmu.swap_task_ctx);
2027 
2028 	static_call_update(x86_pmu_drain_pebs, x86_pmu.drain_pebs);
2029 	static_call_update(x86_pmu_pebs_aliases, x86_pmu.pebs_aliases);
2030 
2031 	static_call_update(x86_pmu_guest_get_msrs, x86_pmu.guest_get_msrs);
2032 	static_call_update(x86_pmu_filter, x86_pmu.filter);
2033 }
2034 
_x86_pmu_read(struct perf_event * event)2035 static void _x86_pmu_read(struct perf_event *event)
2036 {
2037 	static_call(x86_pmu_update)(event);
2038 }
2039 
x86_pmu_show_pmu_cap(int num_counters,int num_counters_fixed,u64 intel_ctrl)2040 void x86_pmu_show_pmu_cap(int num_counters, int num_counters_fixed,
2041 			  u64 intel_ctrl)
2042 {
2043 	pr_info("... version:                %d\n",     x86_pmu.version);
2044 	pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
2045 	pr_info("... generic registers:      %d\n",     num_counters);
2046 	pr_info("... value mask:             %016Lx\n", x86_pmu.cntval_mask);
2047 	pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
2048 	pr_info("... fixed-purpose events:   %lu\n",
2049 			hweight64((((1ULL << num_counters_fixed) - 1)
2050 					<< INTEL_PMC_IDX_FIXED) & intel_ctrl));
2051 	pr_info("... event mask:             %016Lx\n", intel_ctrl);
2052 }
2053 
init_hw_perf_events(void)2054 static int __init init_hw_perf_events(void)
2055 {
2056 	struct x86_pmu_quirk *quirk;
2057 	int err;
2058 
2059 	pr_info("Performance Events: ");
2060 
2061 	switch (boot_cpu_data.x86_vendor) {
2062 	case X86_VENDOR_INTEL:
2063 		err = intel_pmu_init();
2064 		break;
2065 	case X86_VENDOR_AMD:
2066 		err = amd_pmu_init();
2067 		break;
2068 	case X86_VENDOR_HYGON:
2069 		err = amd_pmu_init();
2070 		x86_pmu.name = "HYGON";
2071 		break;
2072 	case X86_VENDOR_ZHAOXIN:
2073 	case X86_VENDOR_CENTAUR:
2074 		err = zhaoxin_pmu_init();
2075 		break;
2076 	default:
2077 		err = -ENOTSUPP;
2078 	}
2079 	if (err != 0) {
2080 		pr_cont("no PMU driver, software events only.\n");
2081 		err = 0;
2082 		goto out_bad_pmu;
2083 	}
2084 
2085 	pmu_check_apic();
2086 
2087 	/* sanity check that the hardware exists or is emulated */
2088 	if (!check_hw_exists(&pmu, x86_pmu.num_counters, x86_pmu.num_counters_fixed))
2089 		goto out_bad_pmu;
2090 
2091 	pr_cont("%s PMU driver.\n", x86_pmu.name);
2092 
2093 	x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */
2094 
2095 	for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
2096 		quirk->func();
2097 
2098 	if (!x86_pmu.intel_ctrl)
2099 		x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
2100 
2101 	perf_events_lapic_init();
2102 	register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
2103 
2104 	unconstrained = (struct event_constraint)
2105 		__EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
2106 				   0, x86_pmu.num_counters, 0, 0);
2107 
2108 	x86_pmu_format_group.attrs = x86_pmu.format_attrs;
2109 
2110 	if (!x86_pmu.events_sysfs_show)
2111 		x86_pmu_events_group.attrs = &empty_attrs;
2112 
2113 	pmu.attr_update = x86_pmu.attr_update;
2114 
2115 	if (!is_hybrid()) {
2116 		x86_pmu_show_pmu_cap(x86_pmu.num_counters,
2117 				     x86_pmu.num_counters_fixed,
2118 				     x86_pmu.intel_ctrl);
2119 	}
2120 
2121 	if (!x86_pmu.read)
2122 		x86_pmu.read = _x86_pmu_read;
2123 
2124 	if (!x86_pmu.guest_get_msrs)
2125 		x86_pmu.guest_get_msrs = (void *)&__static_call_return0;
2126 
2127 	if (!x86_pmu.set_period)
2128 		x86_pmu.set_period = x86_perf_event_set_period;
2129 
2130 	if (!x86_pmu.update)
2131 		x86_pmu.update = x86_perf_event_update;
2132 
2133 	x86_pmu_static_call_update();
2134 
2135 	/*
2136 	 * Install callbacks. Core will call them for each online
2137 	 * cpu.
2138 	 */
2139 	err = cpuhp_setup_state(CPUHP_PERF_X86_PREPARE, "perf/x86:prepare",
2140 				x86_pmu_prepare_cpu, x86_pmu_dead_cpu);
2141 	if (err)
2142 		return err;
2143 
2144 	err = cpuhp_setup_state(CPUHP_AP_PERF_X86_STARTING,
2145 				"perf/x86:starting", x86_pmu_starting_cpu,
2146 				x86_pmu_dying_cpu);
2147 	if (err)
2148 		goto out;
2149 
2150 	err = cpuhp_setup_state(CPUHP_AP_PERF_X86_ONLINE, "perf/x86:online",
2151 				x86_pmu_online_cpu, NULL);
2152 	if (err)
2153 		goto out1;
2154 
2155 	if (!is_hybrid()) {
2156 		err = perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
2157 		if (err)
2158 			goto out2;
2159 	} else {
2160 		struct x86_hybrid_pmu *hybrid_pmu;
2161 		int i, j;
2162 
2163 		for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) {
2164 			hybrid_pmu = &x86_pmu.hybrid_pmu[i];
2165 
2166 			hybrid_pmu->pmu = pmu;
2167 			hybrid_pmu->pmu.type = -1;
2168 			hybrid_pmu->pmu.attr_update = x86_pmu.attr_update;
2169 			hybrid_pmu->pmu.capabilities |= PERF_PMU_CAP_EXTENDED_HW_TYPE;
2170 
2171 			err = perf_pmu_register(&hybrid_pmu->pmu, hybrid_pmu->name,
2172 						(hybrid_pmu->cpu_type == hybrid_big) ? PERF_TYPE_RAW : -1);
2173 			if (err)
2174 				break;
2175 		}
2176 
2177 		if (i < x86_pmu.num_hybrid_pmus) {
2178 			for (j = 0; j < i; j++)
2179 				perf_pmu_unregister(&x86_pmu.hybrid_pmu[j].pmu);
2180 			pr_warn("Failed to register hybrid PMUs\n");
2181 			kfree(x86_pmu.hybrid_pmu);
2182 			x86_pmu.hybrid_pmu = NULL;
2183 			x86_pmu.num_hybrid_pmus = 0;
2184 			goto out2;
2185 		}
2186 	}
2187 
2188 	return 0;
2189 
2190 out2:
2191 	cpuhp_remove_state(CPUHP_AP_PERF_X86_ONLINE);
2192 out1:
2193 	cpuhp_remove_state(CPUHP_AP_PERF_X86_STARTING);
2194 out:
2195 	cpuhp_remove_state(CPUHP_PERF_X86_PREPARE);
2196 out_bad_pmu:
2197 	memset(&x86_pmu, 0, sizeof(x86_pmu));
2198 	return err;
2199 }
2200 early_initcall(init_hw_perf_events);
2201 
x86_pmu_read(struct perf_event * event)2202 static void x86_pmu_read(struct perf_event *event)
2203 {
2204 	static_call(x86_pmu_read)(event);
2205 }
2206 
2207 /*
2208  * Start group events scheduling transaction
2209  * Set the flag to make pmu::enable() not perform the
2210  * schedulability test, it will be performed at commit time
2211  *
2212  * We only support PERF_PMU_TXN_ADD transactions. Save the
2213  * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
2214  * transactions.
2215  */
x86_pmu_start_txn(struct pmu * pmu,unsigned int txn_flags)2216 static void x86_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags)
2217 {
2218 	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2219 
2220 	WARN_ON_ONCE(cpuc->txn_flags);		/* txn already in flight */
2221 
2222 	cpuc->txn_flags = txn_flags;
2223 	if (txn_flags & ~PERF_PMU_TXN_ADD)
2224 		return;
2225 
2226 	perf_pmu_disable(pmu);
2227 	__this_cpu_write(cpu_hw_events.n_txn, 0);
2228 	__this_cpu_write(cpu_hw_events.n_txn_pair, 0);
2229 	__this_cpu_write(cpu_hw_events.n_txn_metric, 0);
2230 }
2231 
2232 /*
2233  * Stop group events scheduling transaction
2234  * Clear the flag and pmu::enable() will perform the
2235  * schedulability test.
2236  */
x86_pmu_cancel_txn(struct pmu * pmu)2237 static void x86_pmu_cancel_txn(struct pmu *pmu)
2238 {
2239 	unsigned int txn_flags;
2240 	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2241 
2242 	WARN_ON_ONCE(!cpuc->txn_flags);	/* no txn in flight */
2243 
2244 	txn_flags = cpuc->txn_flags;
2245 	cpuc->txn_flags = 0;
2246 	if (txn_flags & ~PERF_PMU_TXN_ADD)
2247 		return;
2248 
2249 	/*
2250 	 * Truncate collected array by the number of events added in this
2251 	 * transaction. See x86_pmu_add() and x86_pmu_*_txn().
2252 	 */
2253 	__this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
2254 	__this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
2255 	__this_cpu_sub(cpu_hw_events.n_pair, __this_cpu_read(cpu_hw_events.n_txn_pair));
2256 	__this_cpu_sub(cpu_hw_events.n_metric, __this_cpu_read(cpu_hw_events.n_txn_metric));
2257 	perf_pmu_enable(pmu);
2258 }
2259 
2260 /*
2261  * Commit group events scheduling transaction
2262  * Perform the group schedulability test as a whole
2263  * Return 0 if success
2264  *
2265  * Does not cancel the transaction on failure; expects the caller to do this.
2266  */
x86_pmu_commit_txn(struct pmu * pmu)2267 static int x86_pmu_commit_txn(struct pmu *pmu)
2268 {
2269 	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2270 	int assign[X86_PMC_IDX_MAX];
2271 	int n, ret;
2272 
2273 	WARN_ON_ONCE(!cpuc->txn_flags);	/* no txn in flight */
2274 
2275 	if (cpuc->txn_flags & ~PERF_PMU_TXN_ADD) {
2276 		cpuc->txn_flags = 0;
2277 		return 0;
2278 	}
2279 
2280 	n = cpuc->n_events;
2281 
2282 	if (!x86_pmu_initialized())
2283 		return -EAGAIN;
2284 
2285 	ret = static_call(x86_pmu_schedule_events)(cpuc, n, assign);
2286 	if (ret)
2287 		return ret;
2288 
2289 	/*
2290 	 * copy new assignment, now we know it is possible
2291 	 * will be used by hw_perf_enable()
2292 	 */
2293 	memcpy(cpuc->assign, assign, n*sizeof(int));
2294 
2295 	cpuc->txn_flags = 0;
2296 	perf_pmu_enable(pmu);
2297 	return 0;
2298 }
2299 /*
2300  * a fake_cpuc is used to validate event groups. Due to
2301  * the extra reg logic, we need to also allocate a fake
2302  * per_core and per_cpu structure. Otherwise, group events
2303  * using extra reg may conflict without the kernel being
2304  * able to catch this when the last event gets added to
2305  * the group.
2306  */
free_fake_cpuc(struct cpu_hw_events * cpuc)2307 static void free_fake_cpuc(struct cpu_hw_events *cpuc)
2308 {
2309 	intel_cpuc_finish(cpuc);
2310 	kfree(cpuc);
2311 }
2312 
allocate_fake_cpuc(struct pmu * event_pmu)2313 static struct cpu_hw_events *allocate_fake_cpuc(struct pmu *event_pmu)
2314 {
2315 	struct cpu_hw_events *cpuc;
2316 	int cpu;
2317 
2318 	cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
2319 	if (!cpuc)
2320 		return ERR_PTR(-ENOMEM);
2321 	cpuc->is_fake = 1;
2322 
2323 	if (is_hybrid()) {
2324 		struct x86_hybrid_pmu *h_pmu;
2325 
2326 		h_pmu = hybrid_pmu(event_pmu);
2327 		if (cpumask_empty(&h_pmu->supported_cpus))
2328 			goto error;
2329 		cpu = cpumask_first(&h_pmu->supported_cpus);
2330 	} else
2331 		cpu = raw_smp_processor_id();
2332 	cpuc->pmu = event_pmu;
2333 
2334 	if (intel_cpuc_prepare(cpuc, cpu))
2335 		goto error;
2336 
2337 	return cpuc;
2338 error:
2339 	free_fake_cpuc(cpuc);
2340 	return ERR_PTR(-ENOMEM);
2341 }
2342 
2343 /*
2344  * validate that we can schedule this event
2345  */
validate_event(struct perf_event * event)2346 static int validate_event(struct perf_event *event)
2347 {
2348 	struct cpu_hw_events *fake_cpuc;
2349 	struct event_constraint *c;
2350 	int ret = 0;
2351 
2352 	fake_cpuc = allocate_fake_cpuc(event->pmu);
2353 	if (IS_ERR(fake_cpuc))
2354 		return PTR_ERR(fake_cpuc);
2355 
2356 	c = x86_pmu.get_event_constraints(fake_cpuc, 0, event);
2357 
2358 	if (!c || !c->weight)
2359 		ret = -EINVAL;
2360 
2361 	if (x86_pmu.put_event_constraints)
2362 		x86_pmu.put_event_constraints(fake_cpuc, event);
2363 
2364 	free_fake_cpuc(fake_cpuc);
2365 
2366 	return ret;
2367 }
2368 
2369 /*
2370  * validate a single event group
2371  *
2372  * validation include:
2373  *	- check events are compatible which each other
2374  *	- events do not compete for the same counter
2375  *	- number of events <= number of counters
2376  *
2377  * validation ensures the group can be loaded onto the
2378  * PMU if it was the only group available.
2379  */
validate_group(struct perf_event * event)2380 static int validate_group(struct perf_event *event)
2381 {
2382 	struct perf_event *leader = event->group_leader;
2383 	struct cpu_hw_events *fake_cpuc;
2384 	int ret = -EINVAL, n;
2385 
2386 	/*
2387 	 * Reject events from different hybrid PMUs.
2388 	 */
2389 	if (is_hybrid()) {
2390 		struct perf_event *sibling;
2391 		struct pmu *pmu = NULL;
2392 
2393 		if (is_x86_event(leader))
2394 			pmu = leader->pmu;
2395 
2396 		for_each_sibling_event(sibling, leader) {
2397 			if (!is_x86_event(sibling))
2398 				continue;
2399 			if (!pmu)
2400 				pmu = sibling->pmu;
2401 			else if (pmu != sibling->pmu)
2402 				return ret;
2403 		}
2404 	}
2405 
2406 	fake_cpuc = allocate_fake_cpuc(event->pmu);
2407 	if (IS_ERR(fake_cpuc))
2408 		return PTR_ERR(fake_cpuc);
2409 	/*
2410 	 * the event is not yet connected with its
2411 	 * siblings therefore we must first collect
2412 	 * existing siblings, then add the new event
2413 	 * before we can simulate the scheduling
2414 	 */
2415 	n = collect_events(fake_cpuc, leader, true);
2416 	if (n < 0)
2417 		goto out;
2418 
2419 	fake_cpuc->n_events = n;
2420 	n = collect_events(fake_cpuc, event, false);
2421 	if (n < 0)
2422 		goto out;
2423 
2424 	fake_cpuc->n_events = 0;
2425 	ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
2426 
2427 out:
2428 	free_fake_cpuc(fake_cpuc);
2429 	return ret;
2430 }
2431 
x86_pmu_event_init(struct perf_event * event)2432 static int x86_pmu_event_init(struct perf_event *event)
2433 {
2434 	struct x86_hybrid_pmu *pmu = NULL;
2435 	int err;
2436 
2437 	if ((event->attr.type != event->pmu->type) &&
2438 	    (event->attr.type != PERF_TYPE_HARDWARE) &&
2439 	    (event->attr.type != PERF_TYPE_HW_CACHE))
2440 		return -ENOENT;
2441 
2442 	if (is_hybrid() && (event->cpu != -1)) {
2443 		pmu = hybrid_pmu(event->pmu);
2444 		if (!cpumask_test_cpu(event->cpu, &pmu->supported_cpus))
2445 			return -ENOENT;
2446 	}
2447 
2448 	err = __x86_pmu_event_init(event);
2449 	if (!err) {
2450 		if (event->group_leader != event)
2451 			err = validate_group(event);
2452 		else
2453 			err = validate_event(event);
2454 	}
2455 	if (err) {
2456 		if (event->destroy)
2457 			event->destroy(event);
2458 		event->destroy = NULL;
2459 	}
2460 
2461 	if (READ_ONCE(x86_pmu.attr_rdpmc) &&
2462 	    !(event->hw.flags & PERF_X86_EVENT_LARGE_PEBS))
2463 		event->hw.flags |= PERF_EVENT_FLAG_USER_READ_CNT;
2464 
2465 	return err;
2466 }
2467 
perf_clear_dirty_counters(void)2468 void perf_clear_dirty_counters(void)
2469 {
2470 	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2471 	int i;
2472 
2473 	 /* Don't need to clear the assigned counter. */
2474 	for (i = 0; i < cpuc->n_events; i++)
2475 		__clear_bit(cpuc->assign[i], cpuc->dirty);
2476 
2477 	if (bitmap_empty(cpuc->dirty, X86_PMC_IDX_MAX))
2478 		return;
2479 
2480 	for_each_set_bit(i, cpuc->dirty, X86_PMC_IDX_MAX) {
2481 		if (i >= INTEL_PMC_IDX_FIXED) {
2482 			/* Metrics and fake events don't have corresponding HW counters. */
2483 			if ((i - INTEL_PMC_IDX_FIXED) >= hybrid(cpuc->pmu, num_counters_fixed))
2484 				continue;
2485 
2486 			wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + (i - INTEL_PMC_IDX_FIXED), 0);
2487 		} else {
2488 			wrmsrl(x86_pmu_event_addr(i), 0);
2489 		}
2490 	}
2491 
2492 	bitmap_zero(cpuc->dirty, X86_PMC_IDX_MAX);
2493 }
2494 
x86_pmu_event_mapped(struct perf_event * event,struct mm_struct * mm)2495 static void x86_pmu_event_mapped(struct perf_event *event, struct mm_struct *mm)
2496 {
2497 	if (!(event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT))
2498 		return;
2499 
2500 	/*
2501 	 * This function relies on not being called concurrently in two
2502 	 * tasks in the same mm.  Otherwise one task could observe
2503 	 * perf_rdpmc_allowed > 1 and return all the way back to
2504 	 * userspace with CR4.PCE clear while another task is still
2505 	 * doing on_each_cpu_mask() to propagate CR4.PCE.
2506 	 *
2507 	 * For now, this can't happen because all callers hold mmap_lock
2508 	 * for write.  If this changes, we'll need a different solution.
2509 	 */
2510 	mmap_assert_write_locked(mm);
2511 
2512 	if (atomic_inc_return(&mm->context.perf_rdpmc_allowed) == 1)
2513 		on_each_cpu_mask(mm_cpumask(mm), cr4_update_pce, NULL, 1);
2514 }
2515 
x86_pmu_event_unmapped(struct perf_event * event,struct mm_struct * mm)2516 static void x86_pmu_event_unmapped(struct perf_event *event, struct mm_struct *mm)
2517 {
2518 	if (!(event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT))
2519 		return;
2520 
2521 	if (atomic_dec_and_test(&mm->context.perf_rdpmc_allowed))
2522 		on_each_cpu_mask(mm_cpumask(mm), cr4_update_pce, NULL, 1);
2523 }
2524 
x86_pmu_event_idx(struct perf_event * event)2525 static int x86_pmu_event_idx(struct perf_event *event)
2526 {
2527 	struct hw_perf_event *hwc = &event->hw;
2528 
2529 	if (!(hwc->flags & PERF_EVENT_FLAG_USER_READ_CNT))
2530 		return 0;
2531 
2532 	if (is_metric_idx(hwc->idx))
2533 		return INTEL_PMC_FIXED_RDPMC_METRICS + 1;
2534 	else
2535 		return hwc->event_base_rdpmc + 1;
2536 }
2537 
get_attr_rdpmc(struct device * cdev,struct device_attribute * attr,char * buf)2538 static ssize_t get_attr_rdpmc(struct device *cdev,
2539 			      struct device_attribute *attr,
2540 			      char *buf)
2541 {
2542 	return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc);
2543 }
2544 
set_attr_rdpmc(struct device * cdev,struct device_attribute * attr,const char * buf,size_t count)2545 static ssize_t set_attr_rdpmc(struct device *cdev,
2546 			      struct device_attribute *attr,
2547 			      const char *buf, size_t count)
2548 {
2549 	unsigned long val;
2550 	ssize_t ret;
2551 
2552 	ret = kstrtoul(buf, 0, &val);
2553 	if (ret)
2554 		return ret;
2555 
2556 	if (val > 2)
2557 		return -EINVAL;
2558 
2559 	if (x86_pmu.attr_rdpmc_broken)
2560 		return -ENOTSUPP;
2561 
2562 	if (val != x86_pmu.attr_rdpmc) {
2563 		/*
2564 		 * Changing into or out of never available or always available,
2565 		 * aka perf-event-bypassing mode. This path is extremely slow,
2566 		 * but only root can trigger it, so it's okay.
2567 		 */
2568 		if (val == 0)
2569 			static_branch_inc(&rdpmc_never_available_key);
2570 		else if (x86_pmu.attr_rdpmc == 0)
2571 			static_branch_dec(&rdpmc_never_available_key);
2572 
2573 		if (val == 2)
2574 			static_branch_inc(&rdpmc_always_available_key);
2575 		else if (x86_pmu.attr_rdpmc == 2)
2576 			static_branch_dec(&rdpmc_always_available_key);
2577 
2578 		on_each_cpu(cr4_update_pce, NULL, 1);
2579 		x86_pmu.attr_rdpmc = val;
2580 	}
2581 
2582 	return count;
2583 }
2584 
2585 static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc);
2586 
2587 static struct attribute *x86_pmu_attrs[] = {
2588 	&dev_attr_rdpmc.attr,
2589 	NULL,
2590 };
2591 
2592 static struct attribute_group x86_pmu_attr_group __ro_after_init = {
2593 	.attrs = x86_pmu_attrs,
2594 };
2595 
max_precise_show(struct device * cdev,struct device_attribute * attr,char * buf)2596 static ssize_t max_precise_show(struct device *cdev,
2597 				  struct device_attribute *attr,
2598 				  char *buf)
2599 {
2600 	return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu_max_precise());
2601 }
2602 
2603 static DEVICE_ATTR_RO(max_precise);
2604 
2605 static struct attribute *x86_pmu_caps_attrs[] = {
2606 	&dev_attr_max_precise.attr,
2607 	NULL
2608 };
2609 
2610 static struct attribute_group x86_pmu_caps_group __ro_after_init = {
2611 	.name = "caps",
2612 	.attrs = x86_pmu_caps_attrs,
2613 };
2614 
2615 static const struct attribute_group *x86_pmu_attr_groups[] = {
2616 	&x86_pmu_attr_group,
2617 	&x86_pmu_format_group,
2618 	&x86_pmu_events_group,
2619 	&x86_pmu_caps_group,
2620 	NULL,
2621 };
2622 
x86_pmu_sched_task(struct perf_event_pmu_context * pmu_ctx,bool sched_in)2623 static void x86_pmu_sched_task(struct perf_event_pmu_context *pmu_ctx, bool sched_in)
2624 {
2625 	static_call_cond(x86_pmu_sched_task)(pmu_ctx, sched_in);
2626 }
2627 
x86_pmu_swap_task_ctx(struct perf_event_pmu_context * prev_epc,struct perf_event_pmu_context * next_epc)2628 static void x86_pmu_swap_task_ctx(struct perf_event_pmu_context *prev_epc,
2629 				  struct perf_event_pmu_context *next_epc)
2630 {
2631 	static_call_cond(x86_pmu_swap_task_ctx)(prev_epc, next_epc);
2632 }
2633 
perf_check_microcode(void)2634 void perf_check_microcode(void)
2635 {
2636 	if (x86_pmu.check_microcode)
2637 		x86_pmu.check_microcode();
2638 }
2639 
x86_pmu_check_period(struct perf_event * event,u64 value)2640 static int x86_pmu_check_period(struct perf_event *event, u64 value)
2641 {
2642 	if (x86_pmu.check_period && x86_pmu.check_period(event, value))
2643 		return -EINVAL;
2644 
2645 	if (value && x86_pmu.limit_period) {
2646 		s64 left = value;
2647 		x86_pmu.limit_period(event, &left);
2648 		if (left > value)
2649 			return -EINVAL;
2650 	}
2651 
2652 	return 0;
2653 }
2654 
x86_pmu_aux_output_match(struct perf_event * event)2655 static int x86_pmu_aux_output_match(struct perf_event *event)
2656 {
2657 	if (!(pmu.capabilities & PERF_PMU_CAP_AUX_OUTPUT))
2658 		return 0;
2659 
2660 	if (x86_pmu.aux_output_match)
2661 		return x86_pmu.aux_output_match(event);
2662 
2663 	return 0;
2664 }
2665 
x86_pmu_filter(struct pmu * pmu,int cpu)2666 static bool x86_pmu_filter(struct pmu *pmu, int cpu)
2667 {
2668 	bool ret = false;
2669 
2670 	static_call_cond(x86_pmu_filter)(pmu, cpu, &ret);
2671 
2672 	return ret;
2673 }
2674 
2675 static struct pmu pmu = {
2676 	.pmu_enable		= x86_pmu_enable,
2677 	.pmu_disable		= x86_pmu_disable,
2678 
2679 	.attr_groups		= x86_pmu_attr_groups,
2680 
2681 	.event_init		= x86_pmu_event_init,
2682 
2683 	.event_mapped		= x86_pmu_event_mapped,
2684 	.event_unmapped		= x86_pmu_event_unmapped,
2685 
2686 	.add			= x86_pmu_add,
2687 	.del			= x86_pmu_del,
2688 	.start			= x86_pmu_start,
2689 	.stop			= x86_pmu_stop,
2690 	.read			= x86_pmu_read,
2691 
2692 	.start_txn		= x86_pmu_start_txn,
2693 	.cancel_txn		= x86_pmu_cancel_txn,
2694 	.commit_txn		= x86_pmu_commit_txn,
2695 
2696 	.event_idx		= x86_pmu_event_idx,
2697 	.sched_task		= x86_pmu_sched_task,
2698 	.swap_task_ctx		= x86_pmu_swap_task_ctx,
2699 	.check_period		= x86_pmu_check_period,
2700 
2701 	.aux_output_match	= x86_pmu_aux_output_match,
2702 
2703 	.filter			= x86_pmu_filter,
2704 };
2705 
arch_perf_update_userpage(struct perf_event * event,struct perf_event_mmap_page * userpg,u64 now)2706 void arch_perf_update_userpage(struct perf_event *event,
2707 			       struct perf_event_mmap_page *userpg, u64 now)
2708 {
2709 	struct cyc2ns_data data;
2710 	u64 offset;
2711 
2712 	userpg->cap_user_time = 0;
2713 	userpg->cap_user_time_zero = 0;
2714 	userpg->cap_user_rdpmc =
2715 		!!(event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT);
2716 	userpg->pmc_width = x86_pmu.cntval_bits;
2717 
2718 	if (!using_native_sched_clock() || !sched_clock_stable())
2719 		return;
2720 
2721 	cyc2ns_read_begin(&data);
2722 
2723 	offset = data.cyc2ns_offset + __sched_clock_offset;
2724 
2725 	/*
2726 	 * Internal timekeeping for enabled/running/stopped times
2727 	 * is always in the local_clock domain.
2728 	 */
2729 	userpg->cap_user_time = 1;
2730 	userpg->time_mult = data.cyc2ns_mul;
2731 	userpg->time_shift = data.cyc2ns_shift;
2732 	userpg->time_offset = offset - now;
2733 
2734 	/*
2735 	 * cap_user_time_zero doesn't make sense when we're using a different
2736 	 * time base for the records.
2737 	 */
2738 	if (!event->attr.use_clockid) {
2739 		userpg->cap_user_time_zero = 1;
2740 		userpg->time_zero = offset;
2741 	}
2742 
2743 	cyc2ns_read_end();
2744 }
2745 
2746 /*
2747  * Determine whether the regs were taken from an irq/exception handler rather
2748  * than from perf_arch_fetch_caller_regs().
2749  */
perf_hw_regs(struct pt_regs * regs)2750 static bool perf_hw_regs(struct pt_regs *regs)
2751 {
2752 	return regs->flags & X86_EFLAGS_FIXED;
2753 }
2754 
2755 void
perf_callchain_kernel(struct perf_callchain_entry_ctx * entry,struct pt_regs * regs)2756 perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
2757 {
2758 	struct unwind_state state;
2759 	unsigned long addr;
2760 
2761 	if (perf_guest_state()) {
2762 		/* TODO: We don't support guest os callchain now */
2763 		return;
2764 	}
2765 
2766 	if (perf_callchain_store(entry, regs->ip))
2767 		return;
2768 
2769 	if (perf_hw_regs(regs))
2770 		unwind_start(&state, current, regs, NULL);
2771 	else
2772 		unwind_start(&state, current, NULL, (void *)regs->sp);
2773 
2774 	for (; !unwind_done(&state); unwind_next_frame(&state)) {
2775 		addr = unwind_get_return_address(&state);
2776 		if (!addr || perf_callchain_store(entry, addr))
2777 			return;
2778 	}
2779 }
2780 
2781 static inline int
valid_user_frame(const void __user * fp,unsigned long size)2782 valid_user_frame(const void __user *fp, unsigned long size)
2783 {
2784 	return __access_ok(fp, size);
2785 }
2786 
get_segment_base(unsigned int segment)2787 static unsigned long get_segment_base(unsigned int segment)
2788 {
2789 	struct desc_struct *desc;
2790 	unsigned int idx = segment >> 3;
2791 
2792 	if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2793 #ifdef CONFIG_MODIFY_LDT_SYSCALL
2794 		struct ldt_struct *ldt;
2795 
2796 		/* IRQs are off, so this synchronizes with smp_store_release */
2797 		ldt = READ_ONCE(current->active_mm->context.ldt);
2798 		if (!ldt || idx >= ldt->nr_entries)
2799 			return 0;
2800 
2801 		desc = &ldt->entries[idx];
2802 #else
2803 		return 0;
2804 #endif
2805 	} else {
2806 		if (idx >= GDT_ENTRIES)
2807 			return 0;
2808 
2809 		desc = raw_cpu_ptr(gdt_page.gdt) + idx;
2810 	}
2811 
2812 	return get_desc_base(desc);
2813 }
2814 
2815 #ifdef CONFIG_IA32_EMULATION
2816 
2817 #include <linux/compat.h>
2818 
2819 static inline int
perf_callchain_user32(struct pt_regs * regs,struct perf_callchain_entry_ctx * entry)2820 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry)
2821 {
2822 	/* 32-bit process in 64-bit kernel. */
2823 	unsigned long ss_base, cs_base;
2824 	struct stack_frame_ia32 frame;
2825 	const struct stack_frame_ia32 __user *fp;
2826 
2827 	if (user_64bit_mode(regs))
2828 		return 0;
2829 
2830 	cs_base = get_segment_base(regs->cs);
2831 	ss_base = get_segment_base(regs->ss);
2832 
2833 	fp = compat_ptr(ss_base + regs->bp);
2834 	pagefault_disable();
2835 	while (entry->nr < entry->max_stack) {
2836 		if (!valid_user_frame(fp, sizeof(frame)))
2837 			break;
2838 
2839 		if (__get_user(frame.next_frame, &fp->next_frame))
2840 			break;
2841 		if (__get_user(frame.return_address, &fp->return_address))
2842 			break;
2843 
2844 		perf_callchain_store(entry, cs_base + frame.return_address);
2845 		fp = compat_ptr(ss_base + frame.next_frame);
2846 	}
2847 	pagefault_enable();
2848 	return 1;
2849 }
2850 #else
2851 static inline int
perf_callchain_user32(struct pt_regs * regs,struct perf_callchain_entry_ctx * entry)2852 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry)
2853 {
2854     return 0;
2855 }
2856 #endif
2857 
2858 void
perf_callchain_user(struct perf_callchain_entry_ctx * entry,struct pt_regs * regs)2859 perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
2860 {
2861 	struct stack_frame frame;
2862 	const struct stack_frame __user *fp;
2863 
2864 	if (perf_guest_state()) {
2865 		/* TODO: We don't support guest os callchain now */
2866 		return;
2867 	}
2868 
2869 	/*
2870 	 * We don't know what to do with VM86 stacks.. ignore them for now.
2871 	 */
2872 	if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))
2873 		return;
2874 
2875 	fp = (void __user *)regs->bp;
2876 
2877 	perf_callchain_store(entry, regs->ip);
2878 
2879 	if (!nmi_uaccess_okay())
2880 		return;
2881 
2882 	if (perf_callchain_user32(regs, entry))
2883 		return;
2884 
2885 	pagefault_disable();
2886 	while (entry->nr < entry->max_stack) {
2887 		if (!valid_user_frame(fp, sizeof(frame)))
2888 			break;
2889 
2890 		if (__get_user(frame.next_frame, &fp->next_frame))
2891 			break;
2892 		if (__get_user(frame.return_address, &fp->return_address))
2893 			break;
2894 
2895 		perf_callchain_store(entry, frame.return_address);
2896 		fp = (void __user *)frame.next_frame;
2897 	}
2898 	pagefault_enable();
2899 }
2900 
2901 /*
2902  * Deal with code segment offsets for the various execution modes:
2903  *
2904  *   VM86 - the good olde 16 bit days, where the linear address is
2905  *          20 bits and we use regs->ip + 0x10 * regs->cs.
2906  *
2907  *   IA32 - Where we need to look at GDT/LDT segment descriptor tables
2908  *          to figure out what the 32bit base address is.
2909  *
2910  *    X32 - has TIF_X32 set, but is running in x86_64
2911  *
2912  * X86_64 - CS,DS,SS,ES are all zero based.
2913  */
code_segment_base(struct pt_regs * regs)2914 static unsigned long code_segment_base(struct pt_regs *regs)
2915 {
2916 	/*
2917 	 * For IA32 we look at the GDT/LDT segment base to convert the
2918 	 * effective IP to a linear address.
2919 	 */
2920 
2921 #ifdef CONFIG_X86_32
2922 	/*
2923 	 * If we are in VM86 mode, add the segment offset to convert to a
2924 	 * linear address.
2925 	 */
2926 	if (regs->flags & X86_VM_MASK)
2927 		return 0x10 * regs->cs;
2928 
2929 	if (user_mode(regs) && regs->cs != __USER_CS)
2930 		return get_segment_base(regs->cs);
2931 #else
2932 	if (user_mode(regs) && !user_64bit_mode(regs) &&
2933 	    regs->cs != __USER32_CS)
2934 		return get_segment_base(regs->cs);
2935 #endif
2936 	return 0;
2937 }
2938 
perf_instruction_pointer(struct pt_regs * regs)2939 unsigned long perf_instruction_pointer(struct pt_regs *regs)
2940 {
2941 	if (perf_guest_state())
2942 		return perf_guest_get_ip();
2943 
2944 	return regs->ip + code_segment_base(regs);
2945 }
2946 
perf_misc_flags(struct pt_regs * regs)2947 unsigned long perf_misc_flags(struct pt_regs *regs)
2948 {
2949 	unsigned int guest_state = perf_guest_state();
2950 	int misc = 0;
2951 
2952 	if (guest_state) {
2953 		if (guest_state & PERF_GUEST_USER)
2954 			misc |= PERF_RECORD_MISC_GUEST_USER;
2955 		else
2956 			misc |= PERF_RECORD_MISC_GUEST_KERNEL;
2957 	} else {
2958 		if (user_mode(regs))
2959 			misc |= PERF_RECORD_MISC_USER;
2960 		else
2961 			misc |= PERF_RECORD_MISC_KERNEL;
2962 	}
2963 
2964 	if (regs->flags & PERF_EFLAGS_EXACT)
2965 		misc |= PERF_RECORD_MISC_EXACT_IP;
2966 
2967 	return misc;
2968 }
2969 
perf_get_x86_pmu_capability(struct x86_pmu_capability * cap)2970 void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
2971 {
2972 	/* This API doesn't currently support enumerating hybrid PMUs. */
2973 	if (WARN_ON_ONCE(cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) ||
2974 	    !x86_pmu_initialized()) {
2975 		memset(cap, 0, sizeof(*cap));
2976 		return;
2977 	}
2978 
2979 	/*
2980 	 * Note, hybrid CPU models get tracked as having hybrid PMUs even when
2981 	 * all E-cores are disabled via BIOS.  When E-cores are disabled, the
2982 	 * base PMU holds the correct number of counters for P-cores.
2983 	 */
2984 	cap->version		= x86_pmu.version;
2985 	cap->num_counters_gp	= x86_pmu.num_counters;
2986 	cap->num_counters_fixed	= x86_pmu.num_counters_fixed;
2987 	cap->bit_width_gp	= x86_pmu.cntval_bits;
2988 	cap->bit_width_fixed	= x86_pmu.cntval_bits;
2989 	cap->events_mask	= (unsigned int)x86_pmu.events_maskl;
2990 	cap->events_mask_len	= x86_pmu.events_mask_len;
2991 	cap->pebs_ept		= x86_pmu.pebs_ept;
2992 }
2993 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);
2994 
perf_get_hw_event_config(int hw_event)2995 u64 perf_get_hw_event_config(int hw_event)
2996 {
2997 	int max = x86_pmu.max_events;
2998 
2999 	if (hw_event < max)
3000 		return x86_pmu.event_map(array_index_nospec(hw_event, max));
3001 
3002 	return 0;
3003 }
3004 EXPORT_SYMBOL_GPL(perf_get_hw_event_config);
3005