1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3  * Copyright (c) 2018-2020 The Linux Foundation. All rights reserved.
4  * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
5  */
6 
7 #include <linux/types.h>
8 #include <linux/bitops.h>
9 #include <linux/bitfield.h>
10 
11 #include "core.h"
12 #include "ce.h"
13 #include "hif.h"
14 #include "hal.h"
15 #include "hw.h"
16 
17 /* Map from pdev index to hw mac index */
ath11k_hw_ipq8074_mac_from_pdev_id(int pdev_idx)18 static u8 ath11k_hw_ipq8074_mac_from_pdev_id(int pdev_idx)
19 {
20 	switch (pdev_idx) {
21 	case 0:
22 		return 0;
23 	case 1:
24 		return 2;
25 	case 2:
26 		return 1;
27 	default:
28 		return ATH11K_INVALID_HW_MAC_ID;
29 	}
30 }
31 
ath11k_hw_ipq6018_mac_from_pdev_id(int pdev_idx)32 static u8 ath11k_hw_ipq6018_mac_from_pdev_id(int pdev_idx)
33 {
34 	return pdev_idx;
35 }
36 
ath11k_hw_ipq8074_tx_mesh_enable(struct ath11k_base * ab,struct hal_tcl_data_cmd * tcl_cmd)37 static void ath11k_hw_ipq8074_tx_mesh_enable(struct ath11k_base *ab,
38 					     struct hal_tcl_data_cmd *tcl_cmd)
39 {
40 	tcl_cmd->info2 |= FIELD_PREP(HAL_IPQ8074_TCL_DATA_CMD_INFO2_MESH_ENABLE,
41 				     true);
42 }
43 
ath11k_hw_qcn9074_tx_mesh_enable(struct ath11k_base * ab,struct hal_tcl_data_cmd * tcl_cmd)44 static void ath11k_hw_qcn9074_tx_mesh_enable(struct ath11k_base *ab,
45 					     struct hal_tcl_data_cmd *tcl_cmd)
46 {
47 	tcl_cmd->info3 |= FIELD_PREP(HAL_QCN9074_TCL_DATA_CMD_INFO3_MESH_ENABLE,
48 				     true);
49 }
50 
ath11k_hw_wcn6855_tx_mesh_enable(struct ath11k_base * ab,struct hal_tcl_data_cmd * tcl_cmd)51 static void ath11k_hw_wcn6855_tx_mesh_enable(struct ath11k_base *ab,
52 					     struct hal_tcl_data_cmd *tcl_cmd)
53 {
54 	tcl_cmd->info3 |= FIELD_PREP(HAL_QCN9074_TCL_DATA_CMD_INFO3_MESH_ENABLE,
55 				     true);
56 }
57 
ath11k_init_wmi_config_qca6390(struct ath11k_base * ab,struct target_resource_config * config)58 static void ath11k_init_wmi_config_qca6390(struct ath11k_base *ab,
59 					   struct target_resource_config *config)
60 {
61 	config->num_vdevs = 4;
62 	config->num_peers = 16;
63 	config->num_tids = 32;
64 
65 	config->num_offload_peers = 3;
66 	config->num_offload_reorder_buffs = 3;
67 	config->num_peer_keys = TARGET_NUM_PEER_KEYS;
68 	config->ast_skid_limit = TARGET_AST_SKID_LIMIT;
69 	config->tx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1;
70 	config->rx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1;
71 	config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI;
72 	config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI;
73 	config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI;
74 	config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI;
75 	config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI;
76 	config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS;
77 	config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV;
78 	config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV;
79 	config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES;
80 	config->num_mcast_groups = 0;
81 	config->num_mcast_table_elems = 0;
82 	config->mcast2ucast_mode = 0;
83 	config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE;
84 	config->num_wds_entries = 0;
85 	config->dma_burst_size = 0;
86 	config->rx_skip_defrag_timeout_dup_detection_check = 0;
87 	config->vow_config = TARGET_VOW_CONFIG;
88 	config->gtk_offload_max_vdev = 2;
89 	config->num_msdu_desc = 0x400;
90 	config->beacon_tx_offload_max_vdev = 2;
91 	config->rx_batchmode = TARGET_RX_BATCHMODE;
92 
93 	config->peer_map_unmap_v2_support = 0;
94 	config->use_pdev_id = 1;
95 	config->max_frag_entries = 0xa;
96 	config->num_tdls_vdevs = 0x1;
97 	config->num_tdls_conn_table_entries = 8;
98 	config->beacon_tx_offload_max_vdev = 0x2;
99 	config->num_multicast_filter_entries = 0x20;
100 	config->num_wow_filters = 0x16;
101 	config->num_keep_alive_pattern = 0;
102 	config->flag1 |= WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64;
103 }
104 
ath11k_hw_ipq8074_reo_setup(struct ath11k_base * ab)105 static void ath11k_hw_ipq8074_reo_setup(struct ath11k_base *ab)
106 {
107 	u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG;
108 	u32 val;
109 	/* Each hash entry uses three bits to map to a particular ring. */
110 	u32 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 |
111 		HAL_HASH_ROUTING_RING_SW2 << 3 |
112 		HAL_HASH_ROUTING_RING_SW3 << 6 |
113 		HAL_HASH_ROUTING_RING_SW4 << 9 |
114 		HAL_HASH_ROUTING_RING_SW1 << 12 |
115 		HAL_HASH_ROUTING_RING_SW2 << 15 |
116 		HAL_HASH_ROUTING_RING_SW3 << 18 |
117 		HAL_HASH_ROUTING_RING_SW4 << 21;
118 
119 	val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE);
120 
121 	val &= ~HAL_REO1_GEN_ENABLE_FRAG_DST_RING;
122 	val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_FRAG_DST_RING,
123 			HAL_SRNG_RING_ID_REO2SW1) |
124 		FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE, 1) |
125 		FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE, 1);
126 	ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val);
127 
128 	ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab),
129 			   HAL_DEFAULT_REO_TIMEOUT_USEC);
130 	ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab),
131 			   HAL_DEFAULT_REO_TIMEOUT_USEC);
132 	ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab),
133 			   HAL_DEFAULT_REO_TIMEOUT_USEC);
134 	ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab),
135 			   HAL_DEFAULT_REO_TIMEOUT_USEC);
136 
137 	ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_0,
138 			   FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP,
139 				      ring_hash_map));
140 	ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_1,
141 			   FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP,
142 				      ring_hash_map));
143 	ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2,
144 			   FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP,
145 				      ring_hash_map));
146 	ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3,
147 			   FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP,
148 				      ring_hash_map));
149 }
150 
ath11k_init_wmi_config_ipq8074(struct ath11k_base * ab,struct target_resource_config * config)151 static void ath11k_init_wmi_config_ipq8074(struct ath11k_base *ab,
152 					   struct target_resource_config *config)
153 {
154 	config->num_vdevs = ab->num_radios * TARGET_NUM_VDEVS(ab);
155 
156 	if (ab->num_radios == 2) {
157 		config->num_peers = TARGET_NUM_PEERS(ab, DBS);
158 		config->num_tids = TARGET_NUM_TIDS(ab, DBS);
159 	} else if (ab->num_radios == 3) {
160 		config->num_peers = TARGET_NUM_PEERS(ab, DBS_SBS);
161 		config->num_tids = TARGET_NUM_TIDS(ab, DBS_SBS);
162 	} else {
163 		/* Control should not reach here */
164 		config->num_peers = TARGET_NUM_PEERS(ab, SINGLE);
165 		config->num_tids = TARGET_NUM_TIDS(ab, SINGLE);
166 	}
167 	config->num_offload_peers = TARGET_NUM_OFFLD_PEERS;
168 	config->num_offload_reorder_buffs = TARGET_NUM_OFFLD_REORDER_BUFFS;
169 	config->num_peer_keys = TARGET_NUM_PEER_KEYS;
170 	config->ast_skid_limit = TARGET_AST_SKID_LIMIT;
171 	config->tx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1;
172 	config->rx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1;
173 	config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI;
174 	config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI;
175 	config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI;
176 	config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI;
177 
178 	if (test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags))
179 		config->rx_decap_mode = TARGET_DECAP_MODE_RAW;
180 	else
181 		config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI;
182 
183 	config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS;
184 	config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV;
185 	config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV;
186 	config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES;
187 	config->num_mcast_groups = TARGET_NUM_MCAST_GROUPS;
188 	config->num_mcast_table_elems = TARGET_NUM_MCAST_TABLE_ELEMS;
189 	config->mcast2ucast_mode = TARGET_MCAST2UCAST_MODE;
190 	config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE;
191 	config->num_wds_entries = TARGET_NUM_WDS_ENTRIES;
192 	config->dma_burst_size = TARGET_DMA_BURST_SIZE;
193 	config->rx_skip_defrag_timeout_dup_detection_check =
194 		TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK;
195 	config->vow_config = TARGET_VOW_CONFIG;
196 	config->gtk_offload_max_vdev = TARGET_GTK_OFFLOAD_MAX_VDEV;
197 	config->num_msdu_desc = TARGET_NUM_MSDU_DESC;
198 	config->beacon_tx_offload_max_vdev = ab->num_radios * TARGET_MAX_BCN_OFFLD;
199 	config->rx_batchmode = TARGET_RX_BATCHMODE;
200 	config->peer_map_unmap_v2_support = 1;
201 	config->twt_ap_pdev_count = ab->num_radios;
202 	config->twt_ap_sta_count = 1000;
203 	config->flag1 |= WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64;
204 }
205 
ath11k_hw_mac_id_to_pdev_id_ipq8074(struct ath11k_hw_params * hw,int mac_id)206 static int ath11k_hw_mac_id_to_pdev_id_ipq8074(struct ath11k_hw_params *hw,
207 					       int mac_id)
208 {
209 	return mac_id;
210 }
211 
ath11k_hw_mac_id_to_srng_id_ipq8074(struct ath11k_hw_params * hw,int mac_id)212 static int ath11k_hw_mac_id_to_srng_id_ipq8074(struct ath11k_hw_params *hw,
213 					       int mac_id)
214 {
215 	return 0;
216 }
217 
ath11k_hw_mac_id_to_pdev_id_qca6390(struct ath11k_hw_params * hw,int mac_id)218 static int ath11k_hw_mac_id_to_pdev_id_qca6390(struct ath11k_hw_params *hw,
219 					       int mac_id)
220 {
221 	return 0;
222 }
223 
ath11k_hw_mac_id_to_srng_id_qca6390(struct ath11k_hw_params * hw,int mac_id)224 static int ath11k_hw_mac_id_to_srng_id_qca6390(struct ath11k_hw_params *hw,
225 					       int mac_id)
226 {
227 	return mac_id;
228 }
229 
ath11k_hw_ipq8074_rx_desc_get_first_msdu(struct hal_rx_desc * desc)230 static bool ath11k_hw_ipq8074_rx_desc_get_first_msdu(struct hal_rx_desc *desc)
231 {
232 	return !!FIELD_GET(RX_MSDU_END_INFO2_FIRST_MSDU,
233 			   __le32_to_cpu(desc->u.ipq8074.msdu_end.info2));
234 }
235 
ath11k_hw_ipq8074_rx_desc_get_last_msdu(struct hal_rx_desc * desc)236 static bool ath11k_hw_ipq8074_rx_desc_get_last_msdu(struct hal_rx_desc *desc)
237 {
238 	return !!FIELD_GET(RX_MSDU_END_INFO2_LAST_MSDU,
239 			   __le32_to_cpu(desc->u.ipq8074.msdu_end.info2));
240 }
241 
ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes(struct hal_rx_desc * desc)242 static u8 ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc)
243 {
244 	return FIELD_GET(RX_MSDU_END_INFO2_L3_HDR_PADDING,
245 			 __le32_to_cpu(desc->u.ipq8074.msdu_end.info2));
246 }
247 
ath11k_hw_ipq8074_rx_desc_get_hdr_status(struct hal_rx_desc * desc)248 static u8 *ath11k_hw_ipq8074_rx_desc_get_hdr_status(struct hal_rx_desc *desc)
249 {
250 	return desc->u.ipq8074.hdr_status;
251 }
252 
ath11k_hw_ipq8074_rx_desc_encrypt_valid(struct hal_rx_desc * desc)253 static bool ath11k_hw_ipq8074_rx_desc_encrypt_valid(struct hal_rx_desc *desc)
254 {
255 	return __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1) &
256 	       RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID;
257 }
258 
ath11k_hw_ipq8074_rx_desc_get_encrypt_type(struct hal_rx_desc * desc)259 static u32 ath11k_hw_ipq8074_rx_desc_get_encrypt_type(struct hal_rx_desc *desc)
260 {
261 	return FIELD_GET(RX_MPDU_START_INFO2_ENC_TYPE,
262 			 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info2));
263 }
264 
ath11k_hw_ipq8074_rx_desc_get_decap_type(struct hal_rx_desc * desc)265 static u8 ath11k_hw_ipq8074_rx_desc_get_decap_type(struct hal_rx_desc *desc)
266 {
267 	return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT,
268 			 __le32_to_cpu(desc->u.ipq8074.msdu_start.info2));
269 }
270 
ath11k_hw_ipq8074_rx_desc_get_mesh_ctl(struct hal_rx_desc * desc)271 static u8 ath11k_hw_ipq8074_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc)
272 {
273 	return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT,
274 			 __le32_to_cpu(desc->u.ipq8074.msdu_start.info2));
275 }
276 
ath11k_hw_ipq8074_rx_desc_get_ldpc_support(struct hal_rx_desc * desc)277 static bool ath11k_hw_ipq8074_rx_desc_get_ldpc_support(struct hal_rx_desc *desc)
278 {
279 	return FIELD_GET(RX_MSDU_START_INFO2_LDPC,
280 			 __le32_to_cpu(desc->u.ipq8074.msdu_start.info2));
281 }
282 
ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc * desc)283 static bool ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc)
284 {
285 	return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID,
286 			   __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1));
287 }
288 
ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc * desc)289 static bool ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc)
290 {
291 	return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_FCTRL_VALID,
292 			   __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1));
293 }
294 
ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc * desc)295 static u16 ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc)
296 {
297 	return FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_NUM,
298 			 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1));
299 }
300 
ath11k_hw_ipq8074_rx_desc_get_msdu_len(struct hal_rx_desc * desc)301 static u16 ath11k_hw_ipq8074_rx_desc_get_msdu_len(struct hal_rx_desc *desc)
302 {
303 	return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH,
304 			 __le32_to_cpu(desc->u.ipq8074.msdu_start.info1));
305 }
306 
ath11k_hw_ipq8074_rx_desc_get_msdu_sgi(struct hal_rx_desc * desc)307 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc)
308 {
309 	return FIELD_GET(RX_MSDU_START_INFO3_SGI,
310 			 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3));
311 }
312 
ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc * desc)313 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc)
314 {
315 	return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS,
316 			 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3));
317 }
318 
ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw(struct hal_rx_desc * desc)319 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc)
320 {
321 	return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW,
322 			 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3));
323 }
324 
ath11k_hw_ipq8074_rx_desc_get_msdu_freq(struct hal_rx_desc * desc)325 static u32 ath11k_hw_ipq8074_rx_desc_get_msdu_freq(struct hal_rx_desc *desc)
326 {
327 	return __le32_to_cpu(desc->u.ipq8074.msdu_start.phy_meta_data);
328 }
329 
ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type(struct hal_rx_desc * desc)330 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc)
331 {
332 	return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE,
333 			 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3));
334 }
335 
ath11k_hw_ipq8074_rx_desc_get_msdu_nss(struct hal_rx_desc * desc)336 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_nss(struct hal_rx_desc *desc)
337 {
338 	return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP,
339 			 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3));
340 }
341 
ath11k_hw_ipq8074_rx_desc_get_mpdu_tid(struct hal_rx_desc * desc)342 static u8 ath11k_hw_ipq8074_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc)
343 {
344 	return FIELD_GET(RX_MPDU_START_INFO2_TID,
345 			 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info2));
346 }
347 
ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id(struct hal_rx_desc * desc)348 static u16 ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc)
349 {
350 	return __le16_to_cpu(desc->u.ipq8074.mpdu_start.sw_peer_id);
351 }
352 
ath11k_hw_ipq8074_rx_desc_copy_attn_end(struct hal_rx_desc * fdesc,struct hal_rx_desc * ldesc)353 static void ath11k_hw_ipq8074_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc,
354 						    struct hal_rx_desc *ldesc)
355 {
356 	memcpy((u8 *)&fdesc->u.ipq8074.msdu_end, (u8 *)&ldesc->u.ipq8074.msdu_end,
357 	       sizeof(struct rx_msdu_end_ipq8074));
358 	memcpy((u8 *)&fdesc->u.ipq8074.attention, (u8 *)&ldesc->u.ipq8074.attention,
359 	       sizeof(struct rx_attention));
360 	memcpy((u8 *)&fdesc->u.ipq8074.mpdu_end, (u8 *)&ldesc->u.ipq8074.mpdu_end,
361 	       sizeof(struct rx_mpdu_end));
362 }
363 
ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag(struct hal_rx_desc * desc)364 static u32 ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc)
365 {
366 	return FIELD_GET(HAL_TLV_HDR_TAG,
367 			 __le32_to_cpu(desc->u.ipq8074.mpdu_start_tag));
368 }
369 
ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc * desc)370 static u32 ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc)
371 {
372 	return __le16_to_cpu(desc->u.ipq8074.mpdu_start.phy_ppdu_id);
373 }
374 
ath11k_hw_ipq8074_rx_desc_set_msdu_len(struct hal_rx_desc * desc,u16 len)375 static void ath11k_hw_ipq8074_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len)
376 {
377 	u32 info = __le32_to_cpu(desc->u.ipq8074.msdu_start.info1);
378 
379 	info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH;
380 	info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len);
381 
382 	desc->u.ipq8074.msdu_start.info1 = __cpu_to_le32(info);
383 }
384 
ath11k_hw_ipq8074_rx_desc_mac_addr2_valid(struct hal_rx_desc * desc)385 static bool ath11k_hw_ipq8074_rx_desc_mac_addr2_valid(struct hal_rx_desc *desc)
386 {
387 	return __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1) &
388 	       RX_MPDU_START_INFO1_MAC_ADDR2_VALID;
389 }
390 
ath11k_hw_ipq8074_rx_desc_mpdu_start_addr2(struct hal_rx_desc * desc)391 static u8 *ath11k_hw_ipq8074_rx_desc_mpdu_start_addr2(struct hal_rx_desc *desc)
392 {
393 	return desc->u.ipq8074.mpdu_start.addr2;
394 }
395 
396 static
ath11k_hw_ipq8074_rx_desc_get_attention(struct hal_rx_desc * desc)397 struct rx_attention *ath11k_hw_ipq8074_rx_desc_get_attention(struct hal_rx_desc *desc)
398 {
399 	return &desc->u.ipq8074.attention;
400 }
401 
ath11k_hw_ipq8074_rx_desc_get_msdu_payload(struct hal_rx_desc * desc)402 static u8 *ath11k_hw_ipq8074_rx_desc_get_msdu_payload(struct hal_rx_desc *desc)
403 {
404 	return &desc->u.ipq8074.msdu_payload[0];
405 }
406 
ath11k_hw_qcn9074_rx_desc_get_first_msdu(struct hal_rx_desc * desc)407 static bool ath11k_hw_qcn9074_rx_desc_get_first_msdu(struct hal_rx_desc *desc)
408 {
409 	return !!FIELD_GET(RX_MSDU_END_INFO4_FIRST_MSDU,
410 			   __le16_to_cpu(desc->u.qcn9074.msdu_end.info4));
411 }
412 
ath11k_hw_qcn9074_rx_desc_get_last_msdu(struct hal_rx_desc * desc)413 static bool ath11k_hw_qcn9074_rx_desc_get_last_msdu(struct hal_rx_desc *desc)
414 {
415 	return !!FIELD_GET(RX_MSDU_END_INFO4_LAST_MSDU,
416 			   __le16_to_cpu(desc->u.qcn9074.msdu_end.info4));
417 }
418 
ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes(struct hal_rx_desc * desc)419 static u8 ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc)
420 {
421 	return FIELD_GET(RX_MSDU_END_INFO4_L3_HDR_PADDING,
422 			 __le16_to_cpu(desc->u.qcn9074.msdu_end.info4));
423 }
424 
ath11k_hw_qcn9074_rx_desc_get_hdr_status(struct hal_rx_desc * desc)425 static u8 *ath11k_hw_qcn9074_rx_desc_get_hdr_status(struct hal_rx_desc *desc)
426 {
427 	return desc->u.qcn9074.hdr_status;
428 }
429 
ath11k_hw_qcn9074_rx_desc_encrypt_valid(struct hal_rx_desc * desc)430 static bool ath11k_hw_qcn9074_rx_desc_encrypt_valid(struct hal_rx_desc *desc)
431 {
432 	return __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11) &
433 	       RX_MPDU_START_INFO11_ENCRYPT_INFO_VALID;
434 }
435 
ath11k_hw_qcn9074_rx_desc_get_encrypt_type(struct hal_rx_desc * desc)436 static u32 ath11k_hw_qcn9074_rx_desc_get_encrypt_type(struct hal_rx_desc *desc)
437 {
438 	return FIELD_GET(RX_MPDU_START_INFO9_ENC_TYPE,
439 			 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info9));
440 }
441 
ath11k_hw_qcn9074_rx_desc_get_decap_type(struct hal_rx_desc * desc)442 static u8 ath11k_hw_qcn9074_rx_desc_get_decap_type(struct hal_rx_desc *desc)
443 {
444 	return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT,
445 			 __le32_to_cpu(desc->u.qcn9074.msdu_start.info2));
446 }
447 
ath11k_hw_qcn9074_rx_desc_get_mesh_ctl(struct hal_rx_desc * desc)448 static u8 ath11k_hw_qcn9074_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc)
449 {
450 	return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT,
451 			 __le32_to_cpu(desc->u.qcn9074.msdu_start.info2));
452 }
453 
ath11k_hw_qcn9074_rx_desc_get_ldpc_support(struct hal_rx_desc * desc)454 static bool ath11k_hw_qcn9074_rx_desc_get_ldpc_support(struct hal_rx_desc *desc)
455 {
456 	return FIELD_GET(RX_MSDU_START_INFO2_LDPC,
457 			 __le32_to_cpu(desc->u.qcn9074.msdu_start.info2));
458 }
459 
ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc * desc)460 static bool ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc)
461 {
462 	return !!FIELD_GET(RX_MPDU_START_INFO11_MPDU_SEQ_CTRL_VALID,
463 			   __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11));
464 }
465 
ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc * desc)466 static bool ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc)
467 {
468 	return !!FIELD_GET(RX_MPDU_START_INFO11_MPDU_FCTRL_VALID,
469 			   __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11));
470 }
471 
ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc * desc)472 static u16 ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc)
473 {
474 	return FIELD_GET(RX_MPDU_START_INFO11_MPDU_SEQ_NUM,
475 			 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11));
476 }
477 
ath11k_hw_qcn9074_rx_desc_get_msdu_len(struct hal_rx_desc * desc)478 static u16 ath11k_hw_qcn9074_rx_desc_get_msdu_len(struct hal_rx_desc *desc)
479 {
480 	return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH,
481 			 __le32_to_cpu(desc->u.qcn9074.msdu_start.info1));
482 }
483 
ath11k_hw_qcn9074_rx_desc_get_msdu_sgi(struct hal_rx_desc * desc)484 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc)
485 {
486 	return FIELD_GET(RX_MSDU_START_INFO3_SGI,
487 			 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3));
488 }
489 
ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc * desc)490 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc)
491 {
492 	return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS,
493 			 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3));
494 }
495 
ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw(struct hal_rx_desc * desc)496 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc)
497 {
498 	return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW,
499 			 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3));
500 }
501 
ath11k_hw_qcn9074_rx_desc_get_msdu_freq(struct hal_rx_desc * desc)502 static u32 ath11k_hw_qcn9074_rx_desc_get_msdu_freq(struct hal_rx_desc *desc)
503 {
504 	return __le32_to_cpu(desc->u.qcn9074.msdu_start.phy_meta_data);
505 }
506 
ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type(struct hal_rx_desc * desc)507 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc)
508 {
509 	return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE,
510 			 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3));
511 }
512 
ath11k_hw_qcn9074_rx_desc_get_msdu_nss(struct hal_rx_desc * desc)513 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_nss(struct hal_rx_desc *desc)
514 {
515 	return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP,
516 			 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3));
517 }
518 
ath11k_hw_qcn9074_rx_desc_get_mpdu_tid(struct hal_rx_desc * desc)519 static u8 ath11k_hw_qcn9074_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc)
520 {
521 	return FIELD_GET(RX_MPDU_START_INFO9_TID,
522 			 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info9));
523 }
524 
ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id(struct hal_rx_desc * desc)525 static u16 ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc)
526 {
527 	return __le16_to_cpu(desc->u.qcn9074.mpdu_start.sw_peer_id);
528 }
529 
ath11k_hw_qcn9074_rx_desc_copy_attn_end(struct hal_rx_desc * fdesc,struct hal_rx_desc * ldesc)530 static void ath11k_hw_qcn9074_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc,
531 						    struct hal_rx_desc *ldesc)
532 {
533 	memcpy((u8 *)&fdesc->u.qcn9074.msdu_end, (u8 *)&ldesc->u.qcn9074.msdu_end,
534 	       sizeof(struct rx_msdu_end_qcn9074));
535 	memcpy((u8 *)&fdesc->u.qcn9074.attention, (u8 *)&ldesc->u.qcn9074.attention,
536 	       sizeof(struct rx_attention));
537 	memcpy((u8 *)&fdesc->u.qcn9074.mpdu_end, (u8 *)&ldesc->u.qcn9074.mpdu_end,
538 	       sizeof(struct rx_mpdu_end));
539 }
540 
ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag(struct hal_rx_desc * desc)541 static u32 ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc)
542 {
543 	return FIELD_GET(HAL_TLV_HDR_TAG,
544 			 __le32_to_cpu(desc->u.qcn9074.mpdu_start_tag));
545 }
546 
ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc * desc)547 static u32 ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc)
548 {
549 	return __le16_to_cpu(desc->u.qcn9074.mpdu_start.phy_ppdu_id);
550 }
551 
ath11k_hw_qcn9074_rx_desc_set_msdu_len(struct hal_rx_desc * desc,u16 len)552 static void ath11k_hw_qcn9074_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len)
553 {
554 	u32 info = __le32_to_cpu(desc->u.qcn9074.msdu_start.info1);
555 
556 	info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH;
557 	info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len);
558 
559 	desc->u.qcn9074.msdu_start.info1 = __cpu_to_le32(info);
560 }
561 
562 static
ath11k_hw_qcn9074_rx_desc_get_attention(struct hal_rx_desc * desc)563 struct rx_attention *ath11k_hw_qcn9074_rx_desc_get_attention(struct hal_rx_desc *desc)
564 {
565 	return &desc->u.qcn9074.attention;
566 }
567 
ath11k_hw_qcn9074_rx_desc_get_msdu_payload(struct hal_rx_desc * desc)568 static u8 *ath11k_hw_qcn9074_rx_desc_get_msdu_payload(struct hal_rx_desc *desc)
569 {
570 	return &desc->u.qcn9074.msdu_payload[0];
571 }
572 
ath11k_hw_ipq9074_rx_desc_mac_addr2_valid(struct hal_rx_desc * desc)573 static bool ath11k_hw_ipq9074_rx_desc_mac_addr2_valid(struct hal_rx_desc *desc)
574 {
575 	return __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11) &
576 	       RX_MPDU_START_INFO11_MAC_ADDR2_VALID;
577 }
578 
ath11k_hw_ipq9074_rx_desc_mpdu_start_addr2(struct hal_rx_desc * desc)579 static u8 *ath11k_hw_ipq9074_rx_desc_mpdu_start_addr2(struct hal_rx_desc *desc)
580 {
581 	return desc->u.qcn9074.mpdu_start.addr2;
582 }
583 
ath11k_hw_wcn6855_rx_desc_get_first_msdu(struct hal_rx_desc * desc)584 static bool ath11k_hw_wcn6855_rx_desc_get_first_msdu(struct hal_rx_desc *desc)
585 {
586 	return !!FIELD_GET(RX_MSDU_END_INFO2_FIRST_MSDU_WCN6855,
587 			   __le32_to_cpu(desc->u.wcn6855.msdu_end.info2));
588 }
589 
ath11k_hw_wcn6855_rx_desc_get_last_msdu(struct hal_rx_desc * desc)590 static bool ath11k_hw_wcn6855_rx_desc_get_last_msdu(struct hal_rx_desc *desc)
591 {
592 	return !!FIELD_GET(RX_MSDU_END_INFO2_LAST_MSDU_WCN6855,
593 			   __le32_to_cpu(desc->u.wcn6855.msdu_end.info2));
594 }
595 
ath11k_hw_wcn6855_rx_desc_get_l3_pad_bytes(struct hal_rx_desc * desc)596 static u8 ath11k_hw_wcn6855_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc)
597 {
598 	return FIELD_GET(RX_MSDU_END_INFO2_L3_HDR_PADDING,
599 			 __le32_to_cpu(desc->u.wcn6855.msdu_end.info2));
600 }
601 
ath11k_hw_wcn6855_rx_desc_get_hdr_status(struct hal_rx_desc * desc)602 static u8 *ath11k_hw_wcn6855_rx_desc_get_hdr_status(struct hal_rx_desc *desc)
603 {
604 	return desc->u.wcn6855.hdr_status;
605 }
606 
ath11k_hw_wcn6855_rx_desc_encrypt_valid(struct hal_rx_desc * desc)607 static bool ath11k_hw_wcn6855_rx_desc_encrypt_valid(struct hal_rx_desc *desc)
608 {
609 	return __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1) &
610 	       RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID;
611 }
612 
ath11k_hw_wcn6855_rx_desc_get_encrypt_type(struct hal_rx_desc * desc)613 static u32 ath11k_hw_wcn6855_rx_desc_get_encrypt_type(struct hal_rx_desc *desc)
614 {
615 	return FIELD_GET(RX_MPDU_START_INFO2_ENC_TYPE,
616 			 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info2));
617 }
618 
ath11k_hw_wcn6855_rx_desc_get_decap_type(struct hal_rx_desc * desc)619 static u8 ath11k_hw_wcn6855_rx_desc_get_decap_type(struct hal_rx_desc *desc)
620 {
621 	return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT,
622 			 __le32_to_cpu(desc->u.wcn6855.msdu_start.info2));
623 }
624 
ath11k_hw_wcn6855_rx_desc_get_mesh_ctl(struct hal_rx_desc * desc)625 static u8 ath11k_hw_wcn6855_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc)
626 {
627 	return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT,
628 			 __le32_to_cpu(desc->u.wcn6855.msdu_start.info2));
629 }
630 
ath11k_hw_wcn6855_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc * desc)631 static bool ath11k_hw_wcn6855_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc)
632 {
633 	return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID,
634 			   __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1));
635 }
636 
ath11k_hw_wcn6855_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc * desc)637 static bool ath11k_hw_wcn6855_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc)
638 {
639 	return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_FCTRL_VALID,
640 			   __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1));
641 }
642 
ath11k_hw_wcn6855_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc * desc)643 static u16 ath11k_hw_wcn6855_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc)
644 {
645 	return FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_NUM,
646 			 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1));
647 }
648 
ath11k_hw_wcn6855_rx_desc_get_msdu_len(struct hal_rx_desc * desc)649 static u16 ath11k_hw_wcn6855_rx_desc_get_msdu_len(struct hal_rx_desc *desc)
650 {
651 	return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH,
652 			 __le32_to_cpu(desc->u.wcn6855.msdu_start.info1));
653 }
654 
ath11k_hw_wcn6855_rx_desc_get_msdu_sgi(struct hal_rx_desc * desc)655 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc)
656 {
657 	return FIELD_GET(RX_MSDU_START_INFO3_SGI,
658 			 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3));
659 }
660 
ath11k_hw_wcn6855_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc * desc)661 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc)
662 {
663 	return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS,
664 			 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3));
665 }
666 
ath11k_hw_wcn6855_rx_desc_get_msdu_rx_bw(struct hal_rx_desc * desc)667 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc)
668 {
669 	return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW,
670 			 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3));
671 }
672 
ath11k_hw_wcn6855_rx_desc_get_msdu_freq(struct hal_rx_desc * desc)673 static u32 ath11k_hw_wcn6855_rx_desc_get_msdu_freq(struct hal_rx_desc *desc)
674 {
675 	return __le32_to_cpu(desc->u.wcn6855.msdu_start.phy_meta_data);
676 }
677 
ath11k_hw_wcn6855_rx_desc_get_msdu_pkt_type(struct hal_rx_desc * desc)678 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc)
679 {
680 	return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE,
681 			 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3));
682 }
683 
ath11k_hw_wcn6855_rx_desc_get_msdu_nss(struct hal_rx_desc * desc)684 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_nss(struct hal_rx_desc *desc)
685 {
686 	return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP,
687 			 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3));
688 }
689 
ath11k_hw_wcn6855_rx_desc_get_mpdu_tid(struct hal_rx_desc * desc)690 static u8 ath11k_hw_wcn6855_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc)
691 {
692 	return FIELD_GET(RX_MPDU_START_INFO2_TID_WCN6855,
693 			 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info2));
694 }
695 
ath11k_hw_wcn6855_rx_desc_get_mpdu_peer_id(struct hal_rx_desc * desc)696 static u16 ath11k_hw_wcn6855_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc)
697 {
698 	return __le16_to_cpu(desc->u.wcn6855.mpdu_start.sw_peer_id);
699 }
700 
ath11k_hw_wcn6855_rx_desc_copy_attn_end(struct hal_rx_desc * fdesc,struct hal_rx_desc * ldesc)701 static void ath11k_hw_wcn6855_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc,
702 						    struct hal_rx_desc *ldesc)
703 {
704 	memcpy((u8 *)&fdesc->u.wcn6855.msdu_end, (u8 *)&ldesc->u.wcn6855.msdu_end,
705 	       sizeof(struct rx_msdu_end_wcn6855));
706 	memcpy((u8 *)&fdesc->u.wcn6855.attention, (u8 *)&ldesc->u.wcn6855.attention,
707 	       sizeof(struct rx_attention));
708 	memcpy((u8 *)&fdesc->u.wcn6855.mpdu_end, (u8 *)&ldesc->u.wcn6855.mpdu_end,
709 	       sizeof(struct rx_mpdu_end));
710 }
711 
ath11k_hw_wcn6855_rx_desc_get_mpdu_start_tag(struct hal_rx_desc * desc)712 static u32 ath11k_hw_wcn6855_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc)
713 {
714 	return FIELD_GET(HAL_TLV_HDR_TAG,
715 			 __le32_to_cpu(desc->u.wcn6855.mpdu_start_tag));
716 }
717 
ath11k_hw_wcn6855_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc * desc)718 static u32 ath11k_hw_wcn6855_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc)
719 {
720 	return __le16_to_cpu(desc->u.wcn6855.mpdu_start.phy_ppdu_id);
721 }
722 
ath11k_hw_wcn6855_rx_desc_set_msdu_len(struct hal_rx_desc * desc,u16 len)723 static void ath11k_hw_wcn6855_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len)
724 {
725 	u32 info = __le32_to_cpu(desc->u.wcn6855.msdu_start.info1);
726 
727 	info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH;
728 	info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len);
729 
730 	desc->u.wcn6855.msdu_start.info1 = __cpu_to_le32(info);
731 }
732 
733 static
ath11k_hw_wcn6855_rx_desc_get_attention(struct hal_rx_desc * desc)734 struct rx_attention *ath11k_hw_wcn6855_rx_desc_get_attention(struct hal_rx_desc *desc)
735 {
736 	return &desc->u.wcn6855.attention;
737 }
738 
ath11k_hw_wcn6855_rx_desc_get_msdu_payload(struct hal_rx_desc * desc)739 static u8 *ath11k_hw_wcn6855_rx_desc_get_msdu_payload(struct hal_rx_desc *desc)
740 {
741 	return &desc->u.wcn6855.msdu_payload[0];
742 }
743 
ath11k_hw_wcn6855_rx_desc_mac_addr2_valid(struct hal_rx_desc * desc)744 static bool ath11k_hw_wcn6855_rx_desc_mac_addr2_valid(struct hal_rx_desc *desc)
745 {
746 	return __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1) &
747 	       RX_MPDU_START_INFO1_MAC_ADDR2_VALID;
748 }
749 
ath11k_hw_wcn6855_rx_desc_mpdu_start_addr2(struct hal_rx_desc * desc)750 static u8 *ath11k_hw_wcn6855_rx_desc_mpdu_start_addr2(struct hal_rx_desc *desc)
751 {
752 	return desc->u.wcn6855.mpdu_start.addr2;
753 }
754 
ath11k_hw_wcn6855_reo_setup(struct ath11k_base * ab)755 static void ath11k_hw_wcn6855_reo_setup(struct ath11k_base *ab)
756 {
757 	u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG;
758 	u32 val;
759 	/* Each hash entry uses four bits to map to a particular ring. */
760 	u32 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 |
761 		HAL_HASH_ROUTING_RING_SW2 << 4 |
762 		HAL_HASH_ROUTING_RING_SW3 << 8 |
763 		HAL_HASH_ROUTING_RING_SW4 << 12 |
764 		HAL_HASH_ROUTING_RING_SW1 << 16 |
765 		HAL_HASH_ROUTING_RING_SW2 << 20 |
766 		HAL_HASH_ROUTING_RING_SW3 << 24 |
767 		HAL_HASH_ROUTING_RING_SW4 << 28;
768 
769 	val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE);
770 	val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE, 1) |
771 		FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE, 1);
772 	ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val);
773 
774 	val = ath11k_hif_read32(ab, reo_base + HAL_REO1_MISC_CTL(ab));
775 	val &= ~HAL_REO1_MISC_CTL_FRAGMENT_DST_RING;
776 	val |= FIELD_PREP(HAL_REO1_MISC_CTL_FRAGMENT_DST_RING, HAL_SRNG_RING_ID_REO2SW1);
777 	ath11k_hif_write32(ab, reo_base + HAL_REO1_MISC_CTL(ab), val);
778 
779 	ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab),
780 			   HAL_DEFAULT_REO_TIMEOUT_USEC);
781 	ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab),
782 			   HAL_DEFAULT_REO_TIMEOUT_USEC);
783 	ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab),
784 			   HAL_DEFAULT_REO_TIMEOUT_USEC);
785 	ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab),
786 			   HAL_DEFAULT_REO_TIMEOUT_USEC);
787 
788 	ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2,
789 			   ring_hash_map);
790 	ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3,
791 			   ring_hash_map);
792 }
793 
ath11k_hw_ipq8074_mpdu_info_get_peerid(u8 * tlv_data)794 static u16 ath11k_hw_ipq8074_mpdu_info_get_peerid(u8 *tlv_data)
795 {
796 	u16 peer_id = 0;
797 	struct hal_rx_mpdu_info *mpdu_info =
798 		(struct hal_rx_mpdu_info *)tlv_data;
799 
800 	peer_id = FIELD_GET(HAL_RX_MPDU_INFO_INFO0_PEERID,
801 			    __le32_to_cpu(mpdu_info->info0));
802 
803 	return peer_id;
804 }
805 
ath11k_hw_wcn6855_mpdu_info_get_peerid(u8 * tlv_data)806 static u16 ath11k_hw_wcn6855_mpdu_info_get_peerid(u8 *tlv_data)
807 {
808 	u16 peer_id = 0;
809 	struct hal_rx_mpdu_info_wcn6855 *mpdu_info =
810 		(struct hal_rx_mpdu_info_wcn6855 *)tlv_data;
811 
812 	peer_id = FIELD_GET(HAL_RX_MPDU_INFO_INFO0_PEERID_WCN6855,
813 			    __le32_to_cpu(mpdu_info->info0));
814 	return peer_id;
815 }
816 
ath11k_hw_wcn6855_rx_desc_get_ldpc_support(struct hal_rx_desc * desc)817 static bool ath11k_hw_wcn6855_rx_desc_get_ldpc_support(struct hal_rx_desc *desc)
818 {
819 	return FIELD_GET(RX_MSDU_START_INFO2_LDPC,
820 			 __le32_to_cpu(desc->u.wcn6855.msdu_start.info2));
821 }
822 
ath11k_hw_ipq8074_get_tcl_ring_selector(struct sk_buff * skb)823 static u32 ath11k_hw_ipq8074_get_tcl_ring_selector(struct sk_buff *skb)
824 {
825 	/* Let the default ring selection be based on current processor
826 	 * number, where one of the 3 tcl rings are selected based on
827 	 * the smp_processor_id(). In case that ring
828 	 * is full/busy, we resort to other available rings.
829 	 * If all rings are full, we drop the packet.
830 	 *
831 	 * TODO: Add throttling logic when all rings are full
832 	 */
833 	return smp_processor_id();
834 }
835 
ath11k_hw_wcn6750_get_tcl_ring_selector(struct sk_buff * skb)836 static u32 ath11k_hw_wcn6750_get_tcl_ring_selector(struct sk_buff *skb)
837 {
838 	/* Select the TCL ring based on the flow hash of the SKB instead
839 	 * of CPU ID. Since applications pumping the traffic can be scheduled
840 	 * on multiple CPUs, there is a chance that packets of the same flow
841 	 * could end on different TCL rings, this could sometimes results in
842 	 * an out of order arrival of the packets at the receiver.
843 	 */
844 	return skb_get_hash(skb);
845 }
846 
847 const struct ath11k_hw_ops ipq8074_ops = {
848 	.get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id,
849 	.wmi_init_config = ath11k_init_wmi_config_ipq8074,
850 	.mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074,
851 	.mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074,
852 	.tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable,
853 	.rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu,
854 	.rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu,
855 	.rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes,
856 	.rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status,
857 	.rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid,
858 	.rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type,
859 	.rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type,
860 	.rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl,
861 	.rx_desc_get_ldpc_support = ath11k_hw_ipq8074_rx_desc_get_ldpc_support,
862 	.rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld,
863 	.rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid,
864 	.rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no,
865 	.rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len,
866 	.rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi,
867 	.rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs,
868 	.rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw,
869 	.rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq,
870 	.rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type,
871 	.rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss,
872 	.rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid,
873 	.rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id,
874 	.rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end,
875 	.rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag,
876 	.rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id,
877 	.rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len,
878 	.rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention,
879 	.rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload,
880 	.reo_setup = ath11k_hw_ipq8074_reo_setup,
881 	.mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid,
882 	.rx_desc_mac_addr2_valid = ath11k_hw_ipq8074_rx_desc_mac_addr2_valid,
883 	.rx_desc_mpdu_start_addr2 = ath11k_hw_ipq8074_rx_desc_mpdu_start_addr2,
884 	.get_ring_selector = ath11k_hw_ipq8074_get_tcl_ring_selector,
885 };
886 
887 const struct ath11k_hw_ops ipq6018_ops = {
888 	.get_hw_mac_from_pdev_id = ath11k_hw_ipq6018_mac_from_pdev_id,
889 	.wmi_init_config = ath11k_init_wmi_config_ipq8074,
890 	.mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074,
891 	.mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074,
892 	.tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable,
893 	.rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu,
894 	.rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu,
895 	.rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes,
896 	.rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status,
897 	.rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid,
898 	.rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type,
899 	.rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type,
900 	.rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl,
901 	.rx_desc_get_ldpc_support = ath11k_hw_ipq8074_rx_desc_get_ldpc_support,
902 	.rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld,
903 	.rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid,
904 	.rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no,
905 	.rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len,
906 	.rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi,
907 	.rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs,
908 	.rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw,
909 	.rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq,
910 	.rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type,
911 	.rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss,
912 	.rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid,
913 	.rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id,
914 	.rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end,
915 	.rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag,
916 	.rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id,
917 	.rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len,
918 	.rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention,
919 	.rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload,
920 	.reo_setup = ath11k_hw_ipq8074_reo_setup,
921 	.mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid,
922 	.rx_desc_mac_addr2_valid = ath11k_hw_ipq8074_rx_desc_mac_addr2_valid,
923 	.rx_desc_mpdu_start_addr2 = ath11k_hw_ipq8074_rx_desc_mpdu_start_addr2,
924 	.get_ring_selector = ath11k_hw_ipq8074_get_tcl_ring_selector,
925 };
926 
927 const struct ath11k_hw_ops qca6390_ops = {
928 	.get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id,
929 	.wmi_init_config = ath11k_init_wmi_config_qca6390,
930 	.mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390,
931 	.mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390,
932 	.tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable,
933 	.rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu,
934 	.rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu,
935 	.rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes,
936 	.rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status,
937 	.rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid,
938 	.rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type,
939 	.rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type,
940 	.rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl,
941 	.rx_desc_get_ldpc_support = ath11k_hw_ipq8074_rx_desc_get_ldpc_support,
942 	.rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld,
943 	.rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid,
944 	.rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no,
945 	.rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len,
946 	.rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi,
947 	.rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs,
948 	.rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw,
949 	.rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq,
950 	.rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type,
951 	.rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss,
952 	.rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid,
953 	.rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id,
954 	.rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end,
955 	.rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag,
956 	.rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id,
957 	.rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len,
958 	.rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention,
959 	.rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload,
960 	.reo_setup = ath11k_hw_ipq8074_reo_setup,
961 	.mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid,
962 	.rx_desc_mac_addr2_valid = ath11k_hw_ipq8074_rx_desc_mac_addr2_valid,
963 	.rx_desc_mpdu_start_addr2 = ath11k_hw_ipq8074_rx_desc_mpdu_start_addr2,
964 	.get_ring_selector = ath11k_hw_ipq8074_get_tcl_ring_selector,
965 };
966 
967 const struct ath11k_hw_ops qcn9074_ops = {
968 	.get_hw_mac_from_pdev_id = ath11k_hw_ipq6018_mac_from_pdev_id,
969 	.wmi_init_config = ath11k_init_wmi_config_ipq8074,
970 	.mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074,
971 	.mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074,
972 	.tx_mesh_enable = ath11k_hw_qcn9074_tx_mesh_enable,
973 	.rx_desc_get_first_msdu = ath11k_hw_qcn9074_rx_desc_get_first_msdu,
974 	.rx_desc_get_last_msdu = ath11k_hw_qcn9074_rx_desc_get_last_msdu,
975 	.rx_desc_get_l3_pad_bytes = ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes,
976 	.rx_desc_get_hdr_status = ath11k_hw_qcn9074_rx_desc_get_hdr_status,
977 	.rx_desc_encrypt_valid = ath11k_hw_qcn9074_rx_desc_encrypt_valid,
978 	.rx_desc_get_encrypt_type = ath11k_hw_qcn9074_rx_desc_get_encrypt_type,
979 	.rx_desc_get_decap_type = ath11k_hw_qcn9074_rx_desc_get_decap_type,
980 	.rx_desc_get_mesh_ctl = ath11k_hw_qcn9074_rx_desc_get_mesh_ctl,
981 	.rx_desc_get_ldpc_support = ath11k_hw_qcn9074_rx_desc_get_ldpc_support,
982 	.rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld,
983 	.rx_desc_get_mpdu_fc_valid = ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid,
984 	.rx_desc_get_mpdu_start_seq_no = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no,
985 	.rx_desc_get_msdu_len = ath11k_hw_qcn9074_rx_desc_get_msdu_len,
986 	.rx_desc_get_msdu_sgi = ath11k_hw_qcn9074_rx_desc_get_msdu_sgi,
987 	.rx_desc_get_msdu_rate_mcs = ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs,
988 	.rx_desc_get_msdu_rx_bw = ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw,
989 	.rx_desc_get_msdu_freq = ath11k_hw_qcn9074_rx_desc_get_msdu_freq,
990 	.rx_desc_get_msdu_pkt_type = ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type,
991 	.rx_desc_get_msdu_nss = ath11k_hw_qcn9074_rx_desc_get_msdu_nss,
992 	.rx_desc_get_mpdu_tid = ath11k_hw_qcn9074_rx_desc_get_mpdu_tid,
993 	.rx_desc_get_mpdu_peer_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id,
994 	.rx_desc_copy_attn_end_tlv = ath11k_hw_qcn9074_rx_desc_copy_attn_end,
995 	.rx_desc_get_mpdu_start_tag = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag,
996 	.rx_desc_get_mpdu_ppdu_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id,
997 	.rx_desc_set_msdu_len = ath11k_hw_qcn9074_rx_desc_set_msdu_len,
998 	.rx_desc_get_attention = ath11k_hw_qcn9074_rx_desc_get_attention,
999 	.rx_desc_get_msdu_payload = ath11k_hw_qcn9074_rx_desc_get_msdu_payload,
1000 	.reo_setup = ath11k_hw_ipq8074_reo_setup,
1001 	.mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid,
1002 	.rx_desc_mac_addr2_valid = ath11k_hw_ipq9074_rx_desc_mac_addr2_valid,
1003 	.rx_desc_mpdu_start_addr2 = ath11k_hw_ipq9074_rx_desc_mpdu_start_addr2,
1004 	.get_ring_selector = ath11k_hw_ipq8074_get_tcl_ring_selector,
1005 };
1006 
1007 const struct ath11k_hw_ops wcn6855_ops = {
1008 	.get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id,
1009 	.wmi_init_config = ath11k_init_wmi_config_qca6390,
1010 	.mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390,
1011 	.mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390,
1012 	.tx_mesh_enable = ath11k_hw_wcn6855_tx_mesh_enable,
1013 	.rx_desc_get_first_msdu = ath11k_hw_wcn6855_rx_desc_get_first_msdu,
1014 	.rx_desc_get_last_msdu = ath11k_hw_wcn6855_rx_desc_get_last_msdu,
1015 	.rx_desc_get_l3_pad_bytes = ath11k_hw_wcn6855_rx_desc_get_l3_pad_bytes,
1016 	.rx_desc_get_hdr_status = ath11k_hw_wcn6855_rx_desc_get_hdr_status,
1017 	.rx_desc_encrypt_valid = ath11k_hw_wcn6855_rx_desc_encrypt_valid,
1018 	.rx_desc_get_encrypt_type = ath11k_hw_wcn6855_rx_desc_get_encrypt_type,
1019 	.rx_desc_get_decap_type = ath11k_hw_wcn6855_rx_desc_get_decap_type,
1020 	.rx_desc_get_mesh_ctl = ath11k_hw_wcn6855_rx_desc_get_mesh_ctl,
1021 	.rx_desc_get_ldpc_support = ath11k_hw_wcn6855_rx_desc_get_ldpc_support,
1022 	.rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_wcn6855_rx_desc_get_mpdu_seq_ctl_vld,
1023 	.rx_desc_get_mpdu_fc_valid = ath11k_hw_wcn6855_rx_desc_get_mpdu_fc_valid,
1024 	.rx_desc_get_mpdu_start_seq_no = ath11k_hw_wcn6855_rx_desc_get_mpdu_start_seq_no,
1025 	.rx_desc_get_msdu_len = ath11k_hw_wcn6855_rx_desc_get_msdu_len,
1026 	.rx_desc_get_msdu_sgi = ath11k_hw_wcn6855_rx_desc_get_msdu_sgi,
1027 	.rx_desc_get_msdu_rate_mcs = ath11k_hw_wcn6855_rx_desc_get_msdu_rate_mcs,
1028 	.rx_desc_get_msdu_rx_bw = ath11k_hw_wcn6855_rx_desc_get_msdu_rx_bw,
1029 	.rx_desc_get_msdu_freq = ath11k_hw_wcn6855_rx_desc_get_msdu_freq,
1030 	.rx_desc_get_msdu_pkt_type = ath11k_hw_wcn6855_rx_desc_get_msdu_pkt_type,
1031 	.rx_desc_get_msdu_nss = ath11k_hw_wcn6855_rx_desc_get_msdu_nss,
1032 	.rx_desc_get_mpdu_tid = ath11k_hw_wcn6855_rx_desc_get_mpdu_tid,
1033 	.rx_desc_get_mpdu_peer_id = ath11k_hw_wcn6855_rx_desc_get_mpdu_peer_id,
1034 	.rx_desc_copy_attn_end_tlv = ath11k_hw_wcn6855_rx_desc_copy_attn_end,
1035 	.rx_desc_get_mpdu_start_tag = ath11k_hw_wcn6855_rx_desc_get_mpdu_start_tag,
1036 	.rx_desc_get_mpdu_ppdu_id = ath11k_hw_wcn6855_rx_desc_get_mpdu_ppdu_id,
1037 	.rx_desc_set_msdu_len = ath11k_hw_wcn6855_rx_desc_set_msdu_len,
1038 	.rx_desc_get_attention = ath11k_hw_wcn6855_rx_desc_get_attention,
1039 	.rx_desc_get_msdu_payload = ath11k_hw_wcn6855_rx_desc_get_msdu_payload,
1040 	.reo_setup = ath11k_hw_wcn6855_reo_setup,
1041 	.mpdu_info_get_peerid = ath11k_hw_wcn6855_mpdu_info_get_peerid,
1042 	.rx_desc_mac_addr2_valid = ath11k_hw_wcn6855_rx_desc_mac_addr2_valid,
1043 	.rx_desc_mpdu_start_addr2 = ath11k_hw_wcn6855_rx_desc_mpdu_start_addr2,
1044 	.get_ring_selector = ath11k_hw_ipq8074_get_tcl_ring_selector,
1045 };
1046 
1047 const struct ath11k_hw_ops wcn6750_ops = {
1048 	.get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id,
1049 	.wmi_init_config = ath11k_init_wmi_config_qca6390,
1050 	.mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390,
1051 	.mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390,
1052 	.tx_mesh_enable = ath11k_hw_qcn9074_tx_mesh_enable,
1053 	.rx_desc_get_first_msdu = ath11k_hw_qcn9074_rx_desc_get_first_msdu,
1054 	.rx_desc_get_last_msdu = ath11k_hw_qcn9074_rx_desc_get_last_msdu,
1055 	.rx_desc_get_l3_pad_bytes = ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes,
1056 	.rx_desc_get_hdr_status = ath11k_hw_qcn9074_rx_desc_get_hdr_status,
1057 	.rx_desc_encrypt_valid = ath11k_hw_qcn9074_rx_desc_encrypt_valid,
1058 	.rx_desc_get_encrypt_type = ath11k_hw_qcn9074_rx_desc_get_encrypt_type,
1059 	.rx_desc_get_decap_type = ath11k_hw_qcn9074_rx_desc_get_decap_type,
1060 	.rx_desc_get_mesh_ctl = ath11k_hw_qcn9074_rx_desc_get_mesh_ctl,
1061 	.rx_desc_get_ldpc_support = ath11k_hw_qcn9074_rx_desc_get_ldpc_support,
1062 	.rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld,
1063 	.rx_desc_get_mpdu_fc_valid = ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid,
1064 	.rx_desc_get_mpdu_start_seq_no = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no,
1065 	.rx_desc_get_msdu_len = ath11k_hw_qcn9074_rx_desc_get_msdu_len,
1066 	.rx_desc_get_msdu_sgi = ath11k_hw_qcn9074_rx_desc_get_msdu_sgi,
1067 	.rx_desc_get_msdu_rate_mcs = ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs,
1068 	.rx_desc_get_msdu_rx_bw = ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw,
1069 	.rx_desc_get_msdu_freq = ath11k_hw_qcn9074_rx_desc_get_msdu_freq,
1070 	.rx_desc_get_msdu_pkt_type = ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type,
1071 	.rx_desc_get_msdu_nss = ath11k_hw_qcn9074_rx_desc_get_msdu_nss,
1072 	.rx_desc_get_mpdu_tid = ath11k_hw_qcn9074_rx_desc_get_mpdu_tid,
1073 	.rx_desc_get_mpdu_peer_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id,
1074 	.rx_desc_copy_attn_end_tlv = ath11k_hw_qcn9074_rx_desc_copy_attn_end,
1075 	.rx_desc_get_mpdu_start_tag = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag,
1076 	.rx_desc_get_mpdu_ppdu_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id,
1077 	.rx_desc_set_msdu_len = ath11k_hw_qcn9074_rx_desc_set_msdu_len,
1078 	.rx_desc_get_attention = ath11k_hw_qcn9074_rx_desc_get_attention,
1079 	.rx_desc_get_msdu_payload = ath11k_hw_qcn9074_rx_desc_get_msdu_payload,
1080 	.reo_setup = ath11k_hw_wcn6855_reo_setup,
1081 	.mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid,
1082 	.rx_desc_mac_addr2_valid = ath11k_hw_ipq9074_rx_desc_mac_addr2_valid,
1083 	.rx_desc_mpdu_start_addr2 = ath11k_hw_ipq9074_rx_desc_mpdu_start_addr2,
1084 	.get_ring_selector = ath11k_hw_wcn6750_get_tcl_ring_selector,
1085 };
1086 
1087 #define ATH11K_TX_RING_MASK_0 BIT(0)
1088 #define ATH11K_TX_RING_MASK_1 BIT(1)
1089 #define ATH11K_TX_RING_MASK_2 BIT(2)
1090 #define ATH11K_TX_RING_MASK_3 BIT(3)
1091 #define ATH11K_TX_RING_MASK_4 BIT(4)
1092 
1093 #define ATH11K_RX_RING_MASK_0 0x1
1094 #define ATH11K_RX_RING_MASK_1 0x2
1095 #define ATH11K_RX_RING_MASK_2 0x4
1096 #define ATH11K_RX_RING_MASK_3 0x8
1097 
1098 #define ATH11K_RX_ERR_RING_MASK_0 0x1
1099 
1100 #define ATH11K_RX_WBM_REL_RING_MASK_0 0x1
1101 
1102 #define ATH11K_REO_STATUS_RING_MASK_0 0x1
1103 
1104 #define ATH11K_RXDMA2HOST_RING_MASK_0 0x1
1105 #define ATH11K_RXDMA2HOST_RING_MASK_1 0x2
1106 #define ATH11K_RXDMA2HOST_RING_MASK_2 0x4
1107 
1108 #define ATH11K_HOST2RXDMA_RING_MASK_0 0x1
1109 #define ATH11K_HOST2RXDMA_RING_MASK_1 0x2
1110 #define ATH11K_HOST2RXDMA_RING_MASK_2 0x4
1111 
1112 #define ATH11K_RX_MON_STATUS_RING_MASK_0 0x1
1113 #define ATH11K_RX_MON_STATUS_RING_MASK_1 0x2
1114 #define ATH11K_RX_MON_STATUS_RING_MASK_2 0x4
1115 
1116 const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_ipq8074 = {
1117 	.tx  = {
1118 		ATH11K_TX_RING_MASK_0,
1119 		ATH11K_TX_RING_MASK_1,
1120 		ATH11K_TX_RING_MASK_2,
1121 	},
1122 	.rx_mon_status = {
1123 		0, 0, 0, 0,
1124 		ATH11K_RX_MON_STATUS_RING_MASK_0,
1125 		ATH11K_RX_MON_STATUS_RING_MASK_1,
1126 		ATH11K_RX_MON_STATUS_RING_MASK_2,
1127 	},
1128 	.rx = {
1129 		0, 0, 0, 0, 0, 0, 0,
1130 		ATH11K_RX_RING_MASK_0,
1131 		ATH11K_RX_RING_MASK_1,
1132 		ATH11K_RX_RING_MASK_2,
1133 		ATH11K_RX_RING_MASK_3,
1134 	},
1135 	.rx_err = {
1136 		ATH11K_RX_ERR_RING_MASK_0,
1137 	},
1138 	.rx_wbm_rel = {
1139 		ATH11K_RX_WBM_REL_RING_MASK_0,
1140 	},
1141 	.reo_status = {
1142 		ATH11K_REO_STATUS_RING_MASK_0,
1143 	},
1144 	.rxdma2host = {
1145 		ATH11K_RXDMA2HOST_RING_MASK_0,
1146 		ATH11K_RXDMA2HOST_RING_MASK_1,
1147 		ATH11K_RXDMA2HOST_RING_MASK_2,
1148 	},
1149 	.host2rxdma = {
1150 		ATH11K_HOST2RXDMA_RING_MASK_0,
1151 		ATH11K_HOST2RXDMA_RING_MASK_1,
1152 		ATH11K_HOST2RXDMA_RING_MASK_2,
1153 	},
1154 };
1155 
1156 const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qca6390 = {
1157 	.tx  = {
1158 		ATH11K_TX_RING_MASK_0,
1159 	},
1160 	.rx_mon_status = {
1161 		0, 0, 0, 0,
1162 		ATH11K_RX_MON_STATUS_RING_MASK_0,
1163 		ATH11K_RX_MON_STATUS_RING_MASK_1,
1164 		ATH11K_RX_MON_STATUS_RING_MASK_2,
1165 	},
1166 	.rx = {
1167 		0, 0, 0, 0, 0, 0, 0,
1168 		ATH11K_RX_RING_MASK_0,
1169 		ATH11K_RX_RING_MASK_1,
1170 		ATH11K_RX_RING_MASK_2,
1171 		ATH11K_RX_RING_MASK_3,
1172 	},
1173 	.rx_err = {
1174 		ATH11K_RX_ERR_RING_MASK_0,
1175 	},
1176 	.rx_wbm_rel = {
1177 		ATH11K_RX_WBM_REL_RING_MASK_0,
1178 	},
1179 	.reo_status = {
1180 		ATH11K_REO_STATUS_RING_MASK_0,
1181 	},
1182 	.rxdma2host = {
1183 		ATH11K_RXDMA2HOST_RING_MASK_0,
1184 		ATH11K_RXDMA2HOST_RING_MASK_1,
1185 		ATH11K_RXDMA2HOST_RING_MASK_2,
1186 	},
1187 	.host2rxdma = {
1188 	},
1189 };
1190 
1191 /* Target firmware's Copy Engine configuration. */
1192 const struct ce_pipe_config ath11k_target_ce_config_wlan_ipq8074[] = {
1193 	/* CE0: host->target HTC control and raw streams */
1194 	{
1195 		.pipenum = __cpu_to_le32(0),
1196 		.pipedir = __cpu_to_le32(PIPEDIR_OUT),
1197 		.nentries = __cpu_to_le32(32),
1198 		.nbytes_max = __cpu_to_le32(2048),
1199 		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
1200 		.reserved = __cpu_to_le32(0),
1201 	},
1202 
1203 	/* CE1: target->host HTT + HTC control */
1204 	{
1205 		.pipenum = __cpu_to_le32(1),
1206 		.pipedir = __cpu_to_le32(PIPEDIR_IN),
1207 		.nentries = __cpu_to_le32(32),
1208 		.nbytes_max = __cpu_to_le32(2048),
1209 		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
1210 		.reserved = __cpu_to_le32(0),
1211 	},
1212 
1213 	/* CE2: target->host WMI */
1214 	{
1215 		.pipenum = __cpu_to_le32(2),
1216 		.pipedir = __cpu_to_le32(PIPEDIR_IN),
1217 		.nentries = __cpu_to_le32(32),
1218 		.nbytes_max = __cpu_to_le32(2048),
1219 		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
1220 		.reserved = __cpu_to_le32(0),
1221 	},
1222 
1223 	/* CE3: host->target WMI */
1224 	{
1225 		.pipenum = __cpu_to_le32(3),
1226 		.pipedir = __cpu_to_le32(PIPEDIR_OUT),
1227 		.nentries = __cpu_to_le32(32),
1228 		.nbytes_max = __cpu_to_le32(2048),
1229 		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
1230 		.reserved = __cpu_to_le32(0),
1231 	},
1232 
1233 	/* CE4: host->target HTT */
1234 	{
1235 		.pipenum = __cpu_to_le32(4),
1236 		.pipedir = __cpu_to_le32(PIPEDIR_OUT),
1237 		.nentries = __cpu_to_le32(256),
1238 		.nbytes_max = __cpu_to_le32(256),
1239 		.flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
1240 		.reserved = __cpu_to_le32(0),
1241 	},
1242 
1243 	/* CE5: target->host Pktlog */
1244 	{
1245 		.pipenum = __cpu_to_le32(5),
1246 		.pipedir = __cpu_to_le32(PIPEDIR_IN),
1247 		.nentries = __cpu_to_le32(32),
1248 		.nbytes_max = __cpu_to_le32(2048),
1249 		.flags = __cpu_to_le32(0),
1250 		.reserved = __cpu_to_le32(0),
1251 	},
1252 
1253 	/* CE6: Reserved for target autonomous hif_memcpy */
1254 	{
1255 		.pipenum = __cpu_to_le32(6),
1256 		.pipedir = __cpu_to_le32(PIPEDIR_INOUT),
1257 		.nentries = __cpu_to_le32(32),
1258 		.nbytes_max = __cpu_to_le32(65535),
1259 		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
1260 		.reserved = __cpu_to_le32(0),
1261 	},
1262 
1263 	/* CE7 used only by Host */
1264 	{
1265 		.pipenum = __cpu_to_le32(7),
1266 		.pipedir = __cpu_to_le32(PIPEDIR_OUT),
1267 		.nentries = __cpu_to_le32(32),
1268 		.nbytes_max = __cpu_to_le32(2048),
1269 		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
1270 		.reserved = __cpu_to_le32(0),
1271 	},
1272 
1273 	/* CE8 target->host used only by IPA */
1274 	{
1275 		.pipenum = __cpu_to_le32(8),
1276 		.pipedir = __cpu_to_le32(PIPEDIR_INOUT),
1277 		.nentries = __cpu_to_le32(32),
1278 		.nbytes_max = __cpu_to_le32(65535),
1279 		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
1280 		.reserved = __cpu_to_le32(0),
1281 	},
1282 
1283 	/* CE9 host->target HTT */
1284 	{
1285 		.pipenum = __cpu_to_le32(9),
1286 		.pipedir = __cpu_to_le32(PIPEDIR_OUT),
1287 		.nentries = __cpu_to_le32(32),
1288 		.nbytes_max = __cpu_to_le32(2048),
1289 		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
1290 		.reserved = __cpu_to_le32(0),
1291 	},
1292 
1293 	/* CE10 target->host HTT */
1294 	{
1295 		.pipenum = __cpu_to_le32(10),
1296 		.pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H),
1297 		.nentries = __cpu_to_le32(0),
1298 		.nbytes_max = __cpu_to_le32(0),
1299 		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
1300 		.reserved = __cpu_to_le32(0),
1301 	},
1302 
1303 	/* CE11 Not used */
1304 };
1305 
1306 /* Map from service/endpoint to Copy Engine.
1307  * This table is derived from the CE_PCI TABLE, above.
1308  * It is passed to the Target at startup for use by firmware.
1309  */
1310 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq8074[] = {
1311 	{
1312 		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO),
1313 		.pipedir = __cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
1314 		.pipenum = __cpu_to_le32(3),
1315 	},
1316 	{
1317 		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO),
1318 		.pipedir = __cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
1319 		.pipenum = __cpu_to_le32(2),
1320 	},
1321 	{
1322 		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK),
1323 		.pipedir = __cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
1324 		.pipenum = __cpu_to_le32(3),
1325 	},
1326 	{
1327 		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK),
1328 		.pipedir = __cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
1329 		.pipenum = __cpu_to_le32(2),
1330 	},
1331 	{
1332 		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE),
1333 		.pipedir = __cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
1334 		.pipenum = __cpu_to_le32(3),
1335 	},
1336 	{
1337 		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE),
1338 		.pipedir = __cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
1339 		.pipenum = __cpu_to_le32(2),
1340 	},
1341 	{
1342 		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI),
1343 		.pipedir = __cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
1344 		.pipenum = __cpu_to_le32(3),
1345 	},
1346 	{
1347 		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI),
1348 		.pipedir = __cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
1349 		.pipenum = __cpu_to_le32(2),
1350 	},
1351 	{
1352 		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL),
1353 		.pipedir = __cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
1354 		.pipenum = __cpu_to_le32(3),
1355 	},
1356 	{
1357 		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL),
1358 		.pipedir = __cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
1359 		.pipenum = __cpu_to_le32(2),
1360 	},
1361 	{
1362 		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1),
1363 		.pipedir = __cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
1364 		.pipenum = __cpu_to_le32(7),
1365 	},
1366 	{
1367 		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1),
1368 		.pipedir = __cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
1369 		.pipenum = __cpu_to_le32(2),
1370 	},
1371 	{
1372 		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC2),
1373 		.pipedir = __cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
1374 		.pipenum = __cpu_to_le32(9),
1375 	},
1376 	{
1377 		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC2),
1378 		.pipedir = __cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
1379 		.pipenum = __cpu_to_le32(2),
1380 	},
1381 	{
1382 		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL),
1383 		.pipedir = __cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
1384 		.pipenum = __cpu_to_le32(0),
1385 	},
1386 	{
1387 		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL),
1388 		.pipedir = __cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
1389 		.pipenum = __cpu_to_le32(1),
1390 	},
1391 	{ /* not used */
1392 		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS),
1393 		.pipedir = __cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
1394 		.pipenum = __cpu_to_le32(0),
1395 	},
1396 	{ /* not used */
1397 		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS),
1398 		.pipedir = __cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
1399 		.pipenum = __cpu_to_le32(1),
1400 	},
1401 	{
1402 		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG),
1403 		.pipedir = __cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
1404 		.pipenum = __cpu_to_le32(4),
1405 	},
1406 	{
1407 		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG),
1408 		.pipedir = __cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
1409 		.pipenum = __cpu_to_le32(1),
1410 	},
1411 	{
1412 		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG),
1413 		.pipedir = __cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
1414 		.pipenum = __cpu_to_le32(5),
1415 	},
1416 
1417 	/* (Additions here) */
1418 
1419 	{ /* terminator entry */ }
1420 };
1421 
1422 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq6018[] = {
1423 	{
1424 		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO),
1425 		.pipedir = __cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
1426 		.pipenum = __cpu_to_le32(3),
1427 	},
1428 	{
1429 		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO),
1430 		.pipedir = __cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
1431 		.pipenum = __cpu_to_le32(2),
1432 	},
1433 	{
1434 		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK),
1435 		.pipedir = __cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
1436 		.pipenum = __cpu_to_le32(3),
1437 	},
1438 	{
1439 		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK),
1440 		.pipedir = __cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
1441 		.pipenum = __cpu_to_le32(2),
1442 	},
1443 	{
1444 		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE),
1445 		.pipedir = __cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
1446 		.pipenum = __cpu_to_le32(3),
1447 	},
1448 	{
1449 		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE),
1450 		.pipedir = __cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
1451 		.pipenum = __cpu_to_le32(2),
1452 	},
1453 	{
1454 		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI),
1455 		.pipedir = __cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
1456 		.pipenum = __cpu_to_le32(3),
1457 	},
1458 	{
1459 		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI),
1460 		.pipedir = __cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
1461 		.pipenum = __cpu_to_le32(2),
1462 	},
1463 	{
1464 		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL),
1465 		.pipedir = __cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
1466 		.pipenum = __cpu_to_le32(3),
1467 	},
1468 	{
1469 		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL),
1470 		.pipedir = __cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
1471 		.pipenum = __cpu_to_le32(2),
1472 	},
1473 	{
1474 		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1),
1475 		.pipedir = __cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
1476 		.pipenum = __cpu_to_le32(7),
1477 	},
1478 	{
1479 		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1),
1480 		.pipedir = __cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
1481 		.pipenum = __cpu_to_le32(2),
1482 	},
1483 	{
1484 		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL),
1485 		.pipedir = __cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
1486 		.pipenum = __cpu_to_le32(0),
1487 	},
1488 	{
1489 		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL),
1490 		.pipedir = __cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
1491 		.pipenum = __cpu_to_le32(1),
1492 	},
1493 	{ /* not used */
1494 		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS),
1495 		.pipedir = __cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
1496 		.pipenum = __cpu_to_le32(0),
1497 	},
1498 	{ /* not used */
1499 		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS),
1500 		.pipedir = __cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
1501 		.pipenum = __cpu_to_le32(1),
1502 	},
1503 	{
1504 		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG),
1505 		.pipedir = __cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
1506 		.pipenum = __cpu_to_le32(4),
1507 	},
1508 	{
1509 		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG),
1510 		.pipedir = __cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
1511 		.pipenum = __cpu_to_le32(1),
1512 	},
1513 	{
1514 		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG),
1515 		.pipedir = __cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
1516 		.pipenum = __cpu_to_le32(5),
1517 	},
1518 
1519 	/* (Additions here) */
1520 
1521 	{ /* terminator entry */ }
1522 };
1523 
1524 /* Target firmware's Copy Engine configuration. */
1525 const struct ce_pipe_config ath11k_target_ce_config_wlan_qca6390[] = {
1526 	/* CE0: host->target HTC control and raw streams */
1527 	{
1528 		.pipenum = __cpu_to_le32(0),
1529 		.pipedir = __cpu_to_le32(PIPEDIR_OUT),
1530 		.nentries = __cpu_to_le32(32),
1531 		.nbytes_max = __cpu_to_le32(2048),
1532 		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
1533 		.reserved = __cpu_to_le32(0),
1534 	},
1535 
1536 	/* CE1: target->host HTT + HTC control */
1537 	{
1538 		.pipenum = __cpu_to_le32(1),
1539 		.pipedir = __cpu_to_le32(PIPEDIR_IN),
1540 		.nentries = __cpu_to_le32(32),
1541 		.nbytes_max = __cpu_to_le32(2048),
1542 		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
1543 		.reserved = __cpu_to_le32(0),
1544 	},
1545 
1546 	/* CE2: target->host WMI */
1547 	{
1548 		.pipenum = __cpu_to_le32(2),
1549 		.pipedir = __cpu_to_le32(PIPEDIR_IN),
1550 		.nentries = __cpu_to_le32(32),
1551 		.nbytes_max = __cpu_to_le32(2048),
1552 		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
1553 		.reserved = __cpu_to_le32(0),
1554 	},
1555 
1556 	/* CE3: host->target WMI */
1557 	{
1558 		.pipenum = __cpu_to_le32(3),
1559 		.pipedir = __cpu_to_le32(PIPEDIR_OUT),
1560 		.nentries = __cpu_to_le32(32),
1561 		.nbytes_max = __cpu_to_le32(2048),
1562 		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
1563 		.reserved = __cpu_to_le32(0),
1564 	},
1565 
1566 	/* CE4: host->target HTT */
1567 	{
1568 		.pipenum = __cpu_to_le32(4),
1569 		.pipedir = __cpu_to_le32(PIPEDIR_OUT),
1570 		.nentries = __cpu_to_le32(256),
1571 		.nbytes_max = __cpu_to_le32(256),
1572 		.flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
1573 		.reserved = __cpu_to_le32(0),
1574 	},
1575 
1576 	/* CE5: target->host Pktlog */
1577 	{
1578 		.pipenum = __cpu_to_le32(5),
1579 		.pipedir = __cpu_to_le32(PIPEDIR_IN),
1580 		.nentries = __cpu_to_le32(32),
1581 		.nbytes_max = __cpu_to_le32(2048),
1582 		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
1583 		.reserved = __cpu_to_le32(0),
1584 	},
1585 
1586 	/* CE6: Reserved for target autonomous hif_memcpy */
1587 	{
1588 		.pipenum = __cpu_to_le32(6),
1589 		.pipedir = __cpu_to_le32(PIPEDIR_INOUT),
1590 		.nentries = __cpu_to_le32(32),
1591 		.nbytes_max = __cpu_to_le32(16384),
1592 		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
1593 		.reserved = __cpu_to_le32(0),
1594 	},
1595 
1596 	/* CE7 used only by Host */
1597 	{
1598 		.pipenum = __cpu_to_le32(7),
1599 		.pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H),
1600 		.nentries = __cpu_to_le32(0),
1601 		.nbytes_max = __cpu_to_le32(0),
1602 		.flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
1603 		.reserved = __cpu_to_le32(0),
1604 	},
1605 
1606 	/* CE8 target->host used only by IPA */
1607 	{
1608 		.pipenum = __cpu_to_le32(8),
1609 		.pipedir = __cpu_to_le32(PIPEDIR_INOUT),
1610 		.nentries = __cpu_to_le32(32),
1611 		.nbytes_max = __cpu_to_le32(16384),
1612 		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
1613 		.reserved = __cpu_to_le32(0),
1614 	},
1615 	/* CE 9, 10, 11 are used by MHI driver */
1616 };
1617 
1618 /* Map from service/endpoint to Copy Engine.
1619  * This table is derived from the CE_PCI TABLE, above.
1620  * It is passed to the Target at startup for use by firmware.
1621  */
1622 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qca6390[] = {
1623 	{
1624 		__cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO),
1625 		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
1626 		__cpu_to_le32(3),
1627 	},
1628 	{
1629 		__cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO),
1630 		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
1631 		__cpu_to_le32(2),
1632 	},
1633 	{
1634 		__cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK),
1635 		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
1636 		__cpu_to_le32(3),
1637 	},
1638 	{
1639 		__cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK),
1640 		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
1641 		__cpu_to_le32(2),
1642 	},
1643 	{
1644 		__cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE),
1645 		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
1646 		__cpu_to_le32(3),
1647 	},
1648 	{
1649 		__cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE),
1650 		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
1651 		__cpu_to_le32(2),
1652 	},
1653 	{
1654 		__cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI),
1655 		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
1656 		__cpu_to_le32(3),
1657 	},
1658 	{
1659 		__cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI),
1660 		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
1661 		__cpu_to_le32(2),
1662 	},
1663 	{
1664 		__cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL),
1665 		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
1666 		__cpu_to_le32(3),
1667 	},
1668 	{
1669 		__cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL),
1670 		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
1671 		__cpu_to_le32(2),
1672 	},
1673 	{
1674 		__cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL),
1675 		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
1676 		__cpu_to_le32(0),
1677 	},
1678 	{
1679 		__cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL),
1680 		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
1681 		__cpu_to_le32(2),
1682 	},
1683 	{
1684 		__cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG),
1685 		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
1686 		__cpu_to_le32(4),
1687 	},
1688 	{
1689 		__cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG),
1690 		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
1691 		__cpu_to_le32(1),
1692 	},
1693 
1694 	/* (Additions here) */
1695 
1696 	{ /* must be last */
1697 		__cpu_to_le32(0),
1698 		__cpu_to_le32(0),
1699 		__cpu_to_le32(0),
1700 	},
1701 };
1702 
1703 /* Target firmware's Copy Engine configuration. */
1704 const struct ce_pipe_config ath11k_target_ce_config_wlan_qcn9074[] = {
1705 	/* CE0: host->target HTC control and raw streams */
1706 	{
1707 		.pipenum = __cpu_to_le32(0),
1708 		.pipedir = __cpu_to_le32(PIPEDIR_OUT),
1709 		.nentries = __cpu_to_le32(32),
1710 		.nbytes_max = __cpu_to_le32(2048),
1711 		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
1712 		.reserved = __cpu_to_le32(0),
1713 	},
1714 
1715 	/* CE1: target->host HTT + HTC control */
1716 	{
1717 		.pipenum = __cpu_to_le32(1),
1718 		.pipedir = __cpu_to_le32(PIPEDIR_IN),
1719 		.nentries = __cpu_to_le32(32),
1720 		.nbytes_max = __cpu_to_le32(2048),
1721 		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
1722 		.reserved = __cpu_to_le32(0),
1723 	},
1724 
1725 	/* CE2: target->host WMI */
1726 	{
1727 		.pipenum = __cpu_to_le32(2),
1728 		.pipedir = __cpu_to_le32(PIPEDIR_IN),
1729 		.nentries = __cpu_to_le32(32),
1730 		.nbytes_max = __cpu_to_le32(2048),
1731 		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
1732 		.reserved = __cpu_to_le32(0),
1733 	},
1734 
1735 	/* CE3: host->target WMI */
1736 	{
1737 		.pipenum = __cpu_to_le32(3),
1738 		.pipedir = __cpu_to_le32(PIPEDIR_OUT),
1739 		.nentries = __cpu_to_le32(32),
1740 		.nbytes_max = __cpu_to_le32(2048),
1741 		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
1742 		.reserved = __cpu_to_le32(0),
1743 	},
1744 
1745 	/* CE4: host->target HTT */
1746 	{
1747 		.pipenum = __cpu_to_le32(4),
1748 		.pipedir = __cpu_to_le32(PIPEDIR_OUT),
1749 		.nentries = __cpu_to_le32(256),
1750 		.nbytes_max = __cpu_to_le32(256),
1751 		.flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
1752 		.reserved = __cpu_to_le32(0),
1753 	},
1754 
1755 	/* CE5: target->host Pktlog */
1756 	{
1757 		.pipenum = __cpu_to_le32(5),
1758 		.pipedir = __cpu_to_le32(PIPEDIR_IN),
1759 		.nentries = __cpu_to_le32(32),
1760 		.nbytes_max = __cpu_to_le32(2048),
1761 		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
1762 		.reserved = __cpu_to_le32(0),
1763 	},
1764 
1765 	/* CE6: Reserved for target autonomous hif_memcpy */
1766 	{
1767 		.pipenum = __cpu_to_le32(6),
1768 		.pipedir = __cpu_to_le32(PIPEDIR_INOUT),
1769 		.nentries = __cpu_to_le32(32),
1770 		.nbytes_max = __cpu_to_le32(16384),
1771 		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
1772 		.reserved = __cpu_to_le32(0),
1773 	},
1774 
1775 	/* CE7 used only by Host */
1776 	{
1777 		.pipenum = __cpu_to_le32(7),
1778 		.pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H),
1779 		.nentries = __cpu_to_le32(0),
1780 		.nbytes_max = __cpu_to_le32(0),
1781 		.flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
1782 		.reserved = __cpu_to_le32(0),
1783 	},
1784 
1785 	/* CE8 target->host used only by IPA */
1786 	{
1787 		.pipenum = __cpu_to_le32(8),
1788 		.pipedir = __cpu_to_le32(PIPEDIR_INOUT),
1789 		.nentries = __cpu_to_le32(32),
1790 		.nbytes_max = __cpu_to_le32(16384),
1791 		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
1792 		.reserved = __cpu_to_le32(0),
1793 	},
1794 	/* CE 9, 10, 11 are used by MHI driver */
1795 };
1796 
1797 /* Map from service/endpoint to Copy Engine.
1798  * This table is derived from the CE_PCI TABLE, above.
1799  * It is passed to the Target at startup for use by firmware.
1800  */
1801 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qcn9074[] = {
1802 	{
1803 		__cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO),
1804 		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
1805 		__cpu_to_le32(3),
1806 	},
1807 	{
1808 		__cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO),
1809 		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
1810 		__cpu_to_le32(2),
1811 	},
1812 	{
1813 		__cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK),
1814 		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
1815 		__cpu_to_le32(3),
1816 	},
1817 	{
1818 		__cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK),
1819 		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
1820 		__cpu_to_le32(2),
1821 	},
1822 	{
1823 		__cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE),
1824 		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
1825 		__cpu_to_le32(3),
1826 	},
1827 	{
1828 		__cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE),
1829 		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
1830 		__cpu_to_le32(2),
1831 	},
1832 	{
1833 		__cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI),
1834 		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
1835 		__cpu_to_le32(3),
1836 	},
1837 	{
1838 		__cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI),
1839 		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
1840 		__cpu_to_le32(2),
1841 	},
1842 	{
1843 		__cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL),
1844 		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
1845 		__cpu_to_le32(3),
1846 	},
1847 	{
1848 		__cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL),
1849 		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
1850 		__cpu_to_le32(2),
1851 	},
1852 	{
1853 		__cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL),
1854 		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
1855 		__cpu_to_le32(0),
1856 	},
1857 	{
1858 		__cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL),
1859 		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
1860 		__cpu_to_le32(1),
1861 	},
1862 	{
1863 		__cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS),
1864 		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
1865 		__cpu_to_le32(0),
1866 	},
1867 	{
1868 		__cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS),
1869 		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
1870 		__cpu_to_le32(1),
1871 	},
1872 	{
1873 		__cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG),
1874 		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
1875 		__cpu_to_le32(4),
1876 	},
1877 	{
1878 		__cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG),
1879 		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
1880 		__cpu_to_le32(1),
1881 	},
1882 	{
1883 		__cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG),
1884 		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
1885 		__cpu_to_le32(5),
1886 	},
1887 
1888 	/* (Additions here) */
1889 
1890 	{ /* must be last */
1891 		__cpu_to_le32(0),
1892 		__cpu_to_le32(0),
1893 		__cpu_to_le32(0),
1894 	},
1895 };
1896 
1897 const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qcn9074 = {
1898 	.tx  = {
1899 		ATH11K_TX_RING_MASK_0,
1900 		ATH11K_TX_RING_MASK_1,
1901 		ATH11K_TX_RING_MASK_2,
1902 	},
1903 	.rx_mon_status = {
1904 		0, 0, 0,
1905 		ATH11K_RX_MON_STATUS_RING_MASK_0,
1906 		ATH11K_RX_MON_STATUS_RING_MASK_1,
1907 		ATH11K_RX_MON_STATUS_RING_MASK_2,
1908 	},
1909 	.rx = {
1910 		0, 0, 0, 0,
1911 		ATH11K_RX_RING_MASK_0,
1912 		ATH11K_RX_RING_MASK_1,
1913 		ATH11K_RX_RING_MASK_2,
1914 		ATH11K_RX_RING_MASK_3,
1915 	},
1916 	.rx_err = {
1917 		0, 0, 0,
1918 		ATH11K_RX_ERR_RING_MASK_0,
1919 	},
1920 	.rx_wbm_rel = {
1921 		0, 0, 0,
1922 		ATH11K_RX_WBM_REL_RING_MASK_0,
1923 	},
1924 	.reo_status = {
1925 		0, 0, 0,
1926 		ATH11K_REO_STATUS_RING_MASK_0,
1927 	},
1928 	.rxdma2host = {
1929 		0, 0, 0,
1930 		ATH11K_RXDMA2HOST_RING_MASK_0,
1931 	},
1932 	.host2rxdma = {
1933 		0, 0, 0,
1934 		ATH11K_HOST2RXDMA_RING_MASK_0,
1935 	},
1936 };
1937 
1938 const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_wcn6750 = {
1939 	.tx  = {
1940 		ATH11K_TX_RING_MASK_0,
1941 		0,
1942 		ATH11K_TX_RING_MASK_2,
1943 		0,
1944 		ATH11K_TX_RING_MASK_4,
1945 	},
1946 	.rx_mon_status = {
1947 		0, 0, 0, 0, 0, 0,
1948 		ATH11K_RX_MON_STATUS_RING_MASK_0,
1949 	},
1950 	.rx = {
1951 		0, 0, 0, 0, 0, 0, 0,
1952 		ATH11K_RX_RING_MASK_0,
1953 		ATH11K_RX_RING_MASK_1,
1954 		ATH11K_RX_RING_MASK_2,
1955 		ATH11K_RX_RING_MASK_3,
1956 	},
1957 	.rx_err = {
1958 		0, ATH11K_RX_ERR_RING_MASK_0,
1959 	},
1960 	.rx_wbm_rel = {
1961 		0, ATH11K_RX_WBM_REL_RING_MASK_0,
1962 	},
1963 	.reo_status = {
1964 		0, ATH11K_REO_STATUS_RING_MASK_0,
1965 	},
1966 	.rxdma2host = {
1967 		ATH11K_RXDMA2HOST_RING_MASK_0,
1968 		ATH11K_RXDMA2HOST_RING_MASK_1,
1969 		ATH11K_RXDMA2HOST_RING_MASK_2,
1970 	},
1971 	.host2rxdma = {
1972 	},
1973 };
1974 
1975 const struct ath11k_hw_regs ipq8074_regs = {
1976 	/* SW2TCL(x) R0 ring configuration address */
1977 	.hal_tcl1_ring_base_lsb = 0x00000510,
1978 	.hal_tcl1_ring_base_msb = 0x00000514,
1979 	.hal_tcl1_ring_id = 0x00000518,
1980 	.hal_tcl1_ring_misc = 0x00000520,
1981 	.hal_tcl1_ring_tp_addr_lsb = 0x0000052c,
1982 	.hal_tcl1_ring_tp_addr_msb = 0x00000530,
1983 	.hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000540,
1984 	.hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000544,
1985 	.hal_tcl1_ring_msi1_base_lsb = 0x00000558,
1986 	.hal_tcl1_ring_msi1_base_msb = 0x0000055c,
1987 	.hal_tcl1_ring_msi1_data = 0x00000560,
1988 	.hal_tcl2_ring_base_lsb = 0x00000568,
1989 	.hal_tcl_ring_base_lsb = 0x00000618,
1990 
1991 	/* TCL STATUS ring address */
1992 	.hal_tcl_status_ring_base_lsb = 0x00000720,
1993 
1994 	/* REO2SW(x) R0 ring configuration address */
1995 	.hal_reo1_ring_base_lsb = 0x0000029c,
1996 	.hal_reo1_ring_base_msb = 0x000002a0,
1997 	.hal_reo1_ring_id = 0x000002a4,
1998 	.hal_reo1_ring_misc = 0x000002ac,
1999 	.hal_reo1_ring_hp_addr_lsb = 0x000002b0,
2000 	.hal_reo1_ring_hp_addr_msb = 0x000002b4,
2001 	.hal_reo1_ring_producer_int_setup = 0x000002c0,
2002 	.hal_reo1_ring_msi1_base_lsb = 0x000002e4,
2003 	.hal_reo1_ring_msi1_base_msb = 0x000002e8,
2004 	.hal_reo1_ring_msi1_data = 0x000002ec,
2005 	.hal_reo2_ring_base_lsb = 0x000002f4,
2006 	.hal_reo1_aging_thresh_ix_0 = 0x00000564,
2007 	.hal_reo1_aging_thresh_ix_1 = 0x00000568,
2008 	.hal_reo1_aging_thresh_ix_2 = 0x0000056c,
2009 	.hal_reo1_aging_thresh_ix_3 = 0x00000570,
2010 
2011 	/* REO2SW(x) R2 ring pointers (head/tail) address */
2012 	.hal_reo1_ring_hp = 0x00003038,
2013 	.hal_reo1_ring_tp = 0x0000303c,
2014 	.hal_reo2_ring_hp = 0x00003040,
2015 
2016 	/* REO2TCL R0 ring configuration address */
2017 	.hal_reo_tcl_ring_base_lsb = 0x000003fc,
2018 	.hal_reo_tcl_ring_hp = 0x00003058,
2019 
2020 	/* REO CMD ring address */
2021 	.hal_reo_cmd_ring_base_lsb = 0x00000194,
2022 	.hal_reo_cmd_ring_hp = 0x00003020,
2023 
2024 	/* REO status address */
2025 	.hal_reo_status_ring_base_lsb = 0x00000504,
2026 	.hal_reo_status_hp = 0x00003070,
2027 
2028 	/* SW2REO ring address */
2029 	.hal_sw2reo_ring_base_lsb = 0x000001ec,
2030 	.hal_sw2reo_ring_hp = 0x00003028,
2031 
2032 	/* WCSS relative address */
2033 	.hal_seq_wcss_umac_ce0_src_reg = 0x00a00000,
2034 	.hal_seq_wcss_umac_ce0_dst_reg = 0x00a01000,
2035 	.hal_seq_wcss_umac_ce1_src_reg = 0x00a02000,
2036 	.hal_seq_wcss_umac_ce1_dst_reg = 0x00a03000,
2037 
2038 	/* WBM Idle address */
2039 	.hal_wbm_idle_link_ring_base_lsb = 0x00000860,
2040 	.hal_wbm_idle_link_ring_misc = 0x00000870,
2041 
2042 	/* SW2WBM release address */
2043 	.hal_wbm_release_ring_base_lsb = 0x000001d8,
2044 
2045 	/* WBM2SW release address */
2046 	.hal_wbm0_release_ring_base_lsb = 0x00000910,
2047 	.hal_wbm1_release_ring_base_lsb = 0x00000968,
2048 
2049 	/* PCIe base address */
2050 	.pcie_qserdes_sysclk_en_sel = 0x0,
2051 	.pcie_pcs_osc_dtct_config_base = 0x0,
2052 
2053 	/* Shadow register area */
2054 	.hal_shadow_base_addr = 0x0,
2055 
2056 	/* REO misc control register, not used in IPQ8074 */
2057 	.hal_reo1_misc_ctl = 0x0,
2058 };
2059 
2060 const struct ath11k_hw_regs qca6390_regs = {
2061 	/* SW2TCL(x) R0 ring configuration address */
2062 	.hal_tcl1_ring_base_lsb = 0x00000684,
2063 	.hal_tcl1_ring_base_msb = 0x00000688,
2064 	.hal_tcl1_ring_id = 0x0000068c,
2065 	.hal_tcl1_ring_misc = 0x00000694,
2066 	.hal_tcl1_ring_tp_addr_lsb = 0x000006a0,
2067 	.hal_tcl1_ring_tp_addr_msb = 0x000006a4,
2068 	.hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006b4,
2069 	.hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006b8,
2070 	.hal_tcl1_ring_msi1_base_lsb = 0x000006cc,
2071 	.hal_tcl1_ring_msi1_base_msb = 0x000006d0,
2072 	.hal_tcl1_ring_msi1_data = 0x000006d4,
2073 	.hal_tcl2_ring_base_lsb = 0x000006dc,
2074 	.hal_tcl_ring_base_lsb = 0x0000078c,
2075 
2076 	/* TCL STATUS ring address */
2077 	.hal_tcl_status_ring_base_lsb = 0x00000894,
2078 
2079 	/* REO2SW(x) R0 ring configuration address */
2080 	.hal_reo1_ring_base_lsb = 0x00000244,
2081 	.hal_reo1_ring_base_msb = 0x00000248,
2082 	.hal_reo1_ring_id = 0x0000024c,
2083 	.hal_reo1_ring_misc = 0x00000254,
2084 	.hal_reo1_ring_hp_addr_lsb = 0x00000258,
2085 	.hal_reo1_ring_hp_addr_msb = 0x0000025c,
2086 	.hal_reo1_ring_producer_int_setup = 0x00000268,
2087 	.hal_reo1_ring_msi1_base_lsb = 0x0000028c,
2088 	.hal_reo1_ring_msi1_base_msb = 0x00000290,
2089 	.hal_reo1_ring_msi1_data = 0x00000294,
2090 	.hal_reo2_ring_base_lsb = 0x0000029c,
2091 	.hal_reo1_aging_thresh_ix_0 = 0x0000050c,
2092 	.hal_reo1_aging_thresh_ix_1 = 0x00000510,
2093 	.hal_reo1_aging_thresh_ix_2 = 0x00000514,
2094 	.hal_reo1_aging_thresh_ix_3 = 0x00000518,
2095 
2096 	/* REO2SW(x) R2 ring pointers (head/tail) address */
2097 	.hal_reo1_ring_hp = 0x00003030,
2098 	.hal_reo1_ring_tp = 0x00003034,
2099 	.hal_reo2_ring_hp = 0x00003038,
2100 
2101 	/* REO2TCL R0 ring configuration address */
2102 	.hal_reo_tcl_ring_base_lsb = 0x000003a4,
2103 	.hal_reo_tcl_ring_hp = 0x00003050,
2104 
2105 	/* REO CMD ring address */
2106 	.hal_reo_cmd_ring_base_lsb = 0x00000194,
2107 	.hal_reo_cmd_ring_hp = 0x00003020,
2108 
2109 	/* REO status address */
2110 	.hal_reo_status_ring_base_lsb = 0x000004ac,
2111 	.hal_reo_status_hp = 0x00003068,
2112 
2113 	/* SW2REO ring address */
2114 	.hal_sw2reo_ring_base_lsb = 0x000001ec,
2115 	.hal_sw2reo_ring_hp = 0x00003028,
2116 
2117 	/* WCSS relative address */
2118 	.hal_seq_wcss_umac_ce0_src_reg = 0x00a00000,
2119 	.hal_seq_wcss_umac_ce0_dst_reg = 0x00a01000,
2120 	.hal_seq_wcss_umac_ce1_src_reg = 0x00a02000,
2121 	.hal_seq_wcss_umac_ce1_dst_reg = 0x00a03000,
2122 
2123 	/* WBM Idle address */
2124 	.hal_wbm_idle_link_ring_base_lsb = 0x00000860,
2125 	.hal_wbm_idle_link_ring_misc = 0x00000870,
2126 
2127 	/* SW2WBM release address */
2128 	.hal_wbm_release_ring_base_lsb = 0x000001d8,
2129 
2130 	/* WBM2SW release address */
2131 	.hal_wbm0_release_ring_base_lsb = 0x00000910,
2132 	.hal_wbm1_release_ring_base_lsb = 0x00000968,
2133 
2134 	/* PCIe base address */
2135 	.pcie_qserdes_sysclk_en_sel = 0x01e0c0ac,
2136 	.pcie_pcs_osc_dtct_config_base = 0x01e0c628,
2137 
2138 	/* Shadow register area */
2139 	.hal_shadow_base_addr = 0x000008fc,
2140 
2141 	/* REO misc control register, not used in QCA6390 */
2142 	.hal_reo1_misc_ctl = 0x0,
2143 };
2144 
2145 const struct ath11k_hw_regs qcn9074_regs = {
2146 	/* SW2TCL(x) R0 ring configuration address */
2147 	.hal_tcl1_ring_base_lsb = 0x000004f0,
2148 	.hal_tcl1_ring_base_msb = 0x000004f4,
2149 	.hal_tcl1_ring_id = 0x000004f8,
2150 	.hal_tcl1_ring_misc = 0x00000500,
2151 	.hal_tcl1_ring_tp_addr_lsb = 0x0000050c,
2152 	.hal_tcl1_ring_tp_addr_msb = 0x00000510,
2153 	.hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000520,
2154 	.hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000524,
2155 	.hal_tcl1_ring_msi1_base_lsb = 0x00000538,
2156 	.hal_tcl1_ring_msi1_base_msb = 0x0000053c,
2157 	.hal_tcl1_ring_msi1_data = 0x00000540,
2158 	.hal_tcl2_ring_base_lsb = 0x00000548,
2159 	.hal_tcl_ring_base_lsb = 0x000005f8,
2160 
2161 	/* TCL STATUS ring address */
2162 	.hal_tcl_status_ring_base_lsb = 0x00000700,
2163 
2164 	/* REO2SW(x) R0 ring configuration address */
2165 	.hal_reo1_ring_base_lsb = 0x0000029c,
2166 	.hal_reo1_ring_base_msb = 0x000002a0,
2167 	.hal_reo1_ring_id = 0x000002a4,
2168 	.hal_reo1_ring_misc = 0x000002ac,
2169 	.hal_reo1_ring_hp_addr_lsb = 0x000002b0,
2170 	.hal_reo1_ring_hp_addr_msb = 0x000002b4,
2171 	.hal_reo1_ring_producer_int_setup = 0x000002c0,
2172 	.hal_reo1_ring_msi1_base_lsb = 0x000002e4,
2173 	.hal_reo1_ring_msi1_base_msb = 0x000002e8,
2174 	.hal_reo1_ring_msi1_data = 0x000002ec,
2175 	.hal_reo2_ring_base_lsb = 0x000002f4,
2176 	.hal_reo1_aging_thresh_ix_0 = 0x00000564,
2177 	.hal_reo1_aging_thresh_ix_1 = 0x00000568,
2178 	.hal_reo1_aging_thresh_ix_2 = 0x0000056c,
2179 	.hal_reo1_aging_thresh_ix_3 = 0x00000570,
2180 
2181 	/* REO2SW(x) R2 ring pointers (head/tail) address */
2182 	.hal_reo1_ring_hp = 0x00003038,
2183 	.hal_reo1_ring_tp = 0x0000303c,
2184 	.hal_reo2_ring_hp = 0x00003040,
2185 
2186 	/* REO2TCL R0 ring configuration address */
2187 	.hal_reo_tcl_ring_base_lsb = 0x000003fc,
2188 	.hal_reo_tcl_ring_hp = 0x00003058,
2189 
2190 	/* REO CMD ring address */
2191 	.hal_reo_cmd_ring_base_lsb = 0x00000194,
2192 	.hal_reo_cmd_ring_hp = 0x00003020,
2193 
2194 	/* REO status address */
2195 	.hal_reo_status_ring_base_lsb = 0x00000504,
2196 	.hal_reo_status_hp = 0x00003070,
2197 
2198 	/* SW2REO ring address */
2199 	.hal_sw2reo_ring_base_lsb = 0x000001ec,
2200 	.hal_sw2reo_ring_hp = 0x00003028,
2201 
2202 	/* WCSS relative address */
2203 	.hal_seq_wcss_umac_ce0_src_reg = 0x01b80000,
2204 	.hal_seq_wcss_umac_ce0_dst_reg = 0x01b81000,
2205 	.hal_seq_wcss_umac_ce1_src_reg = 0x01b82000,
2206 	.hal_seq_wcss_umac_ce1_dst_reg = 0x01b83000,
2207 
2208 	/* WBM Idle address */
2209 	.hal_wbm_idle_link_ring_base_lsb = 0x00000874,
2210 	.hal_wbm_idle_link_ring_misc = 0x00000884,
2211 
2212 	/* SW2WBM release address */
2213 	.hal_wbm_release_ring_base_lsb = 0x000001ec,
2214 
2215 	/* WBM2SW release address */
2216 	.hal_wbm0_release_ring_base_lsb = 0x00000924,
2217 	.hal_wbm1_release_ring_base_lsb = 0x0000097c,
2218 
2219 	/* PCIe base address */
2220 	.pcie_qserdes_sysclk_en_sel = 0x01e0e0a8,
2221 	.pcie_pcs_osc_dtct_config_base = 0x01e0f45c,
2222 
2223 	/* Shadow register area */
2224 	.hal_shadow_base_addr = 0x0,
2225 
2226 	/* REO misc control register, not used in QCN9074 */
2227 	.hal_reo1_misc_ctl = 0x0,
2228 };
2229 
2230 const struct ath11k_hw_regs wcn6855_regs = {
2231 	/* SW2TCL(x) R0 ring configuration address */
2232 	.hal_tcl1_ring_base_lsb = 0x00000690,
2233 	.hal_tcl1_ring_base_msb = 0x00000694,
2234 	.hal_tcl1_ring_id = 0x00000698,
2235 	.hal_tcl1_ring_misc = 0x000006a0,
2236 	.hal_tcl1_ring_tp_addr_lsb = 0x000006ac,
2237 	.hal_tcl1_ring_tp_addr_msb = 0x000006b0,
2238 	.hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006c0,
2239 	.hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006c4,
2240 	.hal_tcl1_ring_msi1_base_lsb = 0x000006d8,
2241 	.hal_tcl1_ring_msi1_base_msb = 0x000006dc,
2242 	.hal_tcl1_ring_msi1_data = 0x000006e0,
2243 	.hal_tcl2_ring_base_lsb = 0x000006e8,
2244 	.hal_tcl_ring_base_lsb = 0x00000798,
2245 
2246 	/* TCL STATUS ring address */
2247 	.hal_tcl_status_ring_base_lsb = 0x000008a0,
2248 
2249 	/* REO2SW(x) R0 ring configuration address */
2250 	.hal_reo1_ring_base_lsb = 0x00000244,
2251 	.hal_reo1_ring_base_msb = 0x00000248,
2252 	.hal_reo1_ring_id = 0x0000024c,
2253 	.hal_reo1_ring_misc = 0x00000254,
2254 	.hal_reo1_ring_hp_addr_lsb = 0x00000258,
2255 	.hal_reo1_ring_hp_addr_msb = 0x0000025c,
2256 	.hal_reo1_ring_producer_int_setup = 0x00000268,
2257 	.hal_reo1_ring_msi1_base_lsb = 0x0000028c,
2258 	.hal_reo1_ring_msi1_base_msb = 0x00000290,
2259 	.hal_reo1_ring_msi1_data = 0x00000294,
2260 	.hal_reo2_ring_base_lsb = 0x0000029c,
2261 	.hal_reo1_aging_thresh_ix_0 = 0x000005bc,
2262 	.hal_reo1_aging_thresh_ix_1 = 0x000005c0,
2263 	.hal_reo1_aging_thresh_ix_2 = 0x000005c4,
2264 	.hal_reo1_aging_thresh_ix_3 = 0x000005c8,
2265 
2266 	/* REO2SW(x) R2 ring pointers (head/tail) address */
2267 	.hal_reo1_ring_hp = 0x00003030,
2268 	.hal_reo1_ring_tp = 0x00003034,
2269 	.hal_reo2_ring_hp = 0x00003038,
2270 
2271 	/* REO2TCL R0 ring configuration address */
2272 	.hal_reo_tcl_ring_base_lsb = 0x00000454,
2273 	.hal_reo_tcl_ring_hp = 0x00003060,
2274 
2275 	/* REO CMD ring address */
2276 	.hal_reo_cmd_ring_base_lsb = 0x00000194,
2277 	.hal_reo_cmd_ring_hp = 0x00003020,
2278 
2279 	/* REO status address */
2280 	.hal_reo_status_ring_base_lsb = 0x0000055c,
2281 	.hal_reo_status_hp = 0x00003078,
2282 
2283 	/* SW2REO ring address */
2284 	.hal_sw2reo_ring_base_lsb = 0x000001ec,
2285 	.hal_sw2reo_ring_hp = 0x00003028,
2286 
2287 	/* WCSS relative address */
2288 	.hal_seq_wcss_umac_ce0_src_reg = 0x1b80000,
2289 	.hal_seq_wcss_umac_ce0_dst_reg = 0x1b81000,
2290 	.hal_seq_wcss_umac_ce1_src_reg = 0x1b82000,
2291 	.hal_seq_wcss_umac_ce1_dst_reg = 0x1b83000,
2292 
2293 	/* WBM Idle address */
2294 	.hal_wbm_idle_link_ring_base_lsb = 0x00000870,
2295 	.hal_wbm_idle_link_ring_misc = 0x00000880,
2296 
2297 	/* SW2WBM release address */
2298 	.hal_wbm_release_ring_base_lsb = 0x000001e8,
2299 
2300 	/* WBM2SW release address */
2301 	.hal_wbm0_release_ring_base_lsb = 0x00000920,
2302 	.hal_wbm1_release_ring_base_lsb = 0x00000978,
2303 
2304 	/* PCIe base address */
2305 	.pcie_qserdes_sysclk_en_sel = 0x01e0c0ac,
2306 	.pcie_pcs_osc_dtct_config_base = 0x01e0c628,
2307 
2308 	/* Shadow register area */
2309 	.hal_shadow_base_addr = 0x000008fc,
2310 
2311 	/* REO misc control register, used for fragment
2312 	 * destination ring config in WCN6855.
2313 	 */
2314 	.hal_reo1_misc_ctl = 0x00000630,
2315 };
2316 
2317 const struct ath11k_hw_regs wcn6750_regs = {
2318 	/* SW2TCL(x) R0 ring configuration address */
2319 	.hal_tcl1_ring_base_lsb = 0x00000694,
2320 	.hal_tcl1_ring_base_msb = 0x00000698,
2321 	.hal_tcl1_ring_id = 0x0000069c,
2322 	.hal_tcl1_ring_misc = 0x000006a4,
2323 	.hal_tcl1_ring_tp_addr_lsb = 0x000006b0,
2324 	.hal_tcl1_ring_tp_addr_msb = 0x000006b4,
2325 	.hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006c4,
2326 	.hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006c8,
2327 	.hal_tcl1_ring_msi1_base_lsb = 0x000006dc,
2328 	.hal_tcl1_ring_msi1_base_msb = 0x000006e0,
2329 	.hal_tcl1_ring_msi1_data = 0x000006e4,
2330 	.hal_tcl2_ring_base_lsb = 0x000006ec,
2331 	.hal_tcl_ring_base_lsb = 0x0000079c,
2332 
2333 	/* TCL STATUS ring address */
2334 	.hal_tcl_status_ring_base_lsb = 0x000008a4,
2335 
2336 	/* REO2SW(x) R0 ring configuration address */
2337 	.hal_reo1_ring_base_lsb = 0x000001ec,
2338 	.hal_reo1_ring_base_msb = 0x000001f0,
2339 	.hal_reo1_ring_id = 0x000001f4,
2340 	.hal_reo1_ring_misc = 0x000001fc,
2341 	.hal_reo1_ring_hp_addr_lsb = 0x00000200,
2342 	.hal_reo1_ring_hp_addr_msb = 0x00000204,
2343 	.hal_reo1_ring_producer_int_setup = 0x00000210,
2344 	.hal_reo1_ring_msi1_base_lsb = 0x00000234,
2345 	.hal_reo1_ring_msi1_base_msb = 0x00000238,
2346 	.hal_reo1_ring_msi1_data = 0x0000023c,
2347 	.hal_reo2_ring_base_lsb = 0x00000244,
2348 	.hal_reo1_aging_thresh_ix_0 = 0x00000564,
2349 	.hal_reo1_aging_thresh_ix_1 = 0x00000568,
2350 	.hal_reo1_aging_thresh_ix_2 = 0x0000056c,
2351 	.hal_reo1_aging_thresh_ix_3 = 0x00000570,
2352 
2353 	/* REO2SW(x) R2 ring pointers (head/tail) address */
2354 	.hal_reo1_ring_hp = 0x00003028,
2355 	.hal_reo1_ring_tp = 0x0000302c,
2356 	.hal_reo2_ring_hp = 0x00003030,
2357 
2358 	/* REO2TCL R0 ring configuration address */
2359 	.hal_reo_tcl_ring_base_lsb = 0x000003fc,
2360 	.hal_reo_tcl_ring_hp = 0x00003058,
2361 
2362 	/* REO CMD ring address */
2363 	.hal_reo_cmd_ring_base_lsb = 0x000000e4,
2364 	.hal_reo_cmd_ring_hp = 0x00003010,
2365 
2366 	/* REO status address */
2367 	.hal_reo_status_ring_base_lsb = 0x00000504,
2368 	.hal_reo_status_hp = 0x00003070,
2369 
2370 	/* SW2REO ring address */
2371 	.hal_sw2reo_ring_base_lsb = 0x0000013c,
2372 	.hal_sw2reo_ring_hp = 0x00003018,
2373 
2374 	/* WCSS relative address */
2375 	.hal_seq_wcss_umac_ce0_src_reg = 0x01b80000,
2376 	.hal_seq_wcss_umac_ce0_dst_reg = 0x01b81000,
2377 	.hal_seq_wcss_umac_ce1_src_reg = 0x01b82000,
2378 	.hal_seq_wcss_umac_ce1_dst_reg = 0x01b83000,
2379 
2380 	/* WBM Idle address */
2381 	.hal_wbm_idle_link_ring_base_lsb = 0x00000874,
2382 	.hal_wbm_idle_link_ring_misc = 0x00000884,
2383 
2384 	/* SW2WBM release address */
2385 	.hal_wbm_release_ring_base_lsb = 0x000001ec,
2386 
2387 	/* WBM2SW release address */
2388 	.hal_wbm0_release_ring_base_lsb = 0x00000924,
2389 	.hal_wbm1_release_ring_base_lsb = 0x0000097c,
2390 
2391 	/* PCIe base address */
2392 	.pcie_qserdes_sysclk_en_sel = 0x0,
2393 	.pcie_pcs_osc_dtct_config_base = 0x0,
2394 
2395 	/* Shadow register area */
2396 	.hal_shadow_base_addr = 0x00000504,
2397 
2398 	/* REO misc control register, used for fragment
2399 	 * destination ring config in WCN6750.
2400 	 */
2401 	.hal_reo1_misc_ctl = 0x000005d8,
2402 };
2403 
2404 static const struct ath11k_hw_tcl2wbm_rbm_map ath11k_hw_tcl2wbm_rbm_map_ipq8074[] = {
2405 	{
2406 		.tcl_ring_num = 0,
2407 		.wbm_ring_num = 0,
2408 		.rbm_id = HAL_RX_BUF_RBM_SW0_BM,
2409 	},
2410 	{
2411 		.tcl_ring_num = 1,
2412 		.wbm_ring_num = 1,
2413 		.rbm_id = HAL_RX_BUF_RBM_SW1_BM,
2414 	},
2415 	{
2416 		.tcl_ring_num = 2,
2417 		.wbm_ring_num = 2,
2418 		.rbm_id = HAL_RX_BUF_RBM_SW2_BM,
2419 	},
2420 };
2421 
2422 static const struct ath11k_hw_tcl2wbm_rbm_map ath11k_hw_tcl2wbm_rbm_map_wcn6750[] = {
2423 	{
2424 		.tcl_ring_num = 0,
2425 		.wbm_ring_num = 0,
2426 		.rbm_id = HAL_RX_BUF_RBM_SW0_BM,
2427 	},
2428 	{
2429 		.tcl_ring_num = 1,
2430 		.wbm_ring_num = 4,
2431 		.rbm_id = HAL_RX_BUF_RBM_SW4_BM,
2432 	},
2433 	{
2434 		.tcl_ring_num = 2,
2435 		.wbm_ring_num = 2,
2436 		.rbm_id = HAL_RX_BUF_RBM_SW2_BM,
2437 	},
2438 };
2439 
2440 const struct ath11k_hw_hal_params ath11k_hw_hal_params_ipq8074 = {
2441 	.rx_buf_rbm = HAL_RX_BUF_RBM_SW3_BM,
2442 	.tcl2wbm_rbm_map = ath11k_hw_tcl2wbm_rbm_map_ipq8074,
2443 };
2444 
2445 const struct ath11k_hw_hal_params ath11k_hw_hal_params_qca6390 = {
2446 	.rx_buf_rbm = HAL_RX_BUF_RBM_SW1_BM,
2447 	.tcl2wbm_rbm_map = ath11k_hw_tcl2wbm_rbm_map_ipq8074,
2448 };
2449 
2450 const struct ath11k_hw_hal_params ath11k_hw_hal_params_wcn6750 = {
2451 	.rx_buf_rbm = HAL_RX_BUF_RBM_SW1_BM,
2452 	.tcl2wbm_rbm_map = ath11k_hw_tcl2wbm_rbm_map_wcn6750,
2453 };
2454 
2455 static const struct cfg80211_sar_freq_ranges ath11k_hw_sar_freq_ranges_wcn6855[] = {
2456 	{.start_freq = 2402, .end_freq = 2482 },  /* 2G ch1~ch13 */
2457 	{.start_freq = 5150, .end_freq = 5250 },  /* 5G UNII-1 ch32~ch48 */
2458 	{.start_freq = 5250, .end_freq = 5725 },  /* 5G UNII-2 ch50~ch144 */
2459 	{.start_freq = 5725, .end_freq = 5810 },  /* 5G UNII-3 ch149~ch161 */
2460 	{.start_freq = 5815, .end_freq = 5895 },  /* 5G UNII-4 ch163~ch177 */
2461 	{.start_freq = 5925, .end_freq = 6165 },  /* 6G UNII-5 Ch1, Ch2 ~ Ch41 */
2462 	{.start_freq = 6165, .end_freq = 6425 },  /* 6G UNII-5 ch45~ch93 */
2463 	{.start_freq = 6425, .end_freq = 6525 },  /* 6G UNII-6 ch97~ch113 */
2464 	{.start_freq = 6525, .end_freq = 6705 },  /* 6G UNII-7 ch117~ch149 */
2465 	{.start_freq = 6705, .end_freq = 6875 },  /* 6G UNII-7 ch153~ch185 */
2466 	{.start_freq = 6875, .end_freq = 7125 },  /* 6G UNII-8 ch189~ch233 */
2467 };
2468 
2469 const struct cfg80211_sar_capa ath11k_hw_sar_capa_wcn6855 = {
2470 	.type = NL80211_SAR_TYPE_POWER,
2471 	.num_freq_ranges = (ARRAY_SIZE(ath11k_hw_sar_freq_ranges_wcn6855)),
2472 	.freq_ranges = ath11k_hw_sar_freq_ranges_wcn6855,
2473 };
2474