1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright 2020-2021 NXP
4 */
5
6 #include <linux/init.h>
7 #include <linux/interconnect.h>
8 #include <linux/ioctl.h>
9 #include <linux/list.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/of_address.h>
14 #include <linux/platform_device.h>
15 #include <linux/time64.h>
16 #include <media/videobuf2-v4l2.h>
17 #include <media/videobuf2-dma-contig.h>
18 #include "vpu.h"
19 #include "vpu_rpc.h"
20 #include "vpu_defs.h"
21 #include "vpu_helpers.h"
22 #include "vpu_cmds.h"
23 #include "vpu_v4l2.h"
24 #include "vpu_imx8q.h"
25 #include "vpu_windsor.h"
26
27 #define CMD_SIZE 2560
28 #define MSG_SIZE 25600
29 #define WINDSOR_USER_DATA_WORDS 16
30 #define WINDSOR_MAX_SRC_FRAMES 0x6
31 #define WINDSOR_MAX_REF_FRAMES 0x3
32 #define WINDSOR_BITRATE_UNIT 1024
33 #define WINDSOR_H264_EXTENDED_SAR 255
34
35 enum {
36 GTB_ENC_CMD_NOOP = 0x0,
37 GTB_ENC_CMD_STREAM_START,
38 GTB_ENC_CMD_FRAME_ENCODE,
39 GTB_ENC_CMD_FRAME_SKIP,
40 GTB_ENC_CMD_STREAM_STOP,
41 GTB_ENC_CMD_PARAMETER_UPD,
42 GTB_ENC_CMD_TERMINATE,
43 GTB_ENC_CMD_SNAPSHOT,
44 GTB_ENC_CMD_ROLL_SNAPSHOT,
45 GTB_ENC_CMD_LOCK_SCHEDULER,
46 GTB_ENC_CMD_UNLOCK_SCHEDULER,
47 GTB_ENC_CMD_CONFIGURE_CODEC,
48 GTB_ENC_CMD_DEAD_MARK,
49 GTB_ENC_CMD_FIRM_RESET,
50 GTB_ENC_CMD_FW_STATUS,
51 GTB_ENC_CMD_RESERVED
52 };
53
54 enum {
55 VID_API_EVENT_UNDEFINED = 0x0,
56 VID_API_ENC_EVENT_RESET_DONE = 0x1,
57 VID_API_ENC_EVENT_START_DONE,
58 VID_API_ENC_EVENT_STOP_DONE,
59 VID_API_ENC_EVENT_TERMINATE_DONE,
60 VID_API_ENC_EVENT_FRAME_INPUT_DONE,
61 VID_API_ENC_EVENT_FRAME_DONE,
62 VID_API_ENC_EVENT_FRAME_RELEASE,
63 VID_API_ENC_EVENT_PARA_UPD_DONE,
64 VID_API_ENC_EVENT_MEM_REQUEST,
65 VID_API_ENC_EVENT_FIRMWARE_XCPT,
66 VID_API_ENC_EVENT_RESERVED
67 };
68
69 enum {
70 MEDIAIP_ENC_PIC_TYPE_B_FRAME = 0,
71 MEDIAIP_ENC_PIC_TYPE_P_FRAME,
72 MEDIAIP_ENC_PIC_TYPE_I_FRAME,
73 MEDIAIP_ENC_PIC_TYPE_IDR_FRAME,
74 MEDIAIP_ENC_PIC_TYPE_BI_FRAME
75 };
76
77 struct windsor_iface {
78 u32 exec_base_addr;
79 u32 exec_area_size;
80 struct vpu_rpc_buffer_desc cmd_buffer_desc;
81 struct vpu_rpc_buffer_desc msg_buffer_desc;
82 u32 cmd_int_enable[VID_API_NUM_STREAMS];
83 u32 fw_version;
84 u32 mvd_fw_offset;
85 u32 max_streams;
86 u32 ctrl_iface[VID_API_NUM_STREAMS];
87 struct vpu_rpc_system_config system_config;
88 u32 api_version;
89 struct vpu_rpc_buffer_desc log_buffer_desc;
90 };
91
92 struct windsor_ctrl_iface {
93 u32 enc_yuv_buffer_desc;
94 u32 enc_stream_buffer_desc;
95 u32 enc_expert_mode_param;
96 u32 enc_param;
97 u32 enc_mem_pool;
98 u32 enc_encoding_status;
99 u32 enc_dsa_status;
100 };
101
102 struct vpu_enc_yuv_desc {
103 u32 frame_id;
104 u32 luma_base;
105 u32 chroma_base;
106 u32 param_idx;
107 u32 key_frame;
108 };
109
110 struct vpu_enc_calib_params {
111 u32 use_ame;
112
113 u32 cme_mvx_max;
114 u32 cme_mvy_max;
115 u32 ame_prefresh_y0;
116 u32 ame_prefresh_y1;
117 u32 fme_min_sad;
118 u32 cme_min_sad;
119
120 u32 fme_pred_int_weight;
121 u32 fme_pred_hp_weight;
122 u32 fme_pred_qp_weight;
123 u32 fme_cost_weight;
124 u32 fme_act_thold;
125 u32 fme_sad_thold;
126 u32 fme_zero_sad_thold;
127
128 u32 fme_lrg_mvx_lmt;
129 u32 fme_lrg_mvy_lmt;
130 u32 fme_force_mode;
131 u32 fme_force4mvcost;
132 u32 fme_force2mvcost;
133
134 u32 h264_inter_thrd;
135
136 u32 i16x16_mode_cost;
137 u32 i4x4_mode_lambda;
138 u32 i8x8_mode_lambda;
139
140 u32 inter_mod_mult;
141 u32 inter_sel_mult;
142 u32 inter_bid_cost;
143 u32 inter_bwd_cost;
144 u32 inter_4mv_cost;
145 s32 one_mv_i16_cost;
146 s32 one_mv_i4x4_cost;
147 s32 one_mv_i8x8_cost;
148 s32 two_mv_i16_cost;
149 s32 two_mv_i4x4_cost;
150 s32 two_mv_i8x8_cost;
151 s32 four_mv_i16_cost;
152 s32 four_mv_i4x4_cost;
153 s32 four_mv_i8x8_cost;
154
155 u32 intra_pred_enab;
156 u32 intra_chr_pred;
157 u32 intra16_pred;
158 u32 intra4x4_pred;
159 u32 intra8x8_pred;
160
161 u32 cb_base;
162 u32 cb_size;
163 u32 cb_head_room;
164
165 u32 mem_page_width;
166 u32 mem_page_height;
167 u32 mem_total_size;
168 u32 mem_chunk_phys_addr;
169 u32 mem_chunk_virt_addr;
170 u32 mem_chunk_size;
171 u32 mem_y_stride;
172 u32 mem_uv_stride;
173
174 u32 split_wr_enab;
175 u32 split_wr_req_size;
176 u32 split_rd_enab;
177 u32 split_rd_req_size;
178 };
179
180 struct vpu_enc_config_params {
181 u32 param_change;
182 u32 start_frame;
183 u32 end_frame;
184 u32 userdata_enable;
185 u32 userdata_id[4];
186 u32 userdata_message[WINDSOR_USER_DATA_WORDS];
187 u32 userdata_length;
188 u32 h264_profile_idc;
189 u32 h264_level_idc;
190 u32 h264_au_delimiter;
191 u32 h264_seq_end_code;
192 u32 h264_recovery_points;
193 u32 h264_vui_parameters;
194 u32 h264_aspect_ratio_present;
195 u32 h264_aspect_ratio_sar_width;
196 u32 h264_aspect_ratio_sar_height;
197 u32 h264_overscan_present;
198 u32 h264_video_type_present;
199 u32 h264_video_format;
200 u32 h264_video_full_range;
201 u32 h264_video_colour_descriptor;
202 u32 h264_video_colour_primaries;
203 u32 h264_video_transfer_char;
204 u32 h264_video_matrix_coeff;
205 u32 h264_chroma_loc_info_present;
206 u32 h264_chroma_loc_type_top;
207 u32 h264_chroma_loc_type_bot;
208 u32 h264_timing_info_present;
209 u32 h264_buffering_period_present;
210 u32 h264_low_delay_hrd_flag;
211 u32 aspect_ratio;
212 u32 test_mode; // Automated firmware test mode
213 u32 dsa_test_mode; // Automated test mode for the DSA.
214 u32 fme_test_mode; // Automated test mode for the fme
215 u32 cbr_row_mode; //0: FW mode; 1: HW mode
216 u32 windsor_mode; //0: normal mode; 1: intra only mode; 2: intra+0MV mode
217 u32 encode_mode; // H264, VC1, MPEG2, DIVX
218 u32 frame_width; // display width
219 u32 frame_height; // display height
220 u32 enc_frame_width; // encoding width, should be 16-pix align
221 u32 enc_frame_height; // encoding height, should be 16-pix aligned
222 u32 frame_rate_num;
223 u32 frame_rate_den;
224 u32 vi_field_source;
225 u32 vi_frame_width;
226 u32 vi_frame_height;
227 u32 crop_frame_width;
228 u32 crop_frame_height;
229 u32 crop_x_start_posn;
230 u32 crop_y_start_posn;
231 u32 mode422;
232 u32 mode_yuy2;
233 u32 dsa_luma_en;
234 u32 dsa_chroma_en;
235 u32 dsa_ext_hfilt_en;
236 u32 dsa_di_en;
237 u32 dsa_di_top_ref;
238 u32 dsa_vertf_disable;
239 u32 dsa_disable_pwb;
240 u32 dsa_hor_phase;
241 u32 dsa_ver_phase;
242 u32 dsa_iac_enable;
243 u32 iac_sc_threshold;
244 u32 iac_vm_threshold;
245 u32 iac_skip_mode;
246 u32 iac_grp_width;
247 u32 iac_grp_height;
248 u32 rate_control_mode;
249 u32 rate_control_resolution;
250 u32 buffer_size;
251 u32 buffer_level_init;
252 u32 buffer_I_bit_budget;
253 u32 top_field_first;
254 u32 intra_lum_qoffset;
255 u32 intra_chr_qoffset;
256 u32 inter_lum_qoffset;
257 u32 inter_chr_qoffset;
258 u32 use_def_scaling_mtx;
259 u32 inter_8x8_enab;
260 u32 inter_4x4_enab;
261 u32 fme_enable_qpel;
262 u32 fme_enable_hpel;
263 u32 fme_nozeromv;
264 u32 fme_predmv_en;
265 u32 fme_pred_2mv4mv;
266 u32 fme_smallsadthresh;
267 u32 ame_en_lmvc;
268 u32 ame_x_mult;
269 u32 cme_enable_4mv;
270 u32 cme_enable_1mv;
271 u32 hme_enable_16x8mv;
272 u32 hme_enable_8x16mv;
273 u32 cme_mv_weight;
274 u32 cme_mv_cost;
275 u32 ame_mult_mv;
276 u32 ame_shift_mv;
277 u32 hme_forceto1mv_en;
278 u32 hme_2mv_cost;
279 u32 hme_pred_mode;
280 u32 hme_sc_rnge;
281 u32 hme_sw_rnge;
282 u32 output_format;
283 u32 timestamp_enab;
284 u32 initial_pts_enab;
285 u32 initial_pts;
286 };
287
288 struct vpu_enc_static_params {
289 u32 param_change;
290 u32 gop_length;
291 u32 rate_control_bitrate;
292 u32 rate_control_bitrate_min;
293 u32 rate_control_bitrate_max;
294 u32 rate_control_content_models;
295 u32 rate_control_iframe_maxsize;
296 u32 rate_control_qp_init;
297 u32 rate_control_islice_qp;
298 u32 rate_control_pslice_qp;
299 u32 rate_control_bslice_qp;
300 u32 adaptive_quantization;
301 u32 aq_variance;
302 u32 cost_optimization;
303 u32 fdlp_mode;
304 u32 enable_isegbframes;
305 u32 enable_adaptive_keyratio;
306 u32 keyratio_imin;
307 u32 keyratio_imax;
308 u32 keyratio_pmin;
309 u32 keyratio_pmax;
310 u32 keyratio_bmin;
311 u32 keyratio_bmax;
312 s32 keyratio_istep;
313 s32 keyratio_pstep;
314 s32 keyratio_bstep;
315 u32 enable_paff;
316 u32 enable_b_frame_ref;
317 u32 enable_adaptive_gop;
318 u32 enable_closed_gop;
319 u32 open_gop_refresh_freq;
320 u32 enable_adaptive_sc;
321 u32 enable_fade_detection;
322 s32 fade_detection_threshold;
323 u32 enable_repeat_b;
324 u32 enable_low_delay_b;
325 };
326
327 struct vpu_enc_dynamic_params {
328 u32 param_change;
329 u32 rows_per_slice;
330 u32 mbaff_enable;
331 u32 dbf_enable;
332 u32 field_source;
333 u32 gop_b_length;
334 u32 mb_group_size;
335 u32 cbr_rows_per_group;
336 u32 skip_enable;
337 u32 pts_bits_0_to_31;
338 u32 pts_bit_32;
339 u32 rm_expsv_cff;
340 u32 const_ipred;
341 s32 chr_qp_offset;
342 u32 intra_mb_qp_offset;
343 u32 h264_cabac_init_method;
344 u32 h264_cabac_init_idc;
345 u32 h264_cabac_enable;
346 s32 alpha_c0_offset_div2;
347 s32 beta_offset_div2;
348 u32 intra_prefresh_y0;
349 u32 intra_prefresh_y1;
350 u32 dbg_dump_rec_src;
351 };
352
353 struct vpu_enc_expert_mode_param {
354 struct vpu_enc_calib_params calib_param;
355 struct vpu_enc_config_params config_param;
356 struct vpu_enc_static_params static_param;
357 struct vpu_enc_dynamic_params dynamic_param;
358 };
359
360 enum MEDIAIP_ENC_FMT {
361 MEDIAIP_ENC_FMT_H264 = 0,
362 MEDIAIP_ENC_FMT_VC1,
363 MEDIAIP_ENC_FMT_MPEG2,
364 MEDIAIP_ENC_FMT_MPEG4SP,
365 MEDIAIP_ENC_FMT_H263,
366 MEDIAIP_ENC_FMT_MPEG1,
367 MEDIAIP_ENC_FMT_SHORT_HEADER,
368 MEDIAIP_ENC_FMT_NULL
369 };
370
371 enum MEDIAIP_ENC_PROFILE {
372 MEDIAIP_ENC_PROF_MPEG2_SP = 0,
373 MEDIAIP_ENC_PROF_MPEG2_MP,
374 MEDIAIP_ENC_PROF_MPEG2_HP,
375 MEDIAIP_ENC_PROF_H264_BP,
376 MEDIAIP_ENC_PROF_H264_MP,
377 MEDIAIP_ENC_PROF_H264_HP,
378 MEDIAIP_ENC_PROF_MPEG4_SP,
379 MEDIAIP_ENC_PROF_MPEG4_ASP,
380 MEDIAIP_ENC_PROF_VC1_SP,
381 MEDIAIP_ENC_PROF_VC1_MP,
382 MEDIAIP_ENC_PROF_VC1_AP
383 };
384
385 enum MEDIAIP_ENC_BITRATE_MODE {
386 MEDIAIP_ENC_BITRATE_MODE_VBR = 0x00000001,
387 MEDIAIP_ENC_BITRATE_MODE_CBR = 0x00000002,
388 MEDIAIP_ENC_BITRATE_MODE_CONSTANT_QP = 0x00000004
389 };
390
391 struct vpu_enc_memory_resource {
392 u32 phys;
393 u32 virt;
394 u32 size;
395 };
396
397 struct vpu_enc_param {
398 enum MEDIAIP_ENC_FMT codec_mode;
399 enum MEDIAIP_ENC_PROFILE profile;
400 u32 level;
401
402 struct vpu_enc_memory_resource enc_mem_desc;
403
404 u32 frame_rate;
405 u32 src_stride;
406 u32 src_width;
407 u32 src_height;
408 u32 src_offset_x;
409 u32 src_offset_y;
410 u32 src_crop_width;
411 u32 src_crop_height;
412 u32 out_width;
413 u32 out_height;
414 u32 iframe_interval;
415 u32 bframes;
416 u32 low_latency_mode;
417
418 enum MEDIAIP_ENC_BITRATE_MODE bitrate_mode;
419 u32 target_bitrate;
420 u32 max_bitrate;
421 u32 min_bitrate;
422 u32 init_slice_qp;
423 };
424
425 struct vpu_enc_mem_pool {
426 struct vpu_enc_memory_resource enc_frames[WINDSOR_MAX_SRC_FRAMES];
427 struct vpu_enc_memory_resource ref_frames[WINDSOR_MAX_REF_FRAMES];
428 struct vpu_enc_memory_resource act_frame;
429 };
430
431 struct vpu_enc_encoding_status {
432 u32 frame_id;
433 u32 error_flag; //Error type
434 u32 mb_y;
435 u32 mb_x;
436 u32 reserved[12];
437
438 };
439
440 struct vpu_enc_dsa_status {
441 u32 frame_id;
442 u32 dsa_cyle;
443 u32 mb_y;
444 u32 mb_x;
445 u32 reserved[4];
446 };
447
448 struct vpu_enc_ctrl {
449 struct vpu_enc_yuv_desc *yuv_desc;
450 struct vpu_rpc_buffer_desc *stream_desc;
451 struct vpu_enc_expert_mode_param *expert;
452 struct vpu_enc_param *param;
453 struct vpu_enc_mem_pool *pool;
454 struct vpu_enc_encoding_status *status;
455 struct vpu_enc_dsa_status *dsa;
456 };
457
458 struct vpu_enc_host_ctrls {
459 struct vpu_enc_ctrl ctrls[VID_API_NUM_STREAMS];
460 };
461
462 struct windsor_pic_info {
463 u32 frame_id;
464 u32 pic_encod_done;
465 u32 pic_type;
466 u32 skipped_frame;
467 u32 error_flag;
468 u32 psnr;
469 u32 flush_done;
470 u32 mb_y;
471 u32 mb_x;
472 u32 frame_size;
473 u32 frame_enc_ttl_cycles;
474 u32 frame_enc_ttl_frm_cycles;
475 u32 frame_enc_ttl_slc_cycles;
476 u32 frame_enc_ttl_enc_cycles;
477 u32 frame_enc_ttl_hme_cycles;
478 u32 frame_enc_ttl_dsa_cycles;
479 u32 frame_enc_fw_cycles;
480 u32 frame_crc;
481 u32 num_interrupts_1;
482 u32 num_interrupts_2;
483 u32 poc;
484 u32 ref_info;
485 u32 pic_num;
486 u32 pic_activity;
487 u32 scene_change;
488 u32 mb_stats;
489 u32 enc_cache_count0;
490 u32 enc_cache_count1;
491 u32 mtl_wr_strb_cnt;
492 u32 mtl_rd_strb_cnt;
493 u32 str_buff_wptr;
494 u32 diagnosticEvents;
495 u32 proc_iacc_tot_rd_cnt;
496 u32 proc_dacc_tot_rd_cnt;
497 u32 proc_dacc_tot_wr_cnt;
498 u32 proc_dacc_reg_rd_cnt;
499 u32 proc_dacc_reg_wr_cnt;
500 u32 proc_dacc_rng_rd_cnt;
501 u32 proc_dacc_rng_wr_cnt;
502 s32 tv_s;
503 u32 tv_ns;
504 };
505
vpu_windsor_get_data_size(void)506 u32 vpu_windsor_get_data_size(void)
507 {
508 return sizeof(struct vpu_enc_host_ctrls);
509 }
510
get_yuv_desc(struct vpu_shared_addr * shared,u32 instance)511 static struct vpu_enc_yuv_desc *get_yuv_desc(struct vpu_shared_addr *shared,
512 u32 instance)
513 {
514 struct vpu_enc_host_ctrls *hcs = shared->priv;
515
516 return hcs->ctrls[instance].yuv_desc;
517 }
518
get_mem_pool(struct vpu_shared_addr * shared,u32 instance)519 static struct vpu_enc_mem_pool *get_mem_pool(struct vpu_shared_addr *shared,
520 u32 instance)
521 {
522 struct vpu_enc_host_ctrls *hcs = shared->priv;
523
524 return hcs->ctrls[instance].pool;
525 }
526
get_stream_buf_desc(struct vpu_shared_addr * shared,u32 instance)527 static struct vpu_rpc_buffer_desc *get_stream_buf_desc(struct vpu_shared_addr *shared,
528 u32 instance)
529 {
530 struct vpu_enc_host_ctrls *hcs = shared->priv;
531
532 return hcs->ctrls[instance].stream_desc;
533 }
534
get_expert_param(struct vpu_shared_addr * shared,u32 instance)535 static struct vpu_enc_expert_mode_param *get_expert_param(struct vpu_shared_addr *shared,
536 u32 instance)
537 {
538 struct vpu_enc_host_ctrls *hcs = shared->priv;
539
540 return hcs->ctrls[instance].expert;
541 }
542
get_enc_param(struct vpu_shared_addr * shared,u32 instance)543 static struct vpu_enc_param *get_enc_param(struct vpu_shared_addr *shared, u32 instance)
544 {
545 struct vpu_enc_host_ctrls *hcs = shared->priv;
546
547 return hcs->ctrls[instance].param;
548 }
549
get_ptr(u32 ptr)550 static u32 get_ptr(u32 ptr)
551 {
552 return (ptr | 0x80000000);
553 }
554
vpu_windsor_init_rpc(struct vpu_shared_addr * shared,struct vpu_buffer * rpc,dma_addr_t boot_addr)555 void vpu_windsor_init_rpc(struct vpu_shared_addr *shared,
556 struct vpu_buffer *rpc, dma_addr_t boot_addr)
557 {
558 unsigned long base_phy_addr;
559 unsigned long phy_addr;
560 unsigned long offset;
561 struct windsor_iface *iface;
562 struct windsor_ctrl_iface *ctrl;
563 struct vpu_enc_host_ctrls *hcs;
564 unsigned int i;
565
566 if (rpc->phys < boot_addr)
567 return;
568
569 base_phy_addr = rpc->phys - boot_addr;
570 iface = rpc->virt;
571 shared->iface = iface;
572 shared->boot_addr = boot_addr;
573 hcs = shared->priv;
574
575 iface->exec_base_addr = base_phy_addr;
576 iface->exec_area_size = rpc->length;
577
578 offset = sizeof(struct windsor_iface);
579 phy_addr = base_phy_addr + offset;
580 shared->cmd_desc = &iface->cmd_buffer_desc;
581 shared->cmd_mem_vir = rpc->virt + offset;
582 iface->cmd_buffer_desc.start =
583 iface->cmd_buffer_desc.rptr =
584 iface->cmd_buffer_desc.wptr = phy_addr;
585 iface->cmd_buffer_desc.end = iface->cmd_buffer_desc.start + CMD_SIZE;
586
587 offset += CMD_SIZE;
588 phy_addr = base_phy_addr + offset;
589 shared->msg_desc = &iface->msg_buffer_desc;
590 shared->msg_mem_vir = rpc->virt + offset;
591 iface->msg_buffer_desc.start =
592 iface->msg_buffer_desc.wptr =
593 iface->msg_buffer_desc.rptr = phy_addr;
594 iface->msg_buffer_desc.end = iface->msg_buffer_desc.start + MSG_SIZE;
595
596 offset += MSG_SIZE;
597 for (i = 0; i < ARRAY_SIZE(iface->ctrl_iface); i++) {
598 iface->ctrl_iface[i] = base_phy_addr + offset;
599 offset += sizeof(struct windsor_ctrl_iface);
600 }
601 for (i = 0; i < ARRAY_SIZE(iface->ctrl_iface); i++) {
602 ctrl = rpc->virt + (iface->ctrl_iface[i] - base_phy_addr);
603
604 ctrl->enc_yuv_buffer_desc = base_phy_addr + offset;
605 hcs->ctrls[i].yuv_desc = rpc->virt + offset;
606 offset += sizeof(struct vpu_enc_yuv_desc);
607
608 ctrl->enc_stream_buffer_desc = base_phy_addr + offset;
609 hcs->ctrls[i].stream_desc = rpc->virt + offset;
610 offset += sizeof(struct vpu_rpc_buffer_desc);
611
612 ctrl->enc_expert_mode_param = base_phy_addr + offset;
613 hcs->ctrls[i].expert = rpc->virt + offset;
614 offset += sizeof(struct vpu_enc_expert_mode_param);
615
616 ctrl->enc_param = base_phy_addr + offset;
617 hcs->ctrls[i].param = rpc->virt + offset;
618 offset += sizeof(struct vpu_enc_param);
619
620 ctrl->enc_mem_pool = base_phy_addr + offset;
621 hcs->ctrls[i].pool = rpc->virt + offset;
622 offset += sizeof(struct vpu_enc_mem_pool);
623
624 ctrl->enc_encoding_status = base_phy_addr + offset;
625 hcs->ctrls[i].status = rpc->virt + offset;
626 offset += sizeof(struct vpu_enc_encoding_status);
627
628 ctrl->enc_dsa_status = base_phy_addr + offset;
629 hcs->ctrls[i].dsa = rpc->virt + offset;
630 offset += sizeof(struct vpu_enc_dsa_status);
631 }
632
633 rpc->bytesused = offset;
634 }
635
vpu_windsor_set_log_buf(struct vpu_shared_addr * shared,struct vpu_buffer * log)636 void vpu_windsor_set_log_buf(struct vpu_shared_addr *shared, struct vpu_buffer *log)
637 {
638 struct windsor_iface *iface = shared->iface;
639
640 iface->log_buffer_desc.start =
641 iface->log_buffer_desc.wptr =
642 iface->log_buffer_desc.rptr = log->phys - shared->boot_addr;
643 iface->log_buffer_desc.end = iface->log_buffer_desc.start + log->length;
644 }
645
vpu_windsor_set_system_cfg(struct vpu_shared_addr * shared,u32 regs_base,void __iomem * regs,u32 core_id)646 void vpu_windsor_set_system_cfg(struct vpu_shared_addr *shared,
647 u32 regs_base, void __iomem *regs, u32 core_id)
648 {
649 struct windsor_iface *iface = shared->iface;
650 struct vpu_rpc_system_config *config = &iface->system_config;
651
652 vpu_imx8q_set_system_cfg_common(config, regs_base, core_id);
653 }
654
vpu_windsor_get_stream_buffer_size(struct vpu_shared_addr * shared)655 int vpu_windsor_get_stream_buffer_size(struct vpu_shared_addr *shared)
656 {
657 return 0x300000;
658 }
659
660 static struct vpu_pair windsor_cmds[] = {
661 {VPU_CMD_ID_CONFIGURE_CODEC, GTB_ENC_CMD_CONFIGURE_CODEC},
662 {VPU_CMD_ID_START, GTB_ENC_CMD_STREAM_START},
663 {VPU_CMD_ID_STOP, GTB_ENC_CMD_STREAM_STOP},
664 {VPU_CMD_ID_FRAME_ENCODE, GTB_ENC_CMD_FRAME_ENCODE},
665 {VPU_CMD_ID_SNAPSHOT, GTB_ENC_CMD_SNAPSHOT},
666 {VPU_CMD_ID_FIRM_RESET, GTB_ENC_CMD_FIRM_RESET},
667 {VPU_CMD_ID_UPDATE_PARAMETER, GTB_ENC_CMD_PARAMETER_UPD},
668 {VPU_CMD_ID_DEBUG, GTB_ENC_CMD_FW_STATUS}
669 };
670
671 static struct vpu_pair windsor_msgs[] = {
672 {VPU_MSG_ID_RESET_DONE, VID_API_ENC_EVENT_RESET_DONE},
673 {VPU_MSG_ID_START_DONE, VID_API_ENC_EVENT_START_DONE},
674 {VPU_MSG_ID_STOP_DONE, VID_API_ENC_EVENT_STOP_DONE},
675 {VPU_MSG_ID_FRAME_INPUT_DONE, VID_API_ENC_EVENT_FRAME_INPUT_DONE},
676 {VPU_MSG_ID_ENC_DONE, VID_API_ENC_EVENT_FRAME_DONE},
677 {VPU_MSG_ID_FRAME_RELEASE, VID_API_ENC_EVENT_FRAME_RELEASE},
678 {VPU_MSG_ID_MEM_REQUEST, VID_API_ENC_EVENT_MEM_REQUEST},
679 {VPU_MSG_ID_PARAM_UPD_DONE, VID_API_ENC_EVENT_PARA_UPD_DONE},
680 {VPU_MSG_ID_FIRMWARE_XCPT, VID_API_ENC_EVENT_FIRMWARE_XCPT},
681 };
682
vpu_windsor_pack_cmd(struct vpu_rpc_event * pkt,u32 index,u32 id,void * data)683 int vpu_windsor_pack_cmd(struct vpu_rpc_event *pkt, u32 index, u32 id, void *data)
684 {
685 int ret;
686
687 ret = vpu_find_dst_by_src(windsor_cmds, ARRAY_SIZE(windsor_cmds), id);
688 if (ret < 0)
689 return ret;
690 pkt->hdr.id = ret;
691 pkt->hdr.num = 0;
692 pkt->hdr.index = index;
693 if (id == VPU_CMD_ID_FRAME_ENCODE) {
694 s64 timestamp = *(s64 *)data;
695 struct timespec64 ts = ns_to_timespec64(timestamp);
696
697 pkt->hdr.num = 2;
698 pkt->data[0] = ts.tv_sec;
699 pkt->data[1] = ts.tv_nsec;
700 }
701
702 return 0;
703 }
704
vpu_windsor_convert_msg_id(u32 id)705 int vpu_windsor_convert_msg_id(u32 id)
706 {
707 return vpu_find_src_by_dst(windsor_msgs, ARRAY_SIZE(windsor_msgs), id);
708 }
709
vpu_windsor_unpack_pic_info(struct vpu_rpc_event * pkt,void * data)710 static void vpu_windsor_unpack_pic_info(struct vpu_rpc_event *pkt, void *data)
711 {
712 struct vpu_enc_pic_info *info = data;
713 struct windsor_pic_info *windsor = (struct windsor_pic_info *)pkt->data;
714 struct timespec64 ts = { windsor->tv_s, windsor->tv_ns };
715
716 info->frame_id = windsor->frame_id;
717 switch (windsor->pic_type) {
718 case MEDIAIP_ENC_PIC_TYPE_I_FRAME:
719 case MEDIAIP_ENC_PIC_TYPE_IDR_FRAME:
720 info->pic_type = V4L2_BUF_FLAG_KEYFRAME;
721 break;
722 case MEDIAIP_ENC_PIC_TYPE_P_FRAME:
723 info->pic_type = V4L2_BUF_FLAG_PFRAME;
724 break;
725 case MEDIAIP_ENC_PIC_TYPE_B_FRAME:
726 info->pic_type = V4L2_BUF_FLAG_BFRAME;
727 break;
728 default:
729 break;
730 }
731 info->skipped_frame = windsor->skipped_frame;
732 info->error_flag = windsor->error_flag;
733 info->psnr = windsor->psnr;
734 info->frame_size = windsor->frame_size;
735 info->wptr = get_ptr(windsor->str_buff_wptr);
736 info->crc = windsor->frame_crc;
737 info->timestamp = timespec64_to_ns(&ts);
738 }
739
vpu_windsor_unpack_mem_req(struct vpu_rpc_event * pkt,void * data)740 static void vpu_windsor_unpack_mem_req(struct vpu_rpc_event *pkt, void *data)
741 {
742 struct vpu_pkt_mem_req_data *req_data = data;
743
744 req_data->enc_frame_size = pkt->data[0];
745 req_data->enc_frame_num = pkt->data[1];
746 req_data->ref_frame_size = pkt->data[2];
747 req_data->ref_frame_num = pkt->data[3];
748 req_data->act_buf_size = pkt->data[4];
749 req_data->act_buf_num = 1;
750 }
751
vpu_windsor_unpack_msg_data(struct vpu_rpc_event * pkt,void * data)752 int vpu_windsor_unpack_msg_data(struct vpu_rpc_event *pkt, void *data)
753 {
754 if (!pkt || !data)
755 return -EINVAL;
756
757 switch (pkt->hdr.id) {
758 case VID_API_ENC_EVENT_FRAME_DONE:
759 vpu_windsor_unpack_pic_info(pkt, data);
760 break;
761 case VID_API_ENC_EVENT_MEM_REQUEST:
762 vpu_windsor_unpack_mem_req(pkt, data);
763 break;
764 case VID_API_ENC_EVENT_FRAME_RELEASE:
765 *(u32 *)data = pkt->data[0];
766 break;
767 default:
768 break;
769 }
770
771 return 0;
772 }
773
vpu_windsor_fill_yuv_frame(struct vpu_shared_addr * shared,u32 instance,struct vb2_buffer * vb)774 static int vpu_windsor_fill_yuv_frame(struct vpu_shared_addr *shared,
775 u32 instance,
776 struct vb2_buffer *vb)
777 {
778 struct vpu_enc_yuv_desc *desc;
779 struct vb2_v4l2_buffer *vbuf;
780
781 if (instance >= VID_API_NUM_STREAMS)
782 return -EINVAL;
783
784 desc = get_yuv_desc(shared, instance);
785
786 vbuf = to_vb2_v4l2_buffer(vb);
787 desc->frame_id = vbuf->sequence;
788 if (vbuf->flags & V4L2_BUF_FLAG_KEYFRAME)
789 desc->key_frame = 1;
790 else
791 desc->key_frame = 0;
792 desc->luma_base = vpu_get_vb_phy_addr(vb, 0);
793 desc->chroma_base = vpu_get_vb_phy_addr(vb, 1);
794
795 return 0;
796 }
797
vpu_windsor_input_frame(struct vpu_shared_addr * shared,struct vpu_inst * inst,struct vb2_buffer * vb)798 int vpu_windsor_input_frame(struct vpu_shared_addr *shared,
799 struct vpu_inst *inst, struct vb2_buffer *vb)
800 {
801 vpu_windsor_fill_yuv_frame(shared, inst->id, vb);
802 return vpu_session_encode_frame(inst, vb->timestamp);
803 }
804
vpu_windsor_config_memory_resource(struct vpu_shared_addr * shared,u32 instance,u32 type,u32 index,struct vpu_buffer * buf)805 int vpu_windsor_config_memory_resource(struct vpu_shared_addr *shared,
806 u32 instance,
807 u32 type,
808 u32 index,
809 struct vpu_buffer *buf)
810 {
811 struct vpu_enc_mem_pool *pool;
812 struct vpu_enc_memory_resource *res;
813
814 if (instance >= VID_API_NUM_STREAMS)
815 return -EINVAL;
816
817 pool = get_mem_pool(shared, instance);
818
819 switch (type) {
820 case MEM_RES_ENC:
821 if (index >= ARRAY_SIZE(pool->enc_frames))
822 return -EINVAL;
823 res = &pool->enc_frames[index];
824 break;
825 case MEM_RES_REF:
826 if (index >= ARRAY_SIZE(pool->ref_frames))
827 return -EINVAL;
828 res = &pool->ref_frames[index];
829 break;
830 case MEM_RES_ACT:
831 if (index)
832 return -EINVAL;
833 res = &pool->act_frame;
834 break;
835 default:
836 return -EINVAL;
837 }
838
839 res->phys = buf->phys;
840 res->virt = buf->phys - shared->boot_addr;
841 res->size = buf->length;
842
843 return 0;
844 }
845
vpu_windsor_config_stream_buffer(struct vpu_shared_addr * shared,u32 instance,struct vpu_buffer * buf)846 int vpu_windsor_config_stream_buffer(struct vpu_shared_addr *shared,
847 u32 instance,
848 struct vpu_buffer *buf)
849 {
850 struct vpu_rpc_buffer_desc *desc;
851 struct vpu_enc_expert_mode_param *expert;
852
853 desc = get_stream_buf_desc(shared, instance);
854 expert = get_expert_param(shared, instance);
855
856 desc->start = buf->phys;
857 desc->wptr = buf->phys;
858 desc->rptr = buf->phys;
859 desc->end = buf->phys + buf->length;
860
861 expert->calib_param.mem_chunk_phys_addr = 0;
862 expert->calib_param.mem_chunk_virt_addr = 0;
863 expert->calib_param.mem_chunk_size = 0;
864 expert->calib_param.cb_base = buf->phys;
865 expert->calib_param.cb_size = buf->length;
866
867 return 0;
868 }
869
vpu_windsor_update_stream_buffer(struct vpu_shared_addr * shared,u32 instance,u32 ptr,bool write)870 int vpu_windsor_update_stream_buffer(struct vpu_shared_addr *shared,
871 u32 instance, u32 ptr, bool write)
872 {
873 struct vpu_rpc_buffer_desc *desc;
874
875 desc = get_stream_buf_desc(shared, instance);
876
877 /*update wptr/rptr after data is written or read*/
878 mb();
879 if (write)
880 desc->wptr = ptr;
881 else
882 desc->rptr = ptr;
883
884 return 0;
885 }
886
vpu_windsor_get_stream_buffer_desc(struct vpu_shared_addr * shared,u32 instance,struct vpu_rpc_buffer_desc * desc)887 int vpu_windsor_get_stream_buffer_desc(struct vpu_shared_addr *shared,
888 u32 instance, struct vpu_rpc_buffer_desc *desc)
889 {
890 struct vpu_rpc_buffer_desc *rpc_desc;
891
892 rpc_desc = get_stream_buf_desc(shared, instance);
893 if (desc) {
894 desc->wptr = get_ptr(rpc_desc->wptr);
895 desc->rptr = get_ptr(rpc_desc->rptr);
896 desc->start = get_ptr(rpc_desc->start);
897 desc->end = get_ptr(rpc_desc->end);
898 }
899
900 return 0;
901 }
902
vpu_windsor_get_version(struct vpu_shared_addr * shared)903 u32 vpu_windsor_get_version(struct vpu_shared_addr *shared)
904 {
905 struct windsor_iface *iface = shared->iface;
906
907 return iface->fw_version;
908 }
909
vpu_windsor_set_frame_rate(struct vpu_enc_expert_mode_param * expert,struct vpu_encode_params * params)910 static int vpu_windsor_set_frame_rate(struct vpu_enc_expert_mode_param *expert,
911 struct vpu_encode_params *params)
912 {
913 expert->config_param.frame_rate_num = params->frame_rate.numerator;
914 expert->config_param.frame_rate_den = params->frame_rate.denominator;
915
916 return 0;
917 }
918
vpu_windsor_set_format(struct vpu_enc_param * param,u32 pixelformat)919 static int vpu_windsor_set_format(struct vpu_enc_param *param, u32 pixelformat)
920 {
921 switch (pixelformat) {
922 case V4L2_PIX_FMT_H264:
923 param->codec_mode = MEDIAIP_ENC_FMT_H264;
924 break;
925 default:
926 return -EINVAL;
927 }
928
929 return 0;
930 }
931
vpu_windsor_set_profile(struct vpu_enc_param * param,u32 profile)932 static int vpu_windsor_set_profile(struct vpu_enc_param *param, u32 profile)
933 {
934 switch (profile) {
935 case V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE:
936 param->profile = MEDIAIP_ENC_PROF_H264_BP;
937 break;
938 case V4L2_MPEG_VIDEO_H264_PROFILE_MAIN:
939 param->profile = MEDIAIP_ENC_PROF_H264_MP;
940 break;
941 case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH:
942 param->profile = MEDIAIP_ENC_PROF_H264_HP;
943 break;
944 default:
945 return -EINVAL;
946 }
947
948 return 0;
949 }
950
951 static const u32 h264_level[] = {
952 [V4L2_MPEG_VIDEO_H264_LEVEL_1_0] = 10,
953 [V4L2_MPEG_VIDEO_H264_LEVEL_1B] = 14,
954 [V4L2_MPEG_VIDEO_H264_LEVEL_1_1] = 11,
955 [V4L2_MPEG_VIDEO_H264_LEVEL_1_2] = 12,
956 [V4L2_MPEG_VIDEO_H264_LEVEL_1_3] = 13,
957 [V4L2_MPEG_VIDEO_H264_LEVEL_2_0] = 20,
958 [V4L2_MPEG_VIDEO_H264_LEVEL_2_1] = 21,
959 [V4L2_MPEG_VIDEO_H264_LEVEL_2_2] = 22,
960 [V4L2_MPEG_VIDEO_H264_LEVEL_3_0] = 30,
961 [V4L2_MPEG_VIDEO_H264_LEVEL_3_1] = 31,
962 [V4L2_MPEG_VIDEO_H264_LEVEL_3_2] = 32,
963 [V4L2_MPEG_VIDEO_H264_LEVEL_4_0] = 40,
964 [V4L2_MPEG_VIDEO_H264_LEVEL_4_1] = 41,
965 [V4L2_MPEG_VIDEO_H264_LEVEL_4_2] = 42,
966 [V4L2_MPEG_VIDEO_H264_LEVEL_5_0] = 50,
967 [V4L2_MPEG_VIDEO_H264_LEVEL_5_1] = 51
968 };
969
vpu_windsor_set_level(struct vpu_enc_param * param,u32 level)970 static int vpu_windsor_set_level(struct vpu_enc_param *param, u32 level)
971 {
972 if (level >= ARRAY_SIZE(h264_level))
973 return -EINVAL;
974
975 param->level = h264_level[level];
976
977 return 0;
978 }
979
vpu_windsor_set_size(struct vpu_enc_param * windsor,struct vpu_encode_params * params)980 static int vpu_windsor_set_size(struct vpu_enc_param *windsor,
981 struct vpu_encode_params *params)
982 {
983 windsor->src_stride = params->src_stride;
984 windsor->src_width = params->src_width;
985 windsor->src_height = params->src_height;
986 windsor->src_offset_x = params->crop.left;
987 windsor->src_offset_y = params->crop.top;
988 windsor->src_crop_width = params->crop.width;
989 windsor->src_crop_height = params->crop.height;
990 windsor->out_width = params->out_width;
991 windsor->out_height = params->out_height;
992
993 return 0;
994 }
995
vpu_windsor_set_gop(struct vpu_enc_param * param,u32 gop)996 static int vpu_windsor_set_gop(struct vpu_enc_param *param, u32 gop)
997 {
998 param->iframe_interval = gop;
999
1000 return 0;
1001 }
1002
vpu_windsor_set_bframes(struct vpu_enc_param * param,u32 bframes)1003 static int vpu_windsor_set_bframes(struct vpu_enc_param *param, u32 bframes)
1004 {
1005 if (bframes) {
1006 param->low_latency_mode = 0;
1007 param->bframes = bframes;
1008 } else {
1009 param->low_latency_mode = 1;
1010 param->bframes = 0;
1011 }
1012
1013 return 0;
1014 }
1015
vpu_windsor_set_bitrate_mode(struct vpu_enc_param * param,u32 rc_enable,u32 mode)1016 static int vpu_windsor_set_bitrate_mode(struct vpu_enc_param *param, u32 rc_enable, u32 mode)
1017 {
1018 if (!rc_enable)
1019 param->bitrate_mode = MEDIAIP_ENC_BITRATE_MODE_CONSTANT_QP;
1020 else if (mode == V4L2_MPEG_VIDEO_BITRATE_MODE_VBR)
1021 param->bitrate_mode = MEDIAIP_ENC_BITRATE_MODE_VBR;
1022 else
1023 param->bitrate_mode = MEDIAIP_ENC_BITRATE_MODE_CBR;
1024
1025 return 0;
1026 }
1027
vpu_windsor_bitrate(u32 bitrate)1028 static u32 vpu_windsor_bitrate(u32 bitrate)
1029 {
1030 return DIV_ROUND_CLOSEST(bitrate, WINDSOR_BITRATE_UNIT);
1031 }
1032
vpu_windsor_set_bitrate(struct vpu_enc_param * windsor,struct vpu_encode_params * params)1033 static int vpu_windsor_set_bitrate(struct vpu_enc_param *windsor,
1034 struct vpu_encode_params *params)
1035 {
1036 windsor->target_bitrate = vpu_windsor_bitrate(params->bitrate);
1037 windsor->min_bitrate = vpu_windsor_bitrate(params->bitrate_min);
1038 windsor->max_bitrate = vpu_windsor_bitrate(params->bitrate_max);
1039
1040 return 0;
1041 }
1042
vpu_windsor_set_qp(struct vpu_enc_expert_mode_param * expert,struct vpu_encode_params * params)1043 static int vpu_windsor_set_qp(struct vpu_enc_expert_mode_param *expert,
1044 struct vpu_encode_params *params)
1045 {
1046 expert->static_param.rate_control_islice_qp = params->i_frame_qp;
1047 expert->static_param.rate_control_pslice_qp = params->p_frame_qp;
1048 expert->static_param.rate_control_bslice_qp = params->b_frame_qp;
1049
1050 return 0;
1051 }
1052
vpu_windsor_set_sar(struct vpu_enc_expert_mode_param * expert,struct vpu_encode_params * params)1053 static int vpu_windsor_set_sar(struct vpu_enc_expert_mode_param *expert,
1054 struct vpu_encode_params *params)
1055 {
1056 expert->config_param.h264_aspect_ratio_present = params->sar.enable;
1057 if (params->sar.idc == V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_EXTENDED)
1058 expert->config_param.aspect_ratio = WINDSOR_H264_EXTENDED_SAR;
1059 else
1060 expert->config_param.aspect_ratio = params->sar.idc;
1061 expert->config_param.h264_aspect_ratio_sar_width = params->sar.width;
1062 expert->config_param.h264_aspect_ratio_sar_height = params->sar.height;
1063
1064 return 0;
1065 }
1066
vpu_windsor_set_color(struct vpu_enc_expert_mode_param * expert,struct vpu_encode_params * params)1067 static int vpu_windsor_set_color(struct vpu_enc_expert_mode_param *expert,
1068 struct vpu_encode_params *params)
1069 {
1070 expert->config_param.h264_video_type_present = 1;
1071 expert->config_param.h264_video_format = 5;
1072 expert->config_param.h264_video_colour_descriptor = 1;
1073 expert->config_param.h264_video_colour_primaries =
1074 vpu_color_cvrt_primaries_v2i(params->color.primaries);
1075 expert->config_param.h264_video_transfer_char =
1076 vpu_color_cvrt_transfers_v2i(params->color.transfer);
1077 expert->config_param.h264_video_matrix_coeff =
1078 vpu_color_cvrt_matrix_v2i(params->color.matrix);
1079 expert->config_param.h264_video_full_range =
1080 vpu_color_cvrt_full_range_v2i(params->color.full_range);
1081 return 0;
1082 }
1083
vpu_windsor_update_bitrate(struct vpu_shared_addr * shared,u32 instance,struct vpu_encode_params * params)1084 static int vpu_windsor_update_bitrate(struct vpu_shared_addr *shared,
1085 u32 instance, struct vpu_encode_params *params)
1086 {
1087 struct vpu_enc_param *windsor;
1088 struct vpu_enc_expert_mode_param *expert;
1089
1090 windsor = get_enc_param(shared, instance);
1091 expert = get_expert_param(shared, instance);
1092
1093 if (windsor->bitrate_mode != MEDIAIP_ENC_BITRATE_MODE_CBR)
1094 return 0;
1095 if (!params->rc_enable)
1096 return 0;
1097 if (vpu_windsor_bitrate(params->bitrate) == windsor->target_bitrate)
1098 return 0;
1099
1100 vpu_windsor_set_bitrate(windsor, params);
1101 expert->static_param.rate_control_bitrate = windsor->target_bitrate;
1102 expert->static_param.rate_control_bitrate_min = windsor->min_bitrate;
1103 expert->static_param.rate_control_bitrate_max = windsor->max_bitrate;
1104
1105 return 0;
1106 }
1107
vpu_windsor_set_params(struct vpu_shared_addr * shared,u32 instance,struct vpu_encode_params * params)1108 static int vpu_windsor_set_params(struct vpu_shared_addr *shared,
1109 u32 instance, struct vpu_encode_params *params)
1110 {
1111 struct vpu_enc_param *windsor;
1112 int ret;
1113
1114 windsor = get_enc_param(shared, instance);
1115
1116 if (params->input_format != V4L2_PIX_FMT_NV12 &&
1117 params->input_format != V4L2_PIX_FMT_NV12M)
1118 return -EINVAL;
1119
1120 ret = vpu_windsor_set_format(windsor, params->codec_format);
1121 if (ret)
1122 return ret;
1123 vpu_windsor_set_profile(windsor, params->profile);
1124 vpu_windsor_set_level(windsor, params->level);
1125 vpu_windsor_set_size(windsor, params);
1126 vpu_windsor_set_gop(windsor, params->gop_length);
1127 vpu_windsor_set_bframes(windsor, params->bframes);
1128 vpu_windsor_set_bitrate_mode(windsor, params->rc_enable, params->rc_mode);
1129 vpu_windsor_set_bitrate(windsor, params);
1130 windsor->init_slice_qp = params->i_frame_qp;
1131
1132 if (!params->frame_rate.numerator)
1133 return -EINVAL;
1134 windsor->frame_rate = params->frame_rate.denominator / params->frame_rate.numerator;
1135
1136 return 0;
1137 }
1138
vpu_windsor_update_params(struct vpu_shared_addr * shared,u32 instance,struct vpu_encode_params * params)1139 static int vpu_windsor_update_params(struct vpu_shared_addr *shared,
1140 u32 instance, struct vpu_encode_params *params)
1141 {
1142 struct vpu_enc_expert_mode_param *expert;
1143
1144 expert = get_expert_param(shared, instance);
1145
1146 vpu_windsor_set_frame_rate(expert, params);
1147 vpu_windsor_set_qp(expert, params);
1148 vpu_windsor_set_sar(expert, params);
1149 vpu_windsor_set_color(expert, params);
1150 vpu_windsor_update_bitrate(shared, instance, params);
1151 /*expert->config_param.iac_sc_threshold = 0;*/
1152
1153 return 0;
1154 }
1155
vpu_windsor_set_encode_params(struct vpu_shared_addr * shared,u32 instance,struct vpu_encode_params * params,u32 update)1156 int vpu_windsor_set_encode_params(struct vpu_shared_addr *shared,
1157 u32 instance, struct vpu_encode_params *params, u32 update)
1158 {
1159 if (!params)
1160 return -EINVAL;
1161
1162 if (!update)
1163 return vpu_windsor_set_params(shared, instance, params);
1164 else
1165 return vpu_windsor_update_params(shared, instance, params);
1166 }
1167
vpu_windsor_get_max_instance_count(struct vpu_shared_addr * shared)1168 u32 vpu_windsor_get_max_instance_count(struct vpu_shared_addr *shared)
1169 {
1170 struct windsor_iface *iface = shared->iface;
1171
1172 return iface->max_streams;
1173 }
1174