1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright 2020-2021 NXP
4 */
5
6 #include <linux/init.h>
7 #include <linux/interconnect.h>
8 #include <linux/ioctl.h>
9 #include <linux/list.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/of_address.h>
14 #include <linux/platform_device.h>
15 #include <linux/firmware/imx/ipc.h>
16 #include <linux/firmware/imx/svc/misc.h>
17 #include "vpu.h"
18 #include "vpu_rpc.h"
19 #include "vpu_imx8q.h"
20 #include "vpu_windsor.h"
21 #include "vpu_malone.h"
22
vpu_iface_check_memory_region(struct vpu_core * core,dma_addr_t addr,u32 size)23 int vpu_iface_check_memory_region(struct vpu_core *core, dma_addr_t addr, u32 size)
24 {
25 struct vpu_iface_ops *ops = vpu_core_get_iface(core);
26
27 if (!ops || !ops->check_memory_region)
28 return VPU_CORE_MEMORY_INVALID;
29
30 return ops->check_memory_region(core->fw.phys, addr, size);
31 }
32
vpu_rpc_check_buffer_space(struct vpu_rpc_buffer_desc * desc,bool write)33 static u32 vpu_rpc_check_buffer_space(struct vpu_rpc_buffer_desc *desc, bool write)
34 {
35 u32 ptr1;
36 u32 ptr2;
37 u32 size;
38
39 size = desc->end - desc->start;
40 if (write) {
41 ptr1 = desc->wptr;
42 ptr2 = desc->rptr;
43 } else {
44 ptr1 = desc->rptr;
45 ptr2 = desc->wptr;
46 }
47
48 if (ptr1 == ptr2) {
49 if (!write)
50 return 0;
51 else
52 return size;
53 }
54
55 return (ptr2 + size - ptr1) % size;
56 }
57
vpu_rpc_send_cmd_buf(struct vpu_shared_addr * shared,struct vpu_rpc_event * cmd)58 static int vpu_rpc_send_cmd_buf(struct vpu_shared_addr *shared, struct vpu_rpc_event *cmd)
59 {
60 struct vpu_rpc_buffer_desc *desc;
61 u32 space = 0;
62 u32 *data;
63 u32 wptr;
64 u32 i;
65
66 if (cmd->hdr.num > 0xff || cmd->hdr.num >= ARRAY_SIZE(cmd->data))
67 return -EINVAL;
68 desc = shared->cmd_desc;
69 space = vpu_rpc_check_buffer_space(desc, true);
70 if (space < (((cmd->hdr.num + 1) << 2) + 16))
71 return -EINVAL;
72 wptr = desc->wptr;
73 data = (u32 *)(shared->cmd_mem_vir + desc->wptr - desc->start);
74 *data = 0;
75 *data |= ((cmd->hdr.index & 0xff) << 24);
76 *data |= ((cmd->hdr.num & 0xff) << 16);
77 *data |= (cmd->hdr.id & 0x3fff);
78 wptr += 4;
79 data++;
80 if (wptr >= desc->end) {
81 wptr = desc->start;
82 data = shared->cmd_mem_vir;
83 }
84
85 for (i = 0; i < cmd->hdr.num; i++) {
86 *data = cmd->data[i];
87 wptr += 4;
88 data++;
89 if (wptr >= desc->end) {
90 wptr = desc->start;
91 data = shared->cmd_mem_vir;
92 }
93 }
94
95 /*update wptr after data is written*/
96 mb();
97 desc->wptr = wptr;
98
99 return 0;
100 }
101
vpu_rpc_check_msg(struct vpu_shared_addr * shared)102 static bool vpu_rpc_check_msg(struct vpu_shared_addr *shared)
103 {
104 struct vpu_rpc_buffer_desc *desc;
105 u32 space = 0;
106 u32 msgword;
107 u32 msgnum;
108
109 desc = shared->msg_desc;
110 space = vpu_rpc_check_buffer_space(desc, 0);
111 space = (space >> 2);
112
113 if (space) {
114 msgword = *(u32 *)(shared->msg_mem_vir + desc->rptr - desc->start);
115 msgnum = (msgword & 0xff0000) >> 16;
116 if (msgnum <= space)
117 return true;
118 }
119
120 return false;
121 }
122
vpu_rpc_receive_msg_buf(struct vpu_shared_addr * shared,struct vpu_rpc_event * msg)123 static int vpu_rpc_receive_msg_buf(struct vpu_shared_addr *shared, struct vpu_rpc_event *msg)
124 {
125 struct vpu_rpc_buffer_desc *desc;
126 u32 *data;
127 u32 msgword;
128 u32 rptr;
129 u32 i;
130
131 if (!vpu_rpc_check_msg(shared))
132 return -EINVAL;
133
134 desc = shared->msg_desc;
135 data = (u32 *)(shared->msg_mem_vir + desc->rptr - desc->start);
136 rptr = desc->rptr;
137 msgword = *data;
138 data++;
139 rptr += 4;
140 if (rptr >= desc->end) {
141 rptr = desc->start;
142 data = shared->msg_mem_vir;
143 }
144
145 msg->hdr.index = (msgword >> 24) & 0xff;
146 msg->hdr.num = (msgword >> 16) & 0xff;
147 msg->hdr.id = msgword & 0x3fff;
148
149 if (msg->hdr.num > ARRAY_SIZE(msg->data))
150 return -EINVAL;
151
152 for (i = 0; i < msg->hdr.num; i++) {
153 msg->data[i] = *data;
154 data++;
155 rptr += 4;
156 if (rptr >= desc->end) {
157 rptr = desc->start;
158 data = shared->msg_mem_vir;
159 }
160 }
161
162 /*update rptr after data is read*/
163 mb();
164 desc->rptr = rptr;
165
166 return 0;
167 }
168
169 static struct vpu_iface_ops imx8q_rpc_ops[] = {
170 [VPU_CORE_TYPE_ENC] = {
171 .check_codec = vpu_imx8q_check_codec,
172 .check_fmt = vpu_imx8q_check_fmt,
173 .boot_core = vpu_imx8q_boot_core,
174 .get_power_state = vpu_imx8q_get_power_state,
175 .on_firmware_loaded = vpu_imx8q_on_firmware_loaded,
176 .get_data_size = vpu_windsor_get_data_size,
177 .check_memory_region = vpu_imx8q_check_memory_region,
178 .init_rpc = vpu_windsor_init_rpc,
179 .set_log_buf = vpu_windsor_set_log_buf,
180 .set_system_cfg = vpu_windsor_set_system_cfg,
181 .get_version = vpu_windsor_get_version,
182 .send_cmd_buf = vpu_rpc_send_cmd_buf,
183 .receive_msg_buf = vpu_rpc_receive_msg_buf,
184 .pack_cmd = vpu_windsor_pack_cmd,
185 .convert_msg_id = vpu_windsor_convert_msg_id,
186 .unpack_msg_data = vpu_windsor_unpack_msg_data,
187 .config_memory_resource = vpu_windsor_config_memory_resource,
188 .get_stream_buffer_size = vpu_windsor_get_stream_buffer_size,
189 .config_stream_buffer = vpu_windsor_config_stream_buffer,
190 .get_stream_buffer_desc = vpu_windsor_get_stream_buffer_desc,
191 .update_stream_buffer = vpu_windsor_update_stream_buffer,
192 .set_encode_params = vpu_windsor_set_encode_params,
193 .input_frame = vpu_windsor_input_frame,
194 .get_max_instance_count = vpu_windsor_get_max_instance_count,
195 },
196 [VPU_CORE_TYPE_DEC] = {
197 .check_codec = vpu_imx8q_check_codec,
198 .check_fmt = vpu_malone_check_fmt,
199 .boot_core = vpu_imx8q_boot_core,
200 .get_power_state = vpu_imx8q_get_power_state,
201 .on_firmware_loaded = vpu_imx8q_on_firmware_loaded,
202 .get_data_size = vpu_malone_get_data_size,
203 .check_memory_region = vpu_imx8q_check_memory_region,
204 .init_rpc = vpu_malone_init_rpc,
205 .set_log_buf = vpu_malone_set_log_buf,
206 .set_system_cfg = vpu_malone_set_system_cfg,
207 .get_version = vpu_malone_get_version,
208 .send_cmd_buf = vpu_rpc_send_cmd_buf,
209 .receive_msg_buf = vpu_rpc_receive_msg_buf,
210 .get_stream_buffer_size = vpu_malone_get_stream_buffer_size,
211 .config_stream_buffer = vpu_malone_config_stream_buffer,
212 .set_decode_params = vpu_malone_set_decode_params,
213 .pack_cmd = vpu_malone_pack_cmd,
214 .convert_msg_id = vpu_malone_convert_msg_id,
215 .unpack_msg_data = vpu_malone_unpack_msg_data,
216 .get_stream_buffer_desc = vpu_malone_get_stream_buffer_desc,
217 .update_stream_buffer = vpu_malone_update_stream_buffer,
218 .add_scode = vpu_malone_add_scode,
219 .input_frame = vpu_malone_input_frame,
220 .pre_send_cmd = vpu_malone_pre_cmd,
221 .post_send_cmd = vpu_malone_post_cmd,
222 .init_instance = vpu_malone_init_instance,
223 .get_max_instance_count = vpu_malone_get_max_instance_count,
224 },
225 };
226
vpu_get_iface(struct vpu_dev * vpu,enum vpu_core_type type)227 static struct vpu_iface_ops *vpu_get_iface(struct vpu_dev *vpu, enum vpu_core_type type)
228 {
229 struct vpu_iface_ops *rpc_ops = NULL;
230 u32 size = 0;
231
232 switch (vpu->res->plat_type) {
233 case IMX8QXP:
234 case IMX8QM:
235 rpc_ops = imx8q_rpc_ops;
236 size = ARRAY_SIZE(imx8q_rpc_ops);
237 break;
238 default:
239 return NULL;
240 }
241
242 if (type >= size)
243 return NULL;
244
245 return &rpc_ops[type];
246 }
247
vpu_core_get_iface(struct vpu_core * core)248 struct vpu_iface_ops *vpu_core_get_iface(struct vpu_core *core)
249 {
250 return vpu_get_iface(core->vpu, core->type);
251 }
252
vpu_inst_get_iface(struct vpu_inst * inst)253 struct vpu_iface_ops *vpu_inst_get_iface(struct vpu_inst *inst)
254 {
255 if (inst->core)
256 return vpu_core_get_iface(inst->core);
257
258 return vpu_get_iface(inst->vpu, inst->type);
259 }
260