1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include "drmP.h"
27 #include "radeon_drm.h"
28 #include "radeon.h"
29
30 #include "atom.h"
31 #include "atom-bits.h"
32
33 /* from radeon_encoder.c */
34 extern uint32_t
35 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
36 uint8_t dac);
37 extern void radeon_link_encoder_connector(struct drm_device *dev);
38 extern void
39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
40 uint32_t supported_device, u16 caps);
41
42 /* from radeon_connector.c */
43 extern void
44 radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
47 int connector_type,
48 struct radeon_i2c_bus_rec *i2c_bus,
49 uint32_t igp_lane_info,
50 uint16_t connector_object_id,
51 struct radeon_hpd *hpd,
52 struct radeon_router *router);
53
54 /* from radeon_legacy_encoder.c */
55 extern void
56 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
57 uint32_t supported_device);
58
59 /* local */
60 static int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
61 u16 voltage_id, u16 *voltage);
62
63 union atom_supported_devices {
64 struct _ATOM_SUPPORTED_DEVICES_INFO info;
65 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
66 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
67 };
68
radeon_lookup_i2c_gpio_quirks(struct radeon_device * rdev,ATOM_GPIO_I2C_ASSIGMENT * gpio,u8 index)69 static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev,
70 ATOM_GPIO_I2C_ASSIGMENT *gpio,
71 u8 index)
72 {
73 /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
74 if ((rdev->family == CHIP_R420) ||
75 (rdev->family == CHIP_R423) ||
76 (rdev->family == CHIP_RV410)) {
77 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
78 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
79 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
80 gpio->ucClkMaskShift = 0x19;
81 gpio->ucDataMaskShift = 0x18;
82 }
83 }
84
85 /* some evergreen boards have bad data for this entry */
86 if (ASIC_IS_DCE4(rdev)) {
87 if ((index == 7) &&
88 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
89 (gpio->sucI2cId.ucAccess == 0)) {
90 gpio->sucI2cId.ucAccess = 0x97;
91 gpio->ucDataMaskShift = 8;
92 gpio->ucDataEnShift = 8;
93 gpio->ucDataY_Shift = 8;
94 gpio->ucDataA_Shift = 8;
95 }
96 }
97
98 /* some DCE3 boards have bad data for this entry */
99 if (ASIC_IS_DCE3(rdev)) {
100 if ((index == 4) &&
101 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
102 (gpio->sucI2cId.ucAccess == 0x94))
103 gpio->sucI2cId.ucAccess = 0x14;
104 }
105 }
106
radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT * gpio)107 static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
108 {
109 struct radeon_i2c_bus_rec i2c;
110
111 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
112
113 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
114 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
115 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
116 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
117 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
118 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
119 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
120 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
121 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
122 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
123 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
124 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
125 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
126 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
127 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
128 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
129
130 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
131 i2c.hw_capable = true;
132 else
133 i2c.hw_capable = false;
134
135 if (gpio->sucI2cId.ucAccess == 0xa0)
136 i2c.mm_i2c = true;
137 else
138 i2c.mm_i2c = false;
139
140 i2c.i2c_id = gpio->sucI2cId.ucAccess;
141
142 if (i2c.mask_clk_reg)
143 i2c.valid = true;
144 else
145 i2c.valid = false;
146
147 return i2c;
148 }
149
radeon_lookup_i2c_gpio(struct radeon_device * rdev,uint8_t id)150 static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
151 uint8_t id)
152 {
153 struct atom_context *ctx = rdev->mode_info.atom_context;
154 ATOM_GPIO_I2C_ASSIGMENT *gpio;
155 struct radeon_i2c_bus_rec i2c;
156 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
157 struct _ATOM_GPIO_I2C_INFO *i2c_info;
158 uint16_t data_offset, size;
159 int i, num_indices;
160
161 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
162 i2c.valid = false;
163
164 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
165 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
166
167 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
168 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
169
170 for (i = 0; i < num_indices; i++) {
171 gpio = &i2c_info->asGPIO_Info[i];
172
173 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
174
175 if (gpio->sucI2cId.ucAccess == id) {
176 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
177 break;
178 }
179 }
180 }
181
182 return i2c;
183 }
184
radeon_atombios_i2c_init(struct radeon_device * rdev)185 void radeon_atombios_i2c_init(struct radeon_device *rdev)
186 {
187 struct atom_context *ctx = rdev->mode_info.atom_context;
188 ATOM_GPIO_I2C_ASSIGMENT *gpio;
189 struct radeon_i2c_bus_rec i2c;
190 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
191 struct _ATOM_GPIO_I2C_INFO *i2c_info;
192 uint16_t data_offset, size;
193 int i, num_indices;
194 char stmp[32];
195
196 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
197 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
198
199 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
200 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
201
202 for (i = 0; i < num_indices; i++) {
203 gpio = &i2c_info->asGPIO_Info[i];
204
205 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
206
207 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
208
209 if (i2c.valid) {
210 sprintf(stmp, "0x%x", i2c.i2c_id);
211 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
212 }
213 }
214 }
215 }
216
radeon_lookup_gpio(struct radeon_device * rdev,u8 id)217 static struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
218 u8 id)
219 {
220 struct atom_context *ctx = rdev->mode_info.atom_context;
221 struct radeon_gpio_rec gpio;
222 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
223 struct _ATOM_GPIO_PIN_LUT *gpio_info;
224 ATOM_GPIO_PIN_ASSIGNMENT *pin;
225 u16 data_offset, size;
226 int i, num_indices;
227
228 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
229 gpio.valid = false;
230
231 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
232 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
233
234 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
235 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
236
237 for (i = 0; i < num_indices; i++) {
238 pin = &gpio_info->asGPIO_Pin[i];
239 if (id == pin->ucGPIO_ID) {
240 gpio.id = pin->ucGPIO_ID;
241 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
242 gpio.mask = (1 << pin->ucGpioPinBitShift);
243 gpio.valid = true;
244 break;
245 }
246 }
247 }
248
249 return gpio;
250 }
251
radeon_atom_get_hpd_info_from_gpio(struct radeon_device * rdev,struct radeon_gpio_rec * gpio)252 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
253 struct radeon_gpio_rec *gpio)
254 {
255 struct radeon_hpd hpd;
256 u32 reg;
257
258 memset(&hpd, 0, sizeof(struct radeon_hpd));
259
260 if (ASIC_IS_DCE6(rdev))
261 reg = SI_DC_GPIO_HPD_A;
262 else if (ASIC_IS_DCE4(rdev))
263 reg = EVERGREEN_DC_GPIO_HPD_A;
264 else
265 reg = AVIVO_DC_GPIO_HPD_A;
266
267 hpd.gpio = *gpio;
268 if (gpio->reg == reg) {
269 switch(gpio->mask) {
270 case (1 << 0):
271 hpd.hpd = RADEON_HPD_1;
272 break;
273 case (1 << 8):
274 hpd.hpd = RADEON_HPD_2;
275 break;
276 case (1 << 16):
277 hpd.hpd = RADEON_HPD_3;
278 break;
279 case (1 << 24):
280 hpd.hpd = RADEON_HPD_4;
281 break;
282 case (1 << 26):
283 hpd.hpd = RADEON_HPD_5;
284 break;
285 case (1 << 28):
286 hpd.hpd = RADEON_HPD_6;
287 break;
288 default:
289 hpd.hpd = RADEON_HPD_NONE;
290 break;
291 }
292 } else
293 hpd.hpd = RADEON_HPD_NONE;
294 return hpd;
295 }
296
radeon_atom_apply_quirks(struct drm_device * dev,uint32_t supported_device,int * connector_type,struct radeon_i2c_bus_rec * i2c_bus,uint16_t * line_mux,struct radeon_hpd * hpd)297 static bool radeon_atom_apply_quirks(struct drm_device *dev,
298 uint32_t supported_device,
299 int *connector_type,
300 struct radeon_i2c_bus_rec *i2c_bus,
301 uint16_t *line_mux,
302 struct radeon_hpd *hpd)
303 {
304
305 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
306 if ((dev->pdev->device == 0x791e) &&
307 (dev->pdev->subsystem_vendor == 0x1043) &&
308 (dev->pdev->subsystem_device == 0x826d)) {
309 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
310 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
311 *connector_type = DRM_MODE_CONNECTOR_DVID;
312 }
313
314 /* Asrock RS600 board lists the DVI port as HDMI */
315 if ((dev->pdev->device == 0x7941) &&
316 (dev->pdev->subsystem_vendor == 0x1849) &&
317 (dev->pdev->subsystem_device == 0x7941)) {
318 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
319 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
320 *connector_type = DRM_MODE_CONNECTOR_DVID;
321 }
322
323 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
324 if ((dev->pdev->device == 0x796e) &&
325 (dev->pdev->subsystem_vendor == 0x1462) &&
326 (dev->pdev->subsystem_device == 0x7302)) {
327 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
328 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
329 return false;
330 }
331
332 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
333 if ((dev->pdev->device == 0x7941) &&
334 (dev->pdev->subsystem_vendor == 0x147b) &&
335 (dev->pdev->subsystem_device == 0x2412)) {
336 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
337 return false;
338 }
339
340 /* Falcon NW laptop lists vga ddc line for LVDS */
341 if ((dev->pdev->device == 0x5653) &&
342 (dev->pdev->subsystem_vendor == 0x1462) &&
343 (dev->pdev->subsystem_device == 0x0291)) {
344 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
345 i2c_bus->valid = false;
346 *line_mux = 53;
347 }
348 }
349
350 /* HIS X1300 is DVI+VGA, not DVI+DVI */
351 if ((dev->pdev->device == 0x7146) &&
352 (dev->pdev->subsystem_vendor == 0x17af) &&
353 (dev->pdev->subsystem_device == 0x2058)) {
354 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
355 return false;
356 }
357
358 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
359 if ((dev->pdev->device == 0x7142) &&
360 (dev->pdev->subsystem_vendor == 0x1458) &&
361 (dev->pdev->subsystem_device == 0x2134)) {
362 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
363 return false;
364 }
365
366
367 /* Funky macbooks */
368 if ((dev->pdev->device == 0x71C5) &&
369 (dev->pdev->subsystem_vendor == 0x106b) &&
370 (dev->pdev->subsystem_device == 0x0080)) {
371 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
372 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
373 return false;
374 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
375 *line_mux = 0x90;
376 }
377
378 /* mac rv630, rv730, others */
379 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
380 (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
381 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
382 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
383 }
384
385 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
386 if ((dev->pdev->device == 0x9598) &&
387 (dev->pdev->subsystem_vendor == 0x1043) &&
388 (dev->pdev->subsystem_device == 0x01da)) {
389 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
390 *connector_type = DRM_MODE_CONNECTOR_DVII;
391 }
392 }
393
394 /* ASUS HD 3600 board lists the DVI port as HDMI */
395 if ((dev->pdev->device == 0x9598) &&
396 (dev->pdev->subsystem_vendor == 0x1043) &&
397 (dev->pdev->subsystem_device == 0x01e4)) {
398 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
399 *connector_type = DRM_MODE_CONNECTOR_DVII;
400 }
401 }
402
403 /* ASUS HD 3450 board lists the DVI port as HDMI */
404 if ((dev->pdev->device == 0x95C5) &&
405 (dev->pdev->subsystem_vendor == 0x1043) &&
406 (dev->pdev->subsystem_device == 0x01e2)) {
407 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
408 *connector_type = DRM_MODE_CONNECTOR_DVII;
409 }
410 }
411
412 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
413 * HDMI + VGA reporting as HDMI
414 */
415 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
416 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
417 *connector_type = DRM_MODE_CONNECTOR_VGA;
418 *line_mux = 0;
419 }
420 }
421
422 /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
423 * on the laptop and a DVI port on the docking station and
424 * both share the same encoder, hpd pin, and ddc line.
425 * So while the bios table is technically correct,
426 * we drop the DVI port here since xrandr has no concept of
427 * encoders and will try and drive both connectors
428 * with different crtcs which isn't possible on the hardware
429 * side and leaves no crtcs for LVDS or VGA.
430 */
431 if (((dev->pdev->device == 0x95c4) || (dev->pdev->device == 0x9591)) &&
432 (dev->pdev->subsystem_vendor == 0x1025) &&
433 (dev->pdev->subsystem_device == 0x013c)) {
434 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
435 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
436 /* actually it's a DVI-D port not DVI-I */
437 *connector_type = DRM_MODE_CONNECTOR_DVID;
438 return false;
439 }
440 }
441
442 /* XFX Pine Group device rv730 reports no VGA DDC lines
443 * even though they are wired up to record 0x93
444 */
445 if ((dev->pdev->device == 0x9498) &&
446 (dev->pdev->subsystem_vendor == 0x1682) &&
447 (dev->pdev->subsystem_device == 0x2452) &&
448 (i2c_bus->valid == false) &&
449 !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) {
450 struct radeon_device *rdev = dev->dev_private;
451 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
452 }
453
454 /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
455 if (((dev->pdev->device == 0x9802) || (dev->pdev->device == 0x9806)) &&
456 (dev->pdev->subsystem_vendor == 0x1734) &&
457 (dev->pdev->subsystem_device == 0x11bd)) {
458 if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
459 *connector_type = DRM_MODE_CONNECTOR_DVII;
460 *line_mux = 0x3103;
461 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) {
462 *connector_type = DRM_MODE_CONNECTOR_DVII;
463 }
464 }
465
466
467 return true;
468 }
469
470 const int supported_devices_connector_convert[] = {
471 DRM_MODE_CONNECTOR_Unknown,
472 DRM_MODE_CONNECTOR_VGA,
473 DRM_MODE_CONNECTOR_DVII,
474 DRM_MODE_CONNECTOR_DVID,
475 DRM_MODE_CONNECTOR_DVIA,
476 DRM_MODE_CONNECTOR_SVIDEO,
477 DRM_MODE_CONNECTOR_Composite,
478 DRM_MODE_CONNECTOR_LVDS,
479 DRM_MODE_CONNECTOR_Unknown,
480 DRM_MODE_CONNECTOR_Unknown,
481 DRM_MODE_CONNECTOR_HDMIA,
482 DRM_MODE_CONNECTOR_HDMIB,
483 DRM_MODE_CONNECTOR_Unknown,
484 DRM_MODE_CONNECTOR_Unknown,
485 DRM_MODE_CONNECTOR_9PinDIN,
486 DRM_MODE_CONNECTOR_DisplayPort
487 };
488
489 const uint16_t supported_devices_connector_object_id_convert[] = {
490 CONNECTOR_OBJECT_ID_NONE,
491 CONNECTOR_OBJECT_ID_VGA,
492 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
493 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
494 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
495 CONNECTOR_OBJECT_ID_COMPOSITE,
496 CONNECTOR_OBJECT_ID_SVIDEO,
497 CONNECTOR_OBJECT_ID_LVDS,
498 CONNECTOR_OBJECT_ID_9PIN_DIN,
499 CONNECTOR_OBJECT_ID_9PIN_DIN,
500 CONNECTOR_OBJECT_ID_DISPLAYPORT,
501 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
502 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
503 CONNECTOR_OBJECT_ID_SVIDEO
504 };
505
506 const int object_connector_convert[] = {
507 DRM_MODE_CONNECTOR_Unknown,
508 DRM_MODE_CONNECTOR_DVII,
509 DRM_MODE_CONNECTOR_DVII,
510 DRM_MODE_CONNECTOR_DVID,
511 DRM_MODE_CONNECTOR_DVID,
512 DRM_MODE_CONNECTOR_VGA,
513 DRM_MODE_CONNECTOR_Composite,
514 DRM_MODE_CONNECTOR_SVIDEO,
515 DRM_MODE_CONNECTOR_Unknown,
516 DRM_MODE_CONNECTOR_Unknown,
517 DRM_MODE_CONNECTOR_9PinDIN,
518 DRM_MODE_CONNECTOR_Unknown,
519 DRM_MODE_CONNECTOR_HDMIA,
520 DRM_MODE_CONNECTOR_HDMIB,
521 DRM_MODE_CONNECTOR_LVDS,
522 DRM_MODE_CONNECTOR_9PinDIN,
523 DRM_MODE_CONNECTOR_Unknown,
524 DRM_MODE_CONNECTOR_Unknown,
525 DRM_MODE_CONNECTOR_Unknown,
526 DRM_MODE_CONNECTOR_DisplayPort,
527 DRM_MODE_CONNECTOR_eDP,
528 DRM_MODE_CONNECTOR_Unknown
529 };
530
radeon_get_atom_connector_info_from_object_table(struct drm_device * dev)531 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
532 {
533 struct radeon_device *rdev = dev->dev_private;
534 struct radeon_mode_info *mode_info = &rdev->mode_info;
535 struct atom_context *ctx = mode_info->atom_context;
536 int index = GetIndexIntoMasterTable(DATA, Object_Header);
537 u16 size, data_offset;
538 u8 frev, crev;
539 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
540 ATOM_ENCODER_OBJECT_TABLE *enc_obj;
541 ATOM_OBJECT_TABLE *router_obj;
542 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
543 ATOM_OBJECT_HEADER *obj_header;
544 int i, j, k, path_size, device_support;
545 int connector_type;
546 u16 igp_lane_info, conn_id, connector_object_id;
547 struct radeon_i2c_bus_rec ddc_bus;
548 struct radeon_router router;
549 struct radeon_gpio_rec gpio;
550 struct radeon_hpd hpd;
551
552 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
553 return false;
554
555 if (crev < 2)
556 return false;
557
558 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
559 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
560 (ctx->bios + data_offset +
561 le16_to_cpu(obj_header->usDisplayPathTableOffset));
562 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
563 (ctx->bios + data_offset +
564 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
565 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
566 (ctx->bios + data_offset +
567 le16_to_cpu(obj_header->usEncoderObjectTableOffset));
568 router_obj = (ATOM_OBJECT_TABLE *)
569 (ctx->bios + data_offset +
570 le16_to_cpu(obj_header->usRouterObjectTableOffset));
571 device_support = le16_to_cpu(obj_header->usDeviceSupport);
572
573 path_size = 0;
574 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
575 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
576 ATOM_DISPLAY_OBJECT_PATH *path;
577 addr += path_size;
578 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
579 path_size += le16_to_cpu(path->usSize);
580
581 if (device_support & le16_to_cpu(path->usDeviceTag)) {
582 uint8_t con_obj_id, con_obj_num, con_obj_type;
583
584 con_obj_id =
585 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
586 >> OBJECT_ID_SHIFT;
587 con_obj_num =
588 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
589 >> ENUM_ID_SHIFT;
590 con_obj_type =
591 (le16_to_cpu(path->usConnObjectId) &
592 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
593
594 /* TODO CV support */
595 if (le16_to_cpu(path->usDeviceTag) ==
596 ATOM_DEVICE_CV_SUPPORT)
597 continue;
598
599 /* IGP chips */
600 if ((rdev->flags & RADEON_IS_IGP) &&
601 (con_obj_id ==
602 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
603 uint16_t igp_offset = 0;
604 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
605
606 index =
607 GetIndexIntoMasterTable(DATA,
608 IntegratedSystemInfo);
609
610 if (atom_parse_data_header(ctx, index, &size, &frev,
611 &crev, &igp_offset)) {
612
613 if (crev >= 2) {
614 igp_obj =
615 (ATOM_INTEGRATED_SYSTEM_INFO_V2
616 *) (ctx->bios + igp_offset);
617
618 if (igp_obj) {
619 uint32_t slot_config, ct;
620
621 if (con_obj_num == 1)
622 slot_config =
623 igp_obj->
624 ulDDISlot1Config;
625 else
626 slot_config =
627 igp_obj->
628 ulDDISlot2Config;
629
630 ct = (slot_config >> 16) & 0xff;
631 connector_type =
632 object_connector_convert
633 [ct];
634 connector_object_id = ct;
635 igp_lane_info =
636 slot_config & 0xffff;
637 } else
638 continue;
639 } else
640 continue;
641 } else {
642 igp_lane_info = 0;
643 connector_type =
644 object_connector_convert[con_obj_id];
645 connector_object_id = con_obj_id;
646 }
647 } else {
648 igp_lane_info = 0;
649 connector_type =
650 object_connector_convert[con_obj_id];
651 connector_object_id = con_obj_id;
652 }
653
654 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
655 continue;
656
657 router.ddc_valid = false;
658 router.cd_valid = false;
659 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
660 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
661
662 grph_obj_id =
663 (le16_to_cpu(path->usGraphicObjIds[j]) &
664 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
665 grph_obj_num =
666 (le16_to_cpu(path->usGraphicObjIds[j]) &
667 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
668 grph_obj_type =
669 (le16_to_cpu(path->usGraphicObjIds[j]) &
670 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
671
672 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
673 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
674 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
675 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
676 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
677 (ctx->bios + data_offset +
678 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
679 ATOM_ENCODER_CAP_RECORD *cap_record;
680 u16 caps = 0;
681
682 while (record->ucRecordSize > 0 &&
683 record->ucRecordType > 0 &&
684 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
685 switch (record->ucRecordType) {
686 case ATOM_ENCODER_CAP_RECORD_TYPE:
687 cap_record =(ATOM_ENCODER_CAP_RECORD *)
688 record;
689 caps = le16_to_cpu(cap_record->usEncoderCap);
690 break;
691 }
692 record = (ATOM_COMMON_RECORD_HEADER *)
693 ((char *)record + record->ucRecordSize);
694 }
695 radeon_add_atom_encoder(dev,
696 encoder_obj,
697 le16_to_cpu
698 (path->
699 usDeviceTag),
700 caps);
701 }
702 }
703 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
704 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
705 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
706 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
707 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
708 (ctx->bios + data_offset +
709 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
710 ATOM_I2C_RECORD *i2c_record;
711 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
712 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
713 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
714 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
715 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
716 (ctx->bios + data_offset +
717 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
718 u8 *num_dst_objs = (u8 *)
719 ((u8 *)router_src_dst_table + 1 +
720 (router_src_dst_table->ucNumberOfSrc * 2));
721 u16 *dst_objs = (u16 *)(num_dst_objs + 1);
722 int enum_id;
723
724 router.router_id = router_obj_id;
725 for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) {
726 if (le16_to_cpu(path->usConnObjectId) ==
727 le16_to_cpu(dst_objs[enum_id]))
728 break;
729 }
730
731 while (record->ucRecordSize > 0 &&
732 record->ucRecordType > 0 &&
733 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
734 switch (record->ucRecordType) {
735 case ATOM_I2C_RECORD_TYPE:
736 i2c_record =
737 (ATOM_I2C_RECORD *)
738 record;
739 i2c_config =
740 (ATOM_I2C_ID_CONFIG_ACCESS *)
741 &i2c_record->sucI2cId;
742 router.i2c_info =
743 radeon_lookup_i2c_gpio(rdev,
744 i2c_config->
745 ucAccess);
746 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
747 break;
748 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
749 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
750 record;
751 router.ddc_valid = true;
752 router.ddc_mux_type = ddc_path->ucMuxType;
753 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
754 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
755 break;
756 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
757 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
758 record;
759 router.cd_valid = true;
760 router.cd_mux_type = cd_path->ucMuxType;
761 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
762 router.cd_mux_state = cd_path->ucMuxState[enum_id];
763 break;
764 }
765 record = (ATOM_COMMON_RECORD_HEADER *)
766 ((char *)record + record->ucRecordSize);
767 }
768 }
769 }
770 }
771 }
772
773 /* look up gpio for ddc, hpd */
774 ddc_bus.valid = false;
775 hpd.hpd = RADEON_HPD_NONE;
776 if ((le16_to_cpu(path->usDeviceTag) &
777 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
778 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
779 if (le16_to_cpu(path->usConnObjectId) ==
780 le16_to_cpu(con_obj->asObjects[j].
781 usObjectID)) {
782 ATOM_COMMON_RECORD_HEADER
783 *record =
784 (ATOM_COMMON_RECORD_HEADER
785 *)
786 (ctx->bios + data_offset +
787 le16_to_cpu(con_obj->
788 asObjects[j].
789 usRecordOffset));
790 ATOM_I2C_RECORD *i2c_record;
791 ATOM_HPD_INT_RECORD *hpd_record;
792 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
793
794 while (record->ucRecordSize > 0 &&
795 record->ucRecordType > 0 &&
796 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
797 switch (record->ucRecordType) {
798 case ATOM_I2C_RECORD_TYPE:
799 i2c_record =
800 (ATOM_I2C_RECORD *)
801 record;
802 i2c_config =
803 (ATOM_I2C_ID_CONFIG_ACCESS *)
804 &i2c_record->sucI2cId;
805 ddc_bus = radeon_lookup_i2c_gpio(rdev,
806 i2c_config->
807 ucAccess);
808 break;
809 case ATOM_HPD_INT_RECORD_TYPE:
810 hpd_record =
811 (ATOM_HPD_INT_RECORD *)
812 record;
813 gpio = radeon_lookup_gpio(rdev,
814 hpd_record->ucHPDIntGPIOID);
815 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
816 hpd.plugged_state = hpd_record->ucPlugged_PinState;
817 break;
818 }
819 record =
820 (ATOM_COMMON_RECORD_HEADER
821 *) ((char *)record
822 +
823 record->
824 ucRecordSize);
825 }
826 break;
827 }
828 }
829 }
830
831 /* needed for aux chan transactions */
832 ddc_bus.hpd = hpd.hpd;
833
834 conn_id = le16_to_cpu(path->usConnObjectId);
835
836 if (!radeon_atom_apply_quirks
837 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
838 &ddc_bus, &conn_id, &hpd))
839 continue;
840
841 radeon_add_atom_connector(dev,
842 conn_id,
843 le16_to_cpu(path->
844 usDeviceTag),
845 connector_type, &ddc_bus,
846 igp_lane_info,
847 connector_object_id,
848 &hpd,
849 &router);
850
851 }
852 }
853
854 radeon_link_encoder_connector(dev);
855
856 return true;
857 }
858
atombios_get_connector_object_id(struct drm_device * dev,int connector_type,uint16_t devices)859 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
860 int connector_type,
861 uint16_t devices)
862 {
863 struct radeon_device *rdev = dev->dev_private;
864
865 if (rdev->flags & RADEON_IS_IGP) {
866 return supported_devices_connector_object_id_convert
867 [connector_type];
868 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
869 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
870 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
871 struct radeon_mode_info *mode_info = &rdev->mode_info;
872 struct atom_context *ctx = mode_info->atom_context;
873 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
874 uint16_t size, data_offset;
875 uint8_t frev, crev;
876 ATOM_XTMDS_INFO *xtmds;
877
878 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
879 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
880
881 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
882 if (connector_type == DRM_MODE_CONNECTOR_DVII)
883 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
884 else
885 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
886 } else {
887 if (connector_type == DRM_MODE_CONNECTOR_DVII)
888 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
889 else
890 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
891 }
892 } else
893 return supported_devices_connector_object_id_convert
894 [connector_type];
895 } else {
896 return supported_devices_connector_object_id_convert
897 [connector_type];
898 }
899 }
900
901 struct bios_connector {
902 bool valid;
903 uint16_t line_mux;
904 uint16_t devices;
905 int connector_type;
906 struct radeon_i2c_bus_rec ddc_bus;
907 struct radeon_hpd hpd;
908 };
909
radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device * dev)910 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
911 drm_device
912 *dev)
913 {
914 struct radeon_device *rdev = dev->dev_private;
915 struct radeon_mode_info *mode_info = &rdev->mode_info;
916 struct atom_context *ctx = mode_info->atom_context;
917 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
918 uint16_t size, data_offset;
919 uint8_t frev, crev;
920 uint16_t device_support;
921 uint8_t dac;
922 union atom_supported_devices *supported_devices;
923 int i, j, max_device;
924 struct bios_connector *bios_connectors;
925 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
926 struct radeon_router router;
927
928 router.ddc_valid = false;
929 router.cd_valid = false;
930
931 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
932 if (!bios_connectors)
933 return false;
934
935 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
936 &data_offset)) {
937 kfree(bios_connectors);
938 return false;
939 }
940
941 supported_devices =
942 (union atom_supported_devices *)(ctx->bios + data_offset);
943
944 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
945
946 if (frev > 1)
947 max_device = ATOM_MAX_SUPPORTED_DEVICE;
948 else
949 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
950
951 for (i = 0; i < max_device; i++) {
952 ATOM_CONNECTOR_INFO_I2C ci =
953 supported_devices->info.asConnInfo[i];
954
955 bios_connectors[i].valid = false;
956
957 if (!(device_support & (1 << i))) {
958 continue;
959 }
960
961 if (i == ATOM_DEVICE_CV_INDEX) {
962 DRM_DEBUG_KMS("Skipping Component Video\n");
963 continue;
964 }
965
966 bios_connectors[i].connector_type =
967 supported_devices_connector_convert[ci.sucConnectorInfo.
968 sbfAccess.
969 bfConnectorType];
970
971 if (bios_connectors[i].connector_type ==
972 DRM_MODE_CONNECTOR_Unknown)
973 continue;
974
975 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
976
977 bios_connectors[i].line_mux =
978 ci.sucI2cId.ucAccess;
979
980 /* give tv unique connector ids */
981 if (i == ATOM_DEVICE_TV1_INDEX) {
982 bios_connectors[i].ddc_bus.valid = false;
983 bios_connectors[i].line_mux = 50;
984 } else if (i == ATOM_DEVICE_TV2_INDEX) {
985 bios_connectors[i].ddc_bus.valid = false;
986 bios_connectors[i].line_mux = 51;
987 } else if (i == ATOM_DEVICE_CV_INDEX) {
988 bios_connectors[i].ddc_bus.valid = false;
989 bios_connectors[i].line_mux = 52;
990 } else
991 bios_connectors[i].ddc_bus =
992 radeon_lookup_i2c_gpio(rdev,
993 bios_connectors[i].line_mux);
994
995 if ((crev > 1) && (frev > 1)) {
996 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
997 switch (isb) {
998 case 0x4:
999 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
1000 break;
1001 case 0xa:
1002 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
1003 break;
1004 default:
1005 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1006 break;
1007 }
1008 } else {
1009 if (i == ATOM_DEVICE_DFP1_INDEX)
1010 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
1011 else if (i == ATOM_DEVICE_DFP2_INDEX)
1012 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
1013 else
1014 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1015 }
1016
1017 /* Always set the connector type to VGA for CRT1/CRT2. if they are
1018 * shared with a DVI port, we'll pick up the DVI connector when we
1019 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
1020 */
1021 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
1022 bios_connectors[i].connector_type =
1023 DRM_MODE_CONNECTOR_VGA;
1024
1025 if (!radeon_atom_apply_quirks
1026 (dev, (1 << i), &bios_connectors[i].connector_type,
1027 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1028 &bios_connectors[i].hpd))
1029 continue;
1030
1031 bios_connectors[i].valid = true;
1032 bios_connectors[i].devices = (1 << i);
1033
1034 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1035 radeon_add_atom_encoder(dev,
1036 radeon_get_encoder_enum(dev,
1037 (1 << i),
1038 dac),
1039 (1 << i),
1040 0);
1041 else
1042 radeon_add_legacy_encoder(dev,
1043 radeon_get_encoder_enum(dev,
1044 (1 << i),
1045 dac),
1046 (1 << i));
1047 }
1048
1049 /* combine shared connectors */
1050 for (i = 0; i < max_device; i++) {
1051 if (bios_connectors[i].valid) {
1052 for (j = 0; j < max_device; j++) {
1053 if (bios_connectors[j].valid && (i != j)) {
1054 if (bios_connectors[i].line_mux ==
1055 bios_connectors[j].line_mux) {
1056 /* make sure not to combine LVDS */
1057 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1058 bios_connectors[i].line_mux = 53;
1059 bios_connectors[i].ddc_bus.valid = false;
1060 continue;
1061 }
1062 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1063 bios_connectors[j].line_mux = 53;
1064 bios_connectors[j].ddc_bus.valid = false;
1065 continue;
1066 }
1067 /* combine analog and digital for DVI-I */
1068 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1069 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1070 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1071 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1072 bios_connectors[i].devices |=
1073 bios_connectors[j].devices;
1074 bios_connectors[i].connector_type =
1075 DRM_MODE_CONNECTOR_DVII;
1076 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1077 bios_connectors[i].hpd =
1078 bios_connectors[j].hpd;
1079 bios_connectors[j].valid = false;
1080 }
1081 }
1082 }
1083 }
1084 }
1085 }
1086
1087 /* add the connectors */
1088 for (i = 0; i < max_device; i++) {
1089 if (bios_connectors[i].valid) {
1090 uint16_t connector_object_id =
1091 atombios_get_connector_object_id(dev,
1092 bios_connectors[i].connector_type,
1093 bios_connectors[i].devices);
1094 radeon_add_atom_connector(dev,
1095 bios_connectors[i].line_mux,
1096 bios_connectors[i].devices,
1097 bios_connectors[i].
1098 connector_type,
1099 &bios_connectors[i].ddc_bus,
1100 0,
1101 connector_object_id,
1102 &bios_connectors[i].hpd,
1103 &router);
1104 }
1105 }
1106
1107 radeon_link_encoder_connector(dev);
1108
1109 kfree(bios_connectors);
1110 return true;
1111 }
1112
1113 union firmware_info {
1114 ATOM_FIRMWARE_INFO info;
1115 ATOM_FIRMWARE_INFO_V1_2 info_12;
1116 ATOM_FIRMWARE_INFO_V1_3 info_13;
1117 ATOM_FIRMWARE_INFO_V1_4 info_14;
1118 ATOM_FIRMWARE_INFO_V2_1 info_21;
1119 ATOM_FIRMWARE_INFO_V2_2 info_22;
1120 };
1121
radeon_atom_get_clock_info(struct drm_device * dev)1122 bool radeon_atom_get_clock_info(struct drm_device *dev)
1123 {
1124 struct radeon_device *rdev = dev->dev_private;
1125 struct radeon_mode_info *mode_info = &rdev->mode_info;
1126 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1127 union firmware_info *firmware_info;
1128 uint8_t frev, crev;
1129 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1130 struct radeon_pll *p2pll = &rdev->clock.p2pll;
1131 struct radeon_pll *dcpll = &rdev->clock.dcpll;
1132 struct radeon_pll *spll = &rdev->clock.spll;
1133 struct radeon_pll *mpll = &rdev->clock.mpll;
1134 uint16_t data_offset;
1135
1136 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1137 &frev, &crev, &data_offset)) {
1138 firmware_info =
1139 (union firmware_info *)(mode_info->atom_context->bios +
1140 data_offset);
1141 /* pixel clocks */
1142 p1pll->reference_freq =
1143 le16_to_cpu(firmware_info->info.usReferenceClock);
1144 p1pll->reference_div = 0;
1145
1146 if (crev < 2)
1147 p1pll->pll_out_min =
1148 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1149 else
1150 p1pll->pll_out_min =
1151 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1152 p1pll->pll_out_max =
1153 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1154
1155 if (crev >= 4) {
1156 p1pll->lcd_pll_out_min =
1157 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1158 if (p1pll->lcd_pll_out_min == 0)
1159 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1160 p1pll->lcd_pll_out_max =
1161 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1162 if (p1pll->lcd_pll_out_max == 0)
1163 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1164 } else {
1165 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1166 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1167 }
1168
1169 if (p1pll->pll_out_min == 0) {
1170 if (ASIC_IS_AVIVO(rdev))
1171 p1pll->pll_out_min = 64800;
1172 else
1173 p1pll->pll_out_min = 20000;
1174 }
1175
1176 p1pll->pll_in_min =
1177 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1178 p1pll->pll_in_max =
1179 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1180
1181 *p2pll = *p1pll;
1182
1183 /* system clock */
1184 if (ASIC_IS_DCE4(rdev))
1185 spll->reference_freq =
1186 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1187 else
1188 spll->reference_freq =
1189 le16_to_cpu(firmware_info->info.usReferenceClock);
1190 spll->reference_div = 0;
1191
1192 spll->pll_out_min =
1193 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1194 spll->pll_out_max =
1195 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1196
1197 /* ??? */
1198 if (spll->pll_out_min == 0) {
1199 if (ASIC_IS_AVIVO(rdev))
1200 spll->pll_out_min = 64800;
1201 else
1202 spll->pll_out_min = 20000;
1203 }
1204
1205 spll->pll_in_min =
1206 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1207 spll->pll_in_max =
1208 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1209
1210 /* memory clock */
1211 if (ASIC_IS_DCE4(rdev))
1212 mpll->reference_freq =
1213 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1214 else
1215 mpll->reference_freq =
1216 le16_to_cpu(firmware_info->info.usReferenceClock);
1217 mpll->reference_div = 0;
1218
1219 mpll->pll_out_min =
1220 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1221 mpll->pll_out_max =
1222 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1223
1224 /* ??? */
1225 if (mpll->pll_out_min == 0) {
1226 if (ASIC_IS_AVIVO(rdev))
1227 mpll->pll_out_min = 64800;
1228 else
1229 mpll->pll_out_min = 20000;
1230 }
1231
1232 mpll->pll_in_min =
1233 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1234 mpll->pll_in_max =
1235 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1236
1237 rdev->clock.default_sclk =
1238 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1239 rdev->clock.default_mclk =
1240 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1241
1242 if (ASIC_IS_DCE4(rdev)) {
1243 rdev->clock.default_dispclk =
1244 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1245 if (rdev->clock.default_dispclk == 0) {
1246 if (ASIC_IS_DCE5(rdev))
1247 rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1248 else
1249 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1250 }
1251 rdev->clock.dp_extclk =
1252 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1253 }
1254 *dcpll = *p1pll;
1255
1256 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1257 if (rdev->clock.max_pixel_clock == 0)
1258 rdev->clock.max_pixel_clock = 40000;
1259
1260 return true;
1261 }
1262
1263 return false;
1264 }
1265
1266 union igp_info {
1267 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1268 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1269 };
1270
radeon_atombios_sideport_present(struct radeon_device * rdev)1271 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1272 {
1273 struct radeon_mode_info *mode_info = &rdev->mode_info;
1274 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1275 union igp_info *igp_info;
1276 u8 frev, crev;
1277 u16 data_offset;
1278
1279 /* sideport is AMD only */
1280 if (rdev->family == CHIP_RS600)
1281 return false;
1282
1283 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1284 &frev, &crev, &data_offset)) {
1285 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1286 data_offset);
1287 switch (crev) {
1288 case 1:
1289 if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1290 return true;
1291 break;
1292 case 2:
1293 if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1294 return true;
1295 break;
1296 default:
1297 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1298 break;
1299 }
1300 }
1301 return false;
1302 }
1303
radeon_atombios_get_tmds_info(struct radeon_encoder * encoder,struct radeon_encoder_int_tmds * tmds)1304 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1305 struct radeon_encoder_int_tmds *tmds)
1306 {
1307 struct drm_device *dev = encoder->base.dev;
1308 struct radeon_device *rdev = dev->dev_private;
1309 struct radeon_mode_info *mode_info = &rdev->mode_info;
1310 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1311 uint16_t data_offset;
1312 struct _ATOM_TMDS_INFO *tmds_info;
1313 uint8_t frev, crev;
1314 uint16_t maxfreq;
1315 int i;
1316
1317 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1318 &frev, &crev, &data_offset)) {
1319 tmds_info =
1320 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1321 data_offset);
1322
1323 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1324 for (i = 0; i < 4; i++) {
1325 tmds->tmds_pll[i].freq =
1326 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1327 tmds->tmds_pll[i].value =
1328 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1329 tmds->tmds_pll[i].value |=
1330 (tmds_info->asMiscInfo[i].
1331 ucPLL_VCO_Gain & 0x3f) << 6;
1332 tmds->tmds_pll[i].value |=
1333 (tmds_info->asMiscInfo[i].
1334 ucPLL_DutyCycle & 0xf) << 12;
1335 tmds->tmds_pll[i].value |=
1336 (tmds_info->asMiscInfo[i].
1337 ucPLL_VoltageSwing & 0xf) << 16;
1338
1339 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1340 tmds->tmds_pll[i].freq,
1341 tmds->tmds_pll[i].value);
1342
1343 if (maxfreq == tmds->tmds_pll[i].freq) {
1344 tmds->tmds_pll[i].freq = 0xffffffff;
1345 break;
1346 }
1347 }
1348 return true;
1349 }
1350 return false;
1351 }
1352
radeon_atombios_get_ppll_ss_info(struct radeon_device * rdev,struct radeon_atom_ss * ss,int id)1353 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1354 struct radeon_atom_ss *ss,
1355 int id)
1356 {
1357 struct radeon_mode_info *mode_info = &rdev->mode_info;
1358 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1359 uint16_t data_offset, size;
1360 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1361 uint8_t frev, crev;
1362 int i, num_indices;
1363
1364 memset(ss, 0, sizeof(struct radeon_atom_ss));
1365 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1366 &frev, &crev, &data_offset)) {
1367 ss_info =
1368 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1369
1370 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1371 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1372
1373 for (i = 0; i < num_indices; i++) {
1374 if (ss_info->asSS_Info[i].ucSS_Id == id) {
1375 ss->percentage =
1376 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1377 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1378 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1379 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1380 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1381 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1382 return true;
1383 }
1384 }
1385 }
1386 return false;
1387 }
1388
radeon_atombios_get_igp_ss_overrides(struct radeon_device * rdev,struct radeon_atom_ss * ss,int id)1389 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1390 struct radeon_atom_ss *ss,
1391 int id)
1392 {
1393 struct radeon_mode_info *mode_info = &rdev->mode_info;
1394 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1395 u16 data_offset, size;
1396 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *igp_info;
1397 u8 frev, crev;
1398 u16 percentage = 0, rate = 0;
1399
1400 /* get any igp specific overrides */
1401 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1402 &frev, &crev, &data_offset)) {
1403 igp_info = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *)
1404 (mode_info->atom_context->bios + data_offset);
1405 switch (id) {
1406 case ASIC_INTERNAL_SS_ON_TMDS:
1407 percentage = le16_to_cpu(igp_info->usDVISSPercentage);
1408 rate = le16_to_cpu(igp_info->usDVISSpreadRateIn10Hz);
1409 break;
1410 case ASIC_INTERNAL_SS_ON_HDMI:
1411 percentage = le16_to_cpu(igp_info->usHDMISSPercentage);
1412 rate = le16_to_cpu(igp_info->usHDMISSpreadRateIn10Hz);
1413 break;
1414 case ASIC_INTERNAL_SS_ON_LVDS:
1415 percentage = le16_to_cpu(igp_info->usLvdsSSPercentage);
1416 rate = le16_to_cpu(igp_info->usLvdsSSpreadRateIn10Hz);
1417 break;
1418 }
1419 if (percentage)
1420 ss->percentage = percentage;
1421 if (rate)
1422 ss->rate = rate;
1423 }
1424 }
1425
1426 union asic_ss_info {
1427 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1428 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1429 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1430 };
1431
radeon_atombios_get_asic_ss_info(struct radeon_device * rdev,struct radeon_atom_ss * ss,int id,u32 clock)1432 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1433 struct radeon_atom_ss *ss,
1434 int id, u32 clock)
1435 {
1436 struct radeon_mode_info *mode_info = &rdev->mode_info;
1437 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1438 uint16_t data_offset, size;
1439 union asic_ss_info *ss_info;
1440 uint8_t frev, crev;
1441 int i, num_indices;
1442
1443 memset(ss, 0, sizeof(struct radeon_atom_ss));
1444 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1445 &frev, &crev, &data_offset)) {
1446
1447 ss_info =
1448 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1449
1450 switch (frev) {
1451 case 1:
1452 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1453 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1454
1455 for (i = 0; i < num_indices; i++) {
1456 if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) &&
1457 (clock <= le32_to_cpu(ss_info->info.asSpreadSpectrum[i].ulTargetClockRange))) {
1458 ss->percentage =
1459 le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1460 ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1461 ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz);
1462 return true;
1463 }
1464 }
1465 break;
1466 case 2:
1467 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1468 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1469 for (i = 0; i < num_indices; i++) {
1470 if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) &&
1471 (clock <= le32_to_cpu(ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange))) {
1472 ss->percentage =
1473 le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1474 ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1475 ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1476 return true;
1477 }
1478 }
1479 break;
1480 case 3:
1481 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1482 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1483 for (i = 0; i < num_indices; i++) {
1484 if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) &&
1485 (clock <= le32_to_cpu(ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange))) {
1486 ss->percentage =
1487 le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1488 ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1489 ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1490 if (rdev->flags & RADEON_IS_IGP)
1491 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1492 return true;
1493 }
1494 }
1495 break;
1496 default:
1497 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1498 break;
1499 }
1500
1501 }
1502 return false;
1503 }
1504
1505 union lvds_info {
1506 struct _ATOM_LVDS_INFO info;
1507 struct _ATOM_LVDS_INFO_V12 info_12;
1508 };
1509
radeon_atombios_get_lvds_info(struct radeon_encoder * encoder)1510 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1511 radeon_encoder
1512 *encoder)
1513 {
1514 struct drm_device *dev = encoder->base.dev;
1515 struct radeon_device *rdev = dev->dev_private;
1516 struct radeon_mode_info *mode_info = &rdev->mode_info;
1517 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1518 uint16_t data_offset, misc;
1519 union lvds_info *lvds_info;
1520 uint8_t frev, crev;
1521 struct radeon_encoder_atom_dig *lvds = NULL;
1522 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1523
1524 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1525 &frev, &crev, &data_offset)) {
1526 lvds_info =
1527 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1528 lvds =
1529 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1530
1531 if (!lvds)
1532 return NULL;
1533
1534 lvds->native_mode.clock =
1535 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1536 lvds->native_mode.hdisplay =
1537 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1538 lvds->native_mode.vdisplay =
1539 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1540 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1541 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1542 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1543 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1544 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1545 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1546 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1547 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1548 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1549 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1550 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1551 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1552 lvds->panel_pwr_delay =
1553 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1554 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1555
1556 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1557 if (misc & ATOM_VSYNC_POLARITY)
1558 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1559 if (misc & ATOM_HSYNC_POLARITY)
1560 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1561 if (misc & ATOM_COMPOSITESYNC)
1562 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1563 if (misc & ATOM_INTERLACE)
1564 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1565 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1566 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1567
1568 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1569 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1570
1571 /* set crtc values */
1572 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1573
1574 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1575
1576 encoder->native_mode = lvds->native_mode;
1577
1578 if (encoder_enum == 2)
1579 lvds->linkb = true;
1580 else
1581 lvds->linkb = false;
1582
1583 /* parse the lcd record table */
1584 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
1585 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1586 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1587 bool bad_record = false;
1588 u8 *record;
1589
1590 if ((frev == 1) && (crev < 2))
1591 /* absolute */
1592 record = (u8 *)(mode_info->atom_context->bios +
1593 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1594 else
1595 /* relative */
1596 record = (u8 *)(mode_info->atom_context->bios +
1597 data_offset +
1598 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1599 while (*record != ATOM_RECORD_END_TYPE) {
1600 switch (*record) {
1601 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1602 record += sizeof(ATOM_PATCH_RECORD_MODE);
1603 break;
1604 case LCD_RTS_RECORD_TYPE:
1605 record += sizeof(ATOM_LCD_RTS_RECORD);
1606 break;
1607 case LCD_CAP_RECORD_TYPE:
1608 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1609 break;
1610 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1611 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1612 if (fake_edid_record->ucFakeEDIDLength) {
1613 struct edid *edid;
1614 int edid_size =
1615 max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1616 edid = kmalloc(edid_size, GFP_KERNEL);
1617 if (edid) {
1618 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1619 fake_edid_record->ucFakeEDIDLength);
1620
1621 if (drm_edid_is_valid(edid)) {
1622 rdev->mode_info.bios_hardcoded_edid = edid;
1623 rdev->mode_info.bios_hardcoded_edid_size = edid_size;
1624 } else
1625 kfree(edid);
1626 }
1627 }
1628 record += fake_edid_record->ucFakeEDIDLength ?
1629 fake_edid_record->ucFakeEDIDLength + 2 :
1630 sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1631 break;
1632 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1633 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1634 lvds->native_mode.width_mm = panel_res_record->usHSize;
1635 lvds->native_mode.height_mm = panel_res_record->usVSize;
1636 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1637 break;
1638 default:
1639 DRM_ERROR("Bad LCD record %d\n", *record);
1640 bad_record = true;
1641 break;
1642 }
1643 if (bad_record)
1644 break;
1645 }
1646 }
1647 }
1648 return lvds;
1649 }
1650
1651 struct radeon_encoder_primary_dac *
radeon_atombios_get_primary_dac_info(struct radeon_encoder * encoder)1652 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1653 {
1654 struct drm_device *dev = encoder->base.dev;
1655 struct radeon_device *rdev = dev->dev_private;
1656 struct radeon_mode_info *mode_info = &rdev->mode_info;
1657 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1658 uint16_t data_offset;
1659 struct _COMPASSIONATE_DATA *dac_info;
1660 uint8_t frev, crev;
1661 uint8_t bg, dac;
1662 struct radeon_encoder_primary_dac *p_dac = NULL;
1663
1664 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1665 &frev, &crev, &data_offset)) {
1666 dac_info = (struct _COMPASSIONATE_DATA *)
1667 (mode_info->atom_context->bios + data_offset);
1668
1669 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1670
1671 if (!p_dac)
1672 return NULL;
1673
1674 bg = dac_info->ucDAC1_BG_Adjustment;
1675 dac = dac_info->ucDAC1_DAC_Adjustment;
1676 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1677
1678 }
1679 return p_dac;
1680 }
1681
radeon_atom_get_tv_timings(struct radeon_device * rdev,int index,struct drm_display_mode * mode)1682 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1683 struct drm_display_mode *mode)
1684 {
1685 struct radeon_mode_info *mode_info = &rdev->mode_info;
1686 ATOM_ANALOG_TV_INFO *tv_info;
1687 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1688 ATOM_DTD_FORMAT *dtd_timings;
1689 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1690 u8 frev, crev;
1691 u16 data_offset, misc;
1692
1693 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1694 &frev, &crev, &data_offset))
1695 return false;
1696
1697 switch (crev) {
1698 case 1:
1699 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1700 if (index >= MAX_SUPPORTED_TV_TIMING)
1701 return false;
1702
1703 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1704 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1705 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1706 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1707 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1708
1709 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1710 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1711 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1712 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1713 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1714
1715 mode->flags = 0;
1716 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1717 if (misc & ATOM_VSYNC_POLARITY)
1718 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1719 if (misc & ATOM_HSYNC_POLARITY)
1720 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1721 if (misc & ATOM_COMPOSITESYNC)
1722 mode->flags |= DRM_MODE_FLAG_CSYNC;
1723 if (misc & ATOM_INTERLACE)
1724 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1725 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1726 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1727
1728 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1729
1730 if (index == 1) {
1731 /* PAL timings appear to have wrong values for totals */
1732 mode->crtc_htotal -= 1;
1733 mode->crtc_vtotal -= 1;
1734 }
1735 break;
1736 case 2:
1737 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1738 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1739 return false;
1740
1741 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1742 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1743 le16_to_cpu(dtd_timings->usHBlanking_Time);
1744 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1745 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1746 le16_to_cpu(dtd_timings->usHSyncOffset);
1747 mode->crtc_hsync_end = mode->crtc_hsync_start +
1748 le16_to_cpu(dtd_timings->usHSyncWidth);
1749
1750 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1751 le16_to_cpu(dtd_timings->usVBlanking_Time);
1752 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1753 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1754 le16_to_cpu(dtd_timings->usVSyncOffset);
1755 mode->crtc_vsync_end = mode->crtc_vsync_start +
1756 le16_to_cpu(dtd_timings->usVSyncWidth);
1757
1758 mode->flags = 0;
1759 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1760 if (misc & ATOM_VSYNC_POLARITY)
1761 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1762 if (misc & ATOM_HSYNC_POLARITY)
1763 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1764 if (misc & ATOM_COMPOSITESYNC)
1765 mode->flags |= DRM_MODE_FLAG_CSYNC;
1766 if (misc & ATOM_INTERLACE)
1767 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1768 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1769 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1770
1771 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1772 break;
1773 }
1774 return true;
1775 }
1776
1777 enum radeon_tv_std
radeon_atombios_get_tv_info(struct radeon_device * rdev)1778 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1779 {
1780 struct radeon_mode_info *mode_info = &rdev->mode_info;
1781 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1782 uint16_t data_offset;
1783 uint8_t frev, crev;
1784 struct _ATOM_ANALOG_TV_INFO *tv_info;
1785 enum radeon_tv_std tv_std = TV_STD_NTSC;
1786
1787 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1788 &frev, &crev, &data_offset)) {
1789
1790 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1791 (mode_info->atom_context->bios + data_offset);
1792
1793 switch (tv_info->ucTV_BootUpDefaultStandard) {
1794 case ATOM_TV_NTSC:
1795 tv_std = TV_STD_NTSC;
1796 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1797 break;
1798 case ATOM_TV_NTSCJ:
1799 tv_std = TV_STD_NTSC_J;
1800 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1801 break;
1802 case ATOM_TV_PAL:
1803 tv_std = TV_STD_PAL;
1804 DRM_DEBUG_KMS("Default TV standard: PAL\n");
1805 break;
1806 case ATOM_TV_PALM:
1807 tv_std = TV_STD_PAL_M;
1808 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1809 break;
1810 case ATOM_TV_PALN:
1811 tv_std = TV_STD_PAL_N;
1812 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1813 break;
1814 case ATOM_TV_PALCN:
1815 tv_std = TV_STD_PAL_CN;
1816 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1817 break;
1818 case ATOM_TV_PAL60:
1819 tv_std = TV_STD_PAL_60;
1820 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1821 break;
1822 case ATOM_TV_SECAM:
1823 tv_std = TV_STD_SECAM;
1824 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1825 break;
1826 default:
1827 tv_std = TV_STD_NTSC;
1828 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1829 break;
1830 }
1831 }
1832 return tv_std;
1833 }
1834
1835 struct radeon_encoder_tv_dac *
radeon_atombios_get_tv_dac_info(struct radeon_encoder * encoder)1836 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1837 {
1838 struct drm_device *dev = encoder->base.dev;
1839 struct radeon_device *rdev = dev->dev_private;
1840 struct radeon_mode_info *mode_info = &rdev->mode_info;
1841 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1842 uint16_t data_offset;
1843 struct _COMPASSIONATE_DATA *dac_info;
1844 uint8_t frev, crev;
1845 uint8_t bg, dac;
1846 struct radeon_encoder_tv_dac *tv_dac = NULL;
1847
1848 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1849 &frev, &crev, &data_offset)) {
1850
1851 dac_info = (struct _COMPASSIONATE_DATA *)
1852 (mode_info->atom_context->bios + data_offset);
1853
1854 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1855
1856 if (!tv_dac)
1857 return NULL;
1858
1859 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1860 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1861 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1862
1863 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1864 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1865 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1866
1867 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1868 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1869 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1870
1871 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1872 }
1873 return tv_dac;
1874 }
1875
1876 static const char *thermal_controller_names[] = {
1877 "NONE",
1878 "lm63",
1879 "adm1032",
1880 "adm1030",
1881 "max6649",
1882 "lm64",
1883 "f75375",
1884 "asc7xxx",
1885 };
1886
1887 static const char *pp_lib_thermal_controller_names[] = {
1888 "NONE",
1889 "lm63",
1890 "adm1032",
1891 "adm1030",
1892 "max6649",
1893 "lm64",
1894 "f75375",
1895 "RV6xx",
1896 "RV770",
1897 "adt7473",
1898 "NONE",
1899 "External GPIO",
1900 "Evergreen",
1901 "emc2103",
1902 "Sumo",
1903 "Northern Islands",
1904 "Southern Islands",
1905 "lm96163",
1906 };
1907
1908 union power_info {
1909 struct _ATOM_POWERPLAY_INFO info;
1910 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1911 struct _ATOM_POWERPLAY_INFO_V3 info_3;
1912 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1913 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1914 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1915 };
1916
1917 union pplib_clock_info {
1918 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1919 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1920 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
1921 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
1922 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
1923 };
1924
1925 union pplib_power_state {
1926 struct _ATOM_PPLIB_STATE v1;
1927 struct _ATOM_PPLIB_STATE_V2 v2;
1928 };
1929
radeon_atombios_parse_misc_flags_1_3(struct radeon_device * rdev,int state_index,u32 misc,u32 misc2)1930 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
1931 int state_index,
1932 u32 misc, u32 misc2)
1933 {
1934 rdev->pm.power_state[state_index].misc = misc;
1935 rdev->pm.power_state[state_index].misc2 = misc2;
1936 /* order matters! */
1937 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1938 rdev->pm.power_state[state_index].type =
1939 POWER_STATE_TYPE_POWERSAVE;
1940 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1941 rdev->pm.power_state[state_index].type =
1942 POWER_STATE_TYPE_BATTERY;
1943 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1944 rdev->pm.power_state[state_index].type =
1945 POWER_STATE_TYPE_BATTERY;
1946 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1947 rdev->pm.power_state[state_index].type =
1948 POWER_STATE_TYPE_BALANCED;
1949 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1950 rdev->pm.power_state[state_index].type =
1951 POWER_STATE_TYPE_PERFORMANCE;
1952 rdev->pm.power_state[state_index].flags &=
1953 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1954 }
1955 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1956 rdev->pm.power_state[state_index].type =
1957 POWER_STATE_TYPE_BALANCED;
1958 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1959 rdev->pm.power_state[state_index].type =
1960 POWER_STATE_TYPE_DEFAULT;
1961 rdev->pm.default_power_state_index = state_index;
1962 rdev->pm.power_state[state_index].default_clock_mode =
1963 &rdev->pm.power_state[state_index].clock_info[0];
1964 } else if (state_index == 0) {
1965 rdev->pm.power_state[state_index].clock_info[0].flags |=
1966 RADEON_PM_MODE_NO_DISPLAY;
1967 }
1968 }
1969
radeon_atombios_parse_power_table_1_3(struct radeon_device * rdev)1970 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
1971 {
1972 struct radeon_mode_info *mode_info = &rdev->mode_info;
1973 u32 misc, misc2 = 0;
1974 int num_modes = 0, i;
1975 int state_index = 0;
1976 struct radeon_i2c_bus_rec i2c_bus;
1977 union power_info *power_info;
1978 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1979 u16 data_offset;
1980 u8 frev, crev;
1981
1982 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
1983 &frev, &crev, &data_offset))
1984 return state_index;
1985 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1986
1987 /* add the i2c bus for thermal/fan chip */
1988 if (power_info->info.ucOverdriveThermalController > 0) {
1989 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1990 thermal_controller_names[power_info->info.ucOverdriveThermalController],
1991 power_info->info.ucOverdriveControllerAddress >> 1);
1992 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1993 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1994 if (rdev->pm.i2c_bus) {
1995 struct i2c_board_info info = { };
1996 const char *name = thermal_controller_names[power_info->info.
1997 ucOverdriveThermalController];
1998 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
1999 strlcpy(info.type, name, sizeof(info.type));
2000 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2001 }
2002 }
2003 num_modes = power_info->info.ucNumOfPowerModeEntries;
2004 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
2005 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
2006 if (num_modes == 0)
2007 return state_index;
2008 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL);
2009 if (!rdev->pm.power_state)
2010 return state_index;
2011 /* last mode is usually default, array is low to high */
2012 for (i = 0; i < num_modes; i++) {
2013 rdev->pm.power_state[state_index].clock_info =
2014 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2015 if (!rdev->pm.power_state[state_index].clock_info)
2016 return state_index;
2017 rdev->pm.power_state[state_index].num_clock_modes = 1;
2018 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2019 switch (frev) {
2020 case 1:
2021 rdev->pm.power_state[state_index].clock_info[0].mclk =
2022 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2023 rdev->pm.power_state[state_index].clock_info[0].sclk =
2024 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
2025 /* skip invalid modes */
2026 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2027 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2028 continue;
2029 rdev->pm.power_state[state_index].pcie_lanes =
2030 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2031 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2032 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2033 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2034 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2035 VOLTAGE_GPIO;
2036 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2037 radeon_lookup_gpio(rdev,
2038 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2039 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2040 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2041 true;
2042 else
2043 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2044 false;
2045 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2046 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2047 VOLTAGE_VDDC;
2048 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2049 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2050 }
2051 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2052 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2053 state_index++;
2054 break;
2055 case 2:
2056 rdev->pm.power_state[state_index].clock_info[0].mclk =
2057 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2058 rdev->pm.power_state[state_index].clock_info[0].sclk =
2059 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2060 /* skip invalid modes */
2061 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2062 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2063 continue;
2064 rdev->pm.power_state[state_index].pcie_lanes =
2065 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2066 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2067 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2068 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2069 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2070 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2071 VOLTAGE_GPIO;
2072 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2073 radeon_lookup_gpio(rdev,
2074 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2075 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2076 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2077 true;
2078 else
2079 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2080 false;
2081 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2082 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2083 VOLTAGE_VDDC;
2084 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2085 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2086 }
2087 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2088 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2089 state_index++;
2090 break;
2091 case 3:
2092 rdev->pm.power_state[state_index].clock_info[0].mclk =
2093 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2094 rdev->pm.power_state[state_index].clock_info[0].sclk =
2095 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2096 /* skip invalid modes */
2097 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2098 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2099 continue;
2100 rdev->pm.power_state[state_index].pcie_lanes =
2101 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2102 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2103 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2104 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2105 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2106 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2107 VOLTAGE_GPIO;
2108 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2109 radeon_lookup_gpio(rdev,
2110 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2111 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2112 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2113 true;
2114 else
2115 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2116 false;
2117 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2118 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2119 VOLTAGE_VDDC;
2120 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2121 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2122 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2123 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2124 true;
2125 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2126 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2127 }
2128 }
2129 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2130 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2131 state_index++;
2132 break;
2133 }
2134 }
2135 /* last mode is usually default */
2136 if (rdev->pm.default_power_state_index == -1) {
2137 rdev->pm.power_state[state_index - 1].type =
2138 POWER_STATE_TYPE_DEFAULT;
2139 rdev->pm.default_power_state_index = state_index - 1;
2140 rdev->pm.power_state[state_index - 1].default_clock_mode =
2141 &rdev->pm.power_state[state_index - 1].clock_info[0];
2142 rdev->pm.power_state[state_index].flags &=
2143 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2144 rdev->pm.power_state[state_index].misc = 0;
2145 rdev->pm.power_state[state_index].misc2 = 0;
2146 }
2147 return state_index;
2148 }
2149
radeon_atombios_add_pplib_thermal_controller(struct radeon_device * rdev,ATOM_PPLIB_THERMALCONTROLLER * controller)2150 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2151 ATOM_PPLIB_THERMALCONTROLLER *controller)
2152 {
2153 struct radeon_i2c_bus_rec i2c_bus;
2154
2155 /* add the i2c bus for thermal/fan chip */
2156 if (controller->ucType > 0) {
2157 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2158 DRM_INFO("Internal thermal controller %s fan control\n",
2159 (controller->ucFanParameters &
2160 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2161 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2162 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2163 DRM_INFO("Internal thermal controller %s fan control\n",
2164 (controller->ucFanParameters &
2165 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2166 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2167 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2168 DRM_INFO("Internal thermal controller %s fan control\n",
2169 (controller->ucFanParameters &
2170 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2171 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2172 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2173 DRM_INFO("Internal thermal controller %s fan control\n",
2174 (controller->ucFanParameters &
2175 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2176 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2177 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2178 DRM_INFO("Internal thermal controller %s fan control\n",
2179 (controller->ucFanParameters &
2180 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2181 rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2182 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) {
2183 DRM_INFO("Internal thermal controller %s fan control\n",
2184 (controller->ucFanParameters &
2185 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2186 rdev->pm.int_thermal_type = THERMAL_TYPE_SI;
2187 } else if ((controller->ucType ==
2188 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
2189 (controller->ucType ==
2190 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) ||
2191 (controller->ucType ==
2192 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) {
2193 DRM_INFO("Special thermal controller config\n");
2194 } else {
2195 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2196 pp_lib_thermal_controller_names[controller->ucType],
2197 controller->ucI2cAddress >> 1,
2198 (controller->ucFanParameters &
2199 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2200 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2201 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2202 if (rdev->pm.i2c_bus) {
2203 struct i2c_board_info info = { };
2204 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2205 info.addr = controller->ucI2cAddress >> 1;
2206 strlcpy(info.type, name, sizeof(info.type));
2207 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2208 }
2209 }
2210 }
2211 }
2212
radeon_atombios_get_default_voltages(struct radeon_device * rdev,u16 * vddc,u16 * vddci)2213 static void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2214 u16 *vddc, u16 *vddci)
2215 {
2216 struct radeon_mode_info *mode_info = &rdev->mode_info;
2217 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2218 u8 frev, crev;
2219 u16 data_offset;
2220 union firmware_info *firmware_info;
2221
2222 *vddc = 0;
2223 *vddci = 0;
2224
2225 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2226 &frev, &crev, &data_offset)) {
2227 firmware_info =
2228 (union firmware_info *)(mode_info->atom_context->bios +
2229 data_offset);
2230 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2231 if ((frev == 2) && (crev >= 2))
2232 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
2233 }
2234 }
2235
radeon_atombios_parse_pplib_non_clock_info(struct radeon_device * rdev,int state_index,int mode_index,struct _ATOM_PPLIB_NONCLOCK_INFO * non_clock_info)2236 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2237 int state_index, int mode_index,
2238 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2239 {
2240 int j;
2241 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2242 u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2243 u16 vddc, vddci;
2244
2245 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci);
2246
2247 rdev->pm.power_state[state_index].misc = misc;
2248 rdev->pm.power_state[state_index].misc2 = misc2;
2249 rdev->pm.power_state[state_index].pcie_lanes =
2250 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2251 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2252 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2253 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2254 rdev->pm.power_state[state_index].type =
2255 POWER_STATE_TYPE_BATTERY;
2256 break;
2257 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2258 rdev->pm.power_state[state_index].type =
2259 POWER_STATE_TYPE_BALANCED;
2260 break;
2261 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2262 rdev->pm.power_state[state_index].type =
2263 POWER_STATE_TYPE_PERFORMANCE;
2264 break;
2265 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2266 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2267 rdev->pm.power_state[state_index].type =
2268 POWER_STATE_TYPE_PERFORMANCE;
2269 break;
2270 }
2271 rdev->pm.power_state[state_index].flags = 0;
2272 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2273 rdev->pm.power_state[state_index].flags |=
2274 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2275 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2276 rdev->pm.power_state[state_index].type =
2277 POWER_STATE_TYPE_DEFAULT;
2278 rdev->pm.default_power_state_index = state_index;
2279 rdev->pm.power_state[state_index].default_clock_mode =
2280 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2281 if (ASIC_IS_DCE5(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2282 /* NI chips post without MC ucode, so default clocks are strobe mode only */
2283 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2284 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2285 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2286 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2287 } else {
2288 /* patch the table values with the default slck/mclk from firmware info */
2289 for (j = 0; j < mode_index; j++) {
2290 rdev->pm.power_state[state_index].clock_info[j].mclk =
2291 rdev->clock.default_mclk;
2292 rdev->pm.power_state[state_index].clock_info[j].sclk =
2293 rdev->clock.default_sclk;
2294 if (vddc)
2295 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2296 vddc;
2297 }
2298 }
2299 }
2300 }
2301
radeon_atombios_parse_pplib_clock_info(struct radeon_device * rdev,int state_index,int mode_index,union pplib_clock_info * clock_info)2302 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2303 int state_index, int mode_index,
2304 union pplib_clock_info *clock_info)
2305 {
2306 u32 sclk, mclk;
2307 u16 vddc;
2308
2309 if (rdev->flags & RADEON_IS_IGP) {
2310 if (rdev->family >= CHIP_PALM) {
2311 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2312 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2313 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2314 } else {
2315 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2316 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2317 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2318 }
2319 } else if (ASIC_IS_DCE6(rdev)) {
2320 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
2321 sclk |= clock_info->si.ucEngineClockHigh << 16;
2322 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
2323 mclk |= clock_info->si.ucMemoryClockHigh << 16;
2324 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2325 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2326 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2327 VOLTAGE_SW;
2328 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2329 le16_to_cpu(clock_info->si.usVDDC);
2330 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2331 le16_to_cpu(clock_info->si.usVDDCI);
2332 } else if (ASIC_IS_DCE4(rdev)) {
2333 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2334 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2335 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2336 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2337 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2338 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2339 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2340 VOLTAGE_SW;
2341 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2342 le16_to_cpu(clock_info->evergreen.usVDDC);
2343 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2344 le16_to_cpu(clock_info->evergreen.usVDDCI);
2345 } else {
2346 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2347 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2348 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2349 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2350 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2351 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2352 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2353 VOLTAGE_SW;
2354 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2355 le16_to_cpu(clock_info->r600.usVDDC);
2356 }
2357
2358 /* patch up vddc if necessary */
2359 switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) {
2360 case ATOM_VIRTUAL_VOLTAGE_ID0:
2361 case ATOM_VIRTUAL_VOLTAGE_ID1:
2362 case ATOM_VIRTUAL_VOLTAGE_ID2:
2363 case ATOM_VIRTUAL_VOLTAGE_ID3:
2364 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC,
2365 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage,
2366 &vddc) == 0)
2367 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2368 break;
2369 default:
2370 break;
2371 }
2372
2373 if (rdev->flags & RADEON_IS_IGP) {
2374 /* skip invalid modes */
2375 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2376 return false;
2377 } else {
2378 /* skip invalid modes */
2379 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2380 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2381 return false;
2382 }
2383 return true;
2384 }
2385
radeon_atombios_parse_power_table_4_5(struct radeon_device * rdev)2386 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2387 {
2388 struct radeon_mode_info *mode_info = &rdev->mode_info;
2389 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2390 union pplib_power_state *power_state;
2391 int i, j;
2392 int state_index = 0, mode_index = 0;
2393 union pplib_clock_info *clock_info;
2394 bool valid;
2395 union power_info *power_info;
2396 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2397 u16 data_offset;
2398 u8 frev, crev;
2399
2400 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2401 &frev, &crev, &data_offset))
2402 return state_index;
2403 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2404
2405 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2406 if (power_info->pplib.ucNumStates == 0)
2407 return state_index;
2408 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2409 power_info->pplib.ucNumStates, GFP_KERNEL);
2410 if (!rdev->pm.power_state)
2411 return state_index;
2412 /* first mode is usually default, followed by low to high */
2413 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2414 mode_index = 0;
2415 power_state = (union pplib_power_state *)
2416 (mode_info->atom_context->bios + data_offset +
2417 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2418 i * power_info->pplib.ucStateEntrySize);
2419 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2420 (mode_info->atom_context->bios + data_offset +
2421 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2422 (power_state->v1.ucNonClockStateIndex *
2423 power_info->pplib.ucNonClockSize));
2424 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2425 ((power_info->pplib.ucStateEntrySize - 1) ?
2426 (power_info->pplib.ucStateEntrySize - 1) : 1),
2427 GFP_KERNEL);
2428 if (!rdev->pm.power_state[i].clock_info)
2429 return state_index;
2430 if (power_info->pplib.ucStateEntrySize - 1) {
2431 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2432 clock_info = (union pplib_clock_info *)
2433 (mode_info->atom_context->bios + data_offset +
2434 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2435 (power_state->v1.ucClockStateIndices[j] *
2436 power_info->pplib.ucClockInfoSize));
2437 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2438 state_index, mode_index,
2439 clock_info);
2440 if (valid)
2441 mode_index++;
2442 }
2443 } else {
2444 rdev->pm.power_state[state_index].clock_info[0].mclk =
2445 rdev->clock.default_mclk;
2446 rdev->pm.power_state[state_index].clock_info[0].sclk =
2447 rdev->clock.default_sclk;
2448 mode_index++;
2449 }
2450 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2451 if (mode_index) {
2452 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2453 non_clock_info);
2454 state_index++;
2455 }
2456 }
2457 /* if multiple clock modes, mark the lowest as no display */
2458 for (i = 0; i < state_index; i++) {
2459 if (rdev->pm.power_state[i].num_clock_modes > 1)
2460 rdev->pm.power_state[i].clock_info[0].flags |=
2461 RADEON_PM_MODE_NO_DISPLAY;
2462 }
2463 /* first mode is usually default */
2464 if (rdev->pm.default_power_state_index == -1) {
2465 rdev->pm.power_state[0].type =
2466 POWER_STATE_TYPE_DEFAULT;
2467 rdev->pm.default_power_state_index = 0;
2468 rdev->pm.power_state[0].default_clock_mode =
2469 &rdev->pm.power_state[0].clock_info[0];
2470 }
2471 return state_index;
2472 }
2473
radeon_atombios_parse_power_table_6(struct radeon_device * rdev)2474 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2475 {
2476 struct radeon_mode_info *mode_info = &rdev->mode_info;
2477 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2478 union pplib_power_state *power_state;
2479 int i, j, non_clock_array_index, clock_array_index;
2480 int state_index = 0, mode_index = 0;
2481 union pplib_clock_info *clock_info;
2482 struct _StateArray *state_array;
2483 struct _ClockInfoArray *clock_info_array;
2484 struct _NonClockInfoArray *non_clock_info_array;
2485 bool valid;
2486 union power_info *power_info;
2487 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2488 u16 data_offset;
2489 u8 frev, crev;
2490 u8 *power_state_offset;
2491
2492 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2493 &frev, &crev, &data_offset))
2494 return state_index;
2495 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2496
2497 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2498 state_array = (struct _StateArray *)
2499 (mode_info->atom_context->bios + data_offset +
2500 le16_to_cpu(power_info->pplib.usStateArrayOffset));
2501 clock_info_array = (struct _ClockInfoArray *)
2502 (mode_info->atom_context->bios + data_offset +
2503 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2504 non_clock_info_array = (struct _NonClockInfoArray *)
2505 (mode_info->atom_context->bios + data_offset +
2506 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2507 if (state_array->ucNumEntries == 0)
2508 return state_index;
2509 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2510 state_array->ucNumEntries, GFP_KERNEL);
2511 if (!rdev->pm.power_state)
2512 return state_index;
2513 power_state_offset = (u8 *)state_array->states;
2514 for (i = 0; i < state_array->ucNumEntries; i++) {
2515 mode_index = 0;
2516 power_state = (union pplib_power_state *)power_state_offset;
2517 non_clock_array_index = power_state->v2.nonClockInfoIndex;
2518 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2519 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2520 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2521 (power_state->v2.ucNumDPMLevels ?
2522 power_state->v2.ucNumDPMLevels : 1),
2523 GFP_KERNEL);
2524 if (!rdev->pm.power_state[i].clock_info)
2525 return state_index;
2526 if (power_state->v2.ucNumDPMLevels) {
2527 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2528 clock_array_index = power_state->v2.clockInfoIndex[j];
2529 clock_info = (union pplib_clock_info *)
2530 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
2531 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2532 state_index, mode_index,
2533 clock_info);
2534 if (valid)
2535 mode_index++;
2536 }
2537 } else {
2538 rdev->pm.power_state[state_index].clock_info[0].mclk =
2539 rdev->clock.default_mclk;
2540 rdev->pm.power_state[state_index].clock_info[0].sclk =
2541 rdev->clock.default_sclk;
2542 mode_index++;
2543 }
2544 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2545 if (mode_index) {
2546 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2547 non_clock_info);
2548 state_index++;
2549 }
2550 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
2551 }
2552 /* if multiple clock modes, mark the lowest as no display */
2553 for (i = 0; i < state_index; i++) {
2554 if (rdev->pm.power_state[i].num_clock_modes > 1)
2555 rdev->pm.power_state[i].clock_info[0].flags |=
2556 RADEON_PM_MODE_NO_DISPLAY;
2557 }
2558 /* first mode is usually default */
2559 if (rdev->pm.default_power_state_index == -1) {
2560 rdev->pm.power_state[0].type =
2561 POWER_STATE_TYPE_DEFAULT;
2562 rdev->pm.default_power_state_index = 0;
2563 rdev->pm.power_state[0].default_clock_mode =
2564 &rdev->pm.power_state[0].clock_info[0];
2565 }
2566 return state_index;
2567 }
2568
radeon_atombios_get_power_modes(struct radeon_device * rdev)2569 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2570 {
2571 struct radeon_mode_info *mode_info = &rdev->mode_info;
2572 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2573 u16 data_offset;
2574 u8 frev, crev;
2575 int state_index = 0;
2576
2577 rdev->pm.default_power_state_index = -1;
2578
2579 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2580 &frev, &crev, &data_offset)) {
2581 switch (frev) {
2582 case 1:
2583 case 2:
2584 case 3:
2585 state_index = radeon_atombios_parse_power_table_1_3(rdev);
2586 break;
2587 case 4:
2588 case 5:
2589 state_index = radeon_atombios_parse_power_table_4_5(rdev);
2590 break;
2591 case 6:
2592 state_index = radeon_atombios_parse_power_table_6(rdev);
2593 break;
2594 default:
2595 break;
2596 }
2597 }
2598
2599 if (state_index == 0) {
2600 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2601 if (rdev->pm.power_state) {
2602 rdev->pm.power_state[0].clock_info =
2603 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2604 if (rdev->pm.power_state[0].clock_info) {
2605 /* add the default mode */
2606 rdev->pm.power_state[state_index].type =
2607 POWER_STATE_TYPE_DEFAULT;
2608 rdev->pm.power_state[state_index].num_clock_modes = 1;
2609 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2610 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2611 rdev->pm.power_state[state_index].default_clock_mode =
2612 &rdev->pm.power_state[state_index].clock_info[0];
2613 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2614 rdev->pm.power_state[state_index].pcie_lanes = 16;
2615 rdev->pm.default_power_state_index = state_index;
2616 rdev->pm.power_state[state_index].flags = 0;
2617 state_index++;
2618 }
2619 }
2620 }
2621
2622 rdev->pm.num_power_states = state_index;
2623
2624 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2625 rdev->pm.current_clock_mode_index = 0;
2626 if (rdev->pm.default_power_state_index >= 0)
2627 rdev->pm.current_vddc =
2628 rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2629 else
2630 rdev->pm.current_vddc = 0;
2631 }
2632
radeon_atom_set_clock_gating(struct radeon_device * rdev,int enable)2633 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2634 {
2635 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2636 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
2637
2638 args.ucEnable = enable;
2639
2640 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2641 }
2642
radeon_atom_get_engine_clock(struct radeon_device * rdev)2643 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2644 {
2645 GET_ENGINE_CLOCK_PS_ALLOCATION args;
2646 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2647
2648 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2649 return le32_to_cpu(args.ulReturnEngineClock);
2650 }
2651
radeon_atom_get_memory_clock(struct radeon_device * rdev)2652 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2653 {
2654 GET_MEMORY_CLOCK_PS_ALLOCATION args;
2655 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2656
2657 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2658 return le32_to_cpu(args.ulReturnMemoryClock);
2659 }
2660
radeon_atom_set_engine_clock(struct radeon_device * rdev,uint32_t eng_clock)2661 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2662 uint32_t eng_clock)
2663 {
2664 SET_ENGINE_CLOCK_PS_ALLOCATION args;
2665 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2666
2667 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */
2668
2669 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2670 }
2671
radeon_atom_set_memory_clock(struct radeon_device * rdev,uint32_t mem_clock)2672 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2673 uint32_t mem_clock)
2674 {
2675 SET_MEMORY_CLOCK_PS_ALLOCATION args;
2676 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2677
2678 if (rdev->flags & RADEON_IS_IGP)
2679 return;
2680
2681 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */
2682
2683 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2684 }
2685
2686 union set_voltage {
2687 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2688 struct _SET_VOLTAGE_PARAMETERS v1;
2689 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2690 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
2691 };
2692
radeon_atom_set_voltage(struct radeon_device * rdev,u16 voltage_level,u8 voltage_type)2693 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
2694 {
2695 union set_voltage args;
2696 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2697 u8 frev, crev, volt_index = voltage_level;
2698
2699 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2700 return;
2701
2702 /* 0xff01 is a flag rather then an actual voltage */
2703 if (voltage_level == 0xff01)
2704 return;
2705
2706 switch (crev) {
2707 case 1:
2708 args.v1.ucVoltageType = voltage_type;
2709 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2710 args.v1.ucVoltageIndex = volt_index;
2711 break;
2712 case 2:
2713 args.v2.ucVoltageType = voltage_type;
2714 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
2715 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
2716 break;
2717 case 3:
2718 args.v3.ucVoltageType = voltage_type;
2719 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
2720 args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
2721 break;
2722 default:
2723 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2724 return;
2725 }
2726
2727 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2728 }
2729
radeon_atom_get_max_vddc(struct radeon_device * rdev,u8 voltage_type,u16 voltage_id,u16 * voltage)2730 static int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
2731 u16 voltage_id, u16 *voltage)
2732 {
2733 union set_voltage args;
2734 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2735 u8 frev, crev;
2736
2737 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2738 return -EINVAL;
2739
2740 switch (crev) {
2741 case 1:
2742 return -EINVAL;
2743 case 2:
2744 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
2745 args.v2.ucVoltageMode = 0;
2746 args.v2.usVoltageLevel = 0;
2747
2748 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2749
2750 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
2751 break;
2752 case 3:
2753 args.v3.ucVoltageType = voltage_type;
2754 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
2755 args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
2756
2757 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2758
2759 *voltage = le16_to_cpu(args.v3.usVoltageLevel);
2760 break;
2761 default:
2762 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2763 return -EINVAL;
2764 }
2765
2766 return 0;
2767 }
2768
radeon_atom_initialize_bios_scratch_regs(struct drm_device * dev)2769 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2770 {
2771 struct radeon_device *rdev = dev->dev_private;
2772 uint32_t bios_2_scratch, bios_6_scratch;
2773
2774 if (rdev->family >= CHIP_R600) {
2775 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2776 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2777 } else {
2778 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2779 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2780 }
2781
2782 /* let the bios control the backlight */
2783 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2784
2785 /* tell the bios not to handle mode switching */
2786 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
2787
2788 /* clear the vbios dpms state */
2789 if (ASIC_IS_DCE4(rdev))
2790 bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
2791
2792 if (rdev->family >= CHIP_R600) {
2793 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2794 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2795 } else {
2796 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2797 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2798 }
2799
2800 }
2801
radeon_save_bios_scratch_regs(struct radeon_device * rdev)2802 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2803 {
2804 uint32_t scratch_reg;
2805 int i;
2806
2807 if (rdev->family >= CHIP_R600)
2808 scratch_reg = R600_BIOS_0_SCRATCH;
2809 else
2810 scratch_reg = RADEON_BIOS_0_SCRATCH;
2811
2812 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2813 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2814 }
2815
radeon_restore_bios_scratch_regs(struct radeon_device * rdev)2816 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2817 {
2818 uint32_t scratch_reg;
2819 int i;
2820
2821 if (rdev->family >= CHIP_R600)
2822 scratch_reg = R600_BIOS_0_SCRATCH;
2823 else
2824 scratch_reg = RADEON_BIOS_0_SCRATCH;
2825
2826 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2827 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2828 }
2829
radeon_atom_output_lock(struct drm_encoder * encoder,bool lock)2830 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2831 {
2832 struct drm_device *dev = encoder->dev;
2833 struct radeon_device *rdev = dev->dev_private;
2834 uint32_t bios_6_scratch;
2835
2836 if (rdev->family >= CHIP_R600)
2837 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2838 else
2839 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2840
2841 if (lock) {
2842 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2843 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
2844 } else {
2845 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2846 bios_6_scratch |= ATOM_S6_ACC_MODE;
2847 }
2848
2849 if (rdev->family >= CHIP_R600)
2850 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2851 else
2852 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2853 }
2854
2855 /* at some point we may want to break this out into individual functions */
2856 void
radeon_atombios_connected_scratch_regs(struct drm_connector * connector,struct drm_encoder * encoder,bool connected)2857 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2858 struct drm_encoder *encoder,
2859 bool connected)
2860 {
2861 struct drm_device *dev = connector->dev;
2862 struct radeon_device *rdev = dev->dev_private;
2863 struct radeon_connector *radeon_connector =
2864 to_radeon_connector(connector);
2865 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2866 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2867
2868 if (rdev->family >= CHIP_R600) {
2869 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2870 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2871 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2872 } else {
2873 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2874 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2875 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2876 }
2877
2878 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2879 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2880 if (connected) {
2881 DRM_DEBUG_KMS("TV1 connected\n");
2882 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2883 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2884 } else {
2885 DRM_DEBUG_KMS("TV1 disconnected\n");
2886 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2887 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2888 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2889 }
2890 }
2891 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2892 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2893 if (connected) {
2894 DRM_DEBUG_KMS("CV connected\n");
2895 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2896 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2897 } else {
2898 DRM_DEBUG_KMS("CV disconnected\n");
2899 bios_0_scratch &= ~ATOM_S0_CV_MASK;
2900 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2901 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2902 }
2903 }
2904 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2905 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2906 if (connected) {
2907 DRM_DEBUG_KMS("LCD1 connected\n");
2908 bios_0_scratch |= ATOM_S0_LCD1;
2909 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2910 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2911 } else {
2912 DRM_DEBUG_KMS("LCD1 disconnected\n");
2913 bios_0_scratch &= ~ATOM_S0_LCD1;
2914 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2915 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2916 }
2917 }
2918 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2919 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2920 if (connected) {
2921 DRM_DEBUG_KMS("CRT1 connected\n");
2922 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2923 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2924 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2925 } else {
2926 DRM_DEBUG_KMS("CRT1 disconnected\n");
2927 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2928 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2929 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2930 }
2931 }
2932 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2933 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2934 if (connected) {
2935 DRM_DEBUG_KMS("CRT2 connected\n");
2936 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2937 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2938 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2939 } else {
2940 DRM_DEBUG_KMS("CRT2 disconnected\n");
2941 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2942 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2943 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2944 }
2945 }
2946 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2947 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2948 if (connected) {
2949 DRM_DEBUG_KMS("DFP1 connected\n");
2950 bios_0_scratch |= ATOM_S0_DFP1;
2951 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2952 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2953 } else {
2954 DRM_DEBUG_KMS("DFP1 disconnected\n");
2955 bios_0_scratch &= ~ATOM_S0_DFP1;
2956 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2957 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2958 }
2959 }
2960 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2961 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2962 if (connected) {
2963 DRM_DEBUG_KMS("DFP2 connected\n");
2964 bios_0_scratch |= ATOM_S0_DFP2;
2965 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2966 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2967 } else {
2968 DRM_DEBUG_KMS("DFP2 disconnected\n");
2969 bios_0_scratch &= ~ATOM_S0_DFP2;
2970 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2971 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2972 }
2973 }
2974 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2975 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2976 if (connected) {
2977 DRM_DEBUG_KMS("DFP3 connected\n");
2978 bios_0_scratch |= ATOM_S0_DFP3;
2979 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2980 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2981 } else {
2982 DRM_DEBUG_KMS("DFP3 disconnected\n");
2983 bios_0_scratch &= ~ATOM_S0_DFP3;
2984 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2985 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2986 }
2987 }
2988 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2989 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2990 if (connected) {
2991 DRM_DEBUG_KMS("DFP4 connected\n");
2992 bios_0_scratch |= ATOM_S0_DFP4;
2993 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2994 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2995 } else {
2996 DRM_DEBUG_KMS("DFP4 disconnected\n");
2997 bios_0_scratch &= ~ATOM_S0_DFP4;
2998 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2999 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
3000 }
3001 }
3002 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
3003 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
3004 if (connected) {
3005 DRM_DEBUG_KMS("DFP5 connected\n");
3006 bios_0_scratch |= ATOM_S0_DFP5;
3007 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
3008 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
3009 } else {
3010 DRM_DEBUG_KMS("DFP5 disconnected\n");
3011 bios_0_scratch &= ~ATOM_S0_DFP5;
3012 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
3013 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
3014 }
3015 }
3016 if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) &&
3017 (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) {
3018 if (connected) {
3019 DRM_DEBUG_KMS("DFP6 connected\n");
3020 bios_0_scratch |= ATOM_S0_DFP6;
3021 bios_3_scratch |= ATOM_S3_DFP6_ACTIVE;
3022 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6;
3023 } else {
3024 DRM_DEBUG_KMS("DFP6 disconnected\n");
3025 bios_0_scratch &= ~ATOM_S0_DFP6;
3026 bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE;
3027 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6;
3028 }
3029 }
3030
3031 if (rdev->family >= CHIP_R600) {
3032 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
3033 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
3034 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
3035 } else {
3036 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3037 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
3038 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3039 }
3040 }
3041
3042 void
radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder * encoder,int crtc)3043 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3044 {
3045 struct drm_device *dev = encoder->dev;
3046 struct radeon_device *rdev = dev->dev_private;
3047 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3048 uint32_t bios_3_scratch;
3049
3050 if (ASIC_IS_DCE4(rdev))
3051 return;
3052
3053 if (rdev->family >= CHIP_R600)
3054 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
3055 else
3056 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
3057
3058 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3059 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
3060 bios_3_scratch |= (crtc << 18);
3061 }
3062 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
3063 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
3064 bios_3_scratch |= (crtc << 24);
3065 }
3066 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3067 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
3068 bios_3_scratch |= (crtc << 16);
3069 }
3070 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3071 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
3072 bios_3_scratch |= (crtc << 20);
3073 }
3074 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3075 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
3076 bios_3_scratch |= (crtc << 17);
3077 }
3078 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3079 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
3080 bios_3_scratch |= (crtc << 19);
3081 }
3082 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3083 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
3084 bios_3_scratch |= (crtc << 23);
3085 }
3086 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
3087 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
3088 bios_3_scratch |= (crtc << 25);
3089 }
3090
3091 if (rdev->family >= CHIP_R600)
3092 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
3093 else
3094 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
3095 }
3096
3097 void
radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder * encoder,bool on)3098 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3099 {
3100 struct drm_device *dev = encoder->dev;
3101 struct radeon_device *rdev = dev->dev_private;
3102 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3103 uint32_t bios_2_scratch;
3104
3105 if (ASIC_IS_DCE4(rdev))
3106 return;
3107
3108 if (rdev->family >= CHIP_R600)
3109 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
3110 else
3111 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
3112
3113 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3114 if (on)
3115 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
3116 else
3117 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
3118 }
3119 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
3120 if (on)
3121 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
3122 else
3123 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
3124 }
3125 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3126 if (on)
3127 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
3128 else
3129 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
3130 }
3131 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3132 if (on)
3133 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
3134 else
3135 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
3136 }
3137 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3138 if (on)
3139 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
3140 else
3141 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
3142 }
3143 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3144 if (on)
3145 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
3146 else
3147 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
3148 }
3149 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3150 if (on)
3151 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
3152 else
3153 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
3154 }
3155 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
3156 if (on)
3157 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
3158 else
3159 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
3160 }
3161 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
3162 if (on)
3163 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
3164 else
3165 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
3166 }
3167 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
3168 if (on)
3169 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
3170 else
3171 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
3172 }
3173
3174 if (rdev->family >= CHIP_R600)
3175 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
3176 else
3177 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
3178 }
3179