1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * KVM PMU support for Intel CPUs
4 *
5 * Copyright 2011 Red Hat, Inc. and/or its affiliates.
6 *
7 * Authors:
8 * Avi Kivity <avi@redhat.com>
9 * Gleb Natapov <gleb@redhat.com>
10 */
11 #include <linux/types.h>
12 #include <linux/kvm_host.h>
13 #include <linux/perf_event.h>
14 #include <asm/perf_event.h>
15 #include "x86.h"
16 #include "cpuid.h"
17 #include "lapic.h"
18 #include "nested.h"
19 #include "pmu.h"
20
21 #define MSR_PMC_FULL_WIDTH_BIT (MSR_IA32_PMC0 - MSR_IA32_PERFCTR0)
22
23 static struct kvm_event_hw_type_mapping intel_arch_events[] = {
24 [0] = { 0x3c, 0x00, PERF_COUNT_HW_CPU_CYCLES },
25 [1] = { 0xc0, 0x00, PERF_COUNT_HW_INSTRUCTIONS },
26 [2] = { 0x3c, 0x01, PERF_COUNT_HW_BUS_CYCLES },
27 [3] = { 0x2e, 0x4f, PERF_COUNT_HW_CACHE_REFERENCES },
28 [4] = { 0x2e, 0x41, PERF_COUNT_HW_CACHE_MISSES },
29 [5] = { 0xc4, 0x00, PERF_COUNT_HW_BRANCH_INSTRUCTIONS },
30 [6] = { 0xc5, 0x00, PERF_COUNT_HW_BRANCH_MISSES },
31 /* The above index must match CPUID 0x0A.EBX bit vector */
32 [7] = { 0x00, 0x03, PERF_COUNT_HW_REF_CPU_CYCLES },
33 };
34
35 /* mapping between fixed pmc index and intel_arch_events array */
36 static int fixed_pmc_events[] = {1, 0, 7};
37
reprogram_fixed_counters(struct kvm_pmu * pmu,u64 data)38 static void reprogram_fixed_counters(struct kvm_pmu *pmu, u64 data)
39 {
40 struct kvm_pmc *pmc;
41 u8 old_fixed_ctr_ctrl = pmu->fixed_ctr_ctrl;
42 int i;
43
44 pmu->fixed_ctr_ctrl = data;
45 for (i = 0; i < pmu->nr_arch_fixed_counters; i++) {
46 u8 new_ctrl = fixed_ctrl_field(data, i);
47 u8 old_ctrl = fixed_ctrl_field(old_fixed_ctr_ctrl, i);
48
49 if (old_ctrl == new_ctrl)
50 continue;
51
52 pmc = get_fixed_pmc(pmu, MSR_CORE_PERF_FIXED_CTR0 + i);
53
54 __set_bit(INTEL_PMC_IDX_FIXED + i, pmu->pmc_in_use);
55 reprogram_counter(pmc);
56 }
57 }
58
intel_pmc_idx_to_pmc(struct kvm_pmu * pmu,int pmc_idx)59 static struct kvm_pmc *intel_pmc_idx_to_pmc(struct kvm_pmu *pmu, int pmc_idx)
60 {
61 if (pmc_idx < INTEL_PMC_IDX_FIXED) {
62 return get_gp_pmc(pmu, MSR_P6_EVNTSEL0 + pmc_idx,
63 MSR_P6_EVNTSEL0);
64 } else {
65 u32 idx = pmc_idx - INTEL_PMC_IDX_FIXED;
66
67 return get_fixed_pmc(pmu, idx + MSR_CORE_PERF_FIXED_CTR0);
68 }
69 }
70
reprogram_counters(struct kvm_pmu * pmu,u64 diff)71 static void reprogram_counters(struct kvm_pmu *pmu, u64 diff)
72 {
73 int bit;
74 struct kvm_pmc *pmc;
75
76 for_each_set_bit(bit, (unsigned long *)&diff, X86_PMC_IDX_MAX) {
77 pmc = intel_pmc_idx_to_pmc(pmu, bit);
78 if (pmc)
79 reprogram_counter(pmc);
80 }
81 }
82
intel_hw_event_available(struct kvm_pmc * pmc)83 static bool intel_hw_event_available(struct kvm_pmc *pmc)
84 {
85 struct kvm_pmu *pmu = pmc_to_pmu(pmc);
86 u8 event_select = pmc->eventsel & ARCH_PERFMON_EVENTSEL_EVENT;
87 u8 unit_mask = (pmc->eventsel & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
88 int i;
89
90 for (i = 0; i < ARRAY_SIZE(intel_arch_events); i++) {
91 if (intel_arch_events[i].eventsel != event_select ||
92 intel_arch_events[i].unit_mask != unit_mask)
93 continue;
94
95 /* disable event that reported as not present by cpuid */
96 if ((i < 7) && !(pmu->available_event_types & (1 << i)))
97 return false;
98
99 break;
100 }
101
102 return true;
103 }
104
105 /* check if a PMC is enabled by comparing it with globl_ctrl bits. */
intel_pmc_is_enabled(struct kvm_pmc * pmc)106 static bool intel_pmc_is_enabled(struct kvm_pmc *pmc)
107 {
108 struct kvm_pmu *pmu = pmc_to_pmu(pmc);
109
110 if (!intel_pmu_has_perf_global_ctrl(pmu))
111 return true;
112
113 return test_bit(pmc->idx, (unsigned long *)&pmu->global_ctrl);
114 }
115
intel_is_valid_rdpmc_ecx(struct kvm_vcpu * vcpu,unsigned int idx)116 static bool intel_is_valid_rdpmc_ecx(struct kvm_vcpu *vcpu, unsigned int idx)
117 {
118 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
119 bool fixed = idx & (1u << 30);
120
121 idx &= ~(3u << 30);
122
123 return fixed ? idx < pmu->nr_arch_fixed_counters
124 : idx < pmu->nr_arch_gp_counters;
125 }
126
intel_rdpmc_ecx_to_pmc(struct kvm_vcpu * vcpu,unsigned int idx,u64 * mask)127 static struct kvm_pmc *intel_rdpmc_ecx_to_pmc(struct kvm_vcpu *vcpu,
128 unsigned int idx, u64 *mask)
129 {
130 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
131 bool fixed = idx & (1u << 30);
132 struct kvm_pmc *counters;
133 unsigned int num_counters;
134
135 idx &= ~(3u << 30);
136 if (fixed) {
137 counters = pmu->fixed_counters;
138 num_counters = pmu->nr_arch_fixed_counters;
139 } else {
140 counters = pmu->gp_counters;
141 num_counters = pmu->nr_arch_gp_counters;
142 }
143 if (idx >= num_counters)
144 return NULL;
145 *mask &= pmu->counter_bitmask[fixed ? KVM_PMC_FIXED : KVM_PMC_GP];
146 return &counters[array_index_nospec(idx, num_counters)];
147 }
148
vcpu_get_perf_capabilities(struct kvm_vcpu * vcpu)149 static inline u64 vcpu_get_perf_capabilities(struct kvm_vcpu *vcpu)
150 {
151 if (!guest_cpuid_has(vcpu, X86_FEATURE_PDCM))
152 return 0;
153
154 return vcpu->arch.perf_capabilities;
155 }
156
fw_writes_is_enabled(struct kvm_vcpu * vcpu)157 static inline bool fw_writes_is_enabled(struct kvm_vcpu *vcpu)
158 {
159 return (vcpu_get_perf_capabilities(vcpu) & PMU_CAP_FW_WRITES) != 0;
160 }
161
get_fw_gp_pmc(struct kvm_pmu * pmu,u32 msr)162 static inline struct kvm_pmc *get_fw_gp_pmc(struct kvm_pmu *pmu, u32 msr)
163 {
164 if (!fw_writes_is_enabled(pmu_to_vcpu(pmu)))
165 return NULL;
166
167 return get_gp_pmc(pmu, msr, MSR_IA32_PMC0);
168 }
169
intel_pmu_is_valid_lbr_msr(struct kvm_vcpu * vcpu,u32 index)170 static bool intel_pmu_is_valid_lbr_msr(struct kvm_vcpu *vcpu, u32 index)
171 {
172 struct x86_pmu_lbr *records = vcpu_to_lbr_records(vcpu);
173 bool ret = false;
174
175 if (!intel_pmu_lbr_is_enabled(vcpu))
176 return ret;
177
178 ret = (index == MSR_LBR_SELECT) || (index == MSR_LBR_TOS) ||
179 (index >= records->from && index < records->from + records->nr) ||
180 (index >= records->to && index < records->to + records->nr);
181
182 if (!ret && records->info)
183 ret = (index >= records->info && index < records->info + records->nr);
184
185 return ret;
186 }
187
intel_is_valid_msr(struct kvm_vcpu * vcpu,u32 msr)188 static bool intel_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr)
189 {
190 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
191 u64 perf_capabilities;
192 int ret;
193
194 switch (msr) {
195 case MSR_CORE_PERF_FIXED_CTR_CTRL:
196 case MSR_CORE_PERF_GLOBAL_STATUS:
197 case MSR_CORE_PERF_GLOBAL_CTRL:
198 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
199 return intel_pmu_has_perf_global_ctrl(pmu);
200 break;
201 case MSR_IA32_PEBS_ENABLE:
202 ret = vcpu_get_perf_capabilities(vcpu) & PERF_CAP_PEBS_FORMAT;
203 break;
204 case MSR_IA32_DS_AREA:
205 ret = guest_cpuid_has(vcpu, X86_FEATURE_DS);
206 break;
207 case MSR_PEBS_DATA_CFG:
208 perf_capabilities = vcpu_get_perf_capabilities(vcpu);
209 ret = (perf_capabilities & PERF_CAP_PEBS_BASELINE) &&
210 ((perf_capabilities & PERF_CAP_PEBS_FORMAT) > 3);
211 break;
212 default:
213 ret = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0) ||
214 get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0) ||
215 get_fixed_pmc(pmu, msr) || get_fw_gp_pmc(pmu, msr) ||
216 intel_pmu_is_valid_lbr_msr(vcpu, msr);
217 break;
218 }
219
220 return ret;
221 }
222
intel_msr_idx_to_pmc(struct kvm_vcpu * vcpu,u32 msr)223 static struct kvm_pmc *intel_msr_idx_to_pmc(struct kvm_vcpu *vcpu, u32 msr)
224 {
225 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
226 struct kvm_pmc *pmc;
227
228 pmc = get_fixed_pmc(pmu, msr);
229 pmc = pmc ? pmc : get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0);
230 pmc = pmc ? pmc : get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0);
231
232 return pmc;
233 }
234
intel_pmu_release_guest_lbr_event(struct kvm_vcpu * vcpu)235 static inline void intel_pmu_release_guest_lbr_event(struct kvm_vcpu *vcpu)
236 {
237 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu);
238
239 if (lbr_desc->event) {
240 perf_event_release_kernel(lbr_desc->event);
241 lbr_desc->event = NULL;
242 vcpu_to_pmu(vcpu)->event_count--;
243 }
244 }
245
intel_pmu_create_guest_lbr_event(struct kvm_vcpu * vcpu)246 int intel_pmu_create_guest_lbr_event(struct kvm_vcpu *vcpu)
247 {
248 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu);
249 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
250 struct perf_event *event;
251
252 /*
253 * The perf_event_attr is constructed in the minimum efficient way:
254 * - set 'pinned = true' to make it task pinned so that if another
255 * cpu pinned event reclaims LBR, the event->oncpu will be set to -1;
256 * - set '.exclude_host = true' to record guest branches behavior;
257 *
258 * - set '.config = INTEL_FIXED_VLBR_EVENT' to indicates host perf
259 * schedule the event without a real HW counter but a fake one;
260 * check is_guest_lbr_event() and __intel_get_event_constraints();
261 *
262 * - set 'sample_type = PERF_SAMPLE_BRANCH_STACK' and
263 * 'branch_sample_type = PERF_SAMPLE_BRANCH_CALL_STACK |
264 * PERF_SAMPLE_BRANCH_USER' to configure it as a LBR callstack
265 * event, which helps KVM to save/restore guest LBR records
266 * during host context switches and reduces quite a lot overhead,
267 * check branch_user_callstack() and intel_pmu_lbr_sched_task();
268 */
269 struct perf_event_attr attr = {
270 .type = PERF_TYPE_RAW,
271 .size = sizeof(attr),
272 .config = INTEL_FIXED_VLBR_EVENT,
273 .sample_type = PERF_SAMPLE_BRANCH_STACK,
274 .pinned = true,
275 .exclude_host = true,
276 .branch_sample_type = PERF_SAMPLE_BRANCH_CALL_STACK |
277 PERF_SAMPLE_BRANCH_USER,
278 };
279
280 if (unlikely(lbr_desc->event)) {
281 __set_bit(INTEL_PMC_IDX_FIXED_VLBR, pmu->pmc_in_use);
282 return 0;
283 }
284
285 event = perf_event_create_kernel_counter(&attr, -1,
286 current, NULL, NULL);
287 if (IS_ERR(event)) {
288 pr_debug_ratelimited("%s: failed %ld\n",
289 __func__, PTR_ERR(event));
290 return PTR_ERR(event);
291 }
292 lbr_desc->event = event;
293 pmu->event_count++;
294 __set_bit(INTEL_PMC_IDX_FIXED_VLBR, pmu->pmc_in_use);
295 return 0;
296 }
297
298 /*
299 * It's safe to access LBR msrs from guest when they have not
300 * been passthrough since the host would help restore or reset
301 * the LBR msrs records when the guest LBR event is scheduled in.
302 */
intel_pmu_handle_lbr_msrs_access(struct kvm_vcpu * vcpu,struct msr_data * msr_info,bool read)303 static bool intel_pmu_handle_lbr_msrs_access(struct kvm_vcpu *vcpu,
304 struct msr_data *msr_info, bool read)
305 {
306 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu);
307 u32 index = msr_info->index;
308
309 if (!intel_pmu_is_valid_lbr_msr(vcpu, index))
310 return false;
311
312 if (!lbr_desc->event && intel_pmu_create_guest_lbr_event(vcpu) < 0)
313 goto dummy;
314
315 /*
316 * Disable irq to ensure the LBR feature doesn't get reclaimed by the
317 * host at the time the value is read from the msr, and this avoids the
318 * host LBR value to be leaked to the guest. If LBR has been reclaimed,
319 * return 0 on guest reads.
320 */
321 local_irq_disable();
322 if (lbr_desc->event->state == PERF_EVENT_STATE_ACTIVE) {
323 if (read)
324 rdmsrl(index, msr_info->data);
325 else
326 wrmsrl(index, msr_info->data);
327 __set_bit(INTEL_PMC_IDX_FIXED_VLBR, vcpu_to_pmu(vcpu)->pmc_in_use);
328 local_irq_enable();
329 return true;
330 }
331 clear_bit(INTEL_PMC_IDX_FIXED_VLBR, vcpu_to_pmu(vcpu)->pmc_in_use);
332 local_irq_enable();
333
334 dummy:
335 if (read)
336 msr_info->data = 0;
337 return true;
338 }
339
intel_pmu_get_msr(struct kvm_vcpu * vcpu,struct msr_data * msr_info)340 static int intel_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
341 {
342 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
343 struct kvm_pmc *pmc;
344 u32 msr = msr_info->index;
345
346 switch (msr) {
347 case MSR_CORE_PERF_FIXED_CTR_CTRL:
348 msr_info->data = pmu->fixed_ctr_ctrl;
349 return 0;
350 case MSR_CORE_PERF_GLOBAL_STATUS:
351 msr_info->data = pmu->global_status;
352 return 0;
353 case MSR_CORE_PERF_GLOBAL_CTRL:
354 msr_info->data = pmu->global_ctrl;
355 return 0;
356 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
357 msr_info->data = 0;
358 return 0;
359 case MSR_IA32_PEBS_ENABLE:
360 msr_info->data = pmu->pebs_enable;
361 return 0;
362 case MSR_IA32_DS_AREA:
363 msr_info->data = pmu->ds_area;
364 return 0;
365 case MSR_PEBS_DATA_CFG:
366 msr_info->data = pmu->pebs_data_cfg;
367 return 0;
368 default:
369 if ((pmc = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)) ||
370 (pmc = get_gp_pmc(pmu, msr, MSR_IA32_PMC0))) {
371 u64 val = pmc_read_counter(pmc);
372 msr_info->data =
373 val & pmu->counter_bitmask[KVM_PMC_GP];
374 return 0;
375 } else if ((pmc = get_fixed_pmc(pmu, msr))) {
376 u64 val = pmc_read_counter(pmc);
377 msr_info->data =
378 val & pmu->counter_bitmask[KVM_PMC_FIXED];
379 return 0;
380 } else if ((pmc = get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0))) {
381 msr_info->data = pmc->eventsel;
382 return 0;
383 } else if (intel_pmu_handle_lbr_msrs_access(vcpu, msr_info, true))
384 return 0;
385 }
386
387 return 1;
388 }
389
intel_pmu_set_msr(struct kvm_vcpu * vcpu,struct msr_data * msr_info)390 static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
391 {
392 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
393 struct kvm_pmc *pmc;
394 u32 msr = msr_info->index;
395 u64 data = msr_info->data;
396 u64 reserved_bits, diff;
397
398 switch (msr) {
399 case MSR_CORE_PERF_FIXED_CTR_CTRL:
400 if (pmu->fixed_ctr_ctrl == data)
401 return 0;
402 if (!(data & pmu->fixed_ctr_ctrl_mask)) {
403 reprogram_fixed_counters(pmu, data);
404 return 0;
405 }
406 break;
407 case MSR_CORE_PERF_GLOBAL_STATUS:
408 if (msr_info->host_initiated) {
409 pmu->global_status = data;
410 return 0;
411 }
412 break; /* RO MSR */
413 case MSR_CORE_PERF_GLOBAL_CTRL:
414 if (pmu->global_ctrl == data)
415 return 0;
416 if (kvm_valid_perf_global_ctrl(pmu, data)) {
417 diff = pmu->global_ctrl ^ data;
418 pmu->global_ctrl = data;
419 reprogram_counters(pmu, diff);
420 return 0;
421 }
422 break;
423 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
424 if (!(data & pmu->global_ovf_ctrl_mask)) {
425 if (!msr_info->host_initiated)
426 pmu->global_status &= ~data;
427 return 0;
428 }
429 break;
430 case MSR_IA32_PEBS_ENABLE:
431 if (pmu->pebs_enable == data)
432 return 0;
433 if (!(data & pmu->pebs_enable_mask)) {
434 diff = pmu->pebs_enable ^ data;
435 pmu->pebs_enable = data;
436 reprogram_counters(pmu, diff);
437 return 0;
438 }
439 break;
440 case MSR_IA32_DS_AREA:
441 if (msr_info->host_initiated && data && !guest_cpuid_has(vcpu, X86_FEATURE_DS))
442 return 1;
443 if (is_noncanonical_address(data, vcpu))
444 return 1;
445 pmu->ds_area = data;
446 return 0;
447 case MSR_PEBS_DATA_CFG:
448 if (pmu->pebs_data_cfg == data)
449 return 0;
450 if (!(data & pmu->pebs_data_cfg_mask)) {
451 pmu->pebs_data_cfg = data;
452 return 0;
453 }
454 break;
455 default:
456 if ((pmc = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)) ||
457 (pmc = get_gp_pmc(pmu, msr, MSR_IA32_PMC0))) {
458 if ((msr & MSR_PMC_FULL_WIDTH_BIT) &&
459 (data & ~pmu->counter_bitmask[KVM_PMC_GP]))
460 return 1;
461 if (!msr_info->host_initiated &&
462 !(msr & MSR_PMC_FULL_WIDTH_BIT))
463 data = (s64)(s32)data;
464 pmc->counter += data - pmc_read_counter(pmc);
465 pmc_update_sample_period(pmc);
466 return 0;
467 } else if ((pmc = get_fixed_pmc(pmu, msr))) {
468 pmc->counter += data - pmc_read_counter(pmc);
469 pmc_update_sample_period(pmc);
470 return 0;
471 } else if ((pmc = get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0))) {
472 if (data == pmc->eventsel)
473 return 0;
474 reserved_bits = pmu->reserved_bits;
475 if ((pmc->idx == 2) &&
476 (pmu->raw_event_mask & HSW_IN_TX_CHECKPOINTED))
477 reserved_bits ^= HSW_IN_TX_CHECKPOINTED;
478 if (!(data & reserved_bits)) {
479 pmc->eventsel = data;
480 reprogram_counter(pmc);
481 return 0;
482 }
483 } else if (intel_pmu_handle_lbr_msrs_access(vcpu, msr_info, false))
484 return 0;
485 }
486
487 return 1;
488 }
489
setup_fixed_pmc_eventsel(struct kvm_pmu * pmu)490 static void setup_fixed_pmc_eventsel(struct kvm_pmu *pmu)
491 {
492 size_t size = ARRAY_SIZE(fixed_pmc_events);
493 struct kvm_pmc *pmc;
494 u32 event;
495 int i;
496
497 for (i = 0; i < pmu->nr_arch_fixed_counters; i++) {
498 pmc = &pmu->fixed_counters[i];
499 event = fixed_pmc_events[array_index_nospec(i, size)];
500 pmc->eventsel = (intel_arch_events[event].unit_mask << 8) |
501 intel_arch_events[event].eventsel;
502 }
503 }
504
intel_pmu_refresh(struct kvm_vcpu * vcpu)505 static void intel_pmu_refresh(struct kvm_vcpu *vcpu)
506 {
507 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
508 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu);
509 struct kvm_cpuid_entry2 *entry;
510 union cpuid10_eax eax;
511 union cpuid10_edx edx;
512 u64 perf_capabilities;
513 u64 counter_mask;
514 int i;
515
516 pmu->nr_arch_gp_counters = 0;
517 pmu->nr_arch_fixed_counters = 0;
518 pmu->counter_bitmask[KVM_PMC_GP] = 0;
519 pmu->counter_bitmask[KVM_PMC_FIXED] = 0;
520 pmu->version = 0;
521 pmu->reserved_bits = 0xffffffff00200000ull;
522 pmu->raw_event_mask = X86_RAW_EVENT_MASK;
523 pmu->global_ctrl_mask = ~0ull;
524 pmu->global_ovf_ctrl_mask = ~0ull;
525 pmu->fixed_ctr_ctrl_mask = ~0ull;
526 pmu->pebs_enable_mask = ~0ull;
527 pmu->pebs_data_cfg_mask = ~0ull;
528
529 entry = kvm_find_cpuid_entry(vcpu, 0xa);
530 if (!entry || !vcpu->kvm->arch.enable_pmu)
531 return;
532 eax.full = entry->eax;
533 edx.full = entry->edx;
534
535 pmu->version = eax.split.version_id;
536 if (!pmu->version)
537 return;
538
539 pmu->nr_arch_gp_counters = min_t(int, eax.split.num_counters,
540 kvm_pmu_cap.num_counters_gp);
541 eax.split.bit_width = min_t(int, eax.split.bit_width,
542 kvm_pmu_cap.bit_width_gp);
543 pmu->counter_bitmask[KVM_PMC_GP] = ((u64)1 << eax.split.bit_width) - 1;
544 eax.split.mask_length = min_t(int, eax.split.mask_length,
545 kvm_pmu_cap.events_mask_len);
546 pmu->available_event_types = ~entry->ebx &
547 ((1ull << eax.split.mask_length) - 1);
548
549 if (pmu->version == 1) {
550 pmu->nr_arch_fixed_counters = 0;
551 } else {
552 pmu->nr_arch_fixed_counters =
553 min3(ARRAY_SIZE(fixed_pmc_events),
554 (size_t) edx.split.num_counters_fixed,
555 (size_t)kvm_pmu_cap.num_counters_fixed);
556 edx.split.bit_width_fixed = min_t(int, edx.split.bit_width_fixed,
557 kvm_pmu_cap.bit_width_fixed);
558 pmu->counter_bitmask[KVM_PMC_FIXED] =
559 ((u64)1 << edx.split.bit_width_fixed) - 1;
560 setup_fixed_pmc_eventsel(pmu);
561 }
562
563 for (i = 0; i < pmu->nr_arch_fixed_counters; i++)
564 pmu->fixed_ctr_ctrl_mask &= ~(0xbull << (i * 4));
565 counter_mask = ~(((1ull << pmu->nr_arch_gp_counters) - 1) |
566 (((1ull << pmu->nr_arch_fixed_counters) - 1) << INTEL_PMC_IDX_FIXED));
567 pmu->global_ctrl_mask = counter_mask;
568 pmu->global_ovf_ctrl_mask = pmu->global_ctrl_mask
569 & ~(MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF |
570 MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD);
571 if (vmx_pt_mode_is_host_guest())
572 pmu->global_ovf_ctrl_mask &=
573 ~MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI;
574
575 entry = kvm_find_cpuid_entry_index(vcpu, 7, 0);
576 if (entry &&
577 (boot_cpu_has(X86_FEATURE_HLE) || boot_cpu_has(X86_FEATURE_RTM)) &&
578 (entry->ebx & (X86_FEATURE_HLE|X86_FEATURE_RTM))) {
579 pmu->reserved_bits ^= HSW_IN_TX;
580 pmu->raw_event_mask |= (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
581 }
582
583 bitmap_set(pmu->all_valid_pmc_idx,
584 0, pmu->nr_arch_gp_counters);
585 bitmap_set(pmu->all_valid_pmc_idx,
586 INTEL_PMC_MAX_GENERIC, pmu->nr_arch_fixed_counters);
587
588 perf_capabilities = vcpu_get_perf_capabilities(vcpu);
589 if (cpuid_model_is_consistent(vcpu) &&
590 (perf_capabilities & PMU_CAP_LBR_FMT))
591 x86_perf_get_lbr(&lbr_desc->records);
592 else
593 lbr_desc->records.nr = 0;
594
595 if (lbr_desc->records.nr)
596 bitmap_set(pmu->all_valid_pmc_idx, INTEL_PMC_IDX_FIXED_VLBR, 1);
597
598 if (perf_capabilities & PERF_CAP_PEBS_FORMAT) {
599 if (perf_capabilities & PERF_CAP_PEBS_BASELINE) {
600 pmu->pebs_enable_mask = counter_mask;
601 pmu->reserved_bits &= ~ICL_EVENTSEL_ADAPTIVE;
602 for (i = 0; i < pmu->nr_arch_fixed_counters; i++) {
603 pmu->fixed_ctr_ctrl_mask &=
604 ~(1ULL << (INTEL_PMC_IDX_FIXED + i * 4));
605 }
606 pmu->pebs_data_cfg_mask = ~0xff00000full;
607 } else {
608 pmu->pebs_enable_mask =
609 ~((1ull << pmu->nr_arch_gp_counters) - 1);
610 }
611 }
612 }
613
intel_pmu_init(struct kvm_vcpu * vcpu)614 static void intel_pmu_init(struct kvm_vcpu *vcpu)
615 {
616 int i;
617 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
618 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu);
619
620 for (i = 0; i < KVM_INTEL_PMC_MAX_GENERIC; i++) {
621 pmu->gp_counters[i].type = KVM_PMC_GP;
622 pmu->gp_counters[i].vcpu = vcpu;
623 pmu->gp_counters[i].idx = i;
624 pmu->gp_counters[i].current_config = 0;
625 }
626
627 for (i = 0; i < KVM_PMC_MAX_FIXED; i++) {
628 pmu->fixed_counters[i].type = KVM_PMC_FIXED;
629 pmu->fixed_counters[i].vcpu = vcpu;
630 pmu->fixed_counters[i].idx = i + INTEL_PMC_IDX_FIXED;
631 pmu->fixed_counters[i].current_config = 0;
632 }
633
634 vcpu->arch.perf_capabilities = vmx_get_perf_capabilities();
635 lbr_desc->records.nr = 0;
636 lbr_desc->event = NULL;
637 lbr_desc->msr_passthrough = false;
638 }
639
intel_pmu_reset(struct kvm_vcpu * vcpu)640 static void intel_pmu_reset(struct kvm_vcpu *vcpu)
641 {
642 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
643 struct kvm_pmc *pmc = NULL;
644 int i;
645
646 for (i = 0; i < KVM_INTEL_PMC_MAX_GENERIC; i++) {
647 pmc = &pmu->gp_counters[i];
648
649 pmc_stop_counter(pmc);
650 pmc->counter = pmc->eventsel = 0;
651 }
652
653 for (i = 0; i < KVM_PMC_MAX_FIXED; i++) {
654 pmc = &pmu->fixed_counters[i];
655
656 pmc_stop_counter(pmc);
657 pmc->counter = 0;
658 }
659
660 pmu->fixed_ctr_ctrl = pmu->global_ctrl = pmu->global_status = 0;
661
662 intel_pmu_release_guest_lbr_event(vcpu);
663 }
664
665 /*
666 * Emulate LBR_On_PMI behavior for 1 < pmu.version < 4.
667 *
668 * If Freeze_LBR_On_PMI = 1, the LBR is frozen on PMI and
669 * the KVM emulates to clear the LBR bit (bit 0) in IA32_DEBUGCTL.
670 *
671 * Guest needs to re-enable LBR to resume branches recording.
672 */
intel_pmu_legacy_freezing_lbrs_on_pmi(struct kvm_vcpu * vcpu)673 static void intel_pmu_legacy_freezing_lbrs_on_pmi(struct kvm_vcpu *vcpu)
674 {
675 u64 data = vmcs_read64(GUEST_IA32_DEBUGCTL);
676
677 if (data & DEBUGCTLMSR_FREEZE_LBRS_ON_PMI) {
678 data &= ~DEBUGCTLMSR_LBR;
679 vmcs_write64(GUEST_IA32_DEBUGCTL, data);
680 }
681 }
682
intel_pmu_deliver_pmi(struct kvm_vcpu * vcpu)683 static void intel_pmu_deliver_pmi(struct kvm_vcpu *vcpu)
684 {
685 u8 version = vcpu_to_pmu(vcpu)->version;
686
687 if (!intel_pmu_lbr_is_enabled(vcpu))
688 return;
689
690 if (version > 1 && version < 4)
691 intel_pmu_legacy_freezing_lbrs_on_pmi(vcpu);
692 }
693
vmx_update_intercept_for_lbr_msrs(struct kvm_vcpu * vcpu,bool set)694 static void vmx_update_intercept_for_lbr_msrs(struct kvm_vcpu *vcpu, bool set)
695 {
696 struct x86_pmu_lbr *lbr = vcpu_to_lbr_records(vcpu);
697 int i;
698
699 for (i = 0; i < lbr->nr; i++) {
700 vmx_set_intercept_for_msr(vcpu, lbr->from + i, MSR_TYPE_RW, set);
701 vmx_set_intercept_for_msr(vcpu, lbr->to + i, MSR_TYPE_RW, set);
702 if (lbr->info)
703 vmx_set_intercept_for_msr(vcpu, lbr->info + i, MSR_TYPE_RW, set);
704 }
705
706 vmx_set_intercept_for_msr(vcpu, MSR_LBR_SELECT, MSR_TYPE_RW, set);
707 vmx_set_intercept_for_msr(vcpu, MSR_LBR_TOS, MSR_TYPE_RW, set);
708 }
709
vmx_disable_lbr_msrs_passthrough(struct kvm_vcpu * vcpu)710 static inline void vmx_disable_lbr_msrs_passthrough(struct kvm_vcpu *vcpu)
711 {
712 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu);
713
714 if (!lbr_desc->msr_passthrough)
715 return;
716
717 vmx_update_intercept_for_lbr_msrs(vcpu, true);
718 lbr_desc->msr_passthrough = false;
719 }
720
vmx_enable_lbr_msrs_passthrough(struct kvm_vcpu * vcpu)721 static inline void vmx_enable_lbr_msrs_passthrough(struct kvm_vcpu *vcpu)
722 {
723 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu);
724
725 if (lbr_desc->msr_passthrough)
726 return;
727
728 vmx_update_intercept_for_lbr_msrs(vcpu, false);
729 lbr_desc->msr_passthrough = true;
730 }
731
732 /*
733 * Higher priority host perf events (e.g. cpu pinned) could reclaim the
734 * pmu resources (e.g. LBR) that were assigned to the guest. This is
735 * usually done via ipi calls (more details in perf_install_in_context).
736 *
737 * Before entering the non-root mode (with irq disabled here), double
738 * confirm that the pmu features enabled to the guest are not reclaimed
739 * by higher priority host events. Otherwise, disallow vcpu's access to
740 * the reclaimed features.
741 */
vmx_passthrough_lbr_msrs(struct kvm_vcpu * vcpu)742 void vmx_passthrough_lbr_msrs(struct kvm_vcpu *vcpu)
743 {
744 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
745 struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu);
746
747 if (!lbr_desc->event) {
748 vmx_disable_lbr_msrs_passthrough(vcpu);
749 if (vmcs_read64(GUEST_IA32_DEBUGCTL) & DEBUGCTLMSR_LBR)
750 goto warn;
751 if (test_bit(INTEL_PMC_IDX_FIXED_VLBR, pmu->pmc_in_use))
752 goto warn;
753 return;
754 }
755
756 if (lbr_desc->event->state < PERF_EVENT_STATE_ACTIVE) {
757 vmx_disable_lbr_msrs_passthrough(vcpu);
758 __clear_bit(INTEL_PMC_IDX_FIXED_VLBR, pmu->pmc_in_use);
759 goto warn;
760 } else
761 vmx_enable_lbr_msrs_passthrough(vcpu);
762
763 return;
764
765 warn:
766 pr_warn_ratelimited("kvm: vcpu-%d: fail to passthrough LBR.\n",
767 vcpu->vcpu_id);
768 }
769
intel_pmu_cleanup(struct kvm_vcpu * vcpu)770 static void intel_pmu_cleanup(struct kvm_vcpu *vcpu)
771 {
772 if (!(vmcs_read64(GUEST_IA32_DEBUGCTL) & DEBUGCTLMSR_LBR))
773 intel_pmu_release_guest_lbr_event(vcpu);
774 }
775
intel_pmu_cross_mapped_check(struct kvm_pmu * pmu)776 void intel_pmu_cross_mapped_check(struct kvm_pmu *pmu)
777 {
778 struct kvm_pmc *pmc = NULL;
779 int bit, hw_idx;
780
781 for_each_set_bit(bit, (unsigned long *)&pmu->global_ctrl,
782 X86_PMC_IDX_MAX) {
783 pmc = intel_pmc_idx_to_pmc(pmu, bit);
784
785 if (!pmc || !pmc_speculative_in_use(pmc) ||
786 !intel_pmc_is_enabled(pmc) || !pmc->perf_event)
787 continue;
788
789 /*
790 * A negative index indicates the event isn't mapped to a
791 * physical counter in the host, e.g. due to contention.
792 */
793 hw_idx = pmc->perf_event->hw.idx;
794 if (hw_idx != pmc->idx && hw_idx > -1)
795 pmu->host_cross_mapped_mask |= BIT_ULL(hw_idx);
796 }
797 }
798
799 struct kvm_pmu_ops intel_pmu_ops __initdata = {
800 .hw_event_available = intel_hw_event_available,
801 .pmc_is_enabled = intel_pmc_is_enabled,
802 .pmc_idx_to_pmc = intel_pmc_idx_to_pmc,
803 .rdpmc_ecx_to_pmc = intel_rdpmc_ecx_to_pmc,
804 .msr_idx_to_pmc = intel_msr_idx_to_pmc,
805 .is_valid_rdpmc_ecx = intel_is_valid_rdpmc_ecx,
806 .is_valid_msr = intel_is_valid_msr,
807 .get_msr = intel_pmu_get_msr,
808 .set_msr = intel_pmu_set_msr,
809 .refresh = intel_pmu_refresh,
810 .init = intel_pmu_init,
811 .reset = intel_pmu_reset,
812 .deliver_pmi = intel_pmu_deliver_pmi,
813 .cleanup = intel_pmu_cleanup,
814 };
815