1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Processor capabilities determination functions.
4  *
5  * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
6  */
7 #include <linux/init.h>
8 #include <linux/kernel.h>
9 #include <linux/ptrace.h>
10 #include <linux/smp.h>
11 #include <linux/stddef.h>
12 #include <linux/export.h>
13 #include <linux/printk.h>
14 #include <linux/uaccess.h>
15 
16 #include <asm/cpu-features.h>
17 #include <asm/elf.h>
18 #include <asm/fpu.h>
19 #include <asm/loongarch.h>
20 #include <asm/pgtable-bits.h>
21 #include <asm/setup.h>
22 
23 /* Hardware capabilities */
24 unsigned int elf_hwcap __read_mostly;
25 EXPORT_SYMBOL_GPL(elf_hwcap);
26 
27 /*
28  * Determine the FCSR mask for FPU hardware.
29  */
cpu_set_fpu_fcsr_mask(struct cpuinfo_loongarch * c)30 static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_loongarch *c)
31 {
32 	unsigned long sr, mask, fcsr, fcsr0, fcsr1;
33 
34 	fcsr = c->fpu_csr0;
35 	mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
36 
37 	sr = read_csr_euen();
38 	enable_fpu();
39 
40 	fcsr0 = fcsr & mask;
41 	write_fcsr(LOONGARCH_FCSR0, fcsr0);
42 	fcsr0 = read_fcsr(LOONGARCH_FCSR0);
43 
44 	fcsr1 = fcsr | ~mask;
45 	write_fcsr(LOONGARCH_FCSR0, fcsr1);
46 	fcsr1 = read_fcsr(LOONGARCH_FCSR0);
47 
48 	write_fcsr(LOONGARCH_FCSR0, fcsr);
49 
50 	write_csr_euen(sr);
51 
52 	c->fpu_mask = ~(fcsr0 ^ fcsr1) & ~mask;
53 }
54 
set_elf_platform(int cpu,const char * plat)55 static inline void set_elf_platform(int cpu, const char *plat)
56 {
57 	if (cpu == 0)
58 		__elf_platform = plat;
59 }
60 
61 /* MAP BASE */
62 unsigned long vm_map_base;
63 EXPORT_SYMBOL_GPL(vm_map_base);
64 
cpu_probe_addrbits(struct cpuinfo_loongarch * c)65 static void cpu_probe_addrbits(struct cpuinfo_loongarch *c)
66 {
67 #ifdef __NEED_ADDRBITS_PROBE
68 	c->pabits = (read_cpucfg(LOONGARCH_CPUCFG1) & CPUCFG1_PABITS) >> 4;
69 	c->vabits = (read_cpucfg(LOONGARCH_CPUCFG1) & CPUCFG1_VABITS) >> 12;
70 	vm_map_base = 0UL - (1UL << c->vabits);
71 #endif
72 }
73 
set_isa(struct cpuinfo_loongarch * c,unsigned int isa)74 static void set_isa(struct cpuinfo_loongarch *c, unsigned int isa)
75 {
76 	switch (isa) {
77 	case LOONGARCH_CPU_ISA_LA64:
78 		c->isa_level |= LOONGARCH_CPU_ISA_LA64;
79 		fallthrough;
80 	case LOONGARCH_CPU_ISA_LA32S:
81 		c->isa_level |= LOONGARCH_CPU_ISA_LA32S;
82 		fallthrough;
83 	case LOONGARCH_CPU_ISA_LA32R:
84 		c->isa_level |= LOONGARCH_CPU_ISA_LA32R;
85 		break;
86 	}
87 }
88 
cpu_probe_common(struct cpuinfo_loongarch * c)89 static void cpu_probe_common(struct cpuinfo_loongarch *c)
90 {
91 	unsigned int config;
92 	unsigned long asid_mask;
93 
94 	c->options = LOONGARCH_CPU_CPUCFG | LOONGARCH_CPU_CSR |
95 		     LOONGARCH_CPU_TLB | LOONGARCH_CPU_VINT | LOONGARCH_CPU_WATCH;
96 
97 	elf_hwcap = HWCAP_LOONGARCH_CPUCFG | HWCAP_LOONGARCH_CRC32;
98 
99 	config = read_cpucfg(LOONGARCH_CPUCFG1);
100 	if (config & CPUCFG1_UAL) {
101 		c->options |= LOONGARCH_CPU_UAL;
102 		elf_hwcap |= HWCAP_LOONGARCH_UAL;
103 	}
104 
105 	config = read_cpucfg(LOONGARCH_CPUCFG2);
106 	if (config & CPUCFG2_LAM) {
107 		c->options |= LOONGARCH_CPU_LAM;
108 		elf_hwcap |= HWCAP_LOONGARCH_LAM;
109 	}
110 	if (config & CPUCFG2_FP) {
111 		c->options |= LOONGARCH_CPU_FPU;
112 		elf_hwcap |= HWCAP_LOONGARCH_FPU;
113 	}
114 	if (config & CPUCFG2_COMPLEX) {
115 		c->options |= LOONGARCH_CPU_COMPLEX;
116 		elf_hwcap |= HWCAP_LOONGARCH_COMPLEX;
117 	}
118 	if (config & CPUCFG2_CRYPTO) {
119 		c->options |= LOONGARCH_CPU_CRYPTO;
120 		elf_hwcap |= HWCAP_LOONGARCH_CRYPTO;
121 	}
122 	if (config & CPUCFG2_LVZP) {
123 		c->options |= LOONGARCH_CPU_LVZ;
124 		elf_hwcap |= HWCAP_LOONGARCH_LVZ;
125 	}
126 
127 	config = read_cpucfg(LOONGARCH_CPUCFG6);
128 	if (config & CPUCFG6_PMP)
129 		c->options |= LOONGARCH_CPU_PMP;
130 
131 	config = iocsr_read32(LOONGARCH_IOCSR_FEATURES);
132 	if (config & IOCSRF_CSRIPI)
133 		c->options |= LOONGARCH_CPU_CSRIPI;
134 	if (config & IOCSRF_EXTIOI)
135 		c->options |= LOONGARCH_CPU_EXTIOI;
136 	if (config & IOCSRF_FREQSCALE)
137 		c->options |= LOONGARCH_CPU_SCALEFREQ;
138 	if (config & IOCSRF_FLATMODE)
139 		c->options |= LOONGARCH_CPU_FLATMODE;
140 	if (config & IOCSRF_EIODECODE)
141 		c->options |= LOONGARCH_CPU_EIODECODE;
142 	if (config & IOCSRF_VM)
143 		c->options |= LOONGARCH_CPU_HYPERVISOR;
144 
145 	config = csr_read32(LOONGARCH_CSR_ASID);
146 	config = (config & CSR_ASID_BIT) >> CSR_ASID_BIT_SHIFT;
147 	asid_mask = GENMASK(config - 1, 0);
148 	set_cpu_asid_mask(c, asid_mask);
149 
150 	config = read_csr_prcfg1();
151 	c->ksave_mask = GENMASK((config & CSR_CONF1_KSNUM) - 1, 0);
152 	c->ksave_mask &= ~(EXC_KSAVE_MASK | PERCPU_KSAVE_MASK | KVM_KSAVE_MASK);
153 
154 	config = read_csr_prcfg3();
155 	switch (config & CSR_CONF3_TLBTYPE) {
156 	case 0:
157 		c->tlbsizemtlb = 0;
158 		c->tlbsizestlbsets = 0;
159 		c->tlbsizestlbways = 0;
160 		c->tlbsize = 0;
161 		break;
162 	case 1:
163 		c->tlbsizemtlb = ((config & CSR_CONF3_MTLBSIZE) >> CSR_CONF3_MTLBSIZE_SHIFT) + 1;
164 		c->tlbsizestlbsets = 0;
165 		c->tlbsizestlbways = 0;
166 		c->tlbsize = c->tlbsizemtlb + c->tlbsizestlbsets * c->tlbsizestlbways;
167 		break;
168 	case 2:
169 		c->tlbsizemtlb = ((config & CSR_CONF3_MTLBSIZE) >> CSR_CONF3_MTLBSIZE_SHIFT) + 1;
170 		c->tlbsizestlbsets = 1 << ((config & CSR_CONF3_STLBIDX) >> CSR_CONF3_STLBIDX_SHIFT);
171 		c->tlbsizestlbways = ((config & CSR_CONF3_STLBWAYS) >> CSR_CONF3_STLBWAYS_SHIFT) + 1;
172 		c->tlbsize = c->tlbsizemtlb + c->tlbsizestlbsets * c->tlbsizestlbways;
173 		break;
174 	default:
175 		pr_warn("Warning: unknown TLB type\n");
176 	}
177 }
178 
179 #define MAX_NAME_LEN	32
180 #define VENDOR_OFFSET	0
181 #define CPUNAME_OFFSET	9
182 
183 static char cpu_full_name[MAX_NAME_LEN] = "        -        ";
184 
cpu_probe_loongson(struct cpuinfo_loongarch * c,unsigned int cpu)185 static inline void cpu_probe_loongson(struct cpuinfo_loongarch *c, unsigned int cpu)
186 {
187 	uint64_t *vendor = (void *)(&cpu_full_name[VENDOR_OFFSET]);
188 	uint64_t *cpuname = (void *)(&cpu_full_name[CPUNAME_OFFSET]);
189 
190 	if (!__cpu_full_name[cpu])
191 		__cpu_full_name[cpu] = cpu_full_name;
192 
193 	*vendor = iocsr_read64(LOONGARCH_IOCSR_VENDOR);
194 	*cpuname = iocsr_read64(LOONGARCH_IOCSR_CPUNAME);
195 
196 	switch (c->processor_id & PRID_SERIES_MASK) {
197 	case PRID_SERIES_LA132:
198 		c->cputype = CPU_LOONGSON32;
199 		set_isa(c, LOONGARCH_CPU_ISA_LA32S);
200 		__cpu_family[cpu] = "Loongson-32bit";
201 		pr_info("32-bit Loongson Processor probed (LA132 Core)\n");
202 		break;
203 	case PRID_SERIES_LA264:
204 		c->cputype = CPU_LOONGSON64;
205 		set_isa(c, LOONGARCH_CPU_ISA_LA64);
206 		__cpu_family[cpu] = "Loongson-64bit";
207 		pr_info("64-bit Loongson Processor probed (LA264 Core)\n");
208 		break;
209 	case PRID_SERIES_LA364:
210 		c->cputype = CPU_LOONGSON64;
211 		set_isa(c, LOONGARCH_CPU_ISA_LA64);
212 		__cpu_family[cpu] = "Loongson-64bit";
213 		pr_info("64-bit Loongson Processor probed (LA364 Core)\n");
214 		break;
215 	case PRID_SERIES_LA464:
216 		c->cputype = CPU_LOONGSON64;
217 		set_isa(c, LOONGARCH_CPU_ISA_LA64);
218 		__cpu_family[cpu] = "Loongson-64bit";
219 		pr_info("64-bit Loongson Processor probed (LA464 Core)\n");
220 		break;
221 	case PRID_SERIES_LA664:
222 		c->cputype = CPU_LOONGSON64;
223 		set_isa(c, LOONGARCH_CPU_ISA_LA64);
224 		__cpu_family[cpu] = "Loongson-64bit";
225 		pr_info("64-bit Loongson Processor probed (LA664 Core)\n");
226 		break;
227 	default: /* Default to 64 bit */
228 		c->cputype = CPU_LOONGSON64;
229 		set_isa(c, LOONGARCH_CPU_ISA_LA64);
230 		__cpu_family[cpu] = "Loongson-64bit";
231 		pr_info("64-bit Loongson Processor probed (Unknown Core)\n");
232 	}
233 }
234 
235 #ifdef CONFIG_64BIT
236 /* For use by uaccess.h */
237 u64 __ua_limit;
238 EXPORT_SYMBOL(__ua_limit);
239 #endif
240 
241 const char *__cpu_family[NR_CPUS];
242 const char *__cpu_full_name[NR_CPUS];
243 const char *__elf_platform;
244 
cpu_report(void)245 static void cpu_report(void)
246 {
247 	struct cpuinfo_loongarch *c = &current_cpu_data;
248 
249 	pr_info("CPU%d revision is: %08x (%s)\n",
250 		smp_processor_id(), c->processor_id, cpu_family_string());
251 	if (c->options & LOONGARCH_CPU_FPU)
252 		pr_info("FPU%d revision is: %08x\n", smp_processor_id(), c->fpu_vers);
253 }
254 
cpu_probe(void)255 void cpu_probe(void)
256 {
257 	unsigned int cpu = smp_processor_id();
258 	struct cpuinfo_loongarch *c = &current_cpu_data;
259 
260 	/*
261 	 * Set a default ELF platform, cpu probe may later
262 	 * overwrite it with a more precise value
263 	 */
264 	set_elf_platform(cpu, "loongarch");
265 
266 	c->cputype	= CPU_UNKNOWN;
267 	c->processor_id = read_cpucfg(LOONGARCH_CPUCFG0);
268 	c->fpu_vers     = (read_cpucfg(LOONGARCH_CPUCFG2) & CPUCFG2_FPVERS) >> 3;
269 
270 	c->fpu_csr0	= FPU_CSR_RN;
271 	c->fpu_mask	= FPU_CSR_RSVD;
272 
273 	cpu_probe_common(c);
274 
275 	per_cpu_trap_init(cpu);
276 
277 	switch (c->processor_id & PRID_COMP_MASK) {
278 	case PRID_COMP_LOONGSON:
279 		cpu_probe_loongson(c, cpu);
280 		break;
281 	}
282 
283 	BUG_ON(!__cpu_family[cpu]);
284 	BUG_ON(c->cputype == CPU_UNKNOWN);
285 
286 	cpu_probe_addrbits(c);
287 
288 #ifdef CONFIG_64BIT
289 	if (cpu == 0)
290 		__ua_limit = ~((1ull << cpu_vabits) - 1);
291 #endif
292 
293 	cpu_report();
294 }
295