1 /*
2 * linux/arch/arm/common/vic.c
3 *
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22 #include <linux/export.h>
23 #include <linux/init.h>
24 #include <linux/list.h>
25 #include <linux/io.h>
26 #include <linux/irqdomain.h>
27 #include <linux/of.h>
28 #include <linux/of_address.h>
29 #include <linux/of_irq.h>
30 #include <linux/syscore_ops.h>
31 #include <linux/device.h>
32 #include <linux/amba/bus.h>
33
34 #include <asm/exception.h>
35 #include <asm/mach/irq.h>
36 #include <asm/hardware/vic.h>
37
38 /**
39 * struct vic_device - VIC PM device
40 * @irq: The IRQ number for the base of the VIC.
41 * @base: The register base for the VIC.
42 * @resume_sources: A bitmask of interrupts for resume.
43 * @resume_irqs: The IRQs enabled for resume.
44 * @int_select: Save for VIC_INT_SELECT.
45 * @int_enable: Save for VIC_INT_ENABLE.
46 * @soft_int: Save for VIC_INT_SOFT.
47 * @protect: Save for VIC_PROTECT.
48 * @domain: The IRQ domain for the VIC.
49 */
50 struct vic_device {
51 void __iomem *base;
52 int irq;
53 u32 resume_sources;
54 u32 resume_irqs;
55 u32 int_select;
56 u32 int_enable;
57 u32 soft_int;
58 u32 protect;
59 struct irq_domain *domain;
60 };
61
62 /* we cannot allocate memory when VICs are initially registered */
63 static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];
64
65 static int vic_id;
66
67 /**
68 * vic_init2 - common initialisation code
69 * @base: Base of the VIC.
70 *
71 * Common initialisation code for registration
72 * and resume.
73 */
vic_init2(void __iomem * base)74 static void vic_init2(void __iomem *base)
75 {
76 int i;
77
78 for (i = 0; i < 16; i++) {
79 void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
80 writel(VIC_VECT_CNTL_ENABLE | i, reg);
81 }
82
83 writel(32, base + VIC_PL190_DEF_VECT_ADDR);
84 }
85
86 #ifdef CONFIG_PM
resume_one_vic(struct vic_device * vic)87 static void resume_one_vic(struct vic_device *vic)
88 {
89 void __iomem *base = vic->base;
90
91 printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base);
92
93 /* re-initialise static settings */
94 vic_init2(base);
95
96 writel(vic->int_select, base + VIC_INT_SELECT);
97 writel(vic->protect, base + VIC_PROTECT);
98
99 /* set the enabled ints and then clear the non-enabled */
100 writel(vic->int_enable, base + VIC_INT_ENABLE);
101 writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR);
102
103 /* and the same for the soft-int register */
104
105 writel(vic->soft_int, base + VIC_INT_SOFT);
106 writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR);
107 }
108
vic_resume(void)109 static void vic_resume(void)
110 {
111 int id;
112
113 for (id = vic_id - 1; id >= 0; id--)
114 resume_one_vic(vic_devices + id);
115 }
116
suspend_one_vic(struct vic_device * vic)117 static void suspend_one_vic(struct vic_device *vic)
118 {
119 void __iomem *base = vic->base;
120
121 printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base);
122
123 vic->int_select = readl(base + VIC_INT_SELECT);
124 vic->int_enable = readl(base + VIC_INT_ENABLE);
125 vic->soft_int = readl(base + VIC_INT_SOFT);
126 vic->protect = readl(base + VIC_PROTECT);
127
128 /* set the interrupts (if any) that are used for
129 * resuming the system */
130
131 writel(vic->resume_irqs, base + VIC_INT_ENABLE);
132 writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR);
133 }
134
vic_suspend(void)135 static int vic_suspend(void)
136 {
137 int id;
138
139 for (id = 0; id < vic_id; id++)
140 suspend_one_vic(vic_devices + id);
141
142 return 0;
143 }
144
145 struct syscore_ops vic_syscore_ops = {
146 .suspend = vic_suspend,
147 .resume = vic_resume,
148 };
149
150 /**
151 * vic_pm_init - initicall to register VIC pm
152 *
153 * This is called via late_initcall() to register
154 * the resources for the VICs due to the early
155 * nature of the VIC's registration.
156 */
vic_pm_init(void)157 static int __init vic_pm_init(void)
158 {
159 if (vic_id > 0)
160 register_syscore_ops(&vic_syscore_ops);
161
162 return 0;
163 }
164 late_initcall(vic_pm_init);
165 #endif /* CONFIG_PM */
166
167 /**
168 * vic_register() - Register a VIC.
169 * @base: The base address of the VIC.
170 * @irq: The base IRQ for the VIC.
171 * @resume_sources: bitmask of interrupts allowed for resume sources.
172 * @node: The device tree node associated with the VIC.
173 *
174 * Register the VIC with the system device tree so that it can be notified
175 * of suspend and resume requests and ensure that the correct actions are
176 * taken to re-instate the settings on resume.
177 *
178 * This also configures the IRQ domain for the VIC.
179 */
vic_register(void __iomem * base,unsigned int irq,u32 resume_sources,struct device_node * node)180 static void __init vic_register(void __iomem *base, unsigned int irq,
181 u32 resume_sources, struct device_node *node)
182 {
183 struct vic_device *v;
184
185 if (vic_id >= ARRAY_SIZE(vic_devices)) {
186 printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
187 return;
188 }
189
190 v = &vic_devices[vic_id];
191 v->base = base;
192 v->resume_sources = resume_sources;
193 v->irq = irq;
194 vic_id++;
195 v->domain = irq_domain_add_legacy(node, 32, irq, 0,
196 &irq_domain_simple_ops, v);
197 }
198
vic_ack_irq(struct irq_data * d)199 static void vic_ack_irq(struct irq_data *d)
200 {
201 void __iomem *base = irq_data_get_irq_chip_data(d);
202 unsigned int irq = d->hwirq;
203 writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
204 /* moreover, clear the soft-triggered, in case it was the reason */
205 writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
206 }
207
vic_mask_irq(struct irq_data * d)208 static void vic_mask_irq(struct irq_data *d)
209 {
210 void __iomem *base = irq_data_get_irq_chip_data(d);
211 unsigned int irq = d->hwirq;
212 writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
213 }
214
vic_unmask_irq(struct irq_data * d)215 static void vic_unmask_irq(struct irq_data *d)
216 {
217 void __iomem *base = irq_data_get_irq_chip_data(d);
218 unsigned int irq = d->hwirq;
219 writel(1 << irq, base + VIC_INT_ENABLE);
220 }
221
222 #if defined(CONFIG_PM)
vic_from_irq(unsigned int irq)223 static struct vic_device *vic_from_irq(unsigned int irq)
224 {
225 struct vic_device *v = vic_devices;
226 unsigned int base_irq = irq & ~31;
227 int id;
228
229 for (id = 0; id < vic_id; id++, v++) {
230 if (v->irq == base_irq)
231 return v;
232 }
233
234 return NULL;
235 }
236
vic_set_wake(struct irq_data * d,unsigned int on)237 static int vic_set_wake(struct irq_data *d, unsigned int on)
238 {
239 struct vic_device *v = vic_from_irq(d->irq);
240 unsigned int off = d->hwirq;
241 u32 bit = 1 << off;
242
243 if (!v)
244 return -EINVAL;
245
246 if (!(bit & v->resume_sources))
247 return -EINVAL;
248
249 if (on)
250 v->resume_irqs |= bit;
251 else
252 v->resume_irqs &= ~bit;
253
254 return 0;
255 }
256 #else
257 #define vic_set_wake NULL
258 #endif /* CONFIG_PM */
259
260 static struct irq_chip vic_chip = {
261 .name = "VIC",
262 .irq_ack = vic_ack_irq,
263 .irq_mask = vic_mask_irq,
264 .irq_unmask = vic_unmask_irq,
265 .irq_set_wake = vic_set_wake,
266 };
267
vic_disable(void __iomem * base)268 static void __init vic_disable(void __iomem *base)
269 {
270 writel(0, base + VIC_INT_SELECT);
271 writel(0, base + VIC_INT_ENABLE);
272 writel(~0, base + VIC_INT_ENABLE_CLEAR);
273 writel(0, base + VIC_ITCR);
274 writel(~0, base + VIC_INT_SOFT_CLEAR);
275 }
276
vic_clear_interrupts(void __iomem * base)277 static void __init vic_clear_interrupts(void __iomem *base)
278 {
279 unsigned int i;
280
281 writel(0, base + VIC_PL190_VECT_ADDR);
282 for (i = 0; i < 19; i++) {
283 unsigned int value;
284
285 value = readl(base + VIC_PL190_VECT_ADDR);
286 writel(value, base + VIC_PL190_VECT_ADDR);
287 }
288 }
289
vic_set_irq_sources(void __iomem * base,unsigned int irq_start,u32 vic_sources)290 static void __init vic_set_irq_sources(void __iomem *base,
291 unsigned int irq_start, u32 vic_sources)
292 {
293 unsigned int i;
294
295 for (i = 0; i < 32; i++) {
296 if (vic_sources & (1 << i)) {
297 unsigned int irq = irq_start + i;
298
299 irq_set_chip_and_handler(irq, &vic_chip,
300 handle_level_irq);
301 irq_set_chip_data(irq, base);
302 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
303 }
304 }
305 }
306
307 /*
308 * The PL190 cell from ARM has been modified by ST to handle 64 interrupts.
309 * The original cell has 32 interrupts, while the modified one has 64,
310 * replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case
311 * the probe function is called twice, with base set to offset 000
312 * and 020 within the page. We call this "second block".
313 */
vic_init_st(void __iomem * base,unsigned int irq_start,u32 vic_sources,struct device_node * node)314 static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
315 u32 vic_sources, struct device_node *node)
316 {
317 unsigned int i;
318 int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0;
319
320 /* Disable all interrupts initially. */
321 vic_disable(base);
322
323 /*
324 * Make sure we clear all existing interrupts. The vector registers
325 * in this cell are after the second block of general registers,
326 * so we can address them using standard offsets, but only from
327 * the second base address, which is 0x20 in the page
328 */
329 if (vic_2nd_block) {
330 vic_clear_interrupts(base);
331
332 /* ST has 16 vectors as well, but we don't enable them by now */
333 for (i = 0; i < 16; i++) {
334 void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
335 writel(0, reg);
336 }
337
338 writel(32, base + VIC_PL190_DEF_VECT_ADDR);
339 }
340
341 vic_set_irq_sources(base, irq_start, vic_sources);
342 vic_register(base, irq_start, 0, node);
343 }
344
__vic_init(void __iomem * base,unsigned int irq_start,u32 vic_sources,u32 resume_sources,struct device_node * node)345 void __init __vic_init(void __iomem *base, unsigned int irq_start,
346 u32 vic_sources, u32 resume_sources,
347 struct device_node *node)
348 {
349 unsigned int i;
350 u32 cellid = 0;
351 enum amba_vendor vendor;
352
353 /* Identify which VIC cell this one is, by reading the ID */
354 for (i = 0; i < 4; i++) {
355 void __iomem *addr;
356 addr = (void __iomem *)((u32)base & PAGE_MASK) + 0xfe0 + (i * 4);
357 cellid |= (readl(addr) & 0xff) << (8 * i);
358 }
359 vendor = (cellid >> 12) & 0xff;
360 printk(KERN_INFO "VIC @%p: id 0x%08x, vendor 0x%02x\n",
361 base, cellid, vendor);
362
363 switch(vendor) {
364 case AMBA_VENDOR_ST:
365 vic_init_st(base, irq_start, vic_sources, node);
366 return;
367 default:
368 printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n");
369 /* fall through */
370 case AMBA_VENDOR_ARM:
371 break;
372 }
373
374 /* Disable all interrupts initially. */
375 vic_disable(base);
376
377 /* Make sure we clear all existing interrupts */
378 vic_clear_interrupts(base);
379
380 vic_init2(base);
381
382 vic_set_irq_sources(base, irq_start, vic_sources);
383
384 vic_register(base, irq_start, resume_sources, node);
385 }
386
387 /**
388 * vic_init() - initialise a vectored interrupt controller
389 * @base: iomem base address
390 * @irq_start: starting interrupt number, must be muliple of 32
391 * @vic_sources: bitmask of interrupt sources to allow
392 * @resume_sources: bitmask of interrupt sources to allow for resume
393 */
vic_init(void __iomem * base,unsigned int irq_start,u32 vic_sources,u32 resume_sources)394 void __init vic_init(void __iomem *base, unsigned int irq_start,
395 u32 vic_sources, u32 resume_sources)
396 {
397 __vic_init(base, irq_start, vic_sources, resume_sources, NULL);
398 }
399
400 #ifdef CONFIG_OF
vic_of_init(struct device_node * node,struct device_node * parent)401 int __init vic_of_init(struct device_node *node, struct device_node *parent)
402 {
403 void __iomem *regs;
404 int irq_base;
405
406 if (WARN(parent, "non-root VICs are not supported"))
407 return -EINVAL;
408
409 regs = of_iomap(node, 0);
410 if (WARN_ON(!regs))
411 return -EIO;
412
413 irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
414 if (WARN_ON(irq_base < 0))
415 goto out_unmap;
416
417 __vic_init(regs, irq_base, ~0, ~0, node);
418
419 return 0;
420
421 out_unmap:
422 iounmap(regs);
423
424 return -EIO;
425 }
426 #endif /* CONFIG OF */
427
428 /*
429 * Handle each interrupt in a single VIC. Returns non-zero if we've
430 * handled at least one interrupt. This reads the status register
431 * before handling each interrupt, which is necessary given that
432 * handle_IRQ may briefly re-enable interrupts for soft IRQ handling.
433 */
handle_one_vic(struct vic_device * vic,struct pt_regs * regs)434 static int handle_one_vic(struct vic_device *vic, struct pt_regs *regs)
435 {
436 u32 stat, irq;
437 int handled = 0;
438
439 while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) {
440 irq = ffs(stat) - 1;
441 handle_IRQ(irq_find_mapping(vic->domain, irq), regs);
442 handled = 1;
443 }
444
445 return handled;
446 }
447
448 /*
449 * Keep iterating over all registered VIC's until there are no pending
450 * interrupts.
451 */
vic_handle_irq(struct pt_regs * regs)452 asmlinkage void __exception_irq_entry vic_handle_irq(struct pt_regs *regs)
453 {
454 int i, handled;
455
456 do {
457 for (i = 0, handled = 0; i < vic_id; ++i)
458 handled |= handle_one_vic(&vic_devices[i], regs);
459 } while (handled);
460 }
461