1 /*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21 #include <linux/via-core.h>
22 #include <linux/via_i2c.h>
23 #include "global.h"
24
25 static void tmds_register_write(int index, u8 data);
26 static int tmds_register_read(int index);
27 static int tmds_register_read_bytes(int index, u8 *buff, int buff_len);
28 static void __devinit dvi_get_panel_size_from_DDCv1(
29 struct tmds_chip_information *tmds_chip,
30 struct tmds_setting_information *tmds_setting);
31 static void __devinit dvi_get_panel_size_from_DDCv2(
32 struct tmds_chip_information *tmds_chip,
33 struct tmds_setting_information *tmds_setting);
34 static int viafb_dvi_query_EDID(void);
35
check_tmds_chip(int device_id_subaddr,int device_id)36 static int check_tmds_chip(int device_id_subaddr, int device_id)
37 {
38 if (tmds_register_read(device_id_subaddr) == device_id)
39 return OK;
40 else
41 return FAIL;
42 }
43
viafb_init_dvi_size(struct tmds_chip_information * tmds_chip,struct tmds_setting_information * tmds_setting)44 void __devinit viafb_init_dvi_size(struct tmds_chip_information *tmds_chip,
45 struct tmds_setting_information *tmds_setting)
46 {
47 DEBUG_MSG(KERN_INFO "viafb_init_dvi_size()\n");
48
49 viafb_dvi_sense();
50 switch (viafb_dvi_query_EDID()) {
51 case 1:
52 dvi_get_panel_size_from_DDCv1(tmds_chip, tmds_setting);
53 break;
54 case 2:
55 dvi_get_panel_size_from_DDCv2(tmds_chip, tmds_setting);
56 break;
57 default:
58 printk(KERN_WARNING "viafb_init_dvi_size: DVI panel size undetected!\n");
59 break;
60 }
61
62 return;
63 }
64
viafb_tmds_trasmitter_identify(void)65 int __devinit viafb_tmds_trasmitter_identify(void)
66 {
67 unsigned char sr2a = 0, sr1e = 0, sr3e = 0;
68
69 /* Turn on ouputting pad */
70 switch (viaparinfo->chip_info->gfx_chip_name) {
71 case UNICHROME_K8M890:
72 /*=* DFP Low Pad on *=*/
73 sr2a = viafb_read_reg(VIASR, SR2A);
74 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
75 break;
76
77 case UNICHROME_P4M900:
78 case UNICHROME_P4M890:
79 /* DFP Low Pad on */
80 sr2a = viafb_read_reg(VIASR, SR2A);
81 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
82 /* DVP0 Pad on */
83 sr1e = viafb_read_reg(VIASR, SR1E);
84 viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT6 + BIT7);
85 break;
86
87 default:
88 /* DVP0/DVP1 Pad on */
89 sr1e = viafb_read_reg(VIASR, SR1E);
90 viafb_write_reg_mask(SR1E, VIASR, 0xF0, BIT4 +
91 BIT5 + BIT6 + BIT7);
92 /* SR3E[1]Multi-function selection:
93 0 = Emulate I2C and DDC bus by GPIO2/3/4. */
94 sr3e = viafb_read_reg(VIASR, SR3E);
95 viafb_write_reg_mask(SR3E, VIASR, 0x0, BIT5);
96 break;
97 }
98
99 /* Check for VT1632: */
100 viaparinfo->chip_info->tmds_chip_info.tmds_chip_name = VT1632_TMDS;
101 viaparinfo->chip_info->
102 tmds_chip_info.tmds_chip_slave_addr = VT1632_TMDS_I2C_ADDR;
103 viaparinfo->chip_info->tmds_chip_info.i2c_port = VIA_PORT_31;
104 if (check_tmds_chip(VT1632_DEVICE_ID_REG, VT1632_DEVICE_ID) != FAIL) {
105 /*
106 * Currently only support 12bits,dual edge,add 24bits mode later
107 */
108 tmds_register_write(0x08, 0x3b);
109
110 DEBUG_MSG(KERN_INFO "\n VT1632 TMDS ! \n");
111 DEBUG_MSG(KERN_INFO "\n %2d",
112 viaparinfo->chip_info->tmds_chip_info.tmds_chip_name);
113 DEBUG_MSG(KERN_INFO "\n %2d",
114 viaparinfo->chip_info->tmds_chip_info.i2c_port);
115 return OK;
116 } else {
117 viaparinfo->chip_info->tmds_chip_info.i2c_port = VIA_PORT_2C;
118 if (check_tmds_chip(VT1632_DEVICE_ID_REG, VT1632_DEVICE_ID)
119 != FAIL) {
120 tmds_register_write(0x08, 0x3b);
121 DEBUG_MSG(KERN_INFO "\n VT1632 TMDS ! \n");
122 DEBUG_MSG(KERN_INFO "\n %2d",
123 viaparinfo->chip_info->
124 tmds_chip_info.tmds_chip_name);
125 DEBUG_MSG(KERN_INFO "\n %2d",
126 viaparinfo->chip_info->
127 tmds_chip_info.i2c_port);
128 return OK;
129 }
130 }
131
132 viaparinfo->chip_info->tmds_chip_info.tmds_chip_name = INTEGRATED_TMDS;
133
134 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) &&
135 ((viafb_display_hardware_layout == HW_LAYOUT_DVI_ONLY) ||
136 (viafb_display_hardware_layout == HW_LAYOUT_LCD_DVI))) {
137 DEBUG_MSG(KERN_INFO "\n Integrated TMDS ! \n");
138 return OK;
139 }
140
141 switch (viaparinfo->chip_info->gfx_chip_name) {
142 case UNICHROME_K8M890:
143 viafb_write_reg(SR2A, VIASR, sr2a);
144 break;
145
146 case UNICHROME_P4M900:
147 case UNICHROME_P4M890:
148 viafb_write_reg(SR2A, VIASR, sr2a);
149 viafb_write_reg(SR1E, VIASR, sr1e);
150 break;
151
152 default:
153 viafb_write_reg(SR1E, VIASR, sr1e);
154 viafb_write_reg(SR3E, VIASR, sr3e);
155 break;
156 }
157
158 viaparinfo->chip_info->
159 tmds_chip_info.tmds_chip_name = NON_TMDS_TRANSMITTER;
160 viaparinfo->chip_info->tmds_chip_info.
161 tmds_chip_slave_addr = VT1632_TMDS_I2C_ADDR;
162 return FAIL;
163 }
164
tmds_register_write(int index,u8 data)165 static void tmds_register_write(int index, u8 data)
166 {
167 viafb_i2c_writebyte(viaparinfo->chip_info->tmds_chip_info.i2c_port,
168 viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr,
169 index, data);
170 }
171
tmds_register_read(int index)172 static int tmds_register_read(int index)
173 {
174 u8 data;
175
176 viafb_i2c_readbyte(viaparinfo->chip_info->tmds_chip_info.i2c_port,
177 (u8) viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr,
178 (u8) index, &data);
179 return data;
180 }
181
tmds_register_read_bytes(int index,u8 * buff,int buff_len)182 static int tmds_register_read_bytes(int index, u8 *buff, int buff_len)
183 {
184 viafb_i2c_readbytes(viaparinfo->chip_info->tmds_chip_info.i2c_port,
185 (u8) viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr,
186 (u8) index, buff, buff_len);
187 return 0;
188 }
189
190 /* DVI Set Mode */
viafb_dvi_set_mode(struct VideoModeTable * mode,int mode_bpp,int set_iga)191 void viafb_dvi_set_mode(struct VideoModeTable *mode, int mode_bpp,
192 int set_iga)
193 {
194 struct VideoModeTable *rb_mode;
195 struct crt_mode_table *pDviTiming;
196 unsigned long desirePixelClock, maxPixelClock;
197 pDviTiming = mode->crtc;
198 desirePixelClock = pDviTiming->refresh_rate
199 * pDviTiming->crtc.hor_total * pDviTiming->crtc.ver_total
200 / 1000000;
201 maxPixelClock = (unsigned long)viaparinfo->
202 tmds_setting_info->max_pixel_clock;
203
204 DEBUG_MSG(KERN_INFO "\nDVI_set_mode!!\n");
205
206 if ((maxPixelClock != 0) && (desirePixelClock > maxPixelClock)) {
207 rb_mode = viafb_get_rb_mode(mode->crtc[0].crtc.hor_addr,
208 mode->crtc[0].crtc.ver_addr);
209 if (rb_mode) {
210 mode = rb_mode;
211 pDviTiming = rb_mode->crtc;
212 }
213 }
214 viafb_fill_crtc_timing(pDviTiming, mode, mode_bpp / 8, set_iga);
215 }
216
217 /* Sense DVI Connector */
viafb_dvi_sense(void)218 int viafb_dvi_sense(void)
219 {
220 u8 RegSR1E = 0, RegSR3E = 0, RegCR6B = 0, RegCR91 = 0,
221 RegCR93 = 0, RegCR9B = 0, data;
222 int ret = false;
223
224 DEBUG_MSG(KERN_INFO "viafb_dvi_sense!!\n");
225
226 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
227 /* DI1 Pad on */
228 RegSR1E = viafb_read_reg(VIASR, SR1E);
229 viafb_write_reg(SR1E, VIASR, RegSR1E | 0x30);
230
231 /* CR6B[0]VCK Input Selection: 1 = External clock. */
232 RegCR6B = viafb_read_reg(VIACR, CR6B);
233 viafb_write_reg(CR6B, VIACR, RegCR6B | 0x08);
234
235 /* CR91[4] VDD On [3] Data On [2] VEE On [1] Back Light Off
236 [0] Software Control Power Sequence */
237 RegCR91 = viafb_read_reg(VIACR, CR91);
238 viafb_write_reg(CR91, VIACR, 0x1D);
239
240 /* CR93[7] DI1 Data Source Selection: 1 = DSP2.
241 CR93[5] DI1 Clock Source: 1 = internal.
242 CR93[4] DI1 Clock Polarity.
243 CR93[3:1] DI1 Clock Adjust. CR93[0] DI1 enable */
244 RegCR93 = viafb_read_reg(VIACR, CR93);
245 viafb_write_reg(CR93, VIACR, 0x01);
246 } else {
247 /* DVP0/DVP1 Pad on */
248 RegSR1E = viafb_read_reg(VIASR, SR1E);
249 viafb_write_reg(SR1E, VIASR, RegSR1E | 0xF0);
250
251 /* SR3E[1]Multi-function selection:
252 0 = Emulate I2C and DDC bus by GPIO2/3/4. */
253 RegSR3E = viafb_read_reg(VIASR, SR3E);
254 viafb_write_reg(SR3E, VIASR, RegSR3E & (~0x20));
255
256 /* CR91[4] VDD On [3] Data On [2] VEE On [1] Back Light Off
257 [0] Software Control Power Sequence */
258 RegCR91 = viafb_read_reg(VIACR, CR91);
259 viafb_write_reg(CR91, VIACR, 0x1D);
260
261 /*CR9B[4] DVP1 Data Source Selection: 1 = From secondary
262 display.CR9B[2:0] DVP1 Clock Adjust */
263 RegCR9B = viafb_read_reg(VIACR, CR9B);
264 viafb_write_reg(CR9B, VIACR, 0x01);
265 }
266
267 data = (u8) tmds_register_read(0x09);
268 if (data & 0x04)
269 ret = true;
270
271 if (ret == false) {
272 if (viafb_dvi_query_EDID())
273 ret = true;
274 }
275
276 /* Restore status */
277 viafb_write_reg(SR1E, VIASR, RegSR1E);
278 viafb_write_reg(CR91, VIACR, RegCR91);
279 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
280 viafb_write_reg(CR6B, VIACR, RegCR6B);
281 viafb_write_reg(CR93, VIACR, RegCR93);
282 } else {
283 viafb_write_reg(SR3E, VIASR, RegSR3E);
284 viafb_write_reg(CR9B, VIACR, RegCR9B);
285 }
286
287 return ret;
288 }
289
290 /* Query Flat Panel's EDID Table Version Through DVI Connector */
viafb_dvi_query_EDID(void)291 static int viafb_dvi_query_EDID(void)
292 {
293 u8 data0, data1;
294 int restore;
295
296 DEBUG_MSG(KERN_INFO "viafb_dvi_query_EDID!!\n");
297
298 restore = viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr;
299 viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr = 0xA0;
300
301 data0 = (u8) tmds_register_read(0x00);
302 data1 = (u8) tmds_register_read(0x01);
303 if ((data0 == 0) && (data1 == 0xFF)) {
304 viaparinfo->chip_info->
305 tmds_chip_info.tmds_chip_slave_addr = restore;
306 return EDID_VERSION_1; /* Found EDID1 Table */
307 }
308
309 data0 = (u8) tmds_register_read(0x00);
310 viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr = restore;
311 if (data0 == 0x20)
312 return EDID_VERSION_2; /* Found EDID2 Table */
313 else
314 return false;
315 }
316
317 /* Get Panel Size Using EDID1 Table */
dvi_get_panel_size_from_DDCv1(struct tmds_chip_information * tmds_chip,struct tmds_setting_information * tmds_setting)318 static void __devinit dvi_get_panel_size_from_DDCv1(
319 struct tmds_chip_information *tmds_chip,
320 struct tmds_setting_information *tmds_setting)
321 {
322 int i, max_h = 0, tmp, restore;
323 unsigned char rData;
324 unsigned char EDID_DATA[18];
325
326 DEBUG_MSG(KERN_INFO "\n dvi_get_panel_size_from_DDCv1 \n");
327
328 restore = tmds_chip->tmds_chip_slave_addr;
329 tmds_chip->tmds_chip_slave_addr = 0xA0;
330
331 rData = tmds_register_read(0x23);
332 if (rData & 0x3C)
333 max_h = 640;
334 if (rData & 0xC0)
335 max_h = 720;
336 if (rData & 0x03)
337 max_h = 800;
338
339 rData = tmds_register_read(0x24);
340 if (rData & 0xC0)
341 max_h = 800;
342 if (rData & 0x1E)
343 max_h = 1024;
344 if (rData & 0x01)
345 max_h = 1280;
346
347 for (i = 0x25; i < 0x6D; i++) {
348 switch (i) {
349 case 0x26:
350 case 0x28:
351 case 0x2A:
352 case 0x2C:
353 case 0x2E:
354 case 0x30:
355 case 0x32:
356 case 0x34:
357 rData = tmds_register_read(i);
358 if (rData == 1)
359 break;
360 /* data = (data + 31) * 8 */
361 tmp = (rData + 31) << 3;
362 if (tmp > max_h)
363 max_h = tmp;
364 break;
365
366 case 0x36:
367 case 0x48:
368 case 0x5A:
369 case 0x6C:
370 tmds_register_read_bytes(i, EDID_DATA, 10);
371 if (!(EDID_DATA[0] || EDID_DATA[1])) {
372 /* The first two byte must be zero. */
373 if (EDID_DATA[3] == 0xFD) {
374 /* To get max pixel clock. */
375 tmds_setting->max_pixel_clock =
376 EDID_DATA[9] * 10;
377 }
378 }
379 break;
380
381 default:
382 break;
383 }
384 }
385
386 tmds_setting->max_hres = max_h;
387 switch (max_h) {
388 case 640:
389 tmds_setting->max_vres = 480;
390 break;
391 case 800:
392 tmds_setting->max_vres = 600;
393 break;
394 case 1024:
395 tmds_setting->max_vres = 768;
396 break;
397 case 1280:
398 tmds_setting->max_vres = 1024;
399 break;
400 case 1400:
401 tmds_setting->max_vres = 1050;
402 break;
403 case 1440:
404 tmds_setting->max_vres = 1050;
405 break;
406 case 1600:
407 tmds_setting->max_vres = 1200;
408 break;
409 case 1920:
410 tmds_setting->max_vres = 1080;
411 break;
412 default:
413 DEBUG_MSG(KERN_INFO "Unknown panel size max resolution = %d ! "
414 "set default panel size.\n", max_h);
415 break;
416 }
417
418 DEBUG_MSG(KERN_INFO "DVI max pixelclock = %d\n",
419 tmds_setting->max_pixel_clock);
420 tmds_chip->tmds_chip_slave_addr = restore;
421 }
422
423 /* Get Panel Size Using EDID2 Table */
dvi_get_panel_size_from_DDCv2(struct tmds_chip_information * tmds_chip,struct tmds_setting_information * tmds_setting)424 static void __devinit dvi_get_panel_size_from_DDCv2(
425 struct tmds_chip_information *tmds_chip,
426 struct tmds_setting_information *tmds_setting)
427 {
428 int restore;
429 unsigned char R_Buffer[2];
430
431 DEBUG_MSG(KERN_INFO "\n dvi_get_panel_size_from_DDCv2 \n");
432
433 restore = tmds_chip->tmds_chip_slave_addr;
434 tmds_chip->tmds_chip_slave_addr = 0xA2;
435
436 /* Horizontal: 0x76, 0x77 */
437 tmds_register_read_bytes(0x76, R_Buffer, 2);
438 tmds_setting->max_hres = R_Buffer[0] + (R_Buffer[1] << 8);
439
440 switch (tmds_setting->max_hres) {
441 case 640:
442 tmds_setting->max_vres = 480;
443 break;
444 case 800:
445 tmds_setting->max_vres = 600;
446 break;
447 case 1024:
448 tmds_setting->max_vres = 768;
449 break;
450 case 1280:
451 tmds_setting->max_vres = 1024;
452 break;
453 case 1400:
454 tmds_setting->max_vres = 1050;
455 break;
456 case 1440:
457 tmds_setting->max_vres = 1050;
458 break;
459 case 1600:
460 tmds_setting->max_vres = 1200;
461 break;
462 default:
463 DEBUG_MSG(KERN_INFO "Unknown panel size max resolution = %d! "
464 "set default panel size.\n", tmds_setting->max_hres);
465 break;
466 }
467
468 tmds_chip->tmds_chip_slave_addr = restore;
469 }
470
471 /* If Disable DVI, turn off pad */
viafb_dvi_disable(void)472 void viafb_dvi_disable(void)
473 {
474 if (viaparinfo->chip_info->
475 tmds_chip_info.output_interface == INTERFACE_TMDS)
476 /* Turn off TMDS power. */
477 viafb_write_reg(CRD2, VIACR,
478 viafb_read_reg(VIACR, CRD2) | 0x08);
479 }
480
dvi_patch_skew_dvp0(void)481 static void dvi_patch_skew_dvp0(void)
482 {
483 /* Reset data driving first: */
484 viafb_write_reg_mask(SR1B, VIASR, 0, BIT1);
485 viafb_write_reg_mask(SR2A, VIASR, 0, BIT4);
486
487 switch (viaparinfo->chip_info->gfx_chip_name) {
488 case UNICHROME_P4M890:
489 {
490 if ((viaparinfo->tmds_setting_info->h_active == 1600) &&
491 (viaparinfo->tmds_setting_info->v_active ==
492 1200))
493 viafb_write_reg_mask(CR96, VIACR, 0x03,
494 BIT0 + BIT1 + BIT2);
495 else
496 viafb_write_reg_mask(CR96, VIACR, 0x07,
497 BIT0 + BIT1 + BIT2);
498 break;
499 }
500
501 case UNICHROME_P4M900:
502 {
503 viafb_write_reg_mask(CR96, VIACR, 0x07,
504 BIT0 + BIT1 + BIT2 + BIT3);
505 viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1);
506 viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4);
507 break;
508 }
509
510 default:
511 {
512 break;
513 }
514 }
515 }
516
dvi_patch_skew_dvp_low(void)517 static void dvi_patch_skew_dvp_low(void)
518 {
519 switch (viaparinfo->chip_info->gfx_chip_name) {
520 case UNICHROME_K8M890:
521 {
522 viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1);
523 break;
524 }
525
526 case UNICHROME_P4M900:
527 {
528 viafb_write_reg_mask(CR99, VIACR, 0x08,
529 BIT0 + BIT1 + BIT2 + BIT3);
530 break;
531 }
532
533 case UNICHROME_P4M890:
534 {
535 viafb_write_reg_mask(CR99, VIACR, 0x0F,
536 BIT0 + BIT1 + BIT2 + BIT3);
537 break;
538 }
539
540 default:
541 {
542 break;
543 }
544 }
545 }
546
547 /* If Enable DVI, turn off pad */
viafb_dvi_enable(void)548 void viafb_dvi_enable(void)
549 {
550 u8 data;
551
552 switch (viaparinfo->chip_info->tmds_chip_info.output_interface) {
553 case INTERFACE_DVP0:
554 viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0);
555 viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 + BIT5);
556 dvi_patch_skew_dvp0();
557 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
558 tmds_register_write(0x88, 0x3b);
559 else
560 /*clear CR91[5] to direct on display period
561 in the secondary diplay path */
562 via_write_reg_mask(VIACR, 0x91, 0x00, 0x20);
563 break;
564
565 case INTERFACE_DVP1:
566 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
567 viafb_write_reg_mask(CR93, VIACR, 0x21, BIT0 + BIT5);
568
569 /*fix dvi cann't be enabled with MB VT5718C4 - Al Zhang */
570 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
571 tmds_register_write(0x88, 0x3b);
572 else
573 /*clear CR91[5] to direct on display period
574 in the secondary diplay path */
575 via_write_reg_mask(VIACR, 0x91, 0x00, 0x20);
576
577 /*fix DVI cannot enable on EPIA-M board */
578 if (viafb_platform_epia_dvi == 1) {
579 viafb_write_reg_mask(CR91, VIACR, 0x1f, 0x1f);
580 viafb_write_reg_mask(CR88, VIACR, 0x00, BIT6 + BIT0);
581 if (viafb_bus_width == 24) {
582 if (viafb_device_lcd_dualedge == 1)
583 data = 0x3F;
584 else
585 data = 0x37;
586 viafb_i2c_writebyte(viaparinfo->chip_info->
587 tmds_chip_info.i2c_port,
588 viaparinfo->chip_info->
589 tmds_chip_info.tmds_chip_slave_addr,
590 0x08, data);
591 }
592 }
593 break;
594
595 case INTERFACE_DFP_HIGH:
596 if (viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
597 via_write_reg_mask(VIACR, CR97, 0x03, 0x03);
598
599 via_write_reg_mask(VIACR, 0x91, 0x00, 0x20);
600 break;
601
602 case INTERFACE_DFP_LOW:
603 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
604 break;
605
606 dvi_patch_skew_dvp_low();
607 via_write_reg_mask(VIACR, 0x91, 0x00, 0x20);
608 break;
609
610 case INTERFACE_TMDS:
611 /* Turn on Display period in the panel path. */
612 viafb_write_reg_mask(CR91, VIACR, 0, BIT7);
613
614 /* Turn on TMDS power. */
615 viafb_write_reg_mask(CRD2, VIACR, 0, BIT3);
616 break;
617 }
618
619 if (viaparinfo->tmds_setting_info->iga_path == IGA2) {
620 /* Disable LCD Scaling */
621 viafb_write_reg_mask(CR79, VIACR, 0x00, BIT0);
622 }
623 }
624