1 /*
2 * $Id: quirks.c,v 1.5 1998/05/02 19:24:14 mj Exp $
3 *
4 * This file contains work-arounds for many known PCI hardware
5 * bugs. Devices present only on certain architectures (host
6 * bridges et cetera) should be handled in arch-specific code.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
10 * The bridge optimization stuff has been removed. If you really
11 * have a silly BIOS which is unable to set your host bridge right,
12 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
13 */
14
15 #include <linux/config.h>
16 #include <linux/types.h>
17 #include <linux/kernel.h>
18 #include <linux/pci.h>
19 #include <linux/init.h>
20 #include <linux/delay.h>
21
22 #undef DEBUG
23
24 /* Deal with broken BIOS'es that neglect to enable passive release,
25 which can cause problems in combination with the 82441FX/PPro MTRRs */
quirk_passive_release(struct pci_dev * dev)26 static void __init quirk_passive_release(struct pci_dev *dev)
27 {
28 struct pci_dev *d = NULL;
29 unsigned char dlc;
30
31 /* We have to make sure a particular bit is set in the PIIX3
32 ISA bridge, so we have to go out and find it. */
33 while ((d = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
34 pci_read_config_byte(d, 0x82, &dlc);
35 if (!(dlc & 1<<1)) {
36 printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", d->slot_name);
37 dlc |= 1<<1;
38 pci_write_config_byte(d, 0x82, dlc);
39 }
40 }
41 }
42
43 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
44 but VIA don't answer queries. If you happen to have good contacts at VIA
45 ask them for me please -- Alan
46
47 This appears to be BIOS not version dependent. So presumably there is a
48 chipset level fix */
49
50
51 int isa_dma_bridge_buggy; /* Exported */
52
quirk_isa_dma_hangs(struct pci_dev * dev)53 static void __init quirk_isa_dma_hangs(struct pci_dev *dev)
54 {
55 if (!isa_dma_bridge_buggy) {
56 isa_dma_bridge_buggy=1;
57 printk(KERN_INFO "Activating ISA DMA hang workarounds.\n");
58 }
59 }
60
61 int pci_pci_problems;
62
63 /*
64 * Chipsets where PCI->PCI transfers vanish or hang
65 */
66
quirk_nopcipci(struct pci_dev * dev)67 static void __init quirk_nopcipci(struct pci_dev *dev)
68 {
69 if((pci_pci_problems&PCIPCI_FAIL)==0)
70 {
71 printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n");
72 pci_pci_problems|=PCIPCI_FAIL;
73 }
74 }
75
76 /*
77 * Triton requires workarounds to be used by the drivers
78 */
79
quirk_triton(struct pci_dev * dev)80 static void __init quirk_triton(struct pci_dev *dev)
81 {
82 if((pci_pci_problems&PCIPCI_TRITON)==0)
83 {
84 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
85 pci_pci_problems|=PCIPCI_TRITON;
86 }
87 }
88
89 /*
90 * VIA Apollo KT133 needs PCI latency patch
91 * Made according to a windows driver based patch by George E. Breese
92 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
93 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on which
94 * Mr Breese based his work.
95 *
96 * Updated based on further information from the site and also on
97 * information provided by VIA
98 */
quirk_vialatency(struct pci_dev * dev)99 static void __init quirk_vialatency(struct pci_dev *dev)
100 {
101 struct pci_dev *p;
102 u8 rev;
103 u8 busarb;
104 /* Ok we have a potential problem chipset here. Now see if we have
105 a buggy southbridge */
106
107 p=pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
108 if(p!=NULL)
109 {
110 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
111 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
112 /* Check for buggy part revisions */
113 if (rev < 0x40 || rev > 0x42)
114 return;
115 }
116 else
117 {
118 p = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
119 if(p==NULL) /* No problem parts */
120 return;
121 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
122 /* Check for buggy part revisions */
123 if (rev < 0x10 || rev > 0x12)
124 return;
125 }
126
127 /*
128 * Ok we have the problem. Now set the PCI master grant to
129 * occur every master grant. The apparent bug is that under high
130 * PCI load (quite common in Linux of course) you can get data
131 * loss when the CPU is held off the bus for 3 bus master requests
132 * This happens to include the IDE controllers....
133 *
134 * VIA only apply this fix when an SB Live! is present but under
135 * both Linux and Windows this isnt enough, and we have seen
136 * corruption without SB Live! but with things like 3 UDMA IDE
137 * controllers. So we ignore that bit of the VIA recommendation..
138 */
139
140 pci_read_config_byte(dev, 0x76, &busarb);
141 /* Set bit 4 and bi 5 of byte 76 to 0x01
142 "Master priority rotation on every PCI master grant */
143 busarb &= ~(1<<5);
144 busarb |= (1<<4);
145 pci_write_config_byte(dev, 0x76, busarb);
146 printk(KERN_INFO "Applying VIA southbridge workaround.\n");
147 }
148
149 /*
150 * VIA Apollo VP3 needs ETBF on BT848/878
151 */
152
quirk_viaetbf(struct pci_dev * dev)153 static void __init quirk_viaetbf(struct pci_dev *dev)
154 {
155 if((pci_pci_problems&PCIPCI_VIAETBF)==0)
156 {
157 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
158 pci_pci_problems|=PCIPCI_VIAETBF;
159 }
160 }
quirk_vsfx(struct pci_dev * dev)161 static void __init quirk_vsfx(struct pci_dev *dev)
162 {
163 if((pci_pci_problems&PCIPCI_VSFX)==0)
164 {
165 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
166 pci_pci_problems|=PCIPCI_VSFX;
167 }
168 }
169
170 /*
171 * Ali Magik requires workarounds to be used by the drivers
172 * that DMA to AGP space. Latency must be set to 0xA and triton
173 * workaround applied too
174 * [Info kindly provided by ALi]
175 */
176
quirk_alimagik(struct pci_dev * dev)177 static void __init quirk_alimagik(struct pci_dev *dev)
178 {
179 if((pci_pci_problems&PCIPCI_ALIMAGIK)==0)
180 {
181 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
182 pci_pci_problems|=PCIPCI_ALIMAGIK|PCIPCI_TRITON;
183 }
184 }
185
186 /*
187 * Natoma has some interesting boundary conditions with Zoran stuff
188 * at least
189 */
190
quirk_natoma(struct pci_dev * dev)191 static void __init quirk_natoma(struct pci_dev *dev)
192 {
193 if((pci_pci_problems&PCIPCI_NATOMA)==0)
194 {
195 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
196 pci_pci_problems|=PCIPCI_NATOMA;
197 }
198 }
199
200 /*
201 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
202 * If it's needed, re-allocate the region.
203 */
204
quirk_s3_64M(struct pci_dev * dev)205 static void __init quirk_s3_64M(struct pci_dev *dev)
206 {
207 struct resource *r = &dev->resource[0];
208
209 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
210 r->start = 0;
211 r->end = 0x3ffffff;
212 }
213 }
214
quirk_io_region(struct pci_dev * dev,unsigned region,unsigned size,int nr)215 static void __init quirk_io_region(struct pci_dev *dev, unsigned region, unsigned size, int nr)
216 {
217 region &= ~(size-1);
218 if (region) {
219 struct resource *res = dev->resource + nr;
220
221 res->name = dev->name;
222 res->start = region;
223 res->end = region + size - 1;
224 res->flags = IORESOURCE_IO;
225 pci_claim_resource(dev, nr);
226 }
227 }
228
229 /*
230 * ATI Northbridge setups MCE the processor if you even
231 * read somewhere between 0x3b0->0x3bb or read 0x3d3
232 */
233
quirk_ati_exploding_mce(struct pci_dev * dev)234 static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
235 {
236 printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n");
237 request_region(0x3b0, 0x0C, "RadeonIGP");
238 request_region(0x3d3, 0x01, "RadeonIGP");
239 }
240
241 /*
242 * Let's make the southbridge information explicit instead
243 * of having to worry about people probing the ACPI areas,
244 * for example.. (Yes, it happens, and if you read the wrong
245 * ACPI register it will put the machine to sleep with no
246 * way of waking it up again. Bummer).
247 *
248 * ALI M7101: Two IO regions pointed to by words at
249 * 0xE0 (64 bytes of ACPI registers)
250 * 0xE2 (32 bytes of SMB registers)
251 */
quirk_ali7101_acpi(struct pci_dev * dev)252 static void __init quirk_ali7101_acpi(struct pci_dev *dev)
253 {
254 u16 region;
255
256 pci_read_config_word(dev, 0xE0, ®ion);
257 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES);
258 pci_read_config_word(dev, 0xE2, ®ion);
259 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1);
260 }
261
262 /*
263 * PIIX4 ACPI: Two IO regions pointed to by longwords at
264 * 0x40 (64 bytes of ACPI registers)
265 * 0x90 (32 bytes of SMB registers)
266 */
quirk_piix4_acpi(struct pci_dev * dev)267 static void __init quirk_piix4_acpi(struct pci_dev *dev)
268 {
269 u32 region;
270
271 pci_read_config_dword(dev, 0x40, ®ion);
272 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES);
273 pci_read_config_dword(dev, 0x90, ®ion);
274 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1);
275 }
276
277 /*
278 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
279 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
280 * 0x58 (64 bytes of GPIO I/O space)
281 */
quirk_ich4_lpc_acpi(struct pci_dev * dev)282 static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
283 {
284 u32 region;
285
286 pci_read_config_dword(dev, 0x40, ®ion);
287 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES);
288
289 pci_read_config_dword(dev, 0x58, ®ion);
290 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1);
291 }
292
293 /*
294 * VIA ACPI: One IO region pointed to by longword at
295 * 0x48 or 0x20 (256 bytes of ACPI registers)
296 */
quirk_vt82c586_acpi(struct pci_dev * dev)297 static void __init quirk_vt82c586_acpi(struct pci_dev *dev)
298 {
299 u8 rev;
300 u32 region;
301
302 pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
303 if (rev & 0x10) {
304 pci_read_config_dword(dev, 0x48, ®ion);
305 region &= PCI_BASE_ADDRESS_IO_MASK;
306 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES);
307 }
308 }
309
310 /*
311 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
312 * 0x48 (256 bytes of ACPI registers)
313 * 0x70 (128 bytes of hardware monitoring register)
314 * 0x90 (16 bytes of SMB registers)
315 */
quirk_vt82c686_acpi(struct pci_dev * dev)316 static void __init quirk_vt82c686_acpi(struct pci_dev *dev)
317 {
318 u16 hm;
319 u32 smb;
320
321 quirk_vt82c586_acpi(dev);
322
323 pci_read_config_word(dev, 0x70, &hm);
324 hm &= PCI_BASE_ADDRESS_IO_MASK;
325 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1);
326
327 pci_read_config_dword(dev, 0x90, &smb);
328 smb &= PCI_BASE_ADDRESS_IO_MASK;
329 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2);
330 }
331
332
333 #ifdef CONFIG_X86_IO_APIC
334 extern int nr_ioapics;
335
336 /*
337 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
338 * devices to the external APIC.
339 *
340 * TODO: When we have device-specific interrupt routers,
341 * this code will go away from quirks.
342 */
quirk_via_ioapic(struct pci_dev * dev)343 static void __init quirk_via_ioapic(struct pci_dev *dev)
344 {
345 u8 tmp;
346
347 if (nr_ioapics < 1)
348 tmp = 0; /* nothing routed to external APIC */
349 else
350 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
351
352 printk(KERN_INFO "PCI: %sbling Via external APIC routing\n",
353 tmp == 0 ? "Disa" : "Ena");
354
355 /* Offset 0x58: External APIC IRQ output control */
356 pci_write_config_byte (dev, 0x58, tmp);
357 }
358
359 #endif /* CONFIG_X86_IO_APIC */
360
361
362 /*
363 * Via 686A/B: The PCI_INTERRUPT_LINE register for the on-chip
364 * devices, USB0/1, AC97, MC97, and ACPI, has an unusual feature:
365 * when written, it makes an internal connection to the PIC.
366 * For these devices, this register is defined to be 4 bits wide.
367 * Normally this is fine. However for IO-APIC motherboards, or
368 * non-x86 architectures (yes Via exists on PPC among other places),
369 * we must mask the PCI_INTERRUPT_LINE value versus 0xf to get
370 * interrupts delivered properly.
371 */
372
373 /*
374 * FIXME: it is questionable that quirk_via_acpi
375 * is needed. It shows up as an ISA bridge, and does not
376 * support the PCI_INTERRUPT_LINE register at all. Therefore
377 * it seems like setting the pci_dev's 'irq' to the
378 * value of the ACPI SCI interrupt is only done for convenience.
379 * -jgarzik
380 */
quirk_via_acpi(struct pci_dev * d)381 static void __init quirk_via_acpi(struct pci_dev *d)
382 {
383 /*
384 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
385 */
386 u8 irq;
387 pci_read_config_byte(d, 0x42, &irq);
388 irq &= 0xf;
389 if (irq && (irq != 2))
390 d->irq = irq;
391 }
392
393 /*
394 * PIIX3 USB: We have to disable USB interrupts that are
395 * hardwired to PIRQD# and may be shared with an
396 * external device.
397 *
398 * Legacy Support Register (LEGSUP):
399 * bit13: USB PIRQ Enable (USBPIRQDEN),
400 * bit4: Trap/SMI On IRQ Enable (USBSMIEN).
401 *
402 * We mask out all r/wc bits, too.
403 */
quirk_piix3_usb(struct pci_dev * dev)404 static void __init quirk_piix3_usb(struct pci_dev *dev)
405 {
406 u16 legsup;
407
408 pci_read_config_word(dev, 0xc0, &legsup);
409 legsup &= 0x50ef;
410 pci_write_config_word(dev, 0xc0, legsup);
411 }
412
413 /*
414 * VIA VT82C598 has its device ID settable and many BIOSes
415 * set it to the ID of VT82C597 for backward compatibility.
416 * We need to switch it off to be able to recognize the real
417 * type of the chip.
418 */
quirk_vt82c598_id(struct pci_dev * dev)419 static void __init quirk_vt82c598_id(struct pci_dev *dev)
420 {
421 pci_write_config_byte(dev, 0xfc, 0);
422 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
423 }
424
425 /*
426 * CardBus controllers have a legacy base address that enables them
427 * to respond as i82365 pcmcia controllers. We don't want them to
428 * do this even if the Linux CardBus driver is not loaded, because
429 * the Linux i82365 driver does not (and should not) handle CardBus.
430 */
quirk_cardbus_legacy(struct pci_dev * dev)431 static void __init quirk_cardbus_legacy(struct pci_dev *dev)
432 {
433 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
434 return;
435 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
436 }
437
438 /*
439 * The AMD io apic can hang the box when an apic irq is masked.
440 * We check all revs >= B0 (yet not in the pre production!) as the bug
441 * is currently marked NoFix
442 *
443 * We have multiple reports of hangs with this chipset that went away with
444 * noapic specified. For the moment we assume its the errata. We may be wrong
445 * of course. However the advice is demonstrably good even if so..
446 */
447
quirk_amd_ioapic(struct pci_dev * dev)448 static void __init quirk_amd_ioapic(struct pci_dev *dev)
449 {
450 u8 rev;
451
452 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
453 if(rev >= 0x02)
454 {
455 printk(KERN_WARNING "I/O APIC: AMD Errata #22 may be present. In the event of instability try\n");
456 printk(KERN_WARNING " : booting with the \"noapic\" option.\n");
457 }
458 }
459
460 /*
461 * Following the PCI ordering rules is optional on the AMD762. I'm not
462 * sure what the designers were smoking but let's not inhale...
463 *
464 * To be fair to AMD, it follows the spec by default, its BIOS people
465 * who turn it off!
466 */
467
quirk_amd_ordering(struct pci_dev * dev)468 static void __init quirk_amd_ordering(struct pci_dev *dev)
469 {
470 u32 pcic;
471 pci_read_config_dword(dev, 0x4C, &pcic);
472 if((pcic&6)!=6)
473 {
474 pcic |= 6;
475 printk(KERN_WARNING "BIOS failed to enable PCI standards compliance, fixing this error.\n");
476 pci_write_config_dword(dev, 0x4C, pcic);
477 pci_read_config_dword(dev, 0x84, &pcic);
478 pcic |= (1<<23); /* Required in this mode */
479 pci_write_config_dword(dev, 0x84, pcic);
480 }
481 }
482
483 #ifdef CONFIG_X86_IO_APIC
484
485 #define AMD8131_revA0 0x01
486 #define AMD8131_revB0 0x11
487 #define AMD8131_MISC 0x40
488 #define AMD8131_NIOAMODE_BIT 0
489
quirk_amd_8131_ioapic(struct pci_dev * dev)490 static void __init quirk_amd_8131_ioapic(struct pci_dev *dev)
491 {
492 unsigned char revid, tmp;
493
494 if (nr_ioapics == 0)
495 return;
496
497 pci_read_config_byte(dev, PCI_REVISION_ID, &revid);
498 if (revid == AMD8131_revA0 || revid == AMD8131_revB0) {
499 printk(KERN_INFO "Fixing up AMD8131 IOAPIC mode\n");
500 pci_read_config_byte( dev, AMD8131_MISC, &tmp);
501 tmp &= ~(1 << AMD8131_NIOAMODE_BIT);
502 pci_write_config_byte( dev, AMD8131_MISC, tmp);
503 }
504 }
505 #endif
506
507
508 /*
509 * DreamWorks provided workaround for Dunord I-3000 problem
510 *
511 * This card decodes and responds to addresses not apparently
512 * assigned to it. We force a larger allocation to ensure that
513 * nothing gets put too close to it.
514 */
515
quirk_dunord(struct pci_dev * dev)516 static void __init quirk_dunord ( struct pci_dev * dev )
517 {
518 struct resource * r = & dev -> resource [ 1 ];
519 r -> start = 0;
520 r -> end = 0xffffff;
521 }
522
quirk_transparent_bridge(struct pci_dev * dev)523 static void __init quirk_transparent_bridge(struct pci_dev *dev)
524 {
525 dev->transparent = 1;
526 }
527
528 /*
529 * Common misconfiguration of the MediaGX/Geode PCI master that will
530 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
531 * datasheets found at http://www.national.com/ds/GX for info on what
532 * these bits do. <christer@weinigel.se>
533 */
534
quirk_mediagx_master(struct pci_dev * dev)535 static void __init quirk_mediagx_master(struct pci_dev *dev)
536 {
537 u8 reg;
538 pci_read_config_byte(dev, 0x41, ®);
539 if (reg & 2) {
540 reg &= ~2;
541 printk(KERN_INFO "PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
542 pci_write_config_byte(dev, 0x41, reg);
543 }
544 }
545
546 /*
547 * As per PCI spec, ignore base address registers 0-3 of the IDE controllers
548 * running in Compatible mode (bits 0 and 2 in the ProgIf for primary and
549 * secondary channels respectively). If the device reports Compatible mode
550 * but does use BAR0-3 for address decoding, we assume that firmware has
551 * programmed these BARs with standard values (0x1f0,0x3f4 and 0x170,0x374).
552 * Exceptions (if they exist) must be handled in chip/architecture specific
553 * fixups.
554 *
555 * Note: for non x86 people. You may need an arch specific quirk to handle
556 * moving IDE devices to native mode as well. Some plug in card devices power
557 * up in compatible mode and assume the BIOS will adjust them.
558 *
559 * Q: should we load the 0x1f0,0x3f4 into the registers or zap them as
560 * we do now ? We don't want is pci_enable_device to come along
561 * and assign new resources. Both approaches work for that.
562 */
563
quirk_ide_bases(struct pci_dev * dev)564 static void __devinit quirk_ide_bases(struct pci_dev *dev)
565 {
566 struct resource *res;
567 int first_bar = 2, last_bar = 0;
568
569 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
570 return;
571
572 res = &dev->resource[0];
573
574 /* primary channel: ProgIf bit 0, BAR0, BAR1 */
575 if (!(dev->class & 1) && (res[0].flags || res[1].flags)) {
576 res[0].start = res[0].end = res[0].flags = 0;
577 res[1].start = res[1].end = res[1].flags = 0;
578 first_bar = 0;
579 last_bar = 1;
580 }
581
582 /* secondary channel: ProgIf bit 2, BAR2, BAR3 */
583 if (!(dev->class & 4) && (res[2].flags || res[3].flags)) {
584 res[2].start = res[2].end = res[2].flags = 0;
585 res[3].start = res[3].end = res[3].flags = 0;
586 last_bar = 3;
587 }
588
589 if (!last_bar)
590 return;
591
592 printk(KERN_INFO "PCI: Ignoring BAR%d-%d of IDE controller %s\n",
593 first_bar, last_bar, dev->slot_name);
594 }
595
596 /*
597 * Ensure C0 rev restreaming is off. This is normally done by
598 * the BIOS but in the odd case it is not the results are corruption
599 * hence the presence of a Linux check
600 */
601
quirk_disable_pxb(struct pci_dev * pdev)602 static void __init quirk_disable_pxb(struct pci_dev *pdev)
603 {
604 u16 config;
605 u8 rev;
606
607 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
608 if(rev != 0x04) /* Only C0 requires this */
609 return;
610 pci_read_config_word(pdev, 0x40, &config);
611 if(config & (1<<6))
612 {
613 config &= ~(1<<6);
614 pci_write_config_word(pdev, 0x40, config);
615 printk(KERN_INFO "PCI: C0 revision 450NX. Disabling PCI restreaming.\n");
616 }
617 }
618
619 /*
620 * VIA northbridges care about PCI_INTERRUPT_LINE
621 */
622
623 int via_interrupt_line_quirk;
624
quirk_via_bridge(struct pci_dev * pdev)625 static void __init quirk_via_bridge(struct pci_dev *pdev)
626 {
627 if(pdev->devfn == 0) {
628 printk(KERN_INFO "PCI: Via IRQ fixup\n");
629 via_interrupt_line_quirk = 1;
630 }
631 }
632
633 /*
634 * Serverworks CSB5 IDE does not fully support native mode
635 */
quirk_svwks_csb5ide(struct pci_dev * pdev)636 static void __init quirk_svwks_csb5ide(struct pci_dev *pdev)
637 {
638 u8 prog;
639 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
640 if (prog & 5) {
641 prog &= ~5;
642 pdev->class &= ~5;
643 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
644 /* need to re-assign BARs for compat mode */
645 quirk_ide_bases(pdev);
646 }
647 }
648
649 /*
650 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
651 * is not activated. The myth is that Asus said that they do not want the
652 * users to be irritated by just another PCI Device in the Win98 device
653 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
654 * package 2.7.0 for details)
655 *
656 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
657 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
658 * becomes necessary to do this tweak in two steps -- I've chosen the Host
659 * bridge as trigger.
660 */
661
662 static int __initdata asus_hides_smbus = 0;
663
asus_hides_smbus_hostbridge(struct pci_dev * dev)664 static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
665 {
666 if (likely(dev->subsystem_vendor != PCI_VENDOR_ID_ASUSTEK))
667 return;
668
669 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
670 switch(dev->subsystem_device) {
671 case 0x8070: /* P4B */
672 case 0x8088: /* P4B533 */
673 asus_hides_smbus = 1;
674 }
675 if ((dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) &&
676 (dev->subsystem_device == 0x80b2)) /* P4PE */
677 asus_hides_smbus = 1;
678 if ((dev->device == PCI_DEVICE_ID_INTEL_82850_HB) &&
679 (dev->subsystem_device == 0x8030)) /* P4T533 */
680 asus_hides_smbus = 1;
681 if ((dev->device == PCI_DEVICE_ID_INTEL_7205_0) &&
682 (dev->subsystem_device == 0x8070)) /* P4G8X Deluxe */
683 asus_hides_smbus = 1;
684 return;
685 }
686
asus_hides_smbus_lpc(struct pci_dev * dev)687 static void __init asus_hides_smbus_lpc(struct pci_dev *dev)
688 {
689 u16 val;
690
691 if (likely(!asus_hides_smbus))
692 return;
693
694 pci_read_config_word(dev, 0xF2, &val);
695 if (val & 0x8) {
696 pci_write_config_word(dev, 0xF2, val & (~0x8));
697 pci_read_config_word(dev, 0xF2, &val);
698 if(val & 0x8)
699 printk(KERN_INFO "PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
700 else
701 printk(KERN_INFO "PCI: Enabled i801 SMBus device\n");
702 }
703 }
704
705 /*
706 * The main table of quirks.
707 */
708
709 static struct pci_fixup pci_fixups[] __initdata = {
710 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord },
711 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release },
712 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release },
713 /*
714 * Its not totally clear which chipsets are the problematic ones
715 * We know 82C586 and 82C596 variants are affected.
716 */
717 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs },
718 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs },
719 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs },
720 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb },
721 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M },
722 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M },
723 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton },
724 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton },
725 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton },
726 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton },
727 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma },
728 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma },
729 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma },
730 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma },
731 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma },
732 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma },
733 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik },
734 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik },
735 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci },
736 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci },
737 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency },
738 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency },
739 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency },
740 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx },
741 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf },
742 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id },
743 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi },
744 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi },
745 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi },
746 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi },
747 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi },
748 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_2, quirk_piix3_usb },
749 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_2, quirk_piix3_usb },
750 { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, quirk_ide_bases },
751 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_bridge },
752 { PCI_FIXUP_FINAL, PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy },
753
754 #ifdef CONFIG_X86_IO_APIC
755 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic },
756 #endif
757 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi },
758 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi },
759
760 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic },
761 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering },
762 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_IGP, quirk_ati_exploding_mce },
763 /*
764 * i82380FB mobile docking controller: its PCI-to-PCI bridge
765 * is subtractive decoding (transparent), and does indicate this
766 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
767 * instead of 0x01.
768 */
769 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge },
770 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge },
771
772 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master },
773
774 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide },
775
776 #ifdef CONFIG_X86_IO_APIC
777 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_APIC,
778 quirk_amd_8131_ioapic },
779 #endif
780
781 /*
782 * on Asus P4B boards, the i801SMBus device is disabled at startup.
783 */
784 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge },
785 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge },
786 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge },
787 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge },
788 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc },
789 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc },
790
791 { 0 }
792 };
793
794
pci_do_fixups(struct pci_dev * dev,int pass,struct pci_fixup * f)795 static void pci_do_fixups(struct pci_dev *dev, int pass, struct pci_fixup *f)
796 {
797 while (f->pass) {
798 if (f->pass == pass &&
799 (f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
800 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
801 #ifdef DEBUG
802 printk(KERN_INFO "PCI: Calling quirk %p for %s\n", f->hook, dev->slot_name);
803 #endif
804 f->hook(dev);
805 }
806 f++;
807 }
808 }
809
pci_fixup_device(int pass,struct pci_dev * dev)810 void pci_fixup_device(int pass, struct pci_dev *dev)
811 {
812 pci_do_fixups(dev, pass, pcibios_fixups);
813 pci_do_fixups(dev, pass, pci_fixups);
814 }
815