1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dccg.h"
27 #include "clk_mgr_internal.h"
28
29 // For dce12_get_dp_ref_freq_khz
30 #include "dce100/dce_clk_mgr.h"
31
32 // For dcn20_update_clocks_update_dpp_dto
33 #include "dcn20/dcn20_clk_mgr.h"
34
35 // For DML FPU code
36 #include "dml/dcn20/dcn20_fpu.h"
37
38 #include "vg_clk_mgr.h"
39 #include "dcn301_smu.h"
40 #include "reg_helper.h"
41 #include "core_types.h"
42 #include "dm_helpers.h"
43
44 #include "atomfirmware.h"
45 #include "vangogh_ip_offset.h"
46 #include "clk/clk_11_5_0_offset.h"
47 #include "clk/clk_11_5_0_sh_mask.h"
48
49 /* Constants */
50
51 #define LPDDR_MEM_RETRAIN_LATENCY 4.977 /* Number obtained from LPDDR4 Training Counter Requirement doc */
52
53 /* Macros */
54
55 #define TO_CLK_MGR_VGH(clk_mgr)\
56 container_of(clk_mgr, struct clk_mgr_vgh, base)
57
58 #define REG(reg_name) \
59 (CLK_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
60
61 /* TODO: evaluate how to lower or disable all dcn clocks in screen off case */
vg_get_active_display_cnt_wa(struct dc * dc,struct dc_state * context)62 static int vg_get_active_display_cnt_wa(
63 struct dc *dc,
64 struct dc_state *context)
65 {
66 int i, display_count;
67 bool tmds_present = false;
68
69 display_count = 0;
70 for (i = 0; i < context->stream_count; i++) {
71 const struct dc_stream_state *stream = context->streams[i];
72
73 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
74 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
75 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
76 tmds_present = true;
77 }
78
79 for (i = 0; i < dc->link_count; i++) {
80 const struct dc_link *link = dc->links[i];
81
82 /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
83 if (link->link_enc->funcs->is_dig_enabled &&
84 link->link_enc->funcs->is_dig_enabled(link->link_enc))
85 display_count++;
86 }
87
88 /* WA for hang on HDMI after display off back back on*/
89 if (display_count == 0 && tmds_present)
90 display_count = 1;
91
92 return display_count;
93 }
94
vg_update_clocks(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)95 static void vg_update_clocks(struct clk_mgr *clk_mgr_base,
96 struct dc_state *context,
97 bool safe_to_lower)
98 {
99 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
100 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
101 struct dc *dc = clk_mgr_base->ctx->dc;
102 int display_count;
103 bool update_dppclk = false;
104 bool update_dispclk = false;
105 bool dpp_clock_lowered = false;
106
107 if (dc->work_arounds.skip_clock_update)
108 return;
109
110 /*
111 * if it is safe to lower, but we are already in the lower state, we don't have to do anything
112 * also if safe to lower is false, we just go in the higher state
113 */
114 if (safe_to_lower) {
115 /* check that we're not already in lower */
116 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
117
118 display_count = vg_get_active_display_cnt_wa(dc, context);
119 /* if we can go lower, go lower */
120 if (display_count == 0 && !IS_DIAG_DC(dc->ctx->dce_environment)) {
121 union display_idle_optimization_u idle_info = { 0 };
122
123 idle_info.idle_info.df_request_disabled = 1;
124 idle_info.idle_info.phy_ref_clk_off = 1;
125
126 dcn301_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
127 /* update power state */
128 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
129 }
130 }
131 } else {
132 /* check that we're not already in D0 */
133 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
134 union display_idle_optimization_u idle_info = { 0 };
135
136 dcn301_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
137 /* update power state */
138 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
139 }
140 }
141
142 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz) && !dc->debug.disable_min_fclk) {
143 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
144 dcn301_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
145 }
146
147 if (should_set_clock(safe_to_lower,
148 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz) && !dc->debug.disable_min_fclk) {
149 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
150 dcn301_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
151 }
152
153 // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
154 if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
155 if (new_clocks->dppclk_khz < 100000)
156 new_clocks->dppclk_khz = 100000;
157 }
158
159 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
160 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
161 dpp_clock_lowered = true;
162 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
163 update_dppclk = true;
164 }
165
166 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
167 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
168 dcn301_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
169
170 update_dispclk = true;
171 }
172
173 if (dpp_clock_lowered) {
174 // increase per DPP DTO before lowering global dppclk
175 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
176 dcn301_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
177 } else {
178 // increase global DPPCLK before lowering per DPP DTO
179 if (update_dppclk || update_dispclk)
180 dcn301_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
181 // always update dtos unless clock is lowered and not safe to lower
182 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
183 }
184 }
185
186
get_vco_frequency_from_reg(struct clk_mgr_internal * clk_mgr)187 static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
188 {
189 /* get FbMult value */
190 struct fixed31_32 pll_req;
191 unsigned int fbmult_frac_val = 0;
192 unsigned int fbmult_int_val = 0;
193
194
195 /*
196 * Register value of fbmult is in 8.16 format, we are converting to 31.32
197 * to leverage the fix point operations available in driver
198 */
199
200 REG_GET(CLK1_0_CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/
201 REG_GET(CLK1_0_CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */
202
203 pll_req = dc_fixpt_from_int(fbmult_int_val);
204
205 /*
206 * since fractional part is only 16 bit in register definition but is 32 bit
207 * in our fix point definiton, need to shift left by 16 to obtain correct value
208 */
209 pll_req.value |= fbmult_frac_val << 16;
210
211 /* multiply by REFCLK period */
212 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
213
214 /* integer part is now VCO frequency in kHz */
215 return dc_fixpt_floor(pll_req);
216 }
217
vg_dump_clk_registers_internal(struct dcn301_clk_internal * internal,struct clk_mgr * clk_mgr_base)218 static void vg_dump_clk_registers_internal(struct dcn301_clk_internal *internal, struct clk_mgr *clk_mgr_base)
219 {
220 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
221
222 internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK3_CURRENT_CNT);
223 internal->CLK1_CLK3_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK3_BYPASS_CNTL);
224
225 internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_0_CLK1_CLK3_DS_CNTL); //dcf deep sleep divider
226 internal->CLK1_CLK3_ALLOW_DS = REG_READ(CLK1_0_CLK1_CLK3_ALLOW_DS);
227
228 internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK1_CURRENT_CNT);
229 internal->CLK1_CLK1_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK1_BYPASS_CNTL);
230
231 internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK2_CURRENT_CNT);
232 internal->CLK1_CLK2_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK2_BYPASS_CNTL);
233
234 internal->CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK0_CURRENT_CNT);
235 internal->CLK1_CLK0_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK0_BYPASS_CNTL);
236 }
237
238 /* This function collect raw clk register values */
vg_dump_clk_registers(struct clk_state_registers_and_bypass * regs_and_bypass,struct clk_mgr * clk_mgr_base,struct clk_log_info * log_info)239 static void vg_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
240 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
241 {
242 struct dcn301_clk_internal internal = {0};
243 char *bypass_clks[5] = {"0x0 DFS", "0x1 REFCLK", "0x2 ERROR", "0x3 400 FCH", "0x4 600 FCH"};
244 unsigned int chars_printed = 0;
245 unsigned int remaining_buffer = log_info->bufSize;
246
247 vg_dump_clk_registers_internal(&internal, clk_mgr_base);
248
249 regs_and_bypass->dcfclk = internal.CLK1_CLK3_CURRENT_CNT / 10;
250 regs_and_bypass->dcf_deep_sleep_divider = internal.CLK1_CLK3_DS_CNTL / 10;
251 regs_and_bypass->dcf_deep_sleep_allow = internal.CLK1_CLK3_ALLOW_DS;
252 regs_and_bypass->dprefclk = internal.CLK1_CLK2_CURRENT_CNT / 10;
253 regs_and_bypass->dispclk = internal.CLK1_CLK0_CURRENT_CNT / 10;
254 regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10;
255
256 regs_and_bypass->dppclk_bypass = internal.CLK1_CLK1_BYPASS_CNTL & 0x0007;
257 if (regs_and_bypass->dppclk_bypass < 0 || regs_and_bypass->dppclk_bypass > 4)
258 regs_and_bypass->dppclk_bypass = 0;
259 regs_and_bypass->dcfclk_bypass = internal.CLK1_CLK3_BYPASS_CNTL & 0x0007;
260 if (regs_and_bypass->dcfclk_bypass < 0 || regs_and_bypass->dcfclk_bypass > 4)
261 regs_and_bypass->dcfclk_bypass = 0;
262 regs_and_bypass->dispclk_bypass = internal.CLK1_CLK0_BYPASS_CNTL & 0x0007;
263 if (regs_and_bypass->dispclk_bypass < 0 || regs_and_bypass->dispclk_bypass > 4)
264 regs_and_bypass->dispclk_bypass = 0;
265 regs_and_bypass->dprefclk_bypass = internal.CLK1_CLK2_BYPASS_CNTL & 0x0007;
266 if (regs_and_bypass->dprefclk_bypass < 0 || regs_and_bypass->dprefclk_bypass > 4)
267 regs_and_bypass->dprefclk_bypass = 0;
268
269 if (log_info->enabled) {
270 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "clk_type,clk_value,deepsleep_cntl,deepsleep_allow,bypass\n");
271 remaining_buffer -= chars_printed;
272 *log_info->sum_chars_printed += chars_printed;
273 log_info->pBuf += chars_printed;
274
275 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dcfclk,%d,%d,%d,%s\n",
276 regs_and_bypass->dcfclk,
277 regs_and_bypass->dcf_deep_sleep_divider,
278 regs_and_bypass->dcf_deep_sleep_allow,
279 bypass_clks[(int) regs_and_bypass->dcfclk_bypass]);
280 remaining_buffer -= chars_printed;
281 *log_info->sum_chars_printed += chars_printed;
282 log_info->pBuf += chars_printed;
283
284 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dprefclk,%d,N/A,N/A,%s\n",
285 regs_and_bypass->dprefclk,
286 bypass_clks[(int) regs_and_bypass->dprefclk_bypass]);
287 remaining_buffer -= chars_printed;
288 *log_info->sum_chars_printed += chars_printed;
289 log_info->pBuf += chars_printed;
290
291 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dispclk,%d,N/A,N/A,%s\n",
292 regs_and_bypass->dispclk,
293 bypass_clks[(int) regs_and_bypass->dispclk_bypass]);
294 remaining_buffer -= chars_printed;
295 *log_info->sum_chars_printed += chars_printed;
296 log_info->pBuf += chars_printed;
297
298 //split
299 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "SPLIT\n");
300 remaining_buffer -= chars_printed;
301 *log_info->sum_chars_printed += chars_printed;
302 log_info->pBuf += chars_printed;
303
304 // REGISTER VALUES
305 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "reg_name,value,clk_type\n");
306 remaining_buffer -= chars_printed;
307 *log_info->sum_chars_printed += chars_printed;
308 log_info->pBuf += chars_printed;
309
310 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_CURRENT_CNT,%d,dcfclk\n",
311 internal.CLK1_CLK3_CURRENT_CNT);
312 remaining_buffer -= chars_printed;
313 *log_info->sum_chars_printed += chars_printed;
314 log_info->pBuf += chars_printed;
315
316 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_DS_CNTL,%d,dcf_deep_sleep_divider\n",
317 internal.CLK1_CLK3_DS_CNTL);
318 remaining_buffer -= chars_printed;
319 *log_info->sum_chars_printed += chars_printed;
320 log_info->pBuf += chars_printed;
321
322 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_ALLOW_DS,%d,dcf_deep_sleep_allow\n",
323 internal.CLK1_CLK3_ALLOW_DS);
324 remaining_buffer -= chars_printed;
325 *log_info->sum_chars_printed += chars_printed;
326 log_info->pBuf += chars_printed;
327
328 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK2_CURRENT_CNT,%d,dprefclk\n",
329 internal.CLK1_CLK2_CURRENT_CNT);
330 remaining_buffer -= chars_printed;
331 *log_info->sum_chars_printed += chars_printed;
332 log_info->pBuf += chars_printed;
333
334 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_CURRENT_CNT,%d,dispclk\n",
335 internal.CLK1_CLK0_CURRENT_CNT);
336 remaining_buffer -= chars_printed;
337 *log_info->sum_chars_printed += chars_printed;
338 log_info->pBuf += chars_printed;
339
340 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_CURRENT_CNT,%d,dppclk\n",
341 internal.CLK1_CLK1_CURRENT_CNT);
342 remaining_buffer -= chars_printed;
343 *log_info->sum_chars_printed += chars_printed;
344 log_info->pBuf += chars_printed;
345
346 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_BYPASS_CNTL,%d,dcfclk_bypass\n",
347 internal.CLK1_CLK3_BYPASS_CNTL);
348 remaining_buffer -= chars_printed;
349 *log_info->sum_chars_printed += chars_printed;
350 log_info->pBuf += chars_printed;
351
352 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK2_BYPASS_CNTL,%d,dprefclk_bypass\n",
353 internal.CLK1_CLK2_BYPASS_CNTL);
354 remaining_buffer -= chars_printed;
355 *log_info->sum_chars_printed += chars_printed;
356 log_info->pBuf += chars_printed;
357
358 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_BYPASS_CNTL,%d,dispclk_bypass\n",
359 internal.CLK1_CLK0_BYPASS_CNTL);
360 remaining_buffer -= chars_printed;
361 *log_info->sum_chars_printed += chars_printed;
362 log_info->pBuf += chars_printed;
363
364 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_BYPASS_CNTL,%d,dppclk_bypass\n",
365 internal.CLK1_CLK1_BYPASS_CNTL);
366 remaining_buffer -= chars_printed;
367 *log_info->sum_chars_printed += chars_printed;
368 log_info->pBuf += chars_printed;
369 }
370 }
371
vg_enable_pme_wa(struct clk_mgr * clk_mgr_base)372 static void vg_enable_pme_wa(struct clk_mgr *clk_mgr_base)
373 {
374 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
375
376 dcn301_smu_enable_pme_wa(clk_mgr);
377 }
378
vg_init_clocks(struct clk_mgr * clk_mgr)379 static void vg_init_clocks(struct clk_mgr *clk_mgr)
380 {
381 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
382 // Assumption is that boot state always supports pstate
383 clk_mgr->clks.p_state_change_support = true;
384 clk_mgr->clks.prev_p_state_change_support = true;
385 clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;
386 }
387
vg_build_watermark_ranges(struct clk_bw_params * bw_params,struct watermarks * table)388 static void vg_build_watermark_ranges(struct clk_bw_params *bw_params, struct watermarks *table)
389 {
390 int i, num_valid_sets;
391
392 num_valid_sets = 0;
393
394 for (i = 0; i < WM_SET_COUNT; i++) {
395 /* skip empty entries, the smu array has no holes*/
396 if (!bw_params->wm_table.entries[i].valid)
397 continue;
398
399 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
400 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
401 /* We will not select WM based on fclk, so leave it as unconstrained */
402 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
403 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
404
405 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
406 if (i == 0)
407 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
408 else {
409 /* add 1 to make it non-overlapping with next lvl */
410 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
411 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
412 }
413 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
414 bw_params->clk_table.entries[i].dcfclk_mhz;
415
416 } else {
417 /* unconstrained for memory retraining */
418 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
419 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
420
421 /* Modify previous watermark range to cover up to max */
422 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
423 }
424 num_valid_sets++;
425 }
426
427 ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
428
429 /* modify the min and max to make sure we cover the whole range*/
430 table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;
431 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;
432 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;
433 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
434
435 /* This is for writeback only, does not matter currently as no writeback support*/
436 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;
437 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;
438 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;
439 table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;
440 table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;
441 }
442
443
vg_notify_wm_ranges(struct clk_mgr * clk_mgr_base)444 static void vg_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
445 {
446 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
447 struct clk_mgr_vgh *clk_mgr_vgh = TO_CLK_MGR_VGH(clk_mgr);
448 struct watermarks *table = clk_mgr_vgh->smu_wm_set.wm_set;
449
450 if (!clk_mgr->smu_ver)
451 return;
452
453 if (!table || clk_mgr_vgh->smu_wm_set.mc_address.quad_part == 0)
454 return;
455
456 memset(table, 0, sizeof(*table));
457
458 vg_build_watermark_ranges(clk_mgr_base->bw_params, table);
459
460 dcn301_smu_set_dram_addr_high(clk_mgr,
461 clk_mgr_vgh->smu_wm_set.mc_address.high_part);
462 dcn301_smu_set_dram_addr_low(clk_mgr,
463 clk_mgr_vgh->smu_wm_set.mc_address.low_part);
464 dcn301_smu_transfer_wm_table_dram_2_smu(clk_mgr);
465 }
466
vg_are_clock_states_equal(struct dc_clocks * a,struct dc_clocks * b)467 static bool vg_are_clock_states_equal(struct dc_clocks *a,
468 struct dc_clocks *b)
469 {
470 if (a->dispclk_khz != b->dispclk_khz)
471 return false;
472 else if (a->dppclk_khz != b->dppclk_khz)
473 return false;
474 else if (a->dcfclk_khz != b->dcfclk_khz)
475 return false;
476 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
477 return false;
478
479 return true;
480 }
481
482
483 static struct clk_mgr_funcs vg_funcs = {
484 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
485 .update_clocks = vg_update_clocks,
486 .init_clocks = vg_init_clocks,
487 .enable_pme_wa = vg_enable_pme_wa,
488 .are_clock_states_equal = vg_are_clock_states_equal,
489 .notify_wm_ranges = vg_notify_wm_ranges
490 };
491
492 static struct clk_bw_params vg_bw_params = {
493 .vram_type = Ddr4MemType,
494 .num_channels = 1,
495 .clk_table = {
496 .entries = {
497 {
498 .voltage = 0,
499 .dcfclk_mhz = 400,
500 .fclk_mhz = 400,
501 .memclk_mhz = 800,
502 .socclk_mhz = 0,
503 },
504 {
505 .voltage = 0,
506 .dcfclk_mhz = 483,
507 .fclk_mhz = 800,
508 .memclk_mhz = 1600,
509 .socclk_mhz = 0,
510 },
511 {
512 .voltage = 0,
513 .dcfclk_mhz = 602,
514 .fclk_mhz = 1067,
515 .memclk_mhz = 1067,
516 .socclk_mhz = 0,
517 },
518 {
519 .voltage = 0,
520 .dcfclk_mhz = 738,
521 .fclk_mhz = 1333,
522 .memclk_mhz = 1600,
523 .socclk_mhz = 0,
524 },
525 },
526
527 .num_entries = 4,
528 },
529
530 };
531
find_dcfclk_for_voltage(const struct vg_dpm_clocks * clock_table,unsigned int voltage)532 static unsigned int find_dcfclk_for_voltage(const struct vg_dpm_clocks *clock_table,
533 unsigned int voltage)
534 {
535 int i;
536
537 for (i = 0; i < VG_NUM_SOC_VOLTAGE_LEVELS; i++) {
538 if (clock_table->SocVoltage[i] == voltage)
539 return clock_table->DcfClocks[i];
540 }
541
542 ASSERT(0);
543 return 0;
544 }
545
vg_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal * clk_mgr,struct integrated_info * bios_info,const struct vg_dpm_clocks * clock_table)546 static void vg_clk_mgr_helper_populate_bw_params(
547 struct clk_mgr_internal *clk_mgr,
548 struct integrated_info *bios_info,
549 const struct vg_dpm_clocks *clock_table)
550 {
551 int i, j;
552 struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
553
554 j = -1;
555
556 ASSERT(VG_NUM_FCLK_DPM_LEVELS <= MAX_NUM_DPM_LVL);
557
558 /* Find lowest DPM, FCLK is filled in reverse order*/
559
560 for (i = VG_NUM_FCLK_DPM_LEVELS - 1; i >= 0; i--) {
561 if (clock_table->DfPstateTable[i].fclk != 0) {
562 j = i;
563 break;
564 }
565 }
566
567 if (j == -1) {
568 /* clock table is all 0s, just use our own hardcode */
569 ASSERT(0);
570 return;
571 }
572
573 bw_params->clk_table.num_entries = j + 1;
574
575 for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) {
576 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].fclk;
577 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].memclk;
578 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].voltage;
579 bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->DfPstateTable[j].voltage);
580 }
581
582 bw_params->vram_type = bios_info->memory_type;
583 bw_params->num_channels = bios_info->ma_channel_number;
584
585 for (i = 0; i < WM_SET_COUNT; i++) {
586 bw_params->wm_table.entries[i].wm_inst = i;
587
588 if (i >= bw_params->clk_table.num_entries) {
589 bw_params->wm_table.entries[i].valid = false;
590 continue;
591 }
592
593 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
594 bw_params->wm_table.entries[i].valid = true;
595 }
596
597 if (bw_params->vram_type == LpDdr4MemType) {
598 /*
599 * WM set D will be re-purposed for memory retraining
600 */
601 DC_FP_START();
602 dcn21_clk_mgr_set_bw_params_wm_table(bw_params);
603 DC_FP_END();
604 }
605
606 }
607
608 /* Temporary Place holder until we can get them from fuse */
609 static struct vg_dpm_clocks dummy_clocks = {
610 .DcfClocks = { 201, 403, 403, 403, 403, 403, 403 },
611 .SocClocks = { 400, 600, 600, 600, 600, 600, 600 },
612 .SocVoltage = { 2800, 2860, 2860, 2860, 2860, 2860, 2860, 2860 },
613 .DfPstateTable = {
614 { .fclk = 400, .memclk = 400, .voltage = 2800 },
615 { .fclk = 400, .memclk = 400, .voltage = 2800 },
616 { .fclk = 400, .memclk = 400, .voltage = 2800 },
617 { .fclk = 400, .memclk = 400, .voltage = 2800 }
618 }
619 };
620
621 static struct watermarks dummy_wms = { 0 };
622
vg_get_dpm_table_from_smu(struct clk_mgr_internal * clk_mgr,struct smu_dpm_clks * smu_dpm_clks)623 static void vg_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
624 struct smu_dpm_clks *smu_dpm_clks)
625 {
626 struct vg_dpm_clocks *table = smu_dpm_clks->dpm_clks;
627
628 if (!clk_mgr->smu_ver)
629 return;
630
631 if (!table || smu_dpm_clks->mc_address.quad_part == 0)
632 return;
633
634 memset(table, 0, sizeof(*table));
635
636 dcn301_smu_set_dram_addr_high(clk_mgr,
637 smu_dpm_clks->mc_address.high_part);
638 dcn301_smu_set_dram_addr_low(clk_mgr,
639 smu_dpm_clks->mc_address.low_part);
640 dcn301_smu_transfer_dpm_table_smu_2_dram(clk_mgr);
641 }
642
vg_clk_mgr_construct(struct dc_context * ctx,struct clk_mgr_vgh * clk_mgr,struct pp_smu_funcs * pp_smu,struct dccg * dccg)643 void vg_clk_mgr_construct(
644 struct dc_context *ctx,
645 struct clk_mgr_vgh *clk_mgr,
646 struct pp_smu_funcs *pp_smu,
647 struct dccg *dccg)
648 {
649 struct smu_dpm_clks smu_dpm_clks = { 0 };
650
651 clk_mgr->base.base.ctx = ctx;
652 clk_mgr->base.base.funcs = &vg_funcs;
653
654 clk_mgr->base.pp_smu = pp_smu;
655
656 clk_mgr->base.dccg = dccg;
657 clk_mgr->base.dfs_bypass_disp_clk = 0;
658
659 clk_mgr->base.dprefclk_ss_percentage = 0;
660 clk_mgr->base.dprefclk_ss_divider = 1000;
661 clk_mgr->base.ss_on_dprefclk = false;
662 clk_mgr->base.dfs_ref_freq_khz = 48000;
663
664 clk_mgr->smu_wm_set.wm_set = (struct watermarks *)dm_helpers_allocate_gpu_mem(
665 clk_mgr->base.base.ctx,
666 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
667 sizeof(struct watermarks),
668 &clk_mgr->smu_wm_set.mc_address.quad_part);
669
670 if (!clk_mgr->smu_wm_set.wm_set) {
671 clk_mgr->smu_wm_set.wm_set = &dummy_wms;
672 clk_mgr->smu_wm_set.mc_address.quad_part = 0;
673 }
674 ASSERT(clk_mgr->smu_wm_set.wm_set);
675
676 smu_dpm_clks.dpm_clks = (struct vg_dpm_clocks *)dm_helpers_allocate_gpu_mem(
677 clk_mgr->base.base.ctx,
678 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
679 sizeof(struct vg_dpm_clocks),
680 &smu_dpm_clks.mc_address.quad_part);
681
682 if (smu_dpm_clks.dpm_clks == NULL) {
683 smu_dpm_clks.dpm_clks = &dummy_clocks;
684 smu_dpm_clks.mc_address.quad_part = 0;
685 }
686
687 ASSERT(smu_dpm_clks.dpm_clks);
688
689 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
690 vg_funcs.update_clocks = dcn2_update_clocks_fpga;
691 clk_mgr->base.base.dentist_vco_freq_khz = 3600000;
692 } else {
693 struct clk_log_info log_info = {0};
694
695 clk_mgr->base.smu_ver = dcn301_smu_get_smu_version(&clk_mgr->base);
696
697 if (clk_mgr->base.smu_ver)
698 clk_mgr->base.smu_present = true;
699
700 /* TODO: Check we get what we expect during bringup */
701 clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base);
702
703 /* in case we don't get a value from the register, use default */
704 if (clk_mgr->base.base.dentist_vco_freq_khz == 0)
705 clk_mgr->base.base.dentist_vco_freq_khz = 3600000;
706
707 if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {
708 vg_bw_params.wm_table = lpddr5_wm_table;
709 } else {
710 vg_bw_params.wm_table = ddr4_wm_table;
711 }
712 /* Saved clocks configured at boot for debug purposes */
713 vg_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info);
714 }
715
716 clk_mgr->base.base.dprefclk_khz = 600000;
717 dce_clock_read_ss_info(&clk_mgr->base);
718
719 clk_mgr->base.base.bw_params = &vg_bw_params;
720
721 vg_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);
722 if (ctx->dc_bios && ctx->dc_bios->integrated_info) {
723 vg_clk_mgr_helper_populate_bw_params(
724 &clk_mgr->base,
725 ctx->dc_bios->integrated_info,
726 smu_dpm_clks.dpm_clks);
727 }
728
729 if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
730 dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
731 smu_dpm_clks.dpm_clks);
732 /*
733 if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment) && clk_mgr->base.smu_ver) {
734 enable powerfeatures when displaycount goes to 0
735 dcn301_smu_enable_phy_refclk_pwrdwn(clk_mgr, !debug->disable_48mhz_pwrdwn);
736 }
737 */
738 }
739
vg_clk_mgr_destroy(struct clk_mgr_internal * clk_mgr_int)740 void vg_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int)
741 {
742 struct clk_mgr_vgh *clk_mgr = TO_CLK_MGR_VGH(clk_mgr_int);
743
744 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0)
745 dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
746 clk_mgr->smu_wm_set.wm_set);
747 }
748