1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include "pp_debug.h"
24 #include "smumgr.h"
25 #include "smu_ucode_xfer_vi.h"
26 #include "vegam_smumgr.h"
27 #include "smu/smu_7_1_3_d.h"
28 #include "smu/smu_7_1_3_sh_mask.h"
29 #include "gmc/gmc_8_1_d.h"
30 #include "gmc/gmc_8_1_sh_mask.h"
31 #include "oss/oss_3_0_d.h"
32 #include "gca/gfx_8_0_d.h"
33 #include "bif/bif_5_0_d.h"
34 #include "bif/bif_5_0_sh_mask.h"
35 #include "ppatomctrl.h"
36 #include "cgs_common.h"
37 #include "smu7_ppsmc.h"
38
39 #include "smu7_dyn_defaults.h"
40
41 #include "smu7_hwmgr.h"
42 #include "hardwaremanager.h"
43 #include "atombios.h"
44 #include "pppcielanes.h"
45
46 #include "dce/dce_11_2_d.h"
47 #include "dce/dce_11_2_sh_mask.h"
48
49 #define PPVEGAM_TARGETACTIVITY_DFLT 50
50
51 #define VOLTAGE_VID_OFFSET_SCALE1 625
52 #define VOLTAGE_VID_OFFSET_SCALE2 100
53 #define POWERTUNE_DEFAULT_SET_MAX 1
54 #define VDDC_VDDCI_DELTA 200
55 #define MC_CG_ARB_FREQ_F1 0x0b
56
57 #define STRAP_ASIC_RO_LSB 2168
58 #define STRAP_ASIC_RO_MSB 2175
59
60 #define PPSMC_MSG_ApplyAvfsCksOffVoltage ((uint16_t) 0x415)
61 #define PPSMC_MSG_EnableModeSwitchRLCNotification ((uint16_t) 0x305)
62
63 static const struct vegam_pt_defaults
64 vegam_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
65 /* sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
66 * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT */
67 { 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
68 { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61},
69 { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 } },
70 };
71
72 static const sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] = {
73 {VCO_2_4, POSTDIV_DIV_BY_16, 75, 160, 112},
74 {VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160},
75 {VCO_2_4, POSTDIV_DIV_BY_8, 75, 160, 112},
76 {VCO_3_6, POSTDIV_DIV_BY_8, 112, 224, 160},
77 {VCO_2_4, POSTDIV_DIV_BY_4, 75, 160, 112},
78 {VCO_3_6, POSTDIV_DIV_BY_4, 112, 216, 160},
79 {VCO_2_4, POSTDIV_DIV_BY_2, 75, 160, 108},
80 {VCO_3_6, POSTDIV_DIV_BY_2, 112, 216, 160} };
81
vegam_smu_init(struct pp_hwmgr * hwmgr)82 static int vegam_smu_init(struct pp_hwmgr *hwmgr)
83 {
84 struct vegam_smumgr *smu_data;
85
86 smu_data = kzalloc(sizeof(struct vegam_smumgr), GFP_KERNEL);
87 if (smu_data == NULL)
88 return -ENOMEM;
89
90 hwmgr->smu_backend = smu_data;
91
92 if (smu7_init(hwmgr)) {
93 kfree(smu_data);
94 return -EINVAL;
95 }
96
97 return 0;
98 }
99
vegam_start_smu_in_protection_mode(struct pp_hwmgr * hwmgr)100 static int vegam_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
101 {
102 int result = 0;
103
104 /* Wait for smc boot up */
105 /* PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0) */
106
107 /* Assert reset */
108 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
109 SMC_SYSCON_RESET_CNTL, rst_reg, 1);
110
111 result = smu7_upload_smu_firmware_image(hwmgr);
112 if (result != 0)
113 return result;
114
115 /* Clear status */
116 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0);
117
118 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
119 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
120
121 /* De-assert reset */
122 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
123 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
124
125
126 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);
127
128
129 /* Call Test SMU message with 0x20000 offset to trigger SMU start */
130 smu7_send_msg_to_smc_offset(hwmgr);
131
132 /* Wait done bit to be set */
133 /* Check pass/failed indicator */
134
135 PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, SMU_STATUS, SMU_DONE, 0);
136
137 if (1 != PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
138 SMU_STATUS, SMU_PASS))
139 PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1);
140
141 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0);
142
143 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
144 SMC_SYSCON_RESET_CNTL, rst_reg, 1);
145
146 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
147 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
148
149 /* Wait for firmware to initialize */
150 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
151
152 return result;
153 }
154
vegam_start_smu_in_non_protection_mode(struct pp_hwmgr * hwmgr)155 static int vegam_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr)
156 {
157 int result = 0;
158
159 /* wait for smc boot up */
160 PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0);
161
162 /* Clear firmware interrupt enable flag */
163 /* PHM_WRITE_VFPF_INDIRECT_FIELD(pSmuMgr, SMC_IND, SMC_SYSCON_MISC_CNTL, pre_fetcher_en, 1); */
164 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
165 ixFIRMWARE_FLAGS, 0);
166
167 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
168 SMC_SYSCON_RESET_CNTL,
169 rst_reg, 1);
170
171 result = smu7_upload_smu_firmware_image(hwmgr);
172 if (result != 0)
173 return result;
174
175 /* Set smc instruct start point at 0x0 */
176 smu7_program_jump_on_start(hwmgr);
177
178 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
179 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
180
181 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
182 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
183
184 /* Wait for firmware to initialize */
185
186 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
187 FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
188
189 return result;
190 }
191
vegam_start_smu(struct pp_hwmgr * hwmgr)192 static int vegam_start_smu(struct pp_hwmgr *hwmgr)
193 {
194 int result = 0;
195 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
196
197 /* Only start SMC if SMC RAM is not running */
198 if (!smu7_is_smc_ram_running(hwmgr) && hwmgr->not_vf) {
199 smu_data->protected_mode = (uint8_t)(PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
200 CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE));
201 smu_data->smu7_data.security_hard_key = (uint8_t)(PHM_READ_VFPF_INDIRECT_FIELD(
202 hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL));
203
204 /* Check if SMU is running in protected mode */
205 if (smu_data->protected_mode == 0)
206 result = vegam_start_smu_in_non_protection_mode(hwmgr);
207 else
208 result = vegam_start_smu_in_protection_mode(hwmgr);
209
210 if (result != 0)
211 PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result);
212 }
213
214 /* Setup SoftRegsStart here for register lookup in case DummyBackEnd is used and ProcessFirmwareHeader is not executed */
215 smu7_read_smc_sram_dword(hwmgr,
216 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU75_Firmware_Header, SoftRegisters),
217 &(smu_data->smu7_data.soft_regs_start),
218 0x40000);
219
220 result = smu7_request_smu_load_fw(hwmgr);
221
222 return result;
223 }
224
vegam_process_firmware_header(struct pp_hwmgr * hwmgr)225 static int vegam_process_firmware_header(struct pp_hwmgr *hwmgr)
226 {
227 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
228 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
229 uint32_t tmp;
230 int result;
231 bool error = false;
232
233 result = smu7_read_smc_sram_dword(hwmgr,
234 SMU7_FIRMWARE_HEADER_LOCATION +
235 offsetof(SMU75_Firmware_Header, DpmTable),
236 &tmp, SMC_RAM_END);
237
238 if (0 == result)
239 smu_data->smu7_data.dpm_table_start = tmp;
240
241 error |= (0 != result);
242
243 result = smu7_read_smc_sram_dword(hwmgr,
244 SMU7_FIRMWARE_HEADER_LOCATION +
245 offsetof(SMU75_Firmware_Header, SoftRegisters),
246 &tmp, SMC_RAM_END);
247
248 if (!result) {
249 data->soft_regs_start = tmp;
250 smu_data->smu7_data.soft_regs_start = tmp;
251 }
252
253 error |= (0 != result);
254
255 result = smu7_read_smc_sram_dword(hwmgr,
256 SMU7_FIRMWARE_HEADER_LOCATION +
257 offsetof(SMU75_Firmware_Header, mcRegisterTable),
258 &tmp, SMC_RAM_END);
259
260 if (!result)
261 smu_data->smu7_data.mc_reg_table_start = tmp;
262
263 result = smu7_read_smc_sram_dword(hwmgr,
264 SMU7_FIRMWARE_HEADER_LOCATION +
265 offsetof(SMU75_Firmware_Header, FanTable),
266 &tmp, SMC_RAM_END);
267
268 if (!result)
269 smu_data->smu7_data.fan_table_start = tmp;
270
271 error |= (0 != result);
272
273 result = smu7_read_smc_sram_dword(hwmgr,
274 SMU7_FIRMWARE_HEADER_LOCATION +
275 offsetof(SMU75_Firmware_Header, mcArbDramTimingTable),
276 &tmp, SMC_RAM_END);
277
278 if (!result)
279 smu_data->smu7_data.arb_table_start = tmp;
280
281 error |= (0 != result);
282
283 result = smu7_read_smc_sram_dword(hwmgr,
284 SMU7_FIRMWARE_HEADER_LOCATION +
285 offsetof(SMU75_Firmware_Header, Version),
286 &tmp, SMC_RAM_END);
287
288 if (!result)
289 hwmgr->microcode_version_info.SMC = tmp;
290
291 error |= (0 != result);
292
293 return error ? -1 : 0;
294 }
295
vegam_is_dpm_running(struct pp_hwmgr * hwmgr)296 static bool vegam_is_dpm_running(struct pp_hwmgr *hwmgr)
297 {
298 return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
299 CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
300 ? true : false;
301 }
302
vegam_get_mac_definition(uint32_t value)303 static uint32_t vegam_get_mac_definition(uint32_t value)
304 {
305 switch (value) {
306 case SMU_MAX_LEVELS_GRAPHICS:
307 return SMU75_MAX_LEVELS_GRAPHICS;
308 case SMU_MAX_LEVELS_MEMORY:
309 return SMU75_MAX_LEVELS_MEMORY;
310 case SMU_MAX_LEVELS_LINK:
311 return SMU75_MAX_LEVELS_LINK;
312 case SMU_MAX_ENTRIES_SMIO:
313 return SMU75_MAX_ENTRIES_SMIO;
314 case SMU_MAX_LEVELS_VDDC:
315 return SMU75_MAX_LEVELS_VDDC;
316 case SMU_MAX_LEVELS_VDDGFX:
317 return SMU75_MAX_LEVELS_VDDGFX;
318 case SMU_MAX_LEVELS_VDDCI:
319 return SMU75_MAX_LEVELS_VDDCI;
320 case SMU_MAX_LEVELS_MVDD:
321 return SMU75_MAX_LEVELS_MVDD;
322 case SMU_UVD_MCLK_HANDSHAKE_DISABLE:
323 return SMU7_UVD_MCLK_HANDSHAKE_DISABLE |
324 SMU7_VCE_MCLK_HANDSHAKE_DISABLE;
325 }
326
327 pr_warn("can't get the mac of %x\n", value);
328 return 0;
329 }
330
vegam_update_uvd_smc_table(struct pp_hwmgr * hwmgr)331 static int vegam_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
332 {
333 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
334 uint32_t mm_boot_level_offset, mm_boot_level_value;
335 struct phm_ppt_v1_information *table_info =
336 (struct phm_ppt_v1_information *)(hwmgr->pptable);
337
338 smu_data->smc_state_table.UvdBootLevel = 0;
339 if (table_info->mm_dep_table->count > 0)
340 smu_data->smc_state_table.UvdBootLevel =
341 (uint8_t) (table_info->mm_dep_table->count - 1);
342 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU75_Discrete_DpmTable,
343 UvdBootLevel);
344 mm_boot_level_offset /= 4;
345 mm_boot_level_offset *= 4;
346 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
347 CGS_IND_REG__SMC, mm_boot_level_offset);
348 mm_boot_level_value &= 0x00FFFFFF;
349 mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;
350 cgs_write_ind_register(hwmgr->device,
351 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
352
353 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
354 PHM_PlatformCaps_UVDDPM) ||
355 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
356 PHM_PlatformCaps_StablePState))
357 smum_send_msg_to_smc_with_parameter(hwmgr,
358 PPSMC_MSG_UVDDPM_SetEnabledMask,
359 (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel),
360 NULL);
361 return 0;
362 }
363
vegam_update_vce_smc_table(struct pp_hwmgr * hwmgr)364 static int vegam_update_vce_smc_table(struct pp_hwmgr *hwmgr)
365 {
366 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
367 uint32_t mm_boot_level_offset, mm_boot_level_value;
368 struct phm_ppt_v1_information *table_info =
369 (struct phm_ppt_v1_information *)(hwmgr->pptable);
370
371 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
372 PHM_PlatformCaps_StablePState))
373 smu_data->smc_state_table.VceBootLevel =
374 (uint8_t) (table_info->mm_dep_table->count - 1);
375 else
376 smu_data->smc_state_table.VceBootLevel = 0;
377
378 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
379 offsetof(SMU75_Discrete_DpmTable, VceBootLevel);
380 mm_boot_level_offset /= 4;
381 mm_boot_level_offset *= 4;
382 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
383 CGS_IND_REG__SMC, mm_boot_level_offset);
384 mm_boot_level_value &= 0xFF00FFFF;
385 mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;
386 cgs_write_ind_register(hwmgr->device,
387 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
388
389 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
390 smum_send_msg_to_smc_with_parameter(hwmgr,
391 PPSMC_MSG_VCEDPM_SetEnabledMask,
392 (uint32_t)1 << smu_data->smc_state_table.VceBootLevel,
393 NULL);
394 return 0;
395 }
396
vegam_update_bif_smc_table(struct pp_hwmgr * hwmgr)397 static int vegam_update_bif_smc_table(struct pp_hwmgr *hwmgr)
398 {
399 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
400 struct phm_ppt_v1_information *table_info =
401 (struct phm_ppt_v1_information *)(hwmgr->pptable);
402 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
403 int max_entry, i;
404
405 max_entry = (SMU75_MAX_LEVELS_LINK < pcie_table->count) ?
406 SMU75_MAX_LEVELS_LINK :
407 pcie_table->count;
408 /* Setup BIF_SCLK levels */
409 for (i = 0; i < max_entry; i++)
410 smu_data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk;
411 return 0;
412 }
413
vegam_update_smc_table(struct pp_hwmgr * hwmgr,uint32_t type)414 static int vegam_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
415 {
416 switch (type) {
417 case SMU_UVD_TABLE:
418 vegam_update_uvd_smc_table(hwmgr);
419 break;
420 case SMU_VCE_TABLE:
421 vegam_update_vce_smc_table(hwmgr);
422 break;
423 case SMU_BIF_TABLE:
424 vegam_update_bif_smc_table(hwmgr);
425 break;
426 default:
427 break;
428 }
429 return 0;
430 }
431
vegam_initialize_power_tune_defaults(struct pp_hwmgr * hwmgr)432 static void vegam_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
433 {
434 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
435 struct phm_ppt_v1_information *table_info =
436 (struct phm_ppt_v1_information *)(hwmgr->pptable);
437
438 if (table_info &&
439 table_info->cac_dtp_table->usPowerTuneDataSetID <= POWERTUNE_DEFAULT_SET_MAX &&
440 table_info->cac_dtp_table->usPowerTuneDataSetID)
441 smu_data->power_tune_defaults =
442 &vegam_power_tune_data_set_array
443 [table_info->cac_dtp_table->usPowerTuneDataSetID - 1];
444 else
445 smu_data->power_tune_defaults = &vegam_power_tune_data_set_array[0];
446
447 }
448
vegam_populate_smc_mvdd_table(struct pp_hwmgr * hwmgr,SMU75_Discrete_DpmTable * table)449 static int vegam_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
450 SMU75_Discrete_DpmTable *table)
451 {
452 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
453 uint32_t count, level;
454
455 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
456 count = data->mvdd_voltage_table.count;
457 if (count > SMU_MAX_SMIO_LEVELS)
458 count = SMU_MAX_SMIO_LEVELS;
459 for (level = 0; level < count; level++) {
460 table->SmioTable2.Pattern[level].Voltage = PP_HOST_TO_SMC_US(
461 data->mvdd_voltage_table.entries[level].value * VOLTAGE_SCALE);
462 /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
463 table->SmioTable2.Pattern[level].Smio =
464 (uint8_t) level;
465 table->Smio[level] |=
466 data->mvdd_voltage_table.entries[level].smio_low;
467 }
468 table->SmioMask2 = data->mvdd_voltage_table.mask_low;
469
470 table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);
471 }
472
473 return 0;
474 }
475
vegam_populate_smc_vddci_table(struct pp_hwmgr * hwmgr,struct SMU75_Discrete_DpmTable * table)476 static int vegam_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
477 struct SMU75_Discrete_DpmTable *table)
478 {
479 uint32_t count, level;
480 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
481
482 count = data->vddci_voltage_table.count;
483
484 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
485 if (count > SMU_MAX_SMIO_LEVELS)
486 count = SMU_MAX_SMIO_LEVELS;
487 for (level = 0; level < count; ++level) {
488 table->SmioTable1.Pattern[level].Voltage = PP_HOST_TO_SMC_US(
489 data->vddci_voltage_table.entries[level].value * VOLTAGE_SCALE);
490 table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
491
492 table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;
493 }
494 }
495
496 table->SmioMask1 = data->vddci_voltage_table.mask_low;
497
498 return 0;
499 }
500
vegam_populate_cac_table(struct pp_hwmgr * hwmgr,struct SMU75_Discrete_DpmTable * table)501 static int vegam_populate_cac_table(struct pp_hwmgr *hwmgr,
502 struct SMU75_Discrete_DpmTable *table)
503 {
504 uint32_t count;
505 uint8_t index;
506 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
507 struct phm_ppt_v1_information *table_info =
508 (struct phm_ppt_v1_information *)(hwmgr->pptable);
509 struct phm_ppt_v1_voltage_lookup_table *lookup_table =
510 table_info->vddc_lookup_table;
511 /* tables is already swapped, so in order to use the value from it,
512 * we need to swap it back.
513 * We are populating vddc CAC data to BapmVddc table
514 * in split and merged mode
515 */
516 for (count = 0; count < lookup_table->count; count++) {
517 index = phm_get_voltage_index(lookup_table,
518 data->vddc_voltage_table.entries[count].value);
519 table->BapmVddcVidLoSidd[count] =
520 convert_to_vid(lookup_table->entries[index].us_cac_low);
521 table->BapmVddcVidHiSidd[count] =
522 convert_to_vid(lookup_table->entries[index].us_cac_mid);
523 table->BapmVddcVidHiSidd2[count] =
524 convert_to_vid(lookup_table->entries[index].us_cac_high);
525 }
526
527 return 0;
528 }
529
vegam_populate_smc_voltage_tables(struct pp_hwmgr * hwmgr,struct SMU75_Discrete_DpmTable * table)530 static int vegam_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
531 struct SMU75_Discrete_DpmTable *table)
532 {
533 vegam_populate_smc_vddci_table(hwmgr, table);
534 vegam_populate_smc_mvdd_table(hwmgr, table);
535 vegam_populate_cac_table(hwmgr, table);
536
537 return 0;
538 }
539
vegam_populate_ulv_level(struct pp_hwmgr * hwmgr,struct SMU75_Discrete_Ulv * state)540 static int vegam_populate_ulv_level(struct pp_hwmgr *hwmgr,
541 struct SMU75_Discrete_Ulv *state)
542 {
543 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
544 struct phm_ppt_v1_information *table_info =
545 (struct phm_ppt_v1_information *)(hwmgr->pptable);
546
547 state->CcPwrDynRm = 0;
548 state->CcPwrDynRm1 = 0;
549
550 state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
551 state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
552 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
553
554 state->VddcPhase = data->vddc_phase_shed_control ^ 0x3;
555
556 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
557 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
558 CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
559
560 return 0;
561 }
562
vegam_populate_ulv_state(struct pp_hwmgr * hwmgr,struct SMU75_Discrete_DpmTable * table)563 static int vegam_populate_ulv_state(struct pp_hwmgr *hwmgr,
564 struct SMU75_Discrete_DpmTable *table)
565 {
566 return vegam_populate_ulv_level(hwmgr, &table->Ulv);
567 }
568
vegam_populate_smc_link_level(struct pp_hwmgr * hwmgr,struct SMU75_Discrete_DpmTable * table)569 static int vegam_populate_smc_link_level(struct pp_hwmgr *hwmgr,
570 struct SMU75_Discrete_DpmTable *table)
571 {
572 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
573 struct vegam_smumgr *smu_data =
574 (struct vegam_smumgr *)(hwmgr->smu_backend);
575 struct smu7_dpm_table *dpm_table = &data->dpm_table;
576 int i;
577
578 /* Index (dpm_table->pcie_speed_table.count)
579 * is reserved for PCIE boot level. */
580 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
581 table->LinkLevel[i].PcieGenSpeed =
582 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
583 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
584 dpm_table->pcie_speed_table.dpm_levels[i].param1);
585 table->LinkLevel[i].EnabledForActivity = 1;
586 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
587 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
588 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
589 }
590
591 smu_data->smc_state_table.LinkLevelCount =
592 (uint8_t)dpm_table->pcie_speed_table.count;
593
594 /* To Do move to hwmgr */
595 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
596 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
597
598 return 0;
599 }
600
vegam_get_dependency_volt_by_clk(struct pp_hwmgr * hwmgr,struct phm_ppt_v1_clock_voltage_dependency_table * dep_table,uint32_t clock,SMU_VoltageLevel * voltage,uint32_t * mvdd)601 static int vegam_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
602 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
603 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
604 {
605 uint32_t i;
606 uint16_t vddci;
607 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
608
609 *voltage = *mvdd = 0;
610
611 /* clock - voltage dependency table is empty table */
612 if (dep_table->count == 0)
613 return -EINVAL;
614
615 for (i = 0; i < dep_table->count; i++) {
616 /* find first sclk bigger than request */
617 if (dep_table->entries[i].clk >= clock) {
618 *voltage |= (dep_table->entries[i].vddc *
619 VOLTAGE_SCALE) << VDDC_SHIFT;
620 if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
621 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
622 VOLTAGE_SCALE) << VDDCI_SHIFT;
623 else if (dep_table->entries[i].vddci)
624 *voltage |= (dep_table->entries[i].vddci *
625 VOLTAGE_SCALE) << VDDCI_SHIFT;
626 else {
627 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
628 (dep_table->entries[i].vddc -
629 (uint16_t)VDDC_VDDCI_DELTA));
630 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
631 }
632
633 if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control)
634 *mvdd = data->vbios_boot_state.mvdd_bootup_value *
635 VOLTAGE_SCALE;
636 else if (dep_table->entries[i].mvdd)
637 *mvdd = (uint32_t) dep_table->entries[i].mvdd *
638 VOLTAGE_SCALE;
639
640 *voltage |= 1 << PHASES_SHIFT;
641 return 0;
642 }
643 }
644
645 /* sclk is bigger than max sclk in the dependence table */
646 *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
647
648 if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
649 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
650 VOLTAGE_SCALE) << VDDCI_SHIFT;
651 else if (dep_table->entries[i - 1].vddci)
652 *voltage |= (dep_table->entries[i - 1].vddci *
653 VOLTAGE_SCALE) << VDDC_SHIFT;
654 else {
655 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
656 (dep_table->entries[i - 1].vddc -
657 (uint16_t)VDDC_VDDCI_DELTA));
658
659 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
660 }
661
662 if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control)
663 *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
664 else if (dep_table->entries[i].mvdd)
665 *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
666
667 return 0;
668 }
669
vegam_get_sclk_range_table(struct pp_hwmgr * hwmgr,SMU75_Discrete_DpmTable * table)670 static void vegam_get_sclk_range_table(struct pp_hwmgr *hwmgr,
671 SMU75_Discrete_DpmTable *table)
672 {
673 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
674 uint32_t i, ref_clk;
675
676 struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
677
678 ref_clk = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
679
680 if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
681 for (i = 0; i < NUM_SCLK_RANGE; i++) {
682 table->SclkFcwRangeTable[i].vco_setting =
683 range_table_from_vbios.entry[i].ucVco_setting;
684 table->SclkFcwRangeTable[i].postdiv =
685 range_table_from_vbios.entry[i].ucPostdiv;
686 table->SclkFcwRangeTable[i].fcw_pcc =
687 range_table_from_vbios.entry[i].usFcw_pcc;
688
689 table->SclkFcwRangeTable[i].fcw_trans_upper =
690 range_table_from_vbios.entry[i].usFcw_trans_upper;
691 table->SclkFcwRangeTable[i].fcw_trans_lower =
692 range_table_from_vbios.entry[i].usRcw_trans_lower;
693
694 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
695 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
696 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
697 }
698 return;
699 }
700
701 for (i = 0; i < NUM_SCLK_RANGE; i++) {
702 smu_data->range_table[i].trans_lower_frequency =
703 (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv;
704 smu_data->range_table[i].trans_upper_frequency =
705 (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv;
706
707 table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting;
708 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;
709 table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc;
710
711 table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper;
712 table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower;
713
714 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
715 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
716 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
717 }
718 }
719
vegam_calculate_sclk_params(struct pp_hwmgr * hwmgr,uint32_t clock,SMU_SclkSetting * sclk_setting)720 static int vegam_calculate_sclk_params(struct pp_hwmgr *hwmgr,
721 uint32_t clock, SMU_SclkSetting *sclk_setting)
722 {
723 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
724 const SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table);
725 struct pp_atomctrl_clock_dividers_ai dividers;
726 uint32_t ref_clock;
727 uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq;
728 uint8_t i;
729 int result;
730 uint64_t temp;
731
732 sclk_setting->SclkFrequency = clock;
733 /* get the engine clock dividers for this clock value */
734 result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, ÷rs);
735 if (result == 0) {
736 sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
737 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
738 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
739 sclk_setting->PllRange = dividers.ucSclkPllRange;
740 sclk_setting->Sclk_slew_rate = 0x400;
741 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
742 sclk_setting->Pcc_down_slew_rate = 0xffff;
743 sclk_setting->SSc_En = dividers.ucSscEnable;
744 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
745 sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
746 sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;
747 return result;
748 }
749
750 ref_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
751
752 for (i = 0; i < NUM_SCLK_RANGE; i++) {
753 if (clock > smu_data->range_table[i].trans_lower_frequency
754 && clock <= smu_data->range_table[i].trans_upper_frequency) {
755 sclk_setting->PllRange = i;
756 break;
757 }
758 }
759
760 sclk_setting->Fcw_int = (uint16_t)
761 ((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) /
762 ref_clock);
763 temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
764 temp <<= 0x10;
765 do_div(temp, ref_clock);
766 sclk_setting->Fcw_frac = temp & 0xffff;
767
768 pcc_target_percent = 10; /* Hardcode 10% for now. */
769 pcc_target_freq = clock - (clock * pcc_target_percent / 100);
770 sclk_setting->Pcc_fcw_int = (uint16_t)
771 ((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) /
772 ref_clock);
773
774 ss_target_percent = 2; /* Hardcode 2% for now. */
775 sclk_setting->SSc_En = 0;
776 if (ss_target_percent) {
777 sclk_setting->SSc_En = 1;
778 ss_target_freq = clock - (clock * ss_target_percent / 100);
779 sclk_setting->Fcw1_int = (uint16_t)
780 ((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) /
781 ref_clock);
782 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
783 temp <<= 0x10;
784 do_div(temp, ref_clock);
785 sclk_setting->Fcw1_frac = temp & 0xffff;
786 }
787
788 return 0;
789 }
790
vegam_get_sleep_divider_id_from_clock(uint32_t clock,uint32_t clock_insr)791 static uint8_t vegam_get_sleep_divider_id_from_clock(uint32_t clock,
792 uint32_t clock_insr)
793 {
794 uint8_t i;
795 uint32_t temp;
796 uint32_t min = max(clock_insr, (uint32_t)SMU7_MINIMUM_ENGINE_CLOCK);
797
798 PP_ASSERT_WITH_CODE((clock >= min),
799 "Engine clock can't satisfy stutter requirement!",
800 return 0);
801 for (i = 31; ; i--) {
802 temp = clock / (i + 1);
803
804 if (temp >= min || i == 0)
805 break;
806 }
807 return i;
808 }
809
vegam_populate_single_graphic_level(struct pp_hwmgr * hwmgr,uint32_t clock,struct SMU75_Discrete_GraphicsLevel * level)810 static int vegam_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
811 uint32_t clock, struct SMU75_Discrete_GraphicsLevel *level)
812 {
813 int result;
814 /* PP_Clocks minClocks; */
815 uint32_t mvdd;
816 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
817 struct phm_ppt_v1_information *table_info =
818 (struct phm_ppt_v1_information *)(hwmgr->pptable);
819 SMU_SclkSetting curr_sclk_setting = { 0 };
820
821 result = vegam_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
822
823 /* populate graphics levels */
824 result = vegam_get_dependency_volt_by_clk(hwmgr,
825 table_info->vdd_dep_on_sclk, clock,
826 &level->MinVoltage, &mvdd);
827
828 PP_ASSERT_WITH_CODE((0 == result),
829 "can not find VDDC voltage value for "
830 "VDDC engine clock dependency table",
831 return result);
832 level->ActivityLevel = (uint16_t)(SclkDPMTuning_VEGAM >> DPMTuning_Activity_Shift);
833
834 level->CcPwrDynRm = 0;
835 level->CcPwrDynRm1 = 0;
836 level->EnabledForActivity = 0;
837 level->EnabledForThrottle = 1;
838 level->VoltageDownHyst = 0;
839 level->PowerThrottle = 0;
840 data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr;
841
842 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
843 level->DeepSleepDivId = vegam_get_sleep_divider_id_from_clock(clock,
844 hwmgr->display_config->min_core_set_clock_in_sr);
845
846 level->SclkSetting = curr_sclk_setting;
847
848 CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
849 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
850 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
851 CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
852 CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency);
853 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int);
854 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac);
855 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int);
856 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate);
857 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate);
858 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate);
859 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int);
860 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac);
861 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate);
862 return 0;
863 }
864
vegam_populate_all_graphic_levels(struct pp_hwmgr * hwmgr)865 static int vegam_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
866 {
867 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
868 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
869 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
870 struct phm_ppt_v1_information *table_info =
871 (struct phm_ppt_v1_information *)(hwmgr->pptable);
872 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
873 uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count;
874 int result = 0;
875 uint32_t array = smu_data->smu7_data.dpm_table_start +
876 offsetof(SMU75_Discrete_DpmTable, GraphicsLevel);
877 uint32_t array_size = sizeof(struct SMU75_Discrete_GraphicsLevel) *
878 SMU75_MAX_LEVELS_GRAPHICS;
879 struct SMU75_Discrete_GraphicsLevel *levels =
880 smu_data->smc_state_table.GraphicsLevel;
881 uint32_t i, max_entry;
882 uint8_t hightest_pcie_level_enabled = 0,
883 lowest_pcie_level_enabled = 0,
884 mid_pcie_level_enabled = 0,
885 count = 0;
886
887 vegam_get_sclk_range_table(hwmgr, &(smu_data->smc_state_table));
888
889 for (i = 0; i < dpm_table->sclk_table.count; i++) {
890
891 result = vegam_populate_single_graphic_level(hwmgr,
892 dpm_table->sclk_table.dpm_levels[i].value,
893 &(smu_data->smc_state_table.GraphicsLevel[i]));
894 if (result)
895 return result;
896
897 levels[i].UpHyst = (uint8_t)
898 (SclkDPMTuning_VEGAM >> DPMTuning_Uphyst_Shift);
899 levels[i].DownHyst = (uint8_t)
900 (SclkDPMTuning_VEGAM >> DPMTuning_Downhyst_Shift);
901 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
902 if (i > 1)
903 levels[i].DeepSleepDivId = 0;
904 }
905 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
906 PHM_PlatformCaps_SPLLShutdownSupport))
907 smu_data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
908
909 smu_data->smc_state_table.GraphicsDpmLevelCount =
910 (uint8_t)dpm_table->sclk_table.count;
911 hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask =
912 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
913
914 for (i = 0; i < dpm_table->sclk_table.count; i++)
915 levels[i].EnabledForActivity =
916 (hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask >> i) & 0x1;
917
918 if (pcie_table != NULL) {
919 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
920 "There must be 1 or more PCIE levels defined in PPTable.",
921 return -EINVAL);
922 max_entry = pcie_entry_cnt - 1;
923 for (i = 0; i < dpm_table->sclk_table.count; i++)
924 levels[i].pcieDpmLevel =
925 (uint8_t) ((i < max_entry) ? i : max_entry);
926 } else {
927 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
928 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
929 (1 << (hightest_pcie_level_enabled + 1))) != 0))
930 hightest_pcie_level_enabled++;
931
932 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
933 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
934 (1 << lowest_pcie_level_enabled)) == 0))
935 lowest_pcie_level_enabled++;
936
937 while ((count < hightest_pcie_level_enabled) &&
938 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
939 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
940 count++;
941
942 mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
943 hightest_pcie_level_enabled ?
944 (lowest_pcie_level_enabled + 1 + count) :
945 hightest_pcie_level_enabled;
946
947 /* set pcieDpmLevel to hightest_pcie_level_enabled */
948 for (i = 2; i < dpm_table->sclk_table.count; i++)
949 levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
950
951 /* set pcieDpmLevel to lowest_pcie_level_enabled */
952 levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
953
954 /* set pcieDpmLevel to mid_pcie_level_enabled */
955 levels[1].pcieDpmLevel = mid_pcie_level_enabled;
956 }
957 /* level count will send to smc once at init smc table and never change */
958 result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
959 (uint32_t)array_size, SMC_RAM_END);
960
961 return result;
962 }
963
vegam_calculate_mclk_params(struct pp_hwmgr * hwmgr,uint32_t clock,struct SMU75_Discrete_MemoryLevel * mem_level)964 static int vegam_calculate_mclk_params(struct pp_hwmgr *hwmgr,
965 uint32_t clock, struct SMU75_Discrete_MemoryLevel *mem_level)
966 {
967 struct pp_atomctrl_memory_clock_param_ai mpll_param;
968
969 PP_ASSERT_WITH_CODE(!atomctrl_get_memory_pll_dividers_ai(hwmgr,
970 clock, &mpll_param),
971 "Failed to retrieve memory pll parameter.",
972 return -EINVAL);
973
974 mem_level->MclkFrequency = (uint32_t)mpll_param.ulClock;
975 mem_level->Fcw_int = (uint16_t)mpll_param.ulMclk_fcw_int;
976 mem_level->Fcw_frac = (uint16_t)mpll_param.ulMclk_fcw_frac;
977 mem_level->Postdiv = (uint8_t)mpll_param.ulPostDiv;
978
979 return 0;
980 }
981
vegam_populate_single_memory_level(struct pp_hwmgr * hwmgr,uint32_t clock,struct SMU75_Discrete_MemoryLevel * mem_level)982 static int vegam_populate_single_memory_level(struct pp_hwmgr *hwmgr,
983 uint32_t clock, struct SMU75_Discrete_MemoryLevel *mem_level)
984 {
985 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
986 struct phm_ppt_v1_information *table_info =
987 (struct phm_ppt_v1_information *)(hwmgr->pptable);
988 int result = 0;
989 uint32_t mclk_stutter_mode_threshold = 60000;
990
991
992 if (table_info->vdd_dep_on_mclk) {
993 result = vegam_get_dependency_volt_by_clk(hwmgr,
994 table_info->vdd_dep_on_mclk, clock,
995 &mem_level->MinVoltage, &mem_level->MinMvdd);
996 PP_ASSERT_WITH_CODE(!result,
997 "can not find MinVddc voltage value from memory "
998 "VDDC voltage dependency table", return result);
999 }
1000
1001 result = vegam_calculate_mclk_params(hwmgr, clock, mem_level);
1002 PP_ASSERT_WITH_CODE(!result,
1003 "Failed to calculate mclk params.",
1004 return -EINVAL);
1005
1006 mem_level->EnabledForThrottle = 1;
1007 mem_level->EnabledForActivity = 0;
1008 mem_level->VoltageDownHyst = 0;
1009 mem_level->ActivityLevel = (uint16_t)
1010 (MemoryDPMTuning_VEGAM >> DPMTuning_Activity_Shift);
1011 mem_level->StutterEnable = false;
1012 mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1013
1014 data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
1015 data->display_timing.vrefresh = hwmgr->display_config->vrefresh;
1016
1017 if (mclk_stutter_mode_threshold &&
1018 (clock <= mclk_stutter_mode_threshold) &&
1019 (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
1020 STUTTER_ENABLE) & 0x1))
1021 mem_level->StutterEnable = true;
1022
1023 if (!result) {
1024 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
1025 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
1026 CONVERT_FROM_HOST_TO_SMC_US(mem_level->Fcw_int);
1027 CONVERT_FROM_HOST_TO_SMC_US(mem_level->Fcw_frac);
1028 CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
1029 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
1030 }
1031
1032 return result;
1033 }
1034
vegam_populate_all_memory_levels(struct pp_hwmgr * hwmgr)1035 static int vegam_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1036 {
1037 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1038 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1039 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
1040 int result;
1041 /* populate MCLK dpm table to SMU7 */
1042 uint32_t array = smu_data->smu7_data.dpm_table_start +
1043 offsetof(SMU75_Discrete_DpmTable, MemoryLevel);
1044 uint32_t array_size = sizeof(SMU75_Discrete_MemoryLevel) *
1045 SMU75_MAX_LEVELS_MEMORY;
1046 struct SMU75_Discrete_MemoryLevel *levels =
1047 smu_data->smc_state_table.MemoryLevel;
1048 uint32_t i;
1049
1050 for (i = 0; i < dpm_table->mclk_table.count; i++) {
1051 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
1052 "can not populate memory level as memory clock is zero",
1053 return -EINVAL);
1054 result = vegam_populate_single_memory_level(hwmgr,
1055 dpm_table->mclk_table.dpm_levels[i].value,
1056 &levels[i]);
1057
1058 if (result)
1059 return result;
1060
1061 levels[i].UpHyst = (uint8_t)
1062 (MemoryDPMTuning_VEGAM >> DPMTuning_Uphyst_Shift);
1063 levels[i].DownHyst = (uint8_t)
1064 (MemoryDPMTuning_VEGAM >> DPMTuning_Downhyst_Shift);
1065 }
1066
1067 smu_data->smc_state_table.MemoryDpmLevelCount =
1068 (uint8_t)dpm_table->mclk_table.count;
1069 hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask =
1070 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
1071
1072 for (i = 0; i < dpm_table->mclk_table.count; i++)
1073 levels[i].EnabledForActivity =
1074 (hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask >> i) & 0x1;
1075
1076 levels[dpm_table->mclk_table.count - 1].DisplayWatermark =
1077 PPSMC_DISPLAY_WATERMARK_HIGH;
1078
1079 /* level count will send to smc once at init smc table and never change */
1080 result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
1081 (uint32_t)array_size, SMC_RAM_END);
1082
1083 return result;
1084 }
1085
vegam_populate_mvdd_value(struct pp_hwmgr * hwmgr,uint32_t mclk,SMIO_Pattern * smio_pat)1086 static int vegam_populate_mvdd_value(struct pp_hwmgr *hwmgr,
1087 uint32_t mclk, SMIO_Pattern *smio_pat)
1088 {
1089 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1090 struct phm_ppt_v1_information *table_info =
1091 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1092 uint32_t i = 0;
1093
1094 if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
1095 /* find mvdd value which clock is more than request */
1096 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
1097 if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
1098 smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
1099 break;
1100 }
1101 }
1102 PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
1103 "MVDD Voltage is outside the supported range.",
1104 return -EINVAL);
1105 } else
1106 return -EINVAL;
1107
1108 return 0;
1109 }
1110
vegam_populate_smc_acpi_level(struct pp_hwmgr * hwmgr,SMU75_Discrete_DpmTable * table)1111 static int vegam_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
1112 SMU75_Discrete_DpmTable *table)
1113 {
1114 int result = 0;
1115 uint32_t sclk_frequency;
1116 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1117 struct phm_ppt_v1_information *table_info =
1118 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1119 SMIO_Pattern vol_level;
1120 uint32_t mvdd;
1121
1122 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1123
1124 /* Get MinVoltage and Frequency from DPM0,
1125 * already converted to SMC_UL */
1126 sclk_frequency = data->vbios_boot_state.sclk_bootup_value;
1127 result = vegam_get_dependency_volt_by_clk(hwmgr,
1128 table_info->vdd_dep_on_sclk,
1129 sclk_frequency,
1130 &table->ACPILevel.MinVoltage, &mvdd);
1131 PP_ASSERT_WITH_CODE(!result,
1132 "Cannot find ACPI VDDC voltage value "
1133 "in Clock Dependency Table",
1134 );
1135
1136 result = vegam_calculate_sclk_params(hwmgr, sclk_frequency,
1137 &(table->ACPILevel.SclkSetting));
1138 PP_ASSERT_WITH_CODE(!result,
1139 "Error retrieving Engine Clock dividers from VBIOS.",
1140 return result);
1141
1142 table->ACPILevel.DeepSleepDivId = 0;
1143 table->ACPILevel.CcPwrDynRm = 0;
1144 table->ACPILevel.CcPwrDynRm1 = 0;
1145
1146 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1147 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
1148 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1149 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
1150
1151 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency);
1152 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);
1153 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);
1154 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);
1155 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate);
1156 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate);
1157 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate);
1158 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);
1159 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
1160 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);
1161
1162
1163 /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
1164 table->MemoryACPILevel.MclkFrequency = data->vbios_boot_state.mclk_bootup_value;
1165 result = vegam_get_dependency_volt_by_clk(hwmgr,
1166 table_info->vdd_dep_on_mclk,
1167 table->MemoryACPILevel.MclkFrequency,
1168 &table->MemoryACPILevel.MinVoltage, &mvdd);
1169 PP_ASSERT_WITH_CODE((0 == result),
1170 "Cannot find ACPI VDDCI voltage value "
1171 "in Clock Dependency Table",
1172 );
1173
1174 if (!vegam_populate_mvdd_value(hwmgr, 0, &vol_level))
1175 table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);
1176 else
1177 table->MemoryACPILevel.MinMvdd = 0;
1178
1179 table->MemoryACPILevel.StutterEnable = false;
1180
1181 table->MemoryACPILevel.EnabledForThrottle = 0;
1182 table->MemoryACPILevel.EnabledForActivity = 0;
1183 table->MemoryACPILevel.UpHyst = 0;
1184 table->MemoryACPILevel.DownHyst = 100;
1185 table->MemoryACPILevel.VoltageDownHyst = 0;
1186 table->MemoryACPILevel.ActivityLevel =
1187 PP_HOST_TO_SMC_US(data->current_profile_setting.mclk_activity);
1188
1189 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
1190 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
1191
1192 return result;
1193 }
1194
vegam_populate_smc_vce_level(struct pp_hwmgr * hwmgr,SMU75_Discrete_DpmTable * table)1195 static int vegam_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1196 SMU75_Discrete_DpmTable *table)
1197 {
1198 int result = -EINVAL;
1199 uint8_t count;
1200 struct pp_atomctrl_clock_dividers_vi dividers;
1201 struct phm_ppt_v1_information *table_info =
1202 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1203 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1204 table_info->mm_dep_table;
1205 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1206 uint32_t vddci;
1207
1208 table->VceLevelCount = (uint8_t)(mm_table->count);
1209 table->VceBootLevel = 0;
1210
1211 for (count = 0; count < table->VceLevelCount; count++) {
1212 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
1213 table->VceLevel[count].MinVoltage = 0;
1214 table->VceLevel[count].MinVoltage |=
1215 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1216
1217 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1218 vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1219 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1220 else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1221 vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1222 else
1223 vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1224
1225
1226 table->VceLevel[count].MinVoltage |=
1227 (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1228 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1229
1230 /*retrieve divider value for VBIOS */
1231 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1232 table->VceLevel[count].Frequency, ÷rs);
1233 PP_ASSERT_WITH_CODE((0 == result),
1234 "can not find divide id for VCE engine clock",
1235 return result);
1236
1237 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1238
1239 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1240 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
1241 }
1242 return result;
1243 }
1244
vegam_populate_memory_timing_parameters(struct pp_hwmgr * hwmgr,int32_t eng_clock,int32_t mem_clock,SMU75_Discrete_MCArbDramTimingTableEntry * arb_regs)1245 static int vegam_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
1246 int32_t eng_clock, int32_t mem_clock,
1247 SMU75_Discrete_MCArbDramTimingTableEntry *arb_regs)
1248 {
1249 uint32_t dram_timing;
1250 uint32_t dram_timing2;
1251 uint32_t burst_time;
1252 uint32_t rfsh_rate;
1253 uint32_t misc3;
1254
1255 int result;
1256
1257 result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1258 eng_clock, mem_clock);
1259 PP_ASSERT_WITH_CODE(result == 0,
1260 "Error calling VBIOS to set DRAM_TIMING.",
1261 return result);
1262
1263 dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1264 dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1265 burst_time = cgs_read_register(hwmgr->device, mmMC_ARB_BURST_TIME);
1266 rfsh_rate = cgs_read_register(hwmgr->device, mmMC_ARB_RFSH_RATE);
1267 misc3 = cgs_read_register(hwmgr->device, mmMC_ARB_MISC3);
1268
1269 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing);
1270 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
1271 arb_regs->McArbBurstTime = PP_HOST_TO_SMC_UL(burst_time);
1272 arb_regs->McArbRfshRate = PP_HOST_TO_SMC_UL(rfsh_rate);
1273 arb_regs->McArbMisc3 = PP_HOST_TO_SMC_UL(misc3);
1274
1275 return 0;
1276 }
1277
vegam_program_memory_timing_parameters(struct pp_hwmgr * hwmgr)1278 static int vegam_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1279 {
1280 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1281 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1282 struct SMU75_Discrete_MCArbDramTimingTable arb_regs;
1283 uint32_t i, j;
1284 int result = 0;
1285
1286 memset(&arb_regs, 0, sizeof(SMU75_Discrete_MCArbDramTimingTable));
1287
1288 for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) {
1289 for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) {
1290 result = vegam_populate_memory_timing_parameters(hwmgr,
1291 hw_data->dpm_table.sclk_table.dpm_levels[i].value,
1292 hw_data->dpm_table.mclk_table.dpm_levels[j].value,
1293 &arb_regs.entries[i][j]);
1294 if (result)
1295 return result;
1296 }
1297 }
1298
1299 result = smu7_copy_bytes_to_smc(
1300 hwmgr,
1301 smu_data->smu7_data.arb_table_start,
1302 (uint8_t *)&arb_regs,
1303 sizeof(SMU75_Discrete_MCArbDramTimingTable),
1304 SMC_RAM_END);
1305 return result;
1306 }
1307
vegam_populate_smc_uvd_level(struct pp_hwmgr * hwmgr,struct SMU75_Discrete_DpmTable * table)1308 static int vegam_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1309 struct SMU75_Discrete_DpmTable *table)
1310 {
1311 int result = -EINVAL;
1312 uint8_t count;
1313 struct pp_atomctrl_clock_dividers_vi dividers;
1314 struct phm_ppt_v1_information *table_info =
1315 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1316 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1317 table_info->mm_dep_table;
1318 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1319 uint32_t vddci;
1320
1321 table->UvdLevelCount = (uint8_t)(mm_table->count);
1322 table->UvdBootLevel = 0;
1323
1324 for (count = 0; count < table->UvdLevelCount; count++) {
1325 table->UvdLevel[count].MinVoltage = 0;
1326 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1327 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1328 table->UvdLevel[count].MinVoltage |=
1329 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1330
1331 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1332 vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1333 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1334 else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1335 vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1336 else
1337 vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1338
1339 table->UvdLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1340 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1341
1342 /* retrieve divider value for VBIOS */
1343 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1344 table->UvdLevel[count].VclkFrequency, ÷rs);
1345 PP_ASSERT_WITH_CODE((0 == result),
1346 "can not find divide id for Vclk clock", return result);
1347
1348 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1349
1350 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1351 table->UvdLevel[count].DclkFrequency, ÷rs);
1352 PP_ASSERT_WITH_CODE((0 == result),
1353 "can not find divide id for Dclk clock", return result);
1354
1355 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1356
1357 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1358 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1359 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
1360 }
1361
1362 return result;
1363 }
1364
vegam_populate_smc_boot_level(struct pp_hwmgr * hwmgr,struct SMU75_Discrete_DpmTable * table)1365 static int vegam_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1366 struct SMU75_Discrete_DpmTable *table)
1367 {
1368 int result = 0;
1369 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1370
1371 table->GraphicsBootLevel = 0;
1372 table->MemoryBootLevel = 0;
1373
1374 /* find boot level from dpm table */
1375 result = phm_find_boot_level(&(data->dpm_table.sclk_table),
1376 data->vbios_boot_state.sclk_bootup_value,
1377 (uint32_t *)&(table->GraphicsBootLevel));
1378 if (result)
1379 return result;
1380
1381 result = phm_find_boot_level(&(data->dpm_table.mclk_table),
1382 data->vbios_boot_state.mclk_bootup_value,
1383 (uint32_t *)&(table->MemoryBootLevel));
1384
1385 if (result)
1386 return result;
1387
1388 table->BootVddc = data->vbios_boot_state.vddc_bootup_value *
1389 VOLTAGE_SCALE;
1390 table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
1391 VOLTAGE_SCALE;
1392 table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value *
1393 VOLTAGE_SCALE;
1394
1395 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
1396 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
1397 CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
1398
1399 return 0;
1400 }
1401
vegam_populate_smc_initial_state(struct pp_hwmgr * hwmgr)1402 static int vegam_populate_smc_initial_state(struct pp_hwmgr *hwmgr)
1403 {
1404 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1405 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1406 struct phm_ppt_v1_information *table_info =
1407 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1408 uint8_t count, level;
1409
1410 count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
1411
1412 for (level = 0; level < count; level++) {
1413 if (table_info->vdd_dep_on_sclk->entries[level].clk >=
1414 hw_data->vbios_boot_state.sclk_bootup_value) {
1415 smu_data->smc_state_table.GraphicsBootLevel = level;
1416 break;
1417 }
1418 }
1419
1420 count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
1421 for (level = 0; level < count; level++) {
1422 if (table_info->vdd_dep_on_mclk->entries[level].clk >=
1423 hw_data->vbios_boot_state.mclk_bootup_value) {
1424 smu_data->smc_state_table.MemoryBootLevel = level;
1425 break;
1426 }
1427 }
1428
1429 return 0;
1430 }
1431
scale_fan_gain_settings(uint16_t raw_setting)1432 static uint16_t scale_fan_gain_settings(uint16_t raw_setting)
1433 {
1434 uint32_t tmp;
1435 tmp = raw_setting * 4096 / 100;
1436 return (uint16_t)tmp;
1437 }
1438
vegam_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr * hwmgr)1439 static int vegam_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
1440 {
1441 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1442
1443 const struct vegam_pt_defaults *defaults = smu_data->power_tune_defaults;
1444 SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1445 struct phm_ppt_v1_information *table_info =
1446 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1447 struct phm_cac_tdp_table *cac_dtp_table = table_info->cac_dtp_table;
1448 struct pp_advance_fan_control_parameters *fan_table =
1449 &hwmgr->thermal_controller.advanceFanControlParameters;
1450 int i, j, k;
1451 const uint16_t *pdef1;
1452 const uint16_t *pdef2;
1453
1454 table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));
1455 table->TargetTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));
1456
1457 PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255,
1458 "Target Operating Temp is out of Range!",
1459 );
1460
1461 table->TemperatureLimitEdge = PP_HOST_TO_SMC_US(
1462 cac_dtp_table->usTargetOperatingTemp * 256);
1463 table->TemperatureLimitHotspot = PP_HOST_TO_SMC_US(
1464 cac_dtp_table->usTemperatureLimitHotspot * 256);
1465 table->FanGainEdge = PP_HOST_TO_SMC_US(
1466 scale_fan_gain_settings(fan_table->usFanGainEdge));
1467 table->FanGainHotspot = PP_HOST_TO_SMC_US(
1468 scale_fan_gain_settings(fan_table->usFanGainHotspot));
1469
1470 pdef1 = defaults->BAPMTI_R;
1471 pdef2 = defaults->BAPMTI_RC;
1472
1473 for (i = 0; i < SMU75_DTE_ITERATIONS; i++) {
1474 for (j = 0; j < SMU75_DTE_SOURCES; j++) {
1475 for (k = 0; k < SMU75_DTE_SINKS; k++) {
1476 table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*pdef1);
1477 table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*pdef2);
1478 pdef1++;
1479 pdef2++;
1480 }
1481 }
1482 }
1483
1484 return 0;
1485 }
1486
vegam_populate_clock_stretcher_data_table(struct pp_hwmgr * hwmgr)1487 static int vegam_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
1488 {
1489 uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min;
1490 struct vegam_smumgr *smu_data =
1491 (struct vegam_smumgr *)(hwmgr->smu_backend);
1492
1493 uint8_t i, stretch_amount, volt_offset = 0;
1494 struct phm_ppt_v1_information *table_info =
1495 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1496 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1497 table_info->vdd_dep_on_sclk;
1498
1499 stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
1500
1501 atomctrl_read_efuse(hwmgr, STRAP_ASIC_RO_LSB, STRAP_ASIC_RO_MSB,
1502 &efuse);
1503
1504 min = 1200;
1505 max = 2500;
1506
1507 ro = efuse * (max - min) / 255 + min;
1508
1509 /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
1510 for (i = 0; i < sclk_table->count; i++) {
1511 smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |=
1512 sclk_table->entries[i].cks_enable << i;
1513 volt_without_cks = (uint32_t)((2753594000U + (sclk_table->entries[i].clk/100) *
1514 136418 - (ro - 70) * 1000000) /
1515 (2424180 - (sclk_table->entries[i].clk/100) * 1132925/1000));
1516 volt_with_cks = (uint32_t)((2797202000U + sclk_table->entries[i].clk/100 *
1517 3232 - (ro - 65) * 1000000) /
1518 (2522480 - sclk_table->entries[i].clk/100 * 115764/100));
1519
1520 if (volt_without_cks >= volt_with_cks)
1521 volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
1522 sclk_table->entries[i].cks_voffset) * 100 + 624) / 625);
1523
1524 smu_data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
1525 }
1526
1527 smu_data->smc_state_table.LdoRefSel =
1528 (table_info->cac_dtp_table->ucCKS_LDO_REFSEL != 0) ?
1529 table_info->cac_dtp_table->ucCKS_LDO_REFSEL : 5;
1530 /* Populate CKS Lookup Table */
1531 if (!(stretch_amount == 1 || stretch_amount == 2 ||
1532 stretch_amount == 5 || stretch_amount == 3 ||
1533 stretch_amount == 4)) {
1534 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1535 PHM_PlatformCaps_ClockStretcher);
1536 PP_ASSERT_WITH_CODE(false,
1537 "Stretch Amount in PPTable not supported\n",
1538 return -EINVAL);
1539 }
1540
1541 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
1542 value &= 0xFFFFFFFE;
1543 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
1544
1545 return 0;
1546 }
1547
vegam_is_hw_avfs_present(struct pp_hwmgr * hwmgr)1548 static bool vegam_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
1549 {
1550 uint32_t efuse;
1551
1552 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1553 ixSMU_EFUSE_0 + (49 * 4));
1554 efuse &= 0x00000001;
1555
1556 if (efuse)
1557 return true;
1558
1559 return false;
1560 }
1561
vegam_populate_avfs_parameters(struct pp_hwmgr * hwmgr)1562 static int vegam_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
1563 {
1564 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1565 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1566
1567 SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1568 int result = 0;
1569 struct pp_atom_ctrl__avfs_parameters avfs_params = {0};
1570 AVFS_meanNsigma_t AVFS_meanNsigma = { {0} };
1571 AVFS_Sclk_Offset_t AVFS_SclkOffset = { {0} };
1572 uint32_t tmp, i;
1573
1574 struct phm_ppt_v1_information *table_info =
1575 (struct phm_ppt_v1_information *)hwmgr->pptable;
1576 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1577 table_info->vdd_dep_on_sclk;
1578
1579 if (!hwmgr->avfs_supported)
1580 return 0;
1581
1582 result = atomctrl_get_avfs_information(hwmgr, &avfs_params);
1583
1584 if (0 == result) {
1585 table->BTCGB_VDROOP_TABLE[0].a0 =
1586 PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0);
1587 table->BTCGB_VDROOP_TABLE[0].a1 =
1588 PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1);
1589 table->BTCGB_VDROOP_TABLE[0].a2 =
1590 PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2);
1591 table->BTCGB_VDROOP_TABLE[1].a0 =
1592 PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0);
1593 table->BTCGB_VDROOP_TABLE[1].a1 =
1594 PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1);
1595 table->BTCGB_VDROOP_TABLE[1].a2 =
1596 PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2);
1597 table->AVFSGB_FUSE_TABLE[0].m1 =
1598 PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1);
1599 table->AVFSGB_FUSE_TABLE[0].m2 =
1600 PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSON_m2);
1601 table->AVFSGB_FUSE_TABLE[0].b =
1602 PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b);
1603 table->AVFSGB_FUSE_TABLE[0].m1_shift = 24;
1604 table->AVFSGB_FUSE_TABLE[0].m2_shift = 12;
1605 table->AVFSGB_FUSE_TABLE[1].m1 =
1606 PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1);
1607 table->AVFSGB_FUSE_TABLE[1].m2 =
1608 PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2);
1609 table->AVFSGB_FUSE_TABLE[1].b =
1610 PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b);
1611 table->AVFSGB_FUSE_TABLE[1].m1_shift = 24;
1612 table->AVFSGB_FUSE_TABLE[1].m2_shift = 12;
1613 table->MaxVoltage = PP_HOST_TO_SMC_US(avfs_params.usMaxVoltage_0_25mv);
1614 AVFS_meanNsigma.Aconstant[0] =
1615 PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant0);
1616 AVFS_meanNsigma.Aconstant[1] =
1617 PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant1);
1618 AVFS_meanNsigma.Aconstant[2] =
1619 PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant2);
1620 AVFS_meanNsigma.DC_tol_sigma =
1621 PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_DC_tol_sigma);
1622 AVFS_meanNsigma.Platform_mean =
1623 PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_mean);
1624 AVFS_meanNsigma.PSM_Age_CompFactor =
1625 PP_HOST_TO_SMC_US(avfs_params.usPSM_Age_ComFactor);
1626 AVFS_meanNsigma.Platform_sigma =
1627 PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_sigma);
1628
1629 for (i = 0; i < sclk_table->count; i++) {
1630 AVFS_meanNsigma.Static_Voltage_Offset[i] =
1631 (uint8_t)(sclk_table->entries[i].cks_voffset * 100 / 625);
1632 AVFS_SclkOffset.Sclk_Offset[i] =
1633 PP_HOST_TO_SMC_US((uint16_t)
1634 (sclk_table->entries[i].sclk_offset) / 100);
1635 }
1636
1637 result = smu7_read_smc_sram_dword(hwmgr,
1638 SMU7_FIRMWARE_HEADER_LOCATION +
1639 offsetof(SMU75_Firmware_Header, AvfsMeanNSigma),
1640 &tmp, SMC_RAM_END);
1641 smu7_copy_bytes_to_smc(hwmgr,
1642 tmp,
1643 (uint8_t *)&AVFS_meanNsigma,
1644 sizeof(AVFS_meanNsigma_t),
1645 SMC_RAM_END);
1646
1647 result = smu7_read_smc_sram_dword(hwmgr,
1648 SMU7_FIRMWARE_HEADER_LOCATION +
1649 offsetof(SMU75_Firmware_Header, AvfsSclkOffsetTable),
1650 &tmp, SMC_RAM_END);
1651 smu7_copy_bytes_to_smc(hwmgr,
1652 tmp,
1653 (uint8_t *)&AVFS_SclkOffset,
1654 sizeof(AVFS_Sclk_Offset_t),
1655 SMC_RAM_END);
1656
1657 data->avfs_vdroop_override_setting =
1658 (avfs_params.ucEnableGB_VDROOP_TABLE_CKSON << BTCGB0_Vdroop_Enable_SHIFT) |
1659 (avfs_params.ucEnableGB_VDROOP_TABLE_CKSOFF << BTCGB1_Vdroop_Enable_SHIFT) |
1660 (avfs_params.ucEnableGB_FUSE_TABLE_CKSON << AVFSGB0_Vdroop_Enable_SHIFT) |
1661 (avfs_params.ucEnableGB_FUSE_TABLE_CKSOFF << AVFSGB1_Vdroop_Enable_SHIFT);
1662 data->apply_avfs_cks_off_voltage =
1663 (avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage == 1) ? true : false;
1664 }
1665 return result;
1666 }
1667
vegam_populate_vr_config(struct pp_hwmgr * hwmgr,struct SMU75_Discrete_DpmTable * table)1668 static int vegam_populate_vr_config(struct pp_hwmgr *hwmgr,
1669 struct SMU75_Discrete_DpmTable *table)
1670 {
1671 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1672 struct vegam_smumgr *smu_data =
1673 (struct vegam_smumgr *)(hwmgr->smu_backend);
1674 uint16_t config;
1675
1676 config = VR_MERGED_WITH_VDDC;
1677 table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
1678
1679 /* Set Vddc Voltage Controller */
1680 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1681 config = VR_SVI2_PLANE_1;
1682 table->VRConfig |= config;
1683 } else {
1684 PP_ASSERT_WITH_CODE(false,
1685 "VDDC should be on SVI2 control in merged mode!",
1686 );
1687 }
1688 /* Set Vddci Voltage Controller */
1689 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
1690 config = VR_SVI2_PLANE_2; /* only in merged mode */
1691 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1692 } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
1693 config = VR_SMIO_PATTERN_1;
1694 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1695 } else {
1696 config = VR_STATIC_VOLTAGE;
1697 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1698 }
1699 /* Set Mvdd Voltage Controller */
1700 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
1701 if (config != VR_SVI2_PLANE_2) {
1702 config = VR_SVI2_PLANE_2;
1703 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1704 cgs_write_ind_register(hwmgr->device,
1705 CGS_IND_REG__SMC,
1706 smu_data->smu7_data.soft_regs_start +
1707 offsetof(SMU75_SoftRegisters, AllowMvddSwitch),
1708 0x1);
1709 } else {
1710 PP_ASSERT_WITH_CODE(false,
1711 "SVI2 Plane 2 is already taken, set MVDD as Static",);
1712 config = VR_STATIC_VOLTAGE;
1713 table->VRConfig = (config << VRCONF_MVDD_SHIFT);
1714 }
1715 } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1716 config = VR_SMIO_PATTERN_2;
1717 table->VRConfig = (config << VRCONF_MVDD_SHIFT);
1718 cgs_write_ind_register(hwmgr->device,
1719 CGS_IND_REG__SMC,
1720 smu_data->smu7_data.soft_regs_start +
1721 offsetof(SMU75_SoftRegisters, AllowMvddSwitch),
1722 0x1);
1723 } else {
1724 config = VR_STATIC_VOLTAGE;
1725 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1726 }
1727
1728 return 0;
1729 }
1730
vegam_populate_svi_load_line(struct pp_hwmgr * hwmgr)1731 static int vegam_populate_svi_load_line(struct pp_hwmgr *hwmgr)
1732 {
1733 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1734 const struct vegam_pt_defaults *defaults = smu_data->power_tune_defaults;
1735
1736 smu_data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn;
1737 smu_data->power_tune_table.SviLoadLineVddC = defaults->SviLoadLineVddC;
1738 smu_data->power_tune_table.SviLoadLineTrimVddC = 3;
1739 smu_data->power_tune_table.SviLoadLineOffsetVddC = 0;
1740
1741 return 0;
1742 }
1743
vegam_populate_tdc_limit(struct pp_hwmgr * hwmgr)1744 static int vegam_populate_tdc_limit(struct pp_hwmgr *hwmgr)
1745 {
1746 uint16_t tdc_limit;
1747 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1748 struct phm_ppt_v1_information *table_info =
1749 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1750 const struct vegam_pt_defaults *defaults = smu_data->power_tune_defaults;
1751
1752 tdc_limit = (uint16_t)(table_info->cac_dtp_table->usTDC * 128);
1753 smu_data->power_tune_table.TDC_VDDC_PkgLimit =
1754 CONVERT_FROM_HOST_TO_SMC_US(tdc_limit);
1755 smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
1756 defaults->TDC_VDDC_ThrottleReleaseLimitPerc;
1757 smu_data->power_tune_table.TDC_MAWt = defaults->TDC_MAWt;
1758
1759 return 0;
1760 }
1761
vegam_populate_dw8(struct pp_hwmgr * hwmgr,uint32_t fuse_table_offset)1762 static int vegam_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
1763 {
1764 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1765 const struct vegam_pt_defaults *defaults = smu_data->power_tune_defaults;
1766 uint32_t temp;
1767
1768 if (smu7_read_smc_sram_dword(hwmgr,
1769 fuse_table_offset +
1770 offsetof(SMU75_Discrete_PmFuses, TdcWaterfallCtl),
1771 (uint32_t *)&temp, SMC_RAM_END))
1772 PP_ASSERT_WITH_CODE(false,
1773 "Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!",
1774 return -EINVAL);
1775 else {
1776 smu_data->power_tune_table.TdcWaterfallCtl = defaults->TdcWaterfallCtl;
1777 smu_data->power_tune_table.LPMLTemperatureMin =
1778 (uint8_t)((temp >> 16) & 0xff);
1779 smu_data->power_tune_table.LPMLTemperatureMax =
1780 (uint8_t)((temp >> 8) & 0xff);
1781 smu_data->power_tune_table.Reserved = (uint8_t)(temp & 0xff);
1782 }
1783 return 0;
1784 }
1785
vegam_populate_temperature_scaler(struct pp_hwmgr * hwmgr)1786 static int vegam_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
1787 {
1788 int i;
1789 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1790
1791 /* Currently not used. Set all to zero. */
1792 for (i = 0; i < 16; i++)
1793 smu_data->power_tune_table.LPMLTemperatureScaler[i] = 0;
1794
1795 return 0;
1796 }
1797
vegam_populate_fuzzy_fan(struct pp_hwmgr * hwmgr)1798 static int vegam_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
1799 {
1800 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1801
1802 /* TO DO move to hwmgr */
1803 if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15))
1804 || 0 == hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity)
1805 hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
1806 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity;
1807
1808 smu_data->power_tune_table.FuzzyFan_PwmSetDelta = PP_HOST_TO_SMC_US(
1809 hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity);
1810 return 0;
1811 }
1812
vegam_populate_gnb_lpml(struct pp_hwmgr * hwmgr)1813 static int vegam_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
1814 {
1815 int i;
1816 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1817
1818 /* Currently not used. Set all to zero. */
1819 for (i = 0; i < 16; i++)
1820 smu_data->power_tune_table.GnbLPML[i] = 0;
1821
1822 return 0;
1823 }
1824
vegam_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr * hwmgr)1825 static int vegam_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
1826 {
1827 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1828 struct phm_ppt_v1_information *table_info =
1829 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1830 uint16_t hi_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
1831 uint16_t lo_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
1832 struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table;
1833
1834 hi_sidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
1835 lo_sidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256);
1836
1837 smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd =
1838 CONVERT_FROM_HOST_TO_SMC_US(hi_sidd);
1839 smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd =
1840 CONVERT_FROM_HOST_TO_SMC_US(lo_sidd);
1841
1842 return 0;
1843 }
1844
vegam_populate_pm_fuses(struct pp_hwmgr * hwmgr)1845 static int vegam_populate_pm_fuses(struct pp_hwmgr *hwmgr)
1846 {
1847 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1848 uint32_t pm_fuse_table_offset;
1849
1850 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1851 PHM_PlatformCaps_PowerContainment)) {
1852 if (smu7_read_smc_sram_dword(hwmgr,
1853 SMU7_FIRMWARE_HEADER_LOCATION +
1854 offsetof(SMU75_Firmware_Header, PmFuseTable),
1855 &pm_fuse_table_offset, SMC_RAM_END))
1856 PP_ASSERT_WITH_CODE(false,
1857 "Attempt to get pm_fuse_table_offset Failed!",
1858 return -EINVAL);
1859
1860 if (vegam_populate_svi_load_line(hwmgr))
1861 PP_ASSERT_WITH_CODE(false,
1862 "Attempt to populate SviLoadLine Failed!",
1863 return -EINVAL);
1864
1865 if (vegam_populate_tdc_limit(hwmgr))
1866 PP_ASSERT_WITH_CODE(false,
1867 "Attempt to populate TDCLimit Failed!", return -EINVAL);
1868
1869 if (vegam_populate_dw8(hwmgr, pm_fuse_table_offset))
1870 PP_ASSERT_WITH_CODE(false,
1871 "Attempt to populate TdcWaterfallCtl, "
1872 "LPMLTemperature Min and Max Failed!",
1873 return -EINVAL);
1874
1875 if (0 != vegam_populate_temperature_scaler(hwmgr))
1876 PP_ASSERT_WITH_CODE(false,
1877 "Attempt to populate LPMLTemperatureScaler Failed!",
1878 return -EINVAL);
1879
1880 if (vegam_populate_fuzzy_fan(hwmgr))
1881 PP_ASSERT_WITH_CODE(false,
1882 "Attempt to populate Fuzzy Fan Control parameters Failed!",
1883 return -EINVAL);
1884
1885 if (vegam_populate_gnb_lpml(hwmgr))
1886 PP_ASSERT_WITH_CODE(false,
1887 "Attempt to populate GnbLPML Failed!",
1888 return -EINVAL);
1889
1890 if (vegam_populate_bapm_vddc_base_leakage_sidd(hwmgr))
1891 PP_ASSERT_WITH_CODE(false,
1892 "Attempt to populate BapmVddCBaseLeakage Hi and Lo "
1893 "Sidd Failed!", return -EINVAL);
1894
1895 if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
1896 (uint8_t *)&smu_data->power_tune_table,
1897 (sizeof(struct SMU75_Discrete_PmFuses) - PMFUSES_AVFSSIZE),
1898 SMC_RAM_END))
1899 PP_ASSERT_WITH_CODE(false,
1900 "Attempt to download PmFuseTable Failed!",
1901 return -EINVAL);
1902 }
1903 return 0;
1904 }
1905
vegam_enable_reconfig_cus(struct pp_hwmgr * hwmgr)1906 static int vegam_enable_reconfig_cus(struct pp_hwmgr *hwmgr)
1907 {
1908 struct amdgpu_device *adev = hwmgr->adev;
1909
1910 smum_send_msg_to_smc_with_parameter(hwmgr,
1911 PPSMC_MSG_EnableModeSwitchRLCNotification,
1912 adev->gfx.cu_info.number,
1913 NULL);
1914
1915 return 0;
1916 }
1917
vegam_init_smc_table(struct pp_hwmgr * hwmgr)1918 static int vegam_init_smc_table(struct pp_hwmgr *hwmgr)
1919 {
1920 int result;
1921 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1922 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1923
1924 struct phm_ppt_v1_information *table_info =
1925 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1926 struct SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1927 uint8_t i;
1928 struct pp_atomctrl_gpio_pin_assignment gpio_pin;
1929 struct phm_ppt_v1_gpio_table *gpio_table =
1930 (struct phm_ppt_v1_gpio_table *)table_info->gpio_table;
1931 pp_atomctrl_clock_dividers_vi dividers;
1932
1933 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1934 PHM_PlatformCaps_AutomaticDCTransition);
1935
1936 vegam_initialize_power_tune_defaults(hwmgr);
1937
1938 if (SMU7_VOLTAGE_CONTROL_NONE != hw_data->voltage_control)
1939 vegam_populate_smc_voltage_tables(hwmgr, table);
1940
1941 table->SystemFlags = 0;
1942 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1943 PHM_PlatformCaps_AutomaticDCTransition))
1944 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
1945
1946 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1947 PHM_PlatformCaps_StepVddc))
1948 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
1949
1950 if (hw_data->is_memory_gddr5)
1951 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
1952
1953 if (hw_data->ulv_supported && table_info->us_ulv_voltage_offset) {
1954 result = vegam_populate_ulv_state(hwmgr, table);
1955 PP_ASSERT_WITH_CODE(!result,
1956 "Failed to initialize ULV state!", return result);
1957 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1958 ixCG_ULV_PARAMETER, SMU7_CGULVPARAMETER_DFLT);
1959 }
1960
1961 result = vegam_populate_smc_link_level(hwmgr, table);
1962 PP_ASSERT_WITH_CODE(!result,
1963 "Failed to initialize Link Level!", return result);
1964
1965 result = vegam_populate_all_graphic_levels(hwmgr);
1966 PP_ASSERT_WITH_CODE(!result,
1967 "Failed to initialize Graphics Level!", return result);
1968
1969 result = vegam_populate_all_memory_levels(hwmgr);
1970 PP_ASSERT_WITH_CODE(!result,
1971 "Failed to initialize Memory Level!", return result);
1972
1973 result = vegam_populate_smc_acpi_level(hwmgr, table);
1974 PP_ASSERT_WITH_CODE(!result,
1975 "Failed to initialize ACPI Level!", return result);
1976
1977 result = vegam_populate_smc_vce_level(hwmgr, table);
1978 PP_ASSERT_WITH_CODE(!result,
1979 "Failed to initialize VCE Level!", return result);
1980
1981 /* Since only the initial state is completely set up at this point
1982 * (the other states are just copies of the boot state) we only
1983 * need to populate the ARB settings for the initial state.
1984 */
1985 result = vegam_program_memory_timing_parameters(hwmgr);
1986 PP_ASSERT_WITH_CODE(!result,
1987 "Failed to Write ARB settings for the initial state.", return result);
1988
1989 result = vegam_populate_smc_uvd_level(hwmgr, table);
1990 PP_ASSERT_WITH_CODE(!result,
1991 "Failed to initialize UVD Level!", return result);
1992
1993 result = vegam_populate_smc_boot_level(hwmgr, table);
1994 PP_ASSERT_WITH_CODE(!result,
1995 "Failed to initialize Boot Level!", return result);
1996
1997 result = vegam_populate_smc_initial_state(hwmgr);
1998 PP_ASSERT_WITH_CODE(!result,
1999 "Failed to initialize Boot State!", return result);
2000
2001 result = vegam_populate_bapm_parameters_in_dpm_table(hwmgr);
2002 PP_ASSERT_WITH_CODE(!result,
2003 "Failed to populate BAPM Parameters!", return result);
2004
2005 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2006 PHM_PlatformCaps_ClockStretcher)) {
2007 result = vegam_populate_clock_stretcher_data_table(hwmgr);
2008 PP_ASSERT_WITH_CODE(!result,
2009 "Failed to populate Clock Stretcher Data Table!",
2010 return result);
2011 }
2012
2013 result = vegam_populate_avfs_parameters(hwmgr);
2014 PP_ASSERT_WITH_CODE(!result,
2015 "Failed to populate AVFS Parameters!", return result;);
2016
2017 table->CurrSclkPllRange = 0xff;
2018 table->GraphicsVoltageChangeEnable = 1;
2019 table->GraphicsThermThrottleEnable = 1;
2020 table->GraphicsInterval = 1;
2021 table->VoltageInterval = 1;
2022 table->ThermalInterval = 1;
2023 table->TemperatureLimitHigh =
2024 table_info->cac_dtp_table->usTargetOperatingTemp *
2025 SMU7_Q88_FORMAT_CONVERSION_UNIT;
2026 table->TemperatureLimitLow =
2027 (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
2028 SMU7_Q88_FORMAT_CONVERSION_UNIT;
2029 table->MemoryVoltageChangeEnable = 1;
2030 table->MemoryInterval = 1;
2031 table->VoltageResponseTime = 0;
2032 table->PhaseResponseTime = 0;
2033 table->MemoryThermThrottleEnable = 1;
2034
2035 PP_ASSERT_WITH_CODE(hw_data->dpm_table.pcie_speed_table.count >= 1,
2036 "There must be 1 or more PCIE levels defined in PPTable.",
2037 return -EINVAL);
2038 table->PCIeBootLinkLevel =
2039 hw_data->dpm_table.pcie_speed_table.count;
2040 table->PCIeGenInterval = 1;
2041 table->VRConfig = 0;
2042
2043 result = vegam_populate_vr_config(hwmgr, table);
2044 PP_ASSERT_WITH_CODE(!result,
2045 "Failed to populate VRConfig setting!", return result);
2046
2047 table->ThermGpio = 17;
2048 table->SclkStepSize = 0x4000;
2049
2050 if (atomctrl_get_pp_assign_pin(hwmgr,
2051 VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
2052 table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
2053 if (gpio_table)
2054 table->VRHotLevel =
2055 table_info->gpio_table->vrhot_triggered_sclk_dpm_index;
2056 } else {
2057 table->VRHotGpio = SMU7_UNUSED_GPIO_PIN;
2058 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2059 PHM_PlatformCaps_RegulatorHot);
2060 }
2061
2062 if (atomctrl_get_pp_assign_pin(hwmgr,
2063 PP_AC_DC_SWITCH_GPIO_PINID, &gpio_pin)) {
2064 table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
2065 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2066 PHM_PlatformCaps_AutomaticDCTransition) &&
2067 !smum_send_msg_to_smc(hwmgr, PPSMC_MSG_UseNewGPIOScheme, NULL))
2068 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2069 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
2070 } else {
2071 table->AcDcGpio = SMU7_UNUSED_GPIO_PIN;
2072 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2073 PHM_PlatformCaps_AutomaticDCTransition);
2074 }
2075
2076 /* Thermal Output GPIO */
2077 if (atomctrl_get_pp_assign_pin(hwmgr,
2078 THERMAL_INT_OUTPUT_GPIO_PINID, &gpio_pin)) {
2079 table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
2080
2081 /* For porlarity read GPIOPAD_A with assigned Gpio pin
2082 * since VBIOS will program this register to set 'inactive state',
2083 * driver can then determine 'active state' from this and
2084 * program SMU with correct polarity
2085 */
2086 table->ThermOutPolarity =
2087 (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) &
2088 (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
2089 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
2090
2091 /* if required, combine VRHot/PCC with thermal out GPIO */
2092 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2093 PHM_PlatformCaps_RegulatorHot) &&
2094 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2095 PHM_PlatformCaps_CombinePCCWithThermalSignal))
2096 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
2097 } else {
2098 table->ThermOutGpio = 17;
2099 table->ThermOutPolarity = 1;
2100 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
2101 }
2102
2103 /* Populate BIF_SCLK levels into SMC DPM table */
2104 for (i = 0; i <= hw_data->dpm_table.pcie_speed_table.count; i++) {
2105 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2106 smu_data->bif_sclk_table[i], ÷rs);
2107 PP_ASSERT_WITH_CODE(!result,
2108 "Can not find DFS divide id for Sclk",
2109 return result);
2110
2111 if (i == 0)
2112 table->Ulv.BifSclkDfs =
2113 PP_HOST_TO_SMC_US((uint16_t)(dividers.pll_post_divider));
2114 else
2115 table->LinkLevel[i - 1].BifSclkDfs =
2116 PP_HOST_TO_SMC_US((uint16_t)(dividers.pll_post_divider));
2117 }
2118
2119 for (i = 0; i < SMU75_MAX_ENTRIES_SMIO; i++)
2120 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
2121
2122 CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
2123 CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
2124 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
2125 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
2126 CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
2127 CONVERT_FROM_HOST_TO_SMC_UL(table->CurrSclkPllRange);
2128 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
2129 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
2130 CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
2131 CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
2132
2133 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2134 result = smu7_copy_bytes_to_smc(hwmgr,
2135 smu_data->smu7_data.dpm_table_start +
2136 offsetof(SMU75_Discrete_DpmTable, SystemFlags),
2137 (uint8_t *)&(table->SystemFlags),
2138 sizeof(SMU75_Discrete_DpmTable) - 3 * sizeof(SMU75_PIDController),
2139 SMC_RAM_END);
2140 PP_ASSERT_WITH_CODE(!result,
2141 "Failed to upload dpm data to SMC memory!", return result);
2142
2143 result = vegam_populate_pm_fuses(hwmgr);
2144 PP_ASSERT_WITH_CODE(!result,
2145 "Failed to populate PM fuses to SMC memory!", return result);
2146
2147 result = vegam_enable_reconfig_cus(hwmgr);
2148 PP_ASSERT_WITH_CODE(!result,
2149 "Failed to enable reconfigurable CUs!", return result);
2150
2151 return 0;
2152 }
2153
vegam_get_offsetof(uint32_t type,uint32_t member)2154 static uint32_t vegam_get_offsetof(uint32_t type, uint32_t member)
2155 {
2156 switch (type) {
2157 case SMU_SoftRegisters:
2158 switch (member) {
2159 case HandshakeDisables:
2160 return offsetof(SMU75_SoftRegisters, HandshakeDisables);
2161 case VoltageChangeTimeout:
2162 return offsetof(SMU75_SoftRegisters, VoltageChangeTimeout);
2163 case AverageGraphicsActivity:
2164 return offsetof(SMU75_SoftRegisters, AverageGraphicsActivity);
2165 case AverageMemoryActivity:
2166 return offsetof(SMU75_SoftRegisters, AverageMemoryActivity);
2167 case PreVBlankGap:
2168 return offsetof(SMU75_SoftRegisters, PreVBlankGap);
2169 case VBlankTimeout:
2170 return offsetof(SMU75_SoftRegisters, VBlankTimeout);
2171 case UcodeLoadStatus:
2172 return offsetof(SMU75_SoftRegisters, UcodeLoadStatus);
2173 case DRAM_LOG_ADDR_H:
2174 return offsetof(SMU75_SoftRegisters, DRAM_LOG_ADDR_H);
2175 case DRAM_LOG_ADDR_L:
2176 return offsetof(SMU75_SoftRegisters, DRAM_LOG_ADDR_L);
2177 case DRAM_LOG_PHY_ADDR_H:
2178 return offsetof(SMU75_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
2179 case DRAM_LOG_PHY_ADDR_L:
2180 return offsetof(SMU75_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
2181 case DRAM_LOG_BUFF_SIZE:
2182 return offsetof(SMU75_SoftRegisters, DRAM_LOG_BUFF_SIZE);
2183 }
2184 break;
2185 case SMU_Discrete_DpmTable:
2186 switch (member) {
2187 case UvdBootLevel:
2188 return offsetof(SMU75_Discrete_DpmTable, UvdBootLevel);
2189 case VceBootLevel:
2190 return offsetof(SMU75_Discrete_DpmTable, VceBootLevel);
2191 case LowSclkInterruptThreshold:
2192 return offsetof(SMU75_Discrete_DpmTable, LowSclkInterruptThreshold);
2193 }
2194 break;
2195 }
2196 pr_warn("can't get the offset of type %x member %x\n", type, member);
2197 return 0;
2198 }
2199
vegam_program_mem_timing_parameters(struct pp_hwmgr * hwmgr)2200 static int vegam_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
2201 {
2202 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2203
2204 if (data->need_update_smu7_dpm_table &
2205 (DPMTABLE_OD_UPDATE_SCLK +
2206 DPMTABLE_UPDATE_SCLK +
2207 DPMTABLE_UPDATE_MCLK))
2208 return vegam_program_memory_timing_parameters(hwmgr);
2209
2210 return 0;
2211 }
2212
vegam_update_sclk_threshold(struct pp_hwmgr * hwmgr)2213 static int vegam_update_sclk_threshold(struct pp_hwmgr *hwmgr)
2214 {
2215 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2216 struct vegam_smumgr *smu_data =
2217 (struct vegam_smumgr *)(hwmgr->smu_backend);
2218 int result = 0;
2219 uint32_t low_sclk_interrupt_threshold = 0;
2220
2221 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2222 PHM_PlatformCaps_SclkThrottleLowNotification)
2223 && (data->low_sclk_interrupt_threshold != 0)) {
2224 low_sclk_interrupt_threshold =
2225 data->low_sclk_interrupt_threshold;
2226
2227 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
2228
2229 result = smu7_copy_bytes_to_smc(
2230 hwmgr,
2231 smu_data->smu7_data.dpm_table_start +
2232 offsetof(SMU75_Discrete_DpmTable,
2233 LowSclkInterruptThreshold),
2234 (uint8_t *)&low_sclk_interrupt_threshold,
2235 sizeof(uint32_t),
2236 SMC_RAM_END);
2237 }
2238 PP_ASSERT_WITH_CODE((result == 0),
2239 "Failed to update SCLK threshold!", return result);
2240
2241 result = vegam_program_mem_timing_parameters(hwmgr);
2242 PP_ASSERT_WITH_CODE((result == 0),
2243 "Failed to program memory timing parameters!",
2244 );
2245
2246 return result;
2247 }
2248
vegam_thermal_avfs_enable(struct pp_hwmgr * hwmgr)2249 static int vegam_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
2250 {
2251 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2252 int ret;
2253
2254 if (!hwmgr->avfs_supported)
2255 return 0;
2256
2257 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAvfs, NULL);
2258 if (!ret) {
2259 if (data->apply_avfs_cks_off_voltage)
2260 ret = smum_send_msg_to_smc(hwmgr,
2261 PPSMC_MSG_ApplyAvfsCksOffVoltage,
2262 NULL);
2263 }
2264
2265 return ret;
2266 }
2267
vegam_thermal_setup_fan_table(struct pp_hwmgr * hwmgr)2268 static int vegam_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
2269 {
2270 PP_ASSERT_WITH_CODE(hwmgr->thermal_controller.fanInfo.bNoFan,
2271 "VBIOS fan info is not correct!",
2272 );
2273 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2274 PHM_PlatformCaps_MicrocodeFanControl);
2275 return 0;
2276 }
2277
2278 const struct pp_smumgr_func vegam_smu_funcs = {
2279 .name = "vegam_smu",
2280 .smu_init = vegam_smu_init,
2281 .smu_fini = smu7_smu_fini,
2282 .start_smu = vegam_start_smu,
2283 .check_fw_load_finish = smu7_check_fw_load_finish,
2284 .request_smu_load_fw = smu7_reload_firmware,
2285 .request_smu_load_specific_fw = NULL,
2286 .send_msg_to_smc = smu7_send_msg_to_smc,
2287 .send_msg_to_smc_with_parameter = smu7_send_msg_to_smc_with_parameter,
2288 .get_argument = smu7_get_argument,
2289 .process_firmware_header = vegam_process_firmware_header,
2290 .is_dpm_running = vegam_is_dpm_running,
2291 .get_mac_definition = vegam_get_mac_definition,
2292 .update_smc_table = vegam_update_smc_table,
2293 .init_smc_table = vegam_init_smc_table,
2294 .get_offsetof = vegam_get_offsetof,
2295 .populate_all_graphic_levels = vegam_populate_all_graphic_levels,
2296 .populate_all_memory_levels = vegam_populate_all_memory_levels,
2297 .update_sclk_threshold = vegam_update_sclk_threshold,
2298 .is_hw_avfs_present = vegam_is_hw_avfs_present,
2299 .thermal_avfs_enable = vegam_thermal_avfs_enable,
2300 .thermal_setup_fan_table = vegam_thermal_setup_fan_table,
2301 };
2302