1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (c) 2023 MediaTek Inc.
4  * Author: Yunfei Dong <yunfei.dong@mediatek.com>
5  */
6 
7 #ifndef _MTK_VCODEC_DEC_DRV_H_
8 #define _MTK_VCODEC_DEC_DRV_H_
9 
10 #include "../common/mtk_vcodec_cmn_drv.h"
11 #include "../common/mtk_vcodec_dbgfs.h"
12 #include "../common/mtk_vcodec_fw_priv.h"
13 #include "../common/mtk_vcodec_util.h"
14 #include "vdec_msg_queue.h"
15 
16 #define MTK_VCODEC_DEC_NAME	"mtk-vcodec-dec"
17 
18 #define IS_VDEC_LAT_ARCH(hw_arch) ((hw_arch) >= MTK_VDEC_LAT_SINGLE_CORE)
19 #define IS_VDEC_INNER_RACING(capability) ((capability) & MTK_VCODEC_INNER_RACING)
20 
21 /*
22  * enum mtk_vdec_format_types - Structure used to get supported
23  *		  format types according to decoder capability
24  */
25 enum mtk_vdec_format_types {
26 	MTK_VDEC_FORMAT_MM21 = 0x20,
27 	MTK_VDEC_FORMAT_MT21C = 0x40,
28 	MTK_VDEC_FORMAT_H264_SLICE = 0x100,
29 	MTK_VDEC_FORMAT_VP8_FRAME = 0x200,
30 	MTK_VDEC_FORMAT_VP9_FRAME = 0x400,
31 	MTK_VDEC_FORMAT_AV1_FRAME = 0x800,
32 	MTK_VDEC_FORMAT_HEVC_FRAME = 0x1000,
33 	MTK_VCODEC_INNER_RACING = 0x20000,
34 	MTK_VDEC_IS_SUPPORT_10BIT = 0x40000,
35 };
36 
37 /*
38  * enum mtk_vdec_hw_count - Supported hardware count
39  */
40 enum mtk_vdec_hw_count {
41 	MTK_VDEC_NO_HW = 0,
42 	MTK_VDEC_ONE_CORE,
43 	MTK_VDEC_ONE_LAT_ONE_CORE,
44 	MTK_VDEC_MAX_HW_COUNT,
45 };
46 
47 /*
48  * enum mtk_vdec_hw_arch - Used to separate different hardware architecture
49  */
50 enum mtk_vdec_hw_arch {
51 	MTK_VDEC_PURE_SINGLE_CORE,
52 	MTK_VDEC_LAT_SINGLE_CORE,
53 };
54 
55 /**
56  * struct vdec_pic_info  - picture size information
57  * @pic_w: picture width
58  * @pic_h: picture height
59  * @buf_w: picture buffer width (64 aligned up from pic_w)
60  * @buf_h: picture buffer heiht (64 aligned up from pic_h)
61  * @fb_sz: bitstream size of each plane
62  * E.g. suppose picture size is 176x144,
63  *      buffer size will be aligned to 176x160.
64  * @cap_fourcc: fourcc number(may changed when resolution change)
65  * @reserved: align struct to 64-bit in order to adjust 32-bit and 64-bit os.
66  */
67 struct vdec_pic_info {
68 	unsigned int pic_w;
69 	unsigned int pic_h;
70 	unsigned int buf_w;
71 	unsigned int buf_h;
72 	unsigned int fb_sz[VIDEO_MAX_PLANES];
73 	unsigned int cap_fourcc;
74 	unsigned int reserved;
75 };
76 
77 /**
78  * struct mtk_vcodec_dec_pdata - compatible data for each IC
79  * @init_vdec_params: init vdec params
80  * @ctrls_setup: init vcodec dec ctrls
81  * @worker: worker to start a decode job
82  * @flush_decoder: function that flushes the decoder
83  * @get_cap_buffer: get capture buffer from capture queue
84  * @cap_to_disp: put capture buffer to disp list for lat and core arch
85  * @vdec_vb2_ops: struct vb2_ops
86  *
87  * @vdec_formats: supported video decoder formats
88  * @num_formats: count of video decoder formats
89  * @default_out_fmt: default output buffer format
90  * @default_cap_fmt: default capture buffer format
91  *
92  * @hw_arch: hardware arch is used to separate pure_sin_core and lat_sin_core
93  *
94  * @is_subdev_supported: whether support parent-node architecture(subdev)
95  * @uses_stateless_api: whether the decoder uses the stateless API with requests
96  */
97 struct mtk_vcodec_dec_pdata {
98 	void (*init_vdec_params)(struct mtk_vcodec_dec_ctx *ctx);
99 	int (*ctrls_setup)(struct mtk_vcodec_dec_ctx *ctx);
100 	void (*worker)(struct work_struct *work);
101 	int (*flush_decoder)(struct mtk_vcodec_dec_ctx *ctx);
102 	struct vdec_fb *(*get_cap_buffer)(struct mtk_vcodec_dec_ctx *ctx);
103 	void (*cap_to_disp)(struct mtk_vcodec_dec_ctx *ctx, int error,
104 			    struct media_request *src_buf_req);
105 
106 	const struct vb2_ops *vdec_vb2_ops;
107 
108 	const struct mtk_video_fmt *vdec_formats;
109 	const int *num_formats;
110 	const struct mtk_video_fmt *default_out_fmt;
111 	const struct mtk_video_fmt *default_cap_fmt;
112 
113 	enum mtk_vdec_hw_arch hw_arch;
114 
115 	bool is_subdev_supported;
116 	bool uses_stateless_api;
117 };
118 
119 /**
120  * struct mtk_vcodec_dec_ctx - Context (instance) private data.
121  *
122  * @type: type of decoder instance
123  * @dev: pointer to the mtk_vcodec_dec_dev of the device
124  * @list: link to ctx_list of mtk_vcodec_dec_dev
125  *
126  * @fh: struct v4l2_fh
127  * @m2m_ctx: pointer to the v4l2_m2m_ctx of the context
128  * @q_data: store information of input and output queue of the context
129  * @id: index of the context that this structure describes
130  * @state: state of the context
131  *
132  * @dec_if: hooked decoder driver interface
133  * @drv_handle: driver handle for specific decode/encode instance
134  *
135  * @picinfo: store picture info after header parsing
136  * @dpb_size: store dpb count after header parsing
137  *
138  * @int_cond: variable used by the waitqueue
139  * @int_type: type of the last interrupt
140  * @queue: waitqueue that can be used to wait for this context to finish
141  * @irq_status: irq status
142  *
143  * @ctrl_hdl: handler for v4l2 framework
144  * @decode_work: worker for the decoding
145  * @last_decoded_picinfo: pic information get from latest decode
146  * @empty_flush_buf: a fake size-0 capture buffer that indicates flush. Used
147  *		     for stateful decoder.
148  * @is_flushing: set to true if flushing is in progress.
149  *
150  * @current_codec: current set input codec, in V4L2 pixel format
151  * @capture_fourcc: capture queue type in V4L2 pixel format
152  *
153  * @colorspace: enum v4l2_colorspace; supplemental to pixelformat
154  * @ycbcr_enc: enum v4l2_ycbcr_encoding, Y'CbCr encoding
155  * @quantization: enum v4l2_quantization, colorspace quantization
156  * @xfer_func: enum v4l2_xfer_func, colorspace transfer function
157  *
158  * @decoded_frame_cnt: number of decoded frames
159  * @lock: protect variables accessed by V4L2 threads and worker thread such as
160  *	  mtk_video_dec_buf.
161  * @hw_id: hardware index used to identify different hardware.
162  *
163  * @msg_queue: msg queue used to store lat buffer information.
164  * @vpu_inst: vpu instance pointer.
165  *
166  * @is_10bit_bitstream: set to true if it's 10bit bitstream
167  */
168 struct mtk_vcodec_dec_ctx {
169 	enum mtk_instance_type type;
170 	struct mtk_vcodec_dec_dev *dev;
171 	struct list_head list;
172 
173 	struct v4l2_fh fh;
174 	struct v4l2_m2m_ctx *m2m_ctx;
175 	struct mtk_q_data q_data[2];
176 	int id;
177 	enum mtk_instance_state state;
178 
179 	const struct vdec_common_if *dec_if;
180 	void *drv_handle;
181 
182 	struct vdec_pic_info picinfo;
183 	int dpb_size;
184 
185 	int int_cond[MTK_VDEC_HW_MAX];
186 	int int_type[MTK_VDEC_HW_MAX];
187 	wait_queue_head_t queue[MTK_VDEC_HW_MAX];
188 	unsigned int irq_status;
189 
190 	struct v4l2_ctrl_handler ctrl_hdl;
191 	struct work_struct decode_work;
192 	struct vdec_pic_info last_decoded_picinfo;
193 	struct v4l2_m2m_buffer empty_flush_buf;
194 	bool is_flushing;
195 
196 	u32 current_codec;
197 	u32 capture_fourcc;
198 
199 	enum v4l2_colorspace colorspace;
200 	enum v4l2_ycbcr_encoding ycbcr_enc;
201 	enum v4l2_quantization quantization;
202 	enum v4l2_xfer_func xfer_func;
203 
204 	int decoded_frame_cnt;
205 	struct mutex lock;
206 	int hw_id;
207 
208 	struct vdec_msg_queue msg_queue;
209 	void *vpu_inst;
210 
211 	bool is_10bit_bitstream;
212 };
213 
214 /**
215  * struct mtk_vcodec_dec_dev - driver data
216  * @v4l2_dev: V4L2 device to register video devices for.
217  * @vfd_dec: Video device for decoder
218  * @mdev_dec: Media device for decoder
219  *
220  * @m2m_dev_dec: m2m device for decoder
221  * @plat_dev: platform device
222  * @ctx_list: list of struct mtk_vcodec_ctx
223  * @curr_ctx: The context that is waiting for codec hardware
224  *
225  * @reg_base: Mapped address of MTK Vcodec registers.
226  * @vdec_pdata: decoder IC-specific data
227  * @vdecsys_regmap: VDEC_SYS register space passed through syscon
228  *
229  * @fw_handler: used to communicate with the firmware.
230  * @id_counter: used to identify current opened instance
231  *
232  * @dec_mutex: decoder hardware lock
233  * @dev_mutex: video_device lock
234  * @decode_workqueue: decode work queue
235  *
236  * @irqlock: protect data access by irq handler and work thread
237  * @dec_irq: decoder irq resource
238  *
239  * @pm: power management control
240  * @dec_capability: used to identify decode capability, ex: 4k
241  *
242  * @core_workqueue: queue used for core hardware decode
243  *
244  * @subdev_dev: subdev hardware device
245  * @subdev_prob_done: check whether all used hw device is prob done
246  * @subdev_bitmap: used to record hardware is ready or not
247  *
248  * @dec_active_cnt: used to mark whether need to record register value
249  * @vdec_racing_info: record register value
250  * @dec_racing_info_mutex: mutex lock used for inner racing mode
251  * @dbgfs: debug log related information
252  */
253 struct mtk_vcodec_dec_dev {
254 	struct v4l2_device v4l2_dev;
255 	struct video_device *vfd_dec;
256 	struct media_device mdev_dec;
257 
258 	struct v4l2_m2m_dev *m2m_dev_dec;
259 	struct platform_device *plat_dev;
260 	struct list_head ctx_list;
261 	struct mtk_vcodec_dec_ctx *curr_ctx;
262 
263 	void __iomem *reg_base[NUM_MAX_VCODEC_REG_BASE];
264 	const struct mtk_vcodec_dec_pdata *vdec_pdata;
265 	struct regmap *vdecsys_regmap;
266 
267 	struct mtk_vcodec_fw *fw_handler;
268 	u64 id_counter;
269 
270 	/* decoder hardware mutex lock */
271 	struct mutex dec_mutex[MTK_VDEC_HW_MAX];
272 	struct mutex dev_mutex;
273 	struct workqueue_struct *decode_workqueue;
274 
275 	spinlock_t irqlock;
276 	int dec_irq;
277 
278 	struct mtk_vcodec_pm pm;
279 	unsigned int dec_capability;
280 
281 	struct workqueue_struct *core_workqueue;
282 
283 	void *subdev_dev[MTK_VDEC_HW_MAX];
284 	int (*subdev_prob_done)(struct mtk_vcodec_dec_dev *vdec_dev);
285 	DECLARE_BITMAP(subdev_bitmap, MTK_VDEC_HW_MAX);
286 
287 	atomic_t dec_active_cnt;
288 	u32 vdec_racing_info[132];
289 	/* Protects access to vdec_racing_info data */
290 	struct mutex dec_racing_info_mutex;
291 	struct mtk_vcodec_dbgfs dbgfs;
292 };
293 
fh_to_dec_ctx(struct v4l2_fh * fh)294 static inline struct mtk_vcodec_dec_ctx *fh_to_dec_ctx(struct v4l2_fh *fh)
295 {
296 	return container_of(fh, struct mtk_vcodec_dec_ctx, fh);
297 }
298 
ctrl_to_dec_ctx(struct v4l2_ctrl * ctrl)299 static inline struct mtk_vcodec_dec_ctx *ctrl_to_dec_ctx(struct v4l2_ctrl *ctrl)
300 {
301 	return container_of(ctrl->handler, struct mtk_vcodec_dec_ctx, ctrl_hdl);
302 }
303 
304 /* Wake up context wait_queue */
305 static inline void
wake_up_dec_ctx(struct mtk_vcodec_dec_ctx * ctx,unsigned int reason,unsigned int hw_id)306 wake_up_dec_ctx(struct mtk_vcodec_dec_ctx *ctx, unsigned int reason, unsigned int hw_id)
307 {
308 	ctx->int_cond[hw_id] = 1;
309 	ctx->int_type[hw_id] = reason;
310 	wake_up_interruptible(&ctx->queue[hw_id]);
311 }
312 
313 #define mtk_vdec_err(ctx, fmt, args...)                               \
314 	mtk_vcodec_err((ctx)->id, (ctx)->dev->plat_dev, fmt, ##args)
315 
316 #define mtk_vdec_debug(ctx, fmt, args...)                             \
317 	mtk_vcodec_debug((ctx)->id, (ctx)->dev->plat_dev, fmt, ##args)
318 
319 #define mtk_v4l2_vdec_err(ctx, fmt, args...) mtk_v4l2_err((ctx)->dev->plat_dev, fmt, ##args)
320 
321 #define mtk_v4l2_vdec_dbg(level, ctx, fmt, args...)             \
322 	mtk_v4l2_debug((ctx)->dev->plat_dev, level, fmt, ##args)
323 
324 #endif /* _MTK_VCODEC_DEC_DRV_H_ */
325