1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
4  */
5 
6 #ifndef __DSI_PHY_H__
7 #define __DSI_PHY_H__
8 
9 #include <linux/clk-provider.h>
10 #include <linux/delay.h>
11 #include <linux/regulator/consumer.h>
12 
13 #include "dsi.h"
14 
15 #define dsi_phy_read(offset) msm_readl((offset))
16 #define dsi_phy_write(offset, data) msm_writel((data), (offset))
17 #define dsi_phy_write_udelay(offset, data, delay_us) { msm_writel((data), (offset)); udelay(delay_us); }
18 #define dsi_phy_write_ndelay(offset, data, delay_ns) { msm_writel((data), (offset)); ndelay(delay_ns); }
19 
20 struct msm_dsi_phy_ops {
21 	int (*pll_init)(struct msm_dsi_phy *phy);
22 	int (*enable)(struct msm_dsi_phy *phy,
23 			struct msm_dsi_phy_clk_request *clk_req);
24 	void (*disable)(struct msm_dsi_phy *phy);
25 	void (*save_pll_state)(struct msm_dsi_phy *phy);
26 	int (*restore_pll_state)(struct msm_dsi_phy *phy);
27 	bool (*set_continuous_clock)(struct msm_dsi_phy *phy, bool enable);
28 	int (*parse_dt_properties)(struct msm_dsi_phy *phy);
29 };
30 
31 struct msm_dsi_phy_cfg {
32 	const struct regulator_bulk_data *regulator_data;
33 	int num_regulators;
34 	struct msm_dsi_phy_ops ops;
35 
36 	unsigned long	min_pll_rate;
37 	unsigned long	max_pll_rate;
38 
39 	const resource_size_t io_start[DSI_MAX];
40 	const int num_dsi_phy;
41 	const int quirks;
42 	bool has_phy_regulator;
43 	bool has_phy_lane;
44 };
45 
46 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs;
47 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs;
48 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs;
49 extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs;
50 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs;
51 extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs;
52 extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs;
53 extern const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs;
54 extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs;
55 extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs;
56 extern const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs;
57 extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs;
58 extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs;
59 
60 struct msm_dsi_dphy_timing {
61 	u32 clk_zero;
62 	u32 clk_trail;
63 	u32 clk_prepare;
64 	u32 hs_exit;
65 	u32 hs_zero;
66 	u32 hs_prepare;
67 	u32 hs_trail;
68 	u32 hs_rqst;
69 	u32 ta_go;
70 	u32 ta_sure;
71 	u32 ta_get;
72 
73 	struct msm_dsi_phy_shared_timings shared_timings;
74 
75 	/* For PHY v2 only */
76 	u32 hs_rqst_ckln;
77 	u32 hs_prep_dly;
78 	u32 hs_prep_dly_ckln;
79 	u8 hs_halfbyte_en;
80 	u8 hs_halfbyte_en_ckln;
81 };
82 
83 #define DSI_BYTE_PLL_CLK		0
84 #define DSI_PIXEL_PLL_CLK		1
85 #define NUM_PROVIDED_CLKS		2
86 
87 #define DSI_LANE_MAX			5
88 
89 struct msm_dsi_phy {
90 	struct platform_device *pdev;
91 	void __iomem *base;
92 	void __iomem *pll_base;
93 	void __iomem *reg_base;
94 	void __iomem *lane_base;
95 	phys_addr_t base_size;
96 	phys_addr_t pll_size;
97 	phys_addr_t reg_size;
98 	phys_addr_t lane_size;
99 	int id;
100 
101 	struct clk *ahb_clk;
102 	struct regulator_bulk_data *supplies;
103 
104 	struct msm_dsi_dphy_timing timing;
105 	const struct msm_dsi_phy_cfg *cfg;
106 	void *tuning_cfg;
107 
108 	enum msm_dsi_phy_usecase usecase;
109 	bool regulator_ldo_mode;
110 	bool cphy_mode;
111 
112 	struct clk_hw *vco_hw;
113 	bool pll_on;
114 
115 	struct clk_hw_onecell_data *provided_clocks;
116 
117 	bool state_saved;
118 };
119 
120 /*
121  * PHY internal functions
122  */
123 int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing,
124 			     struct msm_dsi_phy_clk_request *clk_req);
125 int msm_dsi_dphy_timing_calc_v2(struct msm_dsi_dphy_timing *timing,
126 				struct msm_dsi_phy_clk_request *clk_req);
127 int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing,
128 				struct msm_dsi_phy_clk_request *clk_req);
129 int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
130 				struct msm_dsi_phy_clk_request *clk_req);
131 int msm_dsi_cphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
132 				struct msm_dsi_phy_clk_request *clk_req);
133 
134 #endif /* __DSI_PHY_H__ */
135