1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #ifndef AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_
27 #define AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_
28 
29 struct drm_crtc;
30 struct dm_crtc_state;
31 
32 enum amdgpu_dm_pipe_crc_source {
33 	AMDGPU_DM_PIPE_CRC_SOURCE_NONE = 0,
34 	AMDGPU_DM_PIPE_CRC_SOURCE_CRTC,
35 	AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER,
36 	AMDGPU_DM_PIPE_CRC_SOURCE_DPRX,
37 	AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER,
38 	AMDGPU_DM_PIPE_CRC_SOURCE_MAX,
39 	AMDGPU_DM_PIPE_CRC_SOURCE_INVALID = -1,
40 };
41 
42 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
43 struct crc_window_parm {
44 	uint16_t x_start;
45 	uint16_t y_start;
46 	uint16_t x_end;
47 	uint16_t y_end;
48 	/* CRC windwo is activated or not*/
49 	bool activated;
50 	/* Update crc window during vertical blank or not */
51 	bool update_win;
52 	/* skip reading/writing for few frames */
53 	int skip_frame_cnt;
54 };
55 
56 struct crc_rd_work {
57 	struct work_struct notify_ta_work;
58 	/* To protect crc_rd_work carried fields*/
59 	spinlock_t crc_rd_work_lock;
60 	struct drm_crtc *crtc;
61 	uint8_t phy_inst;
62 };
63 #endif
64 
amdgpu_dm_is_valid_crc_source(enum amdgpu_dm_pipe_crc_source source)65 static inline bool amdgpu_dm_is_valid_crc_source(enum amdgpu_dm_pipe_crc_source source)
66 {
67 	return (source > AMDGPU_DM_PIPE_CRC_SOURCE_NONE) &&
68 	       (source < AMDGPU_DM_PIPE_CRC_SOURCE_MAX);
69 }
70 
71 /* amdgpu_dm_crc.c */
72 #ifdef CONFIG_DEBUG_FS
73 int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
74 					struct dm_crtc_state *dm_crtc_state,
75 					enum amdgpu_dm_pipe_crc_source source);
76 int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name);
77 int amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc,
78 				     const char *src_name,
79 				     size_t *values_cnt);
80 const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc,
81 						  size_t *count);
82 void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc);
83 #else
84 #define amdgpu_dm_crtc_set_crc_source NULL
85 #define amdgpu_dm_crtc_verify_crc_source NULL
86 #define amdgpu_dm_crtc_get_crc_sources NULL
87 #define amdgpu_dm_crtc_handle_crc_irq(x)
88 #endif
89 
90 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
91 bool amdgpu_dm_crc_window_is_activated(struct drm_crtc *crtc);
92 void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc);
93 struct crc_rd_work *amdgpu_dm_crtc_secure_display_create_work(void);
94 #else
95 #define amdgpu_dm_crc_window_is_activated(x)
96 #define amdgpu_dm_crtc_handle_crc_window_irq(x)
97 #define amdgpu_dm_crtc_secure_display_create_work()
98 #endif
99 
100 #endif /* AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_ */
101