1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  *  Copyright (C) 1994  Linus Torvalds
4  *
5  *  Cyrix stuff, June 1998 by:
6  *	- Rafael R. Reilova (moved everything from head.S),
7  *        <rreilova@ececs.uc.edu>
8  *	- Channing Corn (tests & fixes),
9  *	- Andrew D. Balsa (code cleanup).
10  */
11 #include <linux/init.h>
12 #include <linux/utsname.h>
13 #include <linux/cpu.h>
14 #include <linux/module.h>
15 #include <linux/nospec.h>
16 #include <linux/prctl.h>
17 #include <linux/sched/smt.h>
18 #include <linux/pgtable.h>
19 #include <linux/bpf.h>
20 
21 #include <asm/spec-ctrl.h>
22 #include <asm/cmdline.h>
23 #include <asm/bugs.h>
24 #include <asm/processor.h>
25 #include <asm/processor-flags.h>
26 #include <asm/fpu/api.h>
27 #include <asm/msr.h>
28 #include <asm/vmx.h>
29 #include <asm/paravirt.h>
30 #include <asm/alternative.h>
31 #include <asm/set_memory.h>
32 #include <asm/intel-family.h>
33 #include <asm/e820/api.h>
34 #include <asm/hypervisor.h>
35 #include <asm/tlbflush.h>
36 
37 #include "cpu.h"
38 
39 static void __init spectre_v1_select_mitigation(void);
40 static void __init spectre_v2_select_mitigation(void);
41 static void __init retbleed_select_mitigation(void);
42 static void __init spectre_v2_user_select_mitigation(void);
43 static void __init ssb_select_mitigation(void);
44 static void __init l1tf_select_mitigation(void);
45 static void __init mds_select_mitigation(void);
46 static void __init md_clear_update_mitigation(void);
47 static void __init md_clear_select_mitigation(void);
48 static void __init taa_select_mitigation(void);
49 static void __init mmio_select_mitigation(void);
50 static void __init srbds_select_mitigation(void);
51 static void __init l1d_flush_select_mitigation(void);
52 
53 /* The base value of the SPEC_CTRL MSR without task-specific bits set */
54 u64 x86_spec_ctrl_base;
55 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base);
56 
57 /* The current value of the SPEC_CTRL MSR with task-specific bits set */
58 DEFINE_PER_CPU(u64, x86_spec_ctrl_current);
59 EXPORT_SYMBOL_GPL(x86_spec_ctrl_current);
60 
61 static DEFINE_MUTEX(spec_ctrl_mutex);
62 
63 /* Update SPEC_CTRL MSR and its cached copy unconditionally */
update_spec_ctrl(u64 val)64 static void update_spec_ctrl(u64 val)
65 {
66 	this_cpu_write(x86_spec_ctrl_current, val);
67 	wrmsrl(MSR_IA32_SPEC_CTRL, val);
68 }
69 
70 /*
71  * Keep track of the SPEC_CTRL MSR value for the current task, which may differ
72  * from x86_spec_ctrl_base due to STIBP/SSB in __speculation_ctrl_update().
73  */
update_spec_ctrl_cond(u64 val)74 void update_spec_ctrl_cond(u64 val)
75 {
76 	if (this_cpu_read(x86_spec_ctrl_current) == val)
77 		return;
78 
79 	this_cpu_write(x86_spec_ctrl_current, val);
80 
81 	/*
82 	 * When KERNEL_IBRS this MSR is written on return-to-user, unless
83 	 * forced the update can be delayed until that time.
84 	 */
85 	if (!cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS))
86 		wrmsrl(MSR_IA32_SPEC_CTRL, val);
87 }
88 
spec_ctrl_current(void)89 u64 spec_ctrl_current(void)
90 {
91 	return this_cpu_read(x86_spec_ctrl_current);
92 }
93 EXPORT_SYMBOL_GPL(spec_ctrl_current);
94 
95 /*
96  * AMD specific MSR info for Speculative Store Bypass control.
97  * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
98  */
99 u64 __ro_after_init x86_amd_ls_cfg_base;
100 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask;
101 
102 /* Control conditional STIBP in switch_to() */
103 DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp);
104 /* Control conditional IBPB in switch_mm() */
105 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb);
106 /* Control unconditional IBPB in switch_mm() */
107 DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb);
108 
109 /* Control MDS CPU buffer clear before returning to user space */
110 DEFINE_STATIC_KEY_FALSE(mds_user_clear);
111 EXPORT_SYMBOL_GPL(mds_user_clear);
112 /* Control MDS CPU buffer clear before idling (halt, mwait) */
113 DEFINE_STATIC_KEY_FALSE(mds_idle_clear);
114 EXPORT_SYMBOL_GPL(mds_idle_clear);
115 
116 /*
117  * Controls whether l1d flush based mitigations are enabled,
118  * based on hw features and admin setting via boot parameter
119  * defaults to false
120  */
121 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_l1d_flush);
122 
123 /* Controls CPU Fill buffer clear before KVM guest MMIO accesses */
124 DEFINE_STATIC_KEY_FALSE(mmio_stale_data_clear);
125 EXPORT_SYMBOL_GPL(mmio_stale_data_clear);
126 
check_bugs(void)127 void __init check_bugs(void)
128 {
129 	identify_boot_cpu();
130 
131 	/*
132 	 * identify_boot_cpu() initialized SMT support information, let the
133 	 * core code know.
134 	 */
135 	cpu_smt_check_topology();
136 
137 	if (!IS_ENABLED(CONFIG_SMP)) {
138 		pr_info("CPU: ");
139 		print_cpu_info(&boot_cpu_data);
140 	}
141 
142 	/*
143 	 * Read the SPEC_CTRL MSR to account for reserved bits which may
144 	 * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
145 	 * init code as it is not enumerated and depends on the family.
146 	 */
147 	if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
148 		rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
149 
150 	/* Select the proper CPU mitigations before patching alternatives: */
151 	spectre_v1_select_mitigation();
152 	spectre_v2_select_mitigation();
153 	/*
154 	 * retbleed_select_mitigation() relies on the state set by
155 	 * spectre_v2_select_mitigation(); specifically it wants to know about
156 	 * spectre_v2=ibrs.
157 	 */
158 	retbleed_select_mitigation();
159 	/*
160 	 * spectre_v2_user_select_mitigation() relies on the state set by
161 	 * retbleed_select_mitigation(); specifically the STIBP selection is
162 	 * forced for UNRET or IBPB.
163 	 */
164 	spectre_v2_user_select_mitigation();
165 	ssb_select_mitigation();
166 	l1tf_select_mitigation();
167 	md_clear_select_mitigation();
168 	srbds_select_mitigation();
169 	l1d_flush_select_mitigation();
170 
171 	arch_smt_update();
172 
173 #ifdef CONFIG_X86_32
174 	/*
175 	 * Check whether we are able to run this kernel safely on SMP.
176 	 *
177 	 * - i386 is no longer supported.
178 	 * - In order to run on anything without a TSC, we need to be
179 	 *   compiled for a i486.
180 	 */
181 	if (boot_cpu_data.x86 < 4)
182 		panic("Kernel requires i486+ for 'invlpg' and other features");
183 
184 	init_utsname()->machine[1] =
185 		'0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
186 	alternative_instructions();
187 
188 	fpu__init_check_bugs();
189 #else /* CONFIG_X86_64 */
190 	alternative_instructions();
191 
192 	/*
193 	 * Make sure the first 2MB area is not mapped by huge pages
194 	 * There are typically fixed size MTRRs in there and overlapping
195 	 * MTRRs into large pages causes slow downs.
196 	 *
197 	 * Right now we don't do that with gbpages because there seems
198 	 * very little benefit for that case.
199 	 */
200 	if (!direct_gbpages)
201 		set_memory_4k((unsigned long)__va(0), 1);
202 #endif
203 }
204 
205 /*
206  * NOTE: This function is *only* called for SVM, since Intel uses
207  * MSR_IA32_SPEC_CTRL for SSBD.
208  */
209 void
x86_virt_spec_ctrl(u64 guest_virt_spec_ctrl,bool setguest)210 x86_virt_spec_ctrl(u64 guest_virt_spec_ctrl, bool setguest)
211 {
212 	u64 guestval, hostval;
213 	struct thread_info *ti = current_thread_info();
214 
215 	/*
216 	 * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
217 	 * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
218 	 */
219 	if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
220 	    !static_cpu_has(X86_FEATURE_VIRT_SSBD))
221 		return;
222 
223 	/*
224 	 * If the host has SSBD mitigation enabled, force it in the host's
225 	 * virtual MSR value. If its not permanently enabled, evaluate
226 	 * current's TIF_SSBD thread flag.
227 	 */
228 	if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE))
229 		hostval = SPEC_CTRL_SSBD;
230 	else
231 		hostval = ssbd_tif_to_spec_ctrl(ti->flags);
232 
233 	/* Sanitize the guest value */
234 	guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD;
235 
236 	if (hostval != guestval) {
237 		unsigned long tif;
238 
239 		tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) :
240 				 ssbd_spec_ctrl_to_tif(hostval);
241 
242 		speculation_ctrl_update(tif);
243 	}
244 }
245 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl);
246 
x86_amd_ssb_disable(void)247 static void x86_amd_ssb_disable(void)
248 {
249 	u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;
250 
251 	if (boot_cpu_has(X86_FEATURE_VIRT_SSBD))
252 		wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD);
253 	else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
254 		wrmsrl(MSR_AMD64_LS_CFG, msrval);
255 }
256 
257 #undef pr_fmt
258 #define pr_fmt(fmt)	"MDS: " fmt
259 
260 /* Default mitigation for MDS-affected CPUs */
261 static enum mds_mitigations mds_mitigation __ro_after_init = MDS_MITIGATION_FULL;
262 static bool mds_nosmt __ro_after_init = false;
263 
264 static const char * const mds_strings[] = {
265 	[MDS_MITIGATION_OFF]	= "Vulnerable",
266 	[MDS_MITIGATION_FULL]	= "Mitigation: Clear CPU buffers",
267 	[MDS_MITIGATION_VMWERV]	= "Vulnerable: Clear CPU buffers attempted, no microcode",
268 };
269 
mds_select_mitigation(void)270 static void __init mds_select_mitigation(void)
271 {
272 	if (!boot_cpu_has_bug(X86_BUG_MDS) || cpu_mitigations_off()) {
273 		mds_mitigation = MDS_MITIGATION_OFF;
274 		return;
275 	}
276 
277 	if (mds_mitigation == MDS_MITIGATION_FULL) {
278 		if (!boot_cpu_has(X86_FEATURE_MD_CLEAR))
279 			mds_mitigation = MDS_MITIGATION_VMWERV;
280 
281 		static_branch_enable(&mds_user_clear);
282 
283 		if (!boot_cpu_has(X86_BUG_MSBDS_ONLY) &&
284 		    (mds_nosmt || cpu_mitigations_auto_nosmt()))
285 			cpu_smt_disable(false);
286 	}
287 }
288 
mds_cmdline(char * str)289 static int __init mds_cmdline(char *str)
290 {
291 	if (!boot_cpu_has_bug(X86_BUG_MDS))
292 		return 0;
293 
294 	if (!str)
295 		return -EINVAL;
296 
297 	if (!strcmp(str, "off"))
298 		mds_mitigation = MDS_MITIGATION_OFF;
299 	else if (!strcmp(str, "full"))
300 		mds_mitigation = MDS_MITIGATION_FULL;
301 	else if (!strcmp(str, "full,nosmt")) {
302 		mds_mitigation = MDS_MITIGATION_FULL;
303 		mds_nosmt = true;
304 	}
305 
306 	return 0;
307 }
308 early_param("mds", mds_cmdline);
309 
310 #undef pr_fmt
311 #define pr_fmt(fmt)	"TAA: " fmt
312 
313 enum taa_mitigations {
314 	TAA_MITIGATION_OFF,
315 	TAA_MITIGATION_UCODE_NEEDED,
316 	TAA_MITIGATION_VERW,
317 	TAA_MITIGATION_TSX_DISABLED,
318 };
319 
320 /* Default mitigation for TAA-affected CPUs */
321 static enum taa_mitigations taa_mitigation __ro_after_init = TAA_MITIGATION_VERW;
322 static bool taa_nosmt __ro_after_init;
323 
324 static const char * const taa_strings[] = {
325 	[TAA_MITIGATION_OFF]		= "Vulnerable",
326 	[TAA_MITIGATION_UCODE_NEEDED]	= "Vulnerable: Clear CPU buffers attempted, no microcode",
327 	[TAA_MITIGATION_VERW]		= "Mitigation: Clear CPU buffers",
328 	[TAA_MITIGATION_TSX_DISABLED]	= "Mitigation: TSX disabled",
329 };
330 
taa_select_mitigation(void)331 static void __init taa_select_mitigation(void)
332 {
333 	u64 ia32_cap;
334 
335 	if (!boot_cpu_has_bug(X86_BUG_TAA)) {
336 		taa_mitigation = TAA_MITIGATION_OFF;
337 		return;
338 	}
339 
340 	/* TSX previously disabled by tsx=off */
341 	if (!boot_cpu_has(X86_FEATURE_RTM)) {
342 		taa_mitigation = TAA_MITIGATION_TSX_DISABLED;
343 		return;
344 	}
345 
346 	if (cpu_mitigations_off()) {
347 		taa_mitigation = TAA_MITIGATION_OFF;
348 		return;
349 	}
350 
351 	/*
352 	 * TAA mitigation via VERW is turned off if both
353 	 * tsx_async_abort=off and mds=off are specified.
354 	 */
355 	if (taa_mitigation == TAA_MITIGATION_OFF &&
356 	    mds_mitigation == MDS_MITIGATION_OFF)
357 		return;
358 
359 	if (boot_cpu_has(X86_FEATURE_MD_CLEAR))
360 		taa_mitigation = TAA_MITIGATION_VERW;
361 	else
362 		taa_mitigation = TAA_MITIGATION_UCODE_NEEDED;
363 
364 	/*
365 	 * VERW doesn't clear the CPU buffers when MD_CLEAR=1 and MDS_NO=1.
366 	 * A microcode update fixes this behavior to clear CPU buffers. It also
367 	 * adds support for MSR_IA32_TSX_CTRL which is enumerated by the
368 	 * ARCH_CAP_TSX_CTRL_MSR bit.
369 	 *
370 	 * On MDS_NO=1 CPUs if ARCH_CAP_TSX_CTRL_MSR is not set, microcode
371 	 * update is required.
372 	 */
373 	ia32_cap = x86_read_arch_cap_msr();
374 	if ( (ia32_cap & ARCH_CAP_MDS_NO) &&
375 	    !(ia32_cap & ARCH_CAP_TSX_CTRL_MSR))
376 		taa_mitigation = TAA_MITIGATION_UCODE_NEEDED;
377 
378 	/*
379 	 * TSX is enabled, select alternate mitigation for TAA which is
380 	 * the same as MDS. Enable MDS static branch to clear CPU buffers.
381 	 *
382 	 * For guests that can't determine whether the correct microcode is
383 	 * present on host, enable the mitigation for UCODE_NEEDED as well.
384 	 */
385 	static_branch_enable(&mds_user_clear);
386 
387 	if (taa_nosmt || cpu_mitigations_auto_nosmt())
388 		cpu_smt_disable(false);
389 }
390 
tsx_async_abort_parse_cmdline(char * str)391 static int __init tsx_async_abort_parse_cmdline(char *str)
392 {
393 	if (!boot_cpu_has_bug(X86_BUG_TAA))
394 		return 0;
395 
396 	if (!str)
397 		return -EINVAL;
398 
399 	if (!strcmp(str, "off")) {
400 		taa_mitigation = TAA_MITIGATION_OFF;
401 	} else if (!strcmp(str, "full")) {
402 		taa_mitigation = TAA_MITIGATION_VERW;
403 	} else if (!strcmp(str, "full,nosmt")) {
404 		taa_mitigation = TAA_MITIGATION_VERW;
405 		taa_nosmt = true;
406 	}
407 
408 	return 0;
409 }
410 early_param("tsx_async_abort", tsx_async_abort_parse_cmdline);
411 
412 #undef pr_fmt
413 #define pr_fmt(fmt)	"MMIO Stale Data: " fmt
414 
415 enum mmio_mitigations {
416 	MMIO_MITIGATION_OFF,
417 	MMIO_MITIGATION_UCODE_NEEDED,
418 	MMIO_MITIGATION_VERW,
419 };
420 
421 /* Default mitigation for Processor MMIO Stale Data vulnerabilities */
422 static enum mmio_mitigations mmio_mitigation __ro_after_init = MMIO_MITIGATION_VERW;
423 static bool mmio_nosmt __ro_after_init = false;
424 
425 static const char * const mmio_strings[] = {
426 	[MMIO_MITIGATION_OFF]		= "Vulnerable",
427 	[MMIO_MITIGATION_UCODE_NEEDED]	= "Vulnerable: Clear CPU buffers attempted, no microcode",
428 	[MMIO_MITIGATION_VERW]		= "Mitigation: Clear CPU buffers",
429 };
430 
mmio_select_mitigation(void)431 static void __init mmio_select_mitigation(void)
432 {
433 	u64 ia32_cap;
434 
435 	if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA) ||
436 	     boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN) ||
437 	     cpu_mitigations_off()) {
438 		mmio_mitigation = MMIO_MITIGATION_OFF;
439 		return;
440 	}
441 
442 	if (mmio_mitigation == MMIO_MITIGATION_OFF)
443 		return;
444 
445 	ia32_cap = x86_read_arch_cap_msr();
446 
447 	/*
448 	 * Enable CPU buffer clear mitigation for host and VMM, if also affected
449 	 * by MDS or TAA. Otherwise, enable mitigation for VMM only.
450 	 */
451 	if (boot_cpu_has_bug(X86_BUG_MDS) || (boot_cpu_has_bug(X86_BUG_TAA) &&
452 					      boot_cpu_has(X86_FEATURE_RTM)))
453 		static_branch_enable(&mds_user_clear);
454 	else
455 		static_branch_enable(&mmio_stale_data_clear);
456 
457 	/*
458 	 * If Processor-MMIO-Stale-Data bug is present and Fill Buffer data can
459 	 * be propagated to uncore buffers, clearing the Fill buffers on idle
460 	 * is required irrespective of SMT state.
461 	 */
462 	if (!(ia32_cap & ARCH_CAP_FBSDP_NO))
463 		static_branch_enable(&mds_idle_clear);
464 
465 	/*
466 	 * Check if the system has the right microcode.
467 	 *
468 	 * CPU Fill buffer clear mitigation is enumerated by either an explicit
469 	 * FB_CLEAR or by the presence of both MD_CLEAR and L1D_FLUSH on MDS
470 	 * affected systems.
471 	 */
472 	if ((ia32_cap & ARCH_CAP_FB_CLEAR) ||
473 	    (boot_cpu_has(X86_FEATURE_MD_CLEAR) &&
474 	     boot_cpu_has(X86_FEATURE_FLUSH_L1D) &&
475 	     !(ia32_cap & ARCH_CAP_MDS_NO)))
476 		mmio_mitigation = MMIO_MITIGATION_VERW;
477 	else
478 		mmio_mitigation = MMIO_MITIGATION_UCODE_NEEDED;
479 
480 	if (mmio_nosmt || cpu_mitigations_auto_nosmt())
481 		cpu_smt_disable(false);
482 }
483 
mmio_stale_data_parse_cmdline(char * str)484 static int __init mmio_stale_data_parse_cmdline(char *str)
485 {
486 	if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
487 		return 0;
488 
489 	if (!str)
490 		return -EINVAL;
491 
492 	if (!strcmp(str, "off")) {
493 		mmio_mitigation = MMIO_MITIGATION_OFF;
494 	} else if (!strcmp(str, "full")) {
495 		mmio_mitigation = MMIO_MITIGATION_VERW;
496 	} else if (!strcmp(str, "full,nosmt")) {
497 		mmio_mitigation = MMIO_MITIGATION_VERW;
498 		mmio_nosmt = true;
499 	}
500 
501 	return 0;
502 }
503 early_param("mmio_stale_data", mmio_stale_data_parse_cmdline);
504 
505 #undef pr_fmt
506 #define pr_fmt(fmt)     "" fmt
507 
md_clear_update_mitigation(void)508 static void __init md_clear_update_mitigation(void)
509 {
510 	if (cpu_mitigations_off())
511 		return;
512 
513 	if (!static_key_enabled(&mds_user_clear))
514 		goto out;
515 
516 	/*
517 	 * mds_user_clear is now enabled. Update MDS, TAA and MMIO Stale Data
518 	 * mitigation, if necessary.
519 	 */
520 	if (mds_mitigation == MDS_MITIGATION_OFF &&
521 	    boot_cpu_has_bug(X86_BUG_MDS)) {
522 		mds_mitigation = MDS_MITIGATION_FULL;
523 		mds_select_mitigation();
524 	}
525 	if (taa_mitigation == TAA_MITIGATION_OFF &&
526 	    boot_cpu_has_bug(X86_BUG_TAA)) {
527 		taa_mitigation = TAA_MITIGATION_VERW;
528 		taa_select_mitigation();
529 	}
530 	if (mmio_mitigation == MMIO_MITIGATION_OFF &&
531 	    boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA)) {
532 		mmio_mitigation = MMIO_MITIGATION_VERW;
533 		mmio_select_mitigation();
534 	}
535 out:
536 	if (boot_cpu_has_bug(X86_BUG_MDS))
537 		pr_info("MDS: %s\n", mds_strings[mds_mitigation]);
538 	if (boot_cpu_has_bug(X86_BUG_TAA))
539 		pr_info("TAA: %s\n", taa_strings[taa_mitigation]);
540 	if (boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
541 		pr_info("MMIO Stale Data: %s\n", mmio_strings[mmio_mitigation]);
542 	else if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN))
543 		pr_info("MMIO Stale Data: Unknown: No mitigations\n");
544 }
545 
md_clear_select_mitigation(void)546 static void __init md_clear_select_mitigation(void)
547 {
548 	mds_select_mitigation();
549 	taa_select_mitigation();
550 	mmio_select_mitigation();
551 
552 	/*
553 	 * As MDS, TAA and MMIO Stale Data mitigations are inter-related, update
554 	 * and print their mitigation after MDS, TAA and MMIO Stale Data
555 	 * mitigation selection is done.
556 	 */
557 	md_clear_update_mitigation();
558 }
559 
560 #undef pr_fmt
561 #define pr_fmt(fmt)	"SRBDS: " fmt
562 
563 enum srbds_mitigations {
564 	SRBDS_MITIGATION_OFF,
565 	SRBDS_MITIGATION_UCODE_NEEDED,
566 	SRBDS_MITIGATION_FULL,
567 	SRBDS_MITIGATION_TSX_OFF,
568 	SRBDS_MITIGATION_HYPERVISOR,
569 };
570 
571 static enum srbds_mitigations srbds_mitigation __ro_after_init = SRBDS_MITIGATION_FULL;
572 
573 static const char * const srbds_strings[] = {
574 	[SRBDS_MITIGATION_OFF]		= "Vulnerable",
575 	[SRBDS_MITIGATION_UCODE_NEEDED]	= "Vulnerable: No microcode",
576 	[SRBDS_MITIGATION_FULL]		= "Mitigation: Microcode",
577 	[SRBDS_MITIGATION_TSX_OFF]	= "Mitigation: TSX disabled",
578 	[SRBDS_MITIGATION_HYPERVISOR]	= "Unknown: Dependent on hypervisor status",
579 };
580 
581 static bool srbds_off;
582 
update_srbds_msr(void)583 void update_srbds_msr(void)
584 {
585 	u64 mcu_ctrl;
586 
587 	if (!boot_cpu_has_bug(X86_BUG_SRBDS))
588 		return;
589 
590 	if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
591 		return;
592 
593 	if (srbds_mitigation == SRBDS_MITIGATION_UCODE_NEEDED)
594 		return;
595 
596 	/*
597 	 * A MDS_NO CPU for which SRBDS mitigation is not needed due to TSX
598 	 * being disabled and it hasn't received the SRBDS MSR microcode.
599 	 */
600 	if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL))
601 		return;
602 
603 	rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
604 
605 	switch (srbds_mitigation) {
606 	case SRBDS_MITIGATION_OFF:
607 	case SRBDS_MITIGATION_TSX_OFF:
608 		mcu_ctrl |= RNGDS_MITG_DIS;
609 		break;
610 	case SRBDS_MITIGATION_FULL:
611 		mcu_ctrl &= ~RNGDS_MITG_DIS;
612 		break;
613 	default:
614 		break;
615 	}
616 
617 	wrmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
618 }
619 
srbds_select_mitigation(void)620 static void __init srbds_select_mitigation(void)
621 {
622 	u64 ia32_cap;
623 
624 	if (!boot_cpu_has_bug(X86_BUG_SRBDS))
625 		return;
626 
627 	/*
628 	 * Check to see if this is one of the MDS_NO systems supporting TSX that
629 	 * are only exposed to SRBDS when TSX is enabled or when CPU is affected
630 	 * by Processor MMIO Stale Data vulnerability.
631 	 */
632 	ia32_cap = x86_read_arch_cap_msr();
633 	if ((ia32_cap & ARCH_CAP_MDS_NO) && !boot_cpu_has(X86_FEATURE_RTM) &&
634 	    !boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
635 		srbds_mitigation = SRBDS_MITIGATION_TSX_OFF;
636 	else if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
637 		srbds_mitigation = SRBDS_MITIGATION_HYPERVISOR;
638 	else if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL))
639 		srbds_mitigation = SRBDS_MITIGATION_UCODE_NEEDED;
640 	else if (cpu_mitigations_off() || srbds_off)
641 		srbds_mitigation = SRBDS_MITIGATION_OFF;
642 
643 	update_srbds_msr();
644 	pr_info("%s\n", srbds_strings[srbds_mitigation]);
645 }
646 
srbds_parse_cmdline(char * str)647 static int __init srbds_parse_cmdline(char *str)
648 {
649 	if (!str)
650 		return -EINVAL;
651 
652 	if (!boot_cpu_has_bug(X86_BUG_SRBDS))
653 		return 0;
654 
655 	srbds_off = !strcmp(str, "off");
656 	return 0;
657 }
658 early_param("srbds", srbds_parse_cmdline);
659 
660 #undef pr_fmt
661 #define pr_fmt(fmt)     "L1D Flush : " fmt
662 
663 enum l1d_flush_mitigations {
664 	L1D_FLUSH_OFF = 0,
665 	L1D_FLUSH_ON,
666 };
667 
668 static enum l1d_flush_mitigations l1d_flush_mitigation __initdata = L1D_FLUSH_OFF;
669 
l1d_flush_select_mitigation(void)670 static void __init l1d_flush_select_mitigation(void)
671 {
672 	if (!l1d_flush_mitigation || !boot_cpu_has(X86_FEATURE_FLUSH_L1D))
673 		return;
674 
675 	static_branch_enable(&switch_mm_cond_l1d_flush);
676 	pr_info("Conditional flush on switch_mm() enabled\n");
677 }
678 
l1d_flush_parse_cmdline(char * str)679 static int __init l1d_flush_parse_cmdline(char *str)
680 {
681 	if (!strcmp(str, "on"))
682 		l1d_flush_mitigation = L1D_FLUSH_ON;
683 
684 	return 0;
685 }
686 early_param("l1d_flush", l1d_flush_parse_cmdline);
687 
688 #undef pr_fmt
689 #define pr_fmt(fmt)     "Spectre V1 : " fmt
690 
691 enum spectre_v1_mitigation {
692 	SPECTRE_V1_MITIGATION_NONE,
693 	SPECTRE_V1_MITIGATION_AUTO,
694 };
695 
696 static enum spectre_v1_mitigation spectre_v1_mitigation __ro_after_init =
697 	SPECTRE_V1_MITIGATION_AUTO;
698 
699 static const char * const spectre_v1_strings[] = {
700 	[SPECTRE_V1_MITIGATION_NONE] = "Vulnerable: __user pointer sanitization and usercopy barriers only; no swapgs barriers",
701 	[SPECTRE_V1_MITIGATION_AUTO] = "Mitigation: usercopy/swapgs barriers and __user pointer sanitization",
702 };
703 
704 /*
705  * Does SMAP provide full mitigation against speculative kernel access to
706  * userspace?
707  */
smap_works_speculatively(void)708 static bool smap_works_speculatively(void)
709 {
710 	if (!boot_cpu_has(X86_FEATURE_SMAP))
711 		return false;
712 
713 	/*
714 	 * On CPUs which are vulnerable to Meltdown, SMAP does not
715 	 * prevent speculative access to user data in the L1 cache.
716 	 * Consider SMAP to be non-functional as a mitigation on these
717 	 * CPUs.
718 	 */
719 	if (boot_cpu_has(X86_BUG_CPU_MELTDOWN))
720 		return false;
721 
722 	return true;
723 }
724 
spectre_v1_select_mitigation(void)725 static void __init spectre_v1_select_mitigation(void)
726 {
727 	if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V1) || cpu_mitigations_off()) {
728 		spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE;
729 		return;
730 	}
731 
732 	if (spectre_v1_mitigation == SPECTRE_V1_MITIGATION_AUTO) {
733 		/*
734 		 * With Spectre v1, a user can speculatively control either
735 		 * path of a conditional swapgs with a user-controlled GS
736 		 * value.  The mitigation is to add lfences to both code paths.
737 		 *
738 		 * If FSGSBASE is enabled, the user can put a kernel address in
739 		 * GS, in which case SMAP provides no protection.
740 		 *
741 		 * If FSGSBASE is disabled, the user can only put a user space
742 		 * address in GS.  That makes an attack harder, but still
743 		 * possible if there's no SMAP protection.
744 		 */
745 		if (boot_cpu_has(X86_FEATURE_FSGSBASE) ||
746 		    !smap_works_speculatively()) {
747 			/*
748 			 * Mitigation can be provided from SWAPGS itself or
749 			 * PTI as the CR3 write in the Meltdown mitigation
750 			 * is serializing.
751 			 *
752 			 * If neither is there, mitigate with an LFENCE to
753 			 * stop speculation through swapgs.
754 			 */
755 			if (boot_cpu_has_bug(X86_BUG_SWAPGS) &&
756 			    !boot_cpu_has(X86_FEATURE_PTI))
757 				setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_USER);
758 
759 			/*
760 			 * Enable lfences in the kernel entry (non-swapgs)
761 			 * paths, to prevent user entry from speculatively
762 			 * skipping swapgs.
763 			 */
764 			setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_KERNEL);
765 		}
766 	}
767 
768 	pr_info("%s\n", spectre_v1_strings[spectre_v1_mitigation]);
769 }
770 
nospectre_v1_cmdline(char * str)771 static int __init nospectre_v1_cmdline(char *str)
772 {
773 	spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE;
774 	return 0;
775 }
776 early_param("nospectre_v1", nospectre_v1_cmdline);
777 
778 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init =
779 	SPECTRE_V2_NONE;
780 
781 #undef pr_fmt
782 #define pr_fmt(fmt)     "RETBleed: " fmt
783 
784 enum retbleed_mitigation {
785 	RETBLEED_MITIGATION_NONE,
786 	RETBLEED_MITIGATION_UNRET,
787 	RETBLEED_MITIGATION_IBPB,
788 	RETBLEED_MITIGATION_IBRS,
789 	RETBLEED_MITIGATION_EIBRS,
790 };
791 
792 enum retbleed_mitigation_cmd {
793 	RETBLEED_CMD_OFF,
794 	RETBLEED_CMD_AUTO,
795 	RETBLEED_CMD_UNRET,
796 	RETBLEED_CMD_IBPB,
797 };
798 
799 static const char * const retbleed_strings[] = {
800 	[RETBLEED_MITIGATION_NONE]	= "Vulnerable",
801 	[RETBLEED_MITIGATION_UNRET]	= "Mitigation: untrained return thunk",
802 	[RETBLEED_MITIGATION_IBPB]	= "Mitigation: IBPB",
803 	[RETBLEED_MITIGATION_IBRS]	= "Mitigation: IBRS",
804 	[RETBLEED_MITIGATION_EIBRS]	= "Mitigation: Enhanced IBRS",
805 };
806 
807 static enum retbleed_mitigation retbleed_mitigation __ro_after_init =
808 	RETBLEED_MITIGATION_NONE;
809 static enum retbleed_mitigation_cmd retbleed_cmd __ro_after_init =
810 	RETBLEED_CMD_AUTO;
811 
812 static int __ro_after_init retbleed_nosmt = false;
813 
retbleed_parse_cmdline(char * str)814 static int __init retbleed_parse_cmdline(char *str)
815 {
816 	if (!str)
817 		return -EINVAL;
818 
819 	while (str) {
820 		char *next = strchr(str, ',');
821 		if (next) {
822 			*next = 0;
823 			next++;
824 		}
825 
826 		if (!strcmp(str, "off")) {
827 			retbleed_cmd = RETBLEED_CMD_OFF;
828 		} else if (!strcmp(str, "auto")) {
829 			retbleed_cmd = RETBLEED_CMD_AUTO;
830 		} else if (!strcmp(str, "unret")) {
831 			retbleed_cmd = RETBLEED_CMD_UNRET;
832 		} else if (!strcmp(str, "ibpb")) {
833 			retbleed_cmd = RETBLEED_CMD_IBPB;
834 		} else if (!strcmp(str, "nosmt")) {
835 			retbleed_nosmt = true;
836 		} else {
837 			pr_err("Ignoring unknown retbleed option (%s).", str);
838 		}
839 
840 		str = next;
841 	}
842 
843 	return 0;
844 }
845 early_param("retbleed", retbleed_parse_cmdline);
846 
847 #define RETBLEED_UNTRAIN_MSG "WARNING: BTB untrained return thunk mitigation is only effective on AMD/Hygon!\n"
848 #define RETBLEED_INTEL_MSG "WARNING: Spectre v2 mitigation leaves CPU vulnerable to RETBleed attacks, data leaks possible!\n"
849 
retbleed_select_mitigation(void)850 static void __init retbleed_select_mitigation(void)
851 {
852 	bool mitigate_smt = false;
853 
854 	if (!boot_cpu_has_bug(X86_BUG_RETBLEED) || cpu_mitigations_off())
855 		return;
856 
857 	switch (retbleed_cmd) {
858 	case RETBLEED_CMD_OFF:
859 		return;
860 
861 	case RETBLEED_CMD_UNRET:
862 		if (IS_ENABLED(CONFIG_CPU_UNRET_ENTRY)) {
863 			retbleed_mitigation = RETBLEED_MITIGATION_UNRET;
864 		} else {
865 			pr_err("WARNING: kernel not compiled with CPU_UNRET_ENTRY.\n");
866 			goto do_cmd_auto;
867 		}
868 		break;
869 
870 	case RETBLEED_CMD_IBPB:
871 		if (!boot_cpu_has(X86_FEATURE_IBPB)) {
872 			pr_err("WARNING: CPU does not support IBPB.\n");
873 			goto do_cmd_auto;
874 		} else if (IS_ENABLED(CONFIG_CPU_IBPB_ENTRY)) {
875 			retbleed_mitigation = RETBLEED_MITIGATION_IBPB;
876 		} else {
877 			pr_err("WARNING: kernel not compiled with CPU_IBPB_ENTRY.\n");
878 			goto do_cmd_auto;
879 		}
880 		break;
881 
882 do_cmd_auto:
883 	case RETBLEED_CMD_AUTO:
884 	default:
885 		if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
886 		    boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
887 			if (IS_ENABLED(CONFIG_CPU_UNRET_ENTRY))
888 				retbleed_mitigation = RETBLEED_MITIGATION_UNRET;
889 			else if (IS_ENABLED(CONFIG_CPU_IBPB_ENTRY) && boot_cpu_has(X86_FEATURE_IBPB))
890 				retbleed_mitigation = RETBLEED_MITIGATION_IBPB;
891 		}
892 
893 		/*
894 		 * The Intel mitigation (IBRS or eIBRS) was already selected in
895 		 * spectre_v2_select_mitigation().  'retbleed_mitigation' will
896 		 * be set accordingly below.
897 		 */
898 
899 		break;
900 	}
901 
902 	switch (retbleed_mitigation) {
903 	case RETBLEED_MITIGATION_UNRET:
904 		setup_force_cpu_cap(X86_FEATURE_RETHUNK);
905 		setup_force_cpu_cap(X86_FEATURE_UNRET);
906 
907 		if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
908 		    boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
909 			pr_err(RETBLEED_UNTRAIN_MSG);
910 
911 		mitigate_smt = true;
912 		break;
913 
914 	case RETBLEED_MITIGATION_IBPB:
915 		setup_force_cpu_cap(X86_FEATURE_ENTRY_IBPB);
916 		mitigate_smt = true;
917 		break;
918 
919 	default:
920 		break;
921 	}
922 
923 	if (mitigate_smt && !boot_cpu_has(X86_FEATURE_STIBP) &&
924 	    (retbleed_nosmt || cpu_mitigations_auto_nosmt()))
925 		cpu_smt_disable(false);
926 
927 	/*
928 	 * Let IBRS trump all on Intel without affecting the effects of the
929 	 * retbleed= cmdline option.
930 	 */
931 	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {
932 		switch (spectre_v2_enabled) {
933 		case SPECTRE_V2_IBRS:
934 			retbleed_mitigation = RETBLEED_MITIGATION_IBRS;
935 			break;
936 		case SPECTRE_V2_EIBRS:
937 		case SPECTRE_V2_EIBRS_RETPOLINE:
938 		case SPECTRE_V2_EIBRS_LFENCE:
939 			retbleed_mitigation = RETBLEED_MITIGATION_EIBRS;
940 			break;
941 		default:
942 			pr_err(RETBLEED_INTEL_MSG);
943 		}
944 	}
945 
946 	pr_info("%s\n", retbleed_strings[retbleed_mitigation]);
947 }
948 
949 #undef pr_fmt
950 #define pr_fmt(fmt)     "Spectre V2 : " fmt
951 
952 static enum spectre_v2_user_mitigation spectre_v2_user_stibp __ro_after_init =
953 	SPECTRE_V2_USER_NONE;
954 static enum spectre_v2_user_mitigation spectre_v2_user_ibpb __ro_after_init =
955 	SPECTRE_V2_USER_NONE;
956 
957 #ifdef CONFIG_RETPOLINE
958 static bool spectre_v2_bad_module;
959 
retpoline_module_ok(bool has_retpoline)960 bool retpoline_module_ok(bool has_retpoline)
961 {
962 	if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline)
963 		return true;
964 
965 	pr_err("System may be vulnerable to spectre v2\n");
966 	spectre_v2_bad_module = true;
967 	return false;
968 }
969 
spectre_v2_module_string(void)970 static inline const char *spectre_v2_module_string(void)
971 {
972 	return spectre_v2_bad_module ? " - vulnerable module loaded" : "";
973 }
974 #else
spectre_v2_module_string(void)975 static inline const char *spectre_v2_module_string(void) { return ""; }
976 #endif
977 
978 #define SPECTRE_V2_LFENCE_MSG "WARNING: LFENCE mitigation is not recommended for this CPU, data leaks possible!\n"
979 #define SPECTRE_V2_EIBRS_EBPF_MSG "WARNING: Unprivileged eBPF is enabled with eIBRS on, data leaks possible via Spectre v2 BHB attacks!\n"
980 #define SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG "WARNING: Unprivileged eBPF is enabled with eIBRS+LFENCE mitigation and SMT, data leaks possible via Spectre v2 BHB attacks!\n"
981 #define SPECTRE_V2_IBRS_PERF_MSG "WARNING: IBRS mitigation selected on Enhanced IBRS CPU, this may cause unnecessary performance loss\n"
982 
983 #ifdef CONFIG_BPF_SYSCALL
unpriv_ebpf_notify(int new_state)984 void unpriv_ebpf_notify(int new_state)
985 {
986 	if (new_state)
987 		return;
988 
989 	/* Unprivileged eBPF is enabled */
990 
991 	switch (spectre_v2_enabled) {
992 	case SPECTRE_V2_EIBRS:
993 		pr_err(SPECTRE_V2_EIBRS_EBPF_MSG);
994 		break;
995 	case SPECTRE_V2_EIBRS_LFENCE:
996 		if (sched_smt_active())
997 			pr_err(SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG);
998 		break;
999 	default:
1000 		break;
1001 	}
1002 }
1003 #endif
1004 
match_option(const char * arg,int arglen,const char * opt)1005 static inline bool match_option(const char *arg, int arglen, const char *opt)
1006 {
1007 	int len = strlen(opt);
1008 
1009 	return len == arglen && !strncmp(arg, opt, len);
1010 }
1011 
1012 /* The kernel command line selection for spectre v2 */
1013 enum spectre_v2_mitigation_cmd {
1014 	SPECTRE_V2_CMD_NONE,
1015 	SPECTRE_V2_CMD_AUTO,
1016 	SPECTRE_V2_CMD_FORCE,
1017 	SPECTRE_V2_CMD_RETPOLINE,
1018 	SPECTRE_V2_CMD_RETPOLINE_GENERIC,
1019 	SPECTRE_V2_CMD_RETPOLINE_LFENCE,
1020 	SPECTRE_V2_CMD_EIBRS,
1021 	SPECTRE_V2_CMD_EIBRS_RETPOLINE,
1022 	SPECTRE_V2_CMD_EIBRS_LFENCE,
1023 	SPECTRE_V2_CMD_IBRS,
1024 };
1025 
1026 enum spectre_v2_user_cmd {
1027 	SPECTRE_V2_USER_CMD_NONE,
1028 	SPECTRE_V2_USER_CMD_AUTO,
1029 	SPECTRE_V2_USER_CMD_FORCE,
1030 	SPECTRE_V2_USER_CMD_PRCTL,
1031 	SPECTRE_V2_USER_CMD_PRCTL_IBPB,
1032 	SPECTRE_V2_USER_CMD_SECCOMP,
1033 	SPECTRE_V2_USER_CMD_SECCOMP_IBPB,
1034 };
1035 
1036 static const char * const spectre_v2_user_strings[] = {
1037 	[SPECTRE_V2_USER_NONE]			= "User space: Vulnerable",
1038 	[SPECTRE_V2_USER_STRICT]		= "User space: Mitigation: STIBP protection",
1039 	[SPECTRE_V2_USER_STRICT_PREFERRED]	= "User space: Mitigation: STIBP always-on protection",
1040 	[SPECTRE_V2_USER_PRCTL]			= "User space: Mitigation: STIBP via prctl",
1041 	[SPECTRE_V2_USER_SECCOMP]		= "User space: Mitigation: STIBP via seccomp and prctl",
1042 };
1043 
1044 static const struct {
1045 	const char			*option;
1046 	enum spectre_v2_user_cmd	cmd;
1047 	bool				secure;
1048 } v2_user_options[] __initconst = {
1049 	{ "auto",		SPECTRE_V2_USER_CMD_AUTO,		false },
1050 	{ "off",		SPECTRE_V2_USER_CMD_NONE,		false },
1051 	{ "on",			SPECTRE_V2_USER_CMD_FORCE,		true  },
1052 	{ "prctl",		SPECTRE_V2_USER_CMD_PRCTL,		false },
1053 	{ "prctl,ibpb",		SPECTRE_V2_USER_CMD_PRCTL_IBPB,		false },
1054 	{ "seccomp",		SPECTRE_V2_USER_CMD_SECCOMP,		false },
1055 	{ "seccomp,ibpb",	SPECTRE_V2_USER_CMD_SECCOMP_IBPB,	false },
1056 };
1057 
spec_v2_user_print_cond(const char * reason,bool secure)1058 static void __init spec_v2_user_print_cond(const char *reason, bool secure)
1059 {
1060 	if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
1061 		pr_info("spectre_v2_user=%s forced on command line.\n", reason);
1062 }
1063 
1064 static __ro_after_init enum spectre_v2_mitigation_cmd spectre_v2_cmd;
1065 
1066 static enum spectre_v2_user_cmd __init
spectre_v2_parse_user_cmdline(void)1067 spectre_v2_parse_user_cmdline(void)
1068 {
1069 	char arg[20];
1070 	int ret, i;
1071 
1072 	switch (spectre_v2_cmd) {
1073 	case SPECTRE_V2_CMD_NONE:
1074 		return SPECTRE_V2_USER_CMD_NONE;
1075 	case SPECTRE_V2_CMD_FORCE:
1076 		return SPECTRE_V2_USER_CMD_FORCE;
1077 	default:
1078 		break;
1079 	}
1080 
1081 	ret = cmdline_find_option(boot_command_line, "spectre_v2_user",
1082 				  arg, sizeof(arg));
1083 	if (ret < 0)
1084 		return SPECTRE_V2_USER_CMD_AUTO;
1085 
1086 	for (i = 0; i < ARRAY_SIZE(v2_user_options); i++) {
1087 		if (match_option(arg, ret, v2_user_options[i].option)) {
1088 			spec_v2_user_print_cond(v2_user_options[i].option,
1089 						v2_user_options[i].secure);
1090 			return v2_user_options[i].cmd;
1091 		}
1092 	}
1093 
1094 	pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg);
1095 	return SPECTRE_V2_USER_CMD_AUTO;
1096 }
1097 
spectre_v2_in_ibrs_mode(enum spectre_v2_mitigation mode)1098 static inline bool spectre_v2_in_ibrs_mode(enum spectre_v2_mitigation mode)
1099 {
1100 	return mode == SPECTRE_V2_IBRS ||
1101 	       mode == SPECTRE_V2_EIBRS ||
1102 	       mode == SPECTRE_V2_EIBRS_RETPOLINE ||
1103 	       mode == SPECTRE_V2_EIBRS_LFENCE;
1104 }
1105 
1106 static void __init
spectre_v2_user_select_mitigation(void)1107 spectre_v2_user_select_mitigation(void)
1108 {
1109 	enum spectre_v2_user_mitigation mode = SPECTRE_V2_USER_NONE;
1110 	bool smt_possible = IS_ENABLED(CONFIG_SMP);
1111 	enum spectre_v2_user_cmd cmd;
1112 
1113 	if (!boot_cpu_has(X86_FEATURE_IBPB) && !boot_cpu_has(X86_FEATURE_STIBP))
1114 		return;
1115 
1116 	if (cpu_smt_control == CPU_SMT_FORCE_DISABLED ||
1117 	    cpu_smt_control == CPU_SMT_NOT_SUPPORTED)
1118 		smt_possible = false;
1119 
1120 	cmd = spectre_v2_parse_user_cmdline();
1121 	switch (cmd) {
1122 	case SPECTRE_V2_USER_CMD_NONE:
1123 		goto set_mode;
1124 	case SPECTRE_V2_USER_CMD_FORCE:
1125 		mode = SPECTRE_V2_USER_STRICT;
1126 		break;
1127 	case SPECTRE_V2_USER_CMD_AUTO:
1128 	case SPECTRE_V2_USER_CMD_PRCTL:
1129 	case SPECTRE_V2_USER_CMD_PRCTL_IBPB:
1130 		mode = SPECTRE_V2_USER_PRCTL;
1131 		break;
1132 	case SPECTRE_V2_USER_CMD_SECCOMP:
1133 	case SPECTRE_V2_USER_CMD_SECCOMP_IBPB:
1134 		if (IS_ENABLED(CONFIG_SECCOMP))
1135 			mode = SPECTRE_V2_USER_SECCOMP;
1136 		else
1137 			mode = SPECTRE_V2_USER_PRCTL;
1138 		break;
1139 	}
1140 
1141 	/* Initialize Indirect Branch Prediction Barrier */
1142 	if (boot_cpu_has(X86_FEATURE_IBPB)) {
1143 		setup_force_cpu_cap(X86_FEATURE_USE_IBPB);
1144 
1145 		spectre_v2_user_ibpb = mode;
1146 		switch (cmd) {
1147 		case SPECTRE_V2_USER_CMD_FORCE:
1148 		case SPECTRE_V2_USER_CMD_PRCTL_IBPB:
1149 		case SPECTRE_V2_USER_CMD_SECCOMP_IBPB:
1150 			static_branch_enable(&switch_mm_always_ibpb);
1151 			spectre_v2_user_ibpb = SPECTRE_V2_USER_STRICT;
1152 			break;
1153 		case SPECTRE_V2_USER_CMD_PRCTL:
1154 		case SPECTRE_V2_USER_CMD_AUTO:
1155 		case SPECTRE_V2_USER_CMD_SECCOMP:
1156 			static_branch_enable(&switch_mm_cond_ibpb);
1157 			break;
1158 		default:
1159 			break;
1160 		}
1161 
1162 		pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n",
1163 			static_key_enabled(&switch_mm_always_ibpb) ?
1164 			"always-on" : "conditional");
1165 	}
1166 
1167 	/*
1168 	 * If no STIBP, IBRS or enhanced IBRS is enabled, or SMT impossible,
1169 	 * STIBP is not required.
1170 	 */
1171 	if (!boot_cpu_has(X86_FEATURE_STIBP) ||
1172 	    !smt_possible ||
1173 	    spectre_v2_in_ibrs_mode(spectre_v2_enabled))
1174 		return;
1175 
1176 	/*
1177 	 * At this point, an STIBP mode other than "off" has been set.
1178 	 * If STIBP support is not being forced, check if STIBP always-on
1179 	 * is preferred.
1180 	 */
1181 	if (mode != SPECTRE_V2_USER_STRICT &&
1182 	    boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON))
1183 		mode = SPECTRE_V2_USER_STRICT_PREFERRED;
1184 
1185 	if (retbleed_mitigation == RETBLEED_MITIGATION_UNRET ||
1186 	    retbleed_mitigation == RETBLEED_MITIGATION_IBPB) {
1187 		if (mode != SPECTRE_V2_USER_STRICT &&
1188 		    mode != SPECTRE_V2_USER_STRICT_PREFERRED)
1189 			pr_info("Selecting STIBP always-on mode to complement retbleed mitigation\n");
1190 		mode = SPECTRE_V2_USER_STRICT_PREFERRED;
1191 	}
1192 
1193 	spectre_v2_user_stibp = mode;
1194 
1195 set_mode:
1196 	pr_info("%s\n", spectre_v2_user_strings[mode]);
1197 }
1198 
1199 static const char * const spectre_v2_strings[] = {
1200 	[SPECTRE_V2_NONE]			= "Vulnerable",
1201 	[SPECTRE_V2_RETPOLINE]			= "Mitigation: Retpolines",
1202 	[SPECTRE_V2_LFENCE]			= "Mitigation: LFENCE",
1203 	[SPECTRE_V2_EIBRS]			= "Mitigation: Enhanced IBRS",
1204 	[SPECTRE_V2_EIBRS_LFENCE]		= "Mitigation: Enhanced IBRS + LFENCE",
1205 	[SPECTRE_V2_EIBRS_RETPOLINE]		= "Mitigation: Enhanced IBRS + Retpolines",
1206 	[SPECTRE_V2_IBRS]			= "Mitigation: IBRS",
1207 };
1208 
1209 static const struct {
1210 	const char *option;
1211 	enum spectre_v2_mitigation_cmd cmd;
1212 	bool secure;
1213 } mitigation_options[] __initconst = {
1214 	{ "off",		SPECTRE_V2_CMD_NONE,		  false },
1215 	{ "on",			SPECTRE_V2_CMD_FORCE,		  true  },
1216 	{ "retpoline",		SPECTRE_V2_CMD_RETPOLINE,	  false },
1217 	{ "retpoline,amd",	SPECTRE_V2_CMD_RETPOLINE_LFENCE,  false },
1218 	{ "retpoline,lfence",	SPECTRE_V2_CMD_RETPOLINE_LFENCE,  false },
1219 	{ "retpoline,generic",	SPECTRE_V2_CMD_RETPOLINE_GENERIC, false },
1220 	{ "eibrs",		SPECTRE_V2_CMD_EIBRS,		  false },
1221 	{ "eibrs,lfence",	SPECTRE_V2_CMD_EIBRS_LFENCE,	  false },
1222 	{ "eibrs,retpoline",	SPECTRE_V2_CMD_EIBRS_RETPOLINE,	  false },
1223 	{ "auto",		SPECTRE_V2_CMD_AUTO,		  false },
1224 	{ "ibrs",		SPECTRE_V2_CMD_IBRS,              false },
1225 };
1226 
spec_v2_print_cond(const char * reason,bool secure)1227 static void __init spec_v2_print_cond(const char *reason, bool secure)
1228 {
1229 	if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
1230 		pr_info("%s selected on command line.\n", reason);
1231 }
1232 
spectre_v2_parse_cmdline(void)1233 static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
1234 {
1235 	enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO;
1236 	char arg[20];
1237 	int ret, i;
1238 
1239 	if (cmdline_find_option_bool(boot_command_line, "nospectre_v2") ||
1240 	    cpu_mitigations_off())
1241 		return SPECTRE_V2_CMD_NONE;
1242 
1243 	ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg));
1244 	if (ret < 0)
1245 		return SPECTRE_V2_CMD_AUTO;
1246 
1247 	for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) {
1248 		if (!match_option(arg, ret, mitigation_options[i].option))
1249 			continue;
1250 		cmd = mitigation_options[i].cmd;
1251 		break;
1252 	}
1253 
1254 	if (i >= ARRAY_SIZE(mitigation_options)) {
1255 		pr_err("unknown option (%s). Switching to AUTO select\n", arg);
1256 		return SPECTRE_V2_CMD_AUTO;
1257 	}
1258 
1259 	if ((cmd == SPECTRE_V2_CMD_RETPOLINE ||
1260 	     cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE ||
1261 	     cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC ||
1262 	     cmd == SPECTRE_V2_CMD_EIBRS_LFENCE ||
1263 	     cmd == SPECTRE_V2_CMD_EIBRS_RETPOLINE) &&
1264 	    !IS_ENABLED(CONFIG_RETPOLINE)) {
1265 		pr_err("%s selected but not compiled in. Switching to AUTO select\n",
1266 		       mitigation_options[i].option);
1267 		return SPECTRE_V2_CMD_AUTO;
1268 	}
1269 
1270 	if ((cmd == SPECTRE_V2_CMD_EIBRS ||
1271 	     cmd == SPECTRE_V2_CMD_EIBRS_LFENCE ||
1272 	     cmd == SPECTRE_V2_CMD_EIBRS_RETPOLINE) &&
1273 	    !boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) {
1274 		pr_err("%s selected but CPU doesn't have eIBRS. Switching to AUTO select\n",
1275 		       mitigation_options[i].option);
1276 		return SPECTRE_V2_CMD_AUTO;
1277 	}
1278 
1279 	if ((cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE ||
1280 	     cmd == SPECTRE_V2_CMD_EIBRS_LFENCE) &&
1281 	    !boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
1282 		pr_err("%s selected, but CPU doesn't have a serializing LFENCE. Switching to AUTO select\n",
1283 		       mitigation_options[i].option);
1284 		return SPECTRE_V2_CMD_AUTO;
1285 	}
1286 
1287 	if (cmd == SPECTRE_V2_CMD_IBRS && !IS_ENABLED(CONFIG_CPU_IBRS_ENTRY)) {
1288 		pr_err("%s selected but not compiled in. Switching to AUTO select\n",
1289 		       mitigation_options[i].option);
1290 		return SPECTRE_V2_CMD_AUTO;
1291 	}
1292 
1293 	if (cmd == SPECTRE_V2_CMD_IBRS && boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
1294 		pr_err("%s selected but not Intel CPU. Switching to AUTO select\n",
1295 		       mitigation_options[i].option);
1296 		return SPECTRE_V2_CMD_AUTO;
1297 	}
1298 
1299 	if (cmd == SPECTRE_V2_CMD_IBRS && !boot_cpu_has(X86_FEATURE_IBRS)) {
1300 		pr_err("%s selected but CPU doesn't have IBRS. Switching to AUTO select\n",
1301 		       mitigation_options[i].option);
1302 		return SPECTRE_V2_CMD_AUTO;
1303 	}
1304 
1305 	if (cmd == SPECTRE_V2_CMD_IBRS && boot_cpu_has(X86_FEATURE_XENPV)) {
1306 		pr_err("%s selected but running as XenPV guest. Switching to AUTO select\n",
1307 		       mitigation_options[i].option);
1308 		return SPECTRE_V2_CMD_AUTO;
1309 	}
1310 
1311 	spec_v2_print_cond(mitigation_options[i].option,
1312 			   mitigation_options[i].secure);
1313 	return cmd;
1314 }
1315 
spectre_v2_select_retpoline(void)1316 static enum spectre_v2_mitigation __init spectre_v2_select_retpoline(void)
1317 {
1318 	if (!IS_ENABLED(CONFIG_RETPOLINE)) {
1319 		pr_err("Kernel not compiled with retpoline; no mitigation available!");
1320 		return SPECTRE_V2_NONE;
1321 	}
1322 
1323 	return SPECTRE_V2_RETPOLINE;
1324 }
1325 
1326 /* Disable in-kernel use of non-RSB RET predictors */
spec_ctrl_disable_kernel_rrsba(void)1327 static void __init spec_ctrl_disable_kernel_rrsba(void)
1328 {
1329 	u64 ia32_cap;
1330 
1331 	if (!boot_cpu_has(X86_FEATURE_RRSBA_CTRL))
1332 		return;
1333 
1334 	ia32_cap = x86_read_arch_cap_msr();
1335 
1336 	if (ia32_cap & ARCH_CAP_RRSBA) {
1337 		x86_spec_ctrl_base |= SPEC_CTRL_RRSBA_DIS_S;
1338 		update_spec_ctrl(x86_spec_ctrl_base);
1339 	}
1340 }
1341 
spectre_v2_determine_rsb_fill_type_at_vmexit(enum spectre_v2_mitigation mode)1342 static void __init spectre_v2_determine_rsb_fill_type_at_vmexit(enum spectre_v2_mitigation mode)
1343 {
1344 	/*
1345 	 * Similar to context switches, there are two types of RSB attacks
1346 	 * after VM exit:
1347 	 *
1348 	 * 1) RSB underflow
1349 	 *
1350 	 * 2) Poisoned RSB entry
1351 	 *
1352 	 * When retpoline is enabled, both are mitigated by filling/clearing
1353 	 * the RSB.
1354 	 *
1355 	 * When IBRS is enabled, while #1 would be mitigated by the IBRS branch
1356 	 * prediction isolation protections, RSB still needs to be cleared
1357 	 * because of #2.  Note that SMEP provides no protection here, unlike
1358 	 * user-space-poisoned RSB entries.
1359 	 *
1360 	 * eIBRS should protect against RSB poisoning, but if the EIBRS_PBRSB
1361 	 * bug is present then a LITE version of RSB protection is required,
1362 	 * just a single call needs to retire before a RET is executed.
1363 	 */
1364 	switch (mode) {
1365 	case SPECTRE_V2_NONE:
1366 		return;
1367 
1368 	case SPECTRE_V2_EIBRS_LFENCE:
1369 	case SPECTRE_V2_EIBRS:
1370 		if (boot_cpu_has_bug(X86_BUG_EIBRS_PBRSB)) {
1371 			setup_force_cpu_cap(X86_FEATURE_RSB_VMEXIT_LITE);
1372 			pr_info("Spectre v2 / PBRSB-eIBRS: Retire a single CALL on VMEXIT\n");
1373 		}
1374 		return;
1375 
1376 	case SPECTRE_V2_EIBRS_RETPOLINE:
1377 	case SPECTRE_V2_RETPOLINE:
1378 	case SPECTRE_V2_LFENCE:
1379 	case SPECTRE_V2_IBRS:
1380 		setup_force_cpu_cap(X86_FEATURE_RSB_VMEXIT);
1381 		pr_info("Spectre v2 / SpectreRSB : Filling RSB on VMEXIT\n");
1382 		return;
1383 	}
1384 
1385 	pr_warn_once("Unknown Spectre v2 mode, disabling RSB mitigation at VM exit");
1386 	dump_stack();
1387 }
1388 
spectre_v2_select_mitigation(void)1389 static void __init spectre_v2_select_mitigation(void)
1390 {
1391 	enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
1392 	enum spectre_v2_mitigation mode = SPECTRE_V2_NONE;
1393 
1394 	/*
1395 	 * If the CPU is not affected and the command line mode is NONE or AUTO
1396 	 * then nothing to do.
1397 	 */
1398 	if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) &&
1399 	    (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO))
1400 		return;
1401 
1402 	switch (cmd) {
1403 	case SPECTRE_V2_CMD_NONE:
1404 		return;
1405 
1406 	case SPECTRE_V2_CMD_FORCE:
1407 	case SPECTRE_V2_CMD_AUTO:
1408 		if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) {
1409 			mode = SPECTRE_V2_EIBRS;
1410 			break;
1411 		}
1412 
1413 		if (IS_ENABLED(CONFIG_CPU_IBRS_ENTRY) &&
1414 		    boot_cpu_has_bug(X86_BUG_RETBLEED) &&
1415 		    retbleed_cmd != RETBLEED_CMD_OFF &&
1416 		    boot_cpu_has(X86_FEATURE_IBRS) &&
1417 		    boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {
1418 			mode = SPECTRE_V2_IBRS;
1419 			break;
1420 		}
1421 
1422 		mode = spectre_v2_select_retpoline();
1423 		break;
1424 
1425 	case SPECTRE_V2_CMD_RETPOLINE_LFENCE:
1426 		pr_err(SPECTRE_V2_LFENCE_MSG);
1427 		mode = SPECTRE_V2_LFENCE;
1428 		break;
1429 
1430 	case SPECTRE_V2_CMD_RETPOLINE_GENERIC:
1431 		mode = SPECTRE_V2_RETPOLINE;
1432 		break;
1433 
1434 	case SPECTRE_V2_CMD_RETPOLINE:
1435 		mode = spectre_v2_select_retpoline();
1436 		break;
1437 
1438 	case SPECTRE_V2_CMD_IBRS:
1439 		mode = SPECTRE_V2_IBRS;
1440 		break;
1441 
1442 	case SPECTRE_V2_CMD_EIBRS:
1443 		mode = SPECTRE_V2_EIBRS;
1444 		break;
1445 
1446 	case SPECTRE_V2_CMD_EIBRS_LFENCE:
1447 		mode = SPECTRE_V2_EIBRS_LFENCE;
1448 		break;
1449 
1450 	case SPECTRE_V2_CMD_EIBRS_RETPOLINE:
1451 		mode = SPECTRE_V2_EIBRS_RETPOLINE;
1452 		break;
1453 	}
1454 
1455 	if (mode == SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled())
1456 		pr_err(SPECTRE_V2_EIBRS_EBPF_MSG);
1457 
1458 	if (spectre_v2_in_ibrs_mode(mode)) {
1459 		x86_spec_ctrl_base |= SPEC_CTRL_IBRS;
1460 		update_spec_ctrl(x86_spec_ctrl_base);
1461 	}
1462 
1463 	switch (mode) {
1464 	case SPECTRE_V2_NONE:
1465 	case SPECTRE_V2_EIBRS:
1466 		break;
1467 
1468 	case SPECTRE_V2_IBRS:
1469 		setup_force_cpu_cap(X86_FEATURE_KERNEL_IBRS);
1470 		if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED))
1471 			pr_warn(SPECTRE_V2_IBRS_PERF_MSG);
1472 		break;
1473 
1474 	case SPECTRE_V2_LFENCE:
1475 	case SPECTRE_V2_EIBRS_LFENCE:
1476 		setup_force_cpu_cap(X86_FEATURE_RETPOLINE_LFENCE);
1477 		fallthrough;
1478 
1479 	case SPECTRE_V2_RETPOLINE:
1480 	case SPECTRE_V2_EIBRS_RETPOLINE:
1481 		setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
1482 		break;
1483 	}
1484 
1485 	/*
1486 	 * Disable alternate RSB predictions in kernel when indirect CALLs and
1487 	 * JMPs gets protection against BHI and Intramode-BTI, but RET
1488 	 * prediction from a non-RSB predictor is still a risk.
1489 	 */
1490 	if (mode == SPECTRE_V2_EIBRS_LFENCE ||
1491 	    mode == SPECTRE_V2_EIBRS_RETPOLINE ||
1492 	    mode == SPECTRE_V2_RETPOLINE)
1493 		spec_ctrl_disable_kernel_rrsba();
1494 
1495 	spectre_v2_enabled = mode;
1496 	pr_info("%s\n", spectre_v2_strings[mode]);
1497 
1498 	/*
1499 	 * If Spectre v2 protection has been enabled, fill the RSB during a
1500 	 * context switch.  In general there are two types of RSB attacks
1501 	 * across context switches, for which the CALLs/RETs may be unbalanced.
1502 	 *
1503 	 * 1) RSB underflow
1504 	 *
1505 	 *    Some Intel parts have "bottomless RSB".  When the RSB is empty,
1506 	 *    speculated return targets may come from the branch predictor,
1507 	 *    which could have a user-poisoned BTB or BHB entry.
1508 	 *
1509 	 *    AMD has it even worse: *all* returns are speculated from the BTB,
1510 	 *    regardless of the state of the RSB.
1511 	 *
1512 	 *    When IBRS or eIBRS is enabled, the "user -> kernel" attack
1513 	 *    scenario is mitigated by the IBRS branch prediction isolation
1514 	 *    properties, so the RSB buffer filling wouldn't be necessary to
1515 	 *    protect against this type of attack.
1516 	 *
1517 	 *    The "user -> user" attack scenario is mitigated by RSB filling.
1518 	 *
1519 	 * 2) Poisoned RSB entry
1520 	 *
1521 	 *    If the 'next' in-kernel return stack is shorter than 'prev',
1522 	 *    'next' could be tricked into speculating with a user-poisoned RSB
1523 	 *    entry.
1524 	 *
1525 	 *    The "user -> kernel" attack scenario is mitigated by SMEP and
1526 	 *    eIBRS.
1527 	 *
1528 	 *    The "user -> user" scenario, also known as SpectreBHB, requires
1529 	 *    RSB clearing.
1530 	 *
1531 	 * So to mitigate all cases, unconditionally fill RSB on context
1532 	 * switches.
1533 	 *
1534 	 * FIXME: Is this pointless for retbleed-affected AMD?
1535 	 */
1536 	setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
1537 	pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n");
1538 
1539 	spectre_v2_determine_rsb_fill_type_at_vmexit(mode);
1540 
1541 	/*
1542 	 * Retpoline protects the kernel, but doesn't protect firmware.  IBRS
1543 	 * and Enhanced IBRS protect firmware too, so enable IBRS around
1544 	 * firmware calls only when IBRS / Enhanced IBRS aren't otherwise
1545 	 * enabled.
1546 	 *
1547 	 * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because
1548 	 * the user might select retpoline on the kernel command line and if
1549 	 * the CPU supports Enhanced IBRS, kernel might un-intentionally not
1550 	 * enable IBRS around firmware calls.
1551 	 */
1552 	if (boot_cpu_has_bug(X86_BUG_RETBLEED) &&
1553 	    boot_cpu_has(X86_FEATURE_IBPB) &&
1554 	    (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
1555 	     boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)) {
1556 
1557 		if (retbleed_cmd != RETBLEED_CMD_IBPB) {
1558 			setup_force_cpu_cap(X86_FEATURE_USE_IBPB_FW);
1559 			pr_info("Enabling Speculation Barrier for firmware calls\n");
1560 		}
1561 
1562 	} else if (boot_cpu_has(X86_FEATURE_IBRS) && !spectre_v2_in_ibrs_mode(mode)) {
1563 		setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW);
1564 		pr_info("Enabling Restricted Speculation for firmware calls\n");
1565 	}
1566 
1567 	/* Set up IBPB and STIBP depending on the general spectre V2 command */
1568 	spectre_v2_cmd = cmd;
1569 }
1570 
update_stibp_msr(void * __unused)1571 static void update_stibp_msr(void * __unused)
1572 {
1573 	u64 val = spec_ctrl_current() | (x86_spec_ctrl_base & SPEC_CTRL_STIBP);
1574 	update_spec_ctrl(val);
1575 }
1576 
1577 /* Update x86_spec_ctrl_base in case SMT state changed. */
update_stibp_strict(void)1578 static void update_stibp_strict(void)
1579 {
1580 	u64 mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP;
1581 
1582 	if (sched_smt_active())
1583 		mask |= SPEC_CTRL_STIBP;
1584 
1585 	if (mask == x86_spec_ctrl_base)
1586 		return;
1587 
1588 	pr_info("Update user space SMT mitigation: STIBP %s\n",
1589 		mask & SPEC_CTRL_STIBP ? "always-on" : "off");
1590 	x86_spec_ctrl_base = mask;
1591 	on_each_cpu(update_stibp_msr, NULL, 1);
1592 }
1593 
1594 /* Update the static key controlling the evaluation of TIF_SPEC_IB */
update_indir_branch_cond(void)1595 static void update_indir_branch_cond(void)
1596 {
1597 	if (sched_smt_active())
1598 		static_branch_enable(&switch_to_cond_stibp);
1599 	else
1600 		static_branch_disable(&switch_to_cond_stibp);
1601 }
1602 
1603 #undef pr_fmt
1604 #define pr_fmt(fmt) fmt
1605 
1606 /* Update the static key controlling the MDS CPU buffer clear in idle */
update_mds_branch_idle(void)1607 static void update_mds_branch_idle(void)
1608 {
1609 	u64 ia32_cap = x86_read_arch_cap_msr();
1610 
1611 	/*
1612 	 * Enable the idle clearing if SMT is active on CPUs which are
1613 	 * affected only by MSBDS and not any other MDS variant.
1614 	 *
1615 	 * The other variants cannot be mitigated when SMT is enabled, so
1616 	 * clearing the buffers on idle just to prevent the Store Buffer
1617 	 * repartitioning leak would be a window dressing exercise.
1618 	 */
1619 	if (!boot_cpu_has_bug(X86_BUG_MSBDS_ONLY))
1620 		return;
1621 
1622 	if (sched_smt_active()) {
1623 		static_branch_enable(&mds_idle_clear);
1624 	} else if (mmio_mitigation == MMIO_MITIGATION_OFF ||
1625 		   (ia32_cap & ARCH_CAP_FBSDP_NO)) {
1626 		static_branch_disable(&mds_idle_clear);
1627 	}
1628 }
1629 
1630 #define MDS_MSG_SMT "MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details.\n"
1631 #define TAA_MSG_SMT "TAA CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_async_abort.html for more details.\n"
1632 #define MMIO_MSG_SMT "MMIO Stale Data CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/processor_mmio_stale_data.html for more details.\n"
1633 
cpu_bugs_smt_update(void)1634 void cpu_bugs_smt_update(void)
1635 {
1636 	mutex_lock(&spec_ctrl_mutex);
1637 
1638 	if (sched_smt_active() && unprivileged_ebpf_enabled() &&
1639 	    spectre_v2_enabled == SPECTRE_V2_EIBRS_LFENCE)
1640 		pr_warn_once(SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG);
1641 
1642 	switch (spectre_v2_user_stibp) {
1643 	case SPECTRE_V2_USER_NONE:
1644 		break;
1645 	case SPECTRE_V2_USER_STRICT:
1646 	case SPECTRE_V2_USER_STRICT_PREFERRED:
1647 		update_stibp_strict();
1648 		break;
1649 	case SPECTRE_V2_USER_PRCTL:
1650 	case SPECTRE_V2_USER_SECCOMP:
1651 		update_indir_branch_cond();
1652 		break;
1653 	}
1654 
1655 	switch (mds_mitigation) {
1656 	case MDS_MITIGATION_FULL:
1657 	case MDS_MITIGATION_VMWERV:
1658 		if (sched_smt_active() && !boot_cpu_has(X86_BUG_MSBDS_ONLY))
1659 			pr_warn_once(MDS_MSG_SMT);
1660 		update_mds_branch_idle();
1661 		break;
1662 	case MDS_MITIGATION_OFF:
1663 		break;
1664 	}
1665 
1666 	switch (taa_mitigation) {
1667 	case TAA_MITIGATION_VERW:
1668 	case TAA_MITIGATION_UCODE_NEEDED:
1669 		if (sched_smt_active())
1670 			pr_warn_once(TAA_MSG_SMT);
1671 		break;
1672 	case TAA_MITIGATION_TSX_DISABLED:
1673 	case TAA_MITIGATION_OFF:
1674 		break;
1675 	}
1676 
1677 	switch (mmio_mitigation) {
1678 	case MMIO_MITIGATION_VERW:
1679 	case MMIO_MITIGATION_UCODE_NEEDED:
1680 		if (sched_smt_active())
1681 			pr_warn_once(MMIO_MSG_SMT);
1682 		break;
1683 	case MMIO_MITIGATION_OFF:
1684 		break;
1685 	}
1686 
1687 	mutex_unlock(&spec_ctrl_mutex);
1688 }
1689 
1690 #undef pr_fmt
1691 #define pr_fmt(fmt)	"Speculative Store Bypass: " fmt
1692 
1693 static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE;
1694 
1695 /* The kernel command line selection */
1696 enum ssb_mitigation_cmd {
1697 	SPEC_STORE_BYPASS_CMD_NONE,
1698 	SPEC_STORE_BYPASS_CMD_AUTO,
1699 	SPEC_STORE_BYPASS_CMD_ON,
1700 	SPEC_STORE_BYPASS_CMD_PRCTL,
1701 	SPEC_STORE_BYPASS_CMD_SECCOMP,
1702 };
1703 
1704 static const char * const ssb_strings[] = {
1705 	[SPEC_STORE_BYPASS_NONE]	= "Vulnerable",
1706 	[SPEC_STORE_BYPASS_DISABLE]	= "Mitigation: Speculative Store Bypass disabled",
1707 	[SPEC_STORE_BYPASS_PRCTL]	= "Mitigation: Speculative Store Bypass disabled via prctl",
1708 	[SPEC_STORE_BYPASS_SECCOMP]	= "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
1709 };
1710 
1711 static const struct {
1712 	const char *option;
1713 	enum ssb_mitigation_cmd cmd;
1714 } ssb_mitigation_options[]  __initconst = {
1715 	{ "auto",	SPEC_STORE_BYPASS_CMD_AUTO },    /* Platform decides */
1716 	{ "on",		SPEC_STORE_BYPASS_CMD_ON },      /* Disable Speculative Store Bypass */
1717 	{ "off",	SPEC_STORE_BYPASS_CMD_NONE },    /* Don't touch Speculative Store Bypass */
1718 	{ "prctl",	SPEC_STORE_BYPASS_CMD_PRCTL },   /* Disable Speculative Store Bypass via prctl */
1719 	{ "seccomp",	SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */
1720 };
1721 
ssb_parse_cmdline(void)1722 static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
1723 {
1724 	enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO;
1725 	char arg[20];
1726 	int ret, i;
1727 
1728 	if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable") ||
1729 	    cpu_mitigations_off()) {
1730 		return SPEC_STORE_BYPASS_CMD_NONE;
1731 	} else {
1732 		ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable",
1733 					  arg, sizeof(arg));
1734 		if (ret < 0)
1735 			return SPEC_STORE_BYPASS_CMD_AUTO;
1736 
1737 		for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) {
1738 			if (!match_option(arg, ret, ssb_mitigation_options[i].option))
1739 				continue;
1740 
1741 			cmd = ssb_mitigation_options[i].cmd;
1742 			break;
1743 		}
1744 
1745 		if (i >= ARRAY_SIZE(ssb_mitigation_options)) {
1746 			pr_err("unknown option (%s). Switching to AUTO select\n", arg);
1747 			return SPEC_STORE_BYPASS_CMD_AUTO;
1748 		}
1749 	}
1750 
1751 	return cmd;
1752 }
1753 
__ssb_select_mitigation(void)1754 static enum ssb_mitigation __init __ssb_select_mitigation(void)
1755 {
1756 	enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;
1757 	enum ssb_mitigation_cmd cmd;
1758 
1759 	if (!boot_cpu_has(X86_FEATURE_SSBD))
1760 		return mode;
1761 
1762 	cmd = ssb_parse_cmdline();
1763 	if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) &&
1764 	    (cmd == SPEC_STORE_BYPASS_CMD_NONE ||
1765 	     cmd == SPEC_STORE_BYPASS_CMD_AUTO))
1766 		return mode;
1767 
1768 	switch (cmd) {
1769 	case SPEC_STORE_BYPASS_CMD_SECCOMP:
1770 		/*
1771 		 * Choose prctl+seccomp as the default mode if seccomp is
1772 		 * enabled.
1773 		 */
1774 		if (IS_ENABLED(CONFIG_SECCOMP))
1775 			mode = SPEC_STORE_BYPASS_SECCOMP;
1776 		else
1777 			mode = SPEC_STORE_BYPASS_PRCTL;
1778 		break;
1779 	case SPEC_STORE_BYPASS_CMD_ON:
1780 		mode = SPEC_STORE_BYPASS_DISABLE;
1781 		break;
1782 	case SPEC_STORE_BYPASS_CMD_AUTO:
1783 	case SPEC_STORE_BYPASS_CMD_PRCTL:
1784 		mode = SPEC_STORE_BYPASS_PRCTL;
1785 		break;
1786 	case SPEC_STORE_BYPASS_CMD_NONE:
1787 		break;
1788 	}
1789 
1790 	/*
1791 	 * We have three CPU feature flags that are in play here:
1792 	 *  - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
1793 	 *  - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
1794 	 *  - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
1795 	 */
1796 	if (mode == SPEC_STORE_BYPASS_DISABLE) {
1797 		setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
1798 		/*
1799 		 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
1800 		 * use a completely different MSR and bit dependent on family.
1801 		 */
1802 		if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
1803 		    !static_cpu_has(X86_FEATURE_AMD_SSBD)) {
1804 			x86_amd_ssb_disable();
1805 		} else {
1806 			x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
1807 			update_spec_ctrl(x86_spec_ctrl_base);
1808 		}
1809 	}
1810 
1811 	return mode;
1812 }
1813 
ssb_select_mitigation(void)1814 static void ssb_select_mitigation(void)
1815 {
1816 	ssb_mode = __ssb_select_mitigation();
1817 
1818 	if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1819 		pr_info("%s\n", ssb_strings[ssb_mode]);
1820 }
1821 
1822 #undef pr_fmt
1823 #define pr_fmt(fmt)     "Speculation prctl: " fmt
1824 
task_update_spec_tif(struct task_struct * tsk)1825 static void task_update_spec_tif(struct task_struct *tsk)
1826 {
1827 	/* Force the update of the real TIF bits */
1828 	set_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE);
1829 
1830 	/*
1831 	 * Immediately update the speculation control MSRs for the current
1832 	 * task, but for a non-current task delay setting the CPU
1833 	 * mitigation until it is scheduled next.
1834 	 *
1835 	 * This can only happen for SECCOMP mitigation. For PRCTL it's
1836 	 * always the current task.
1837 	 */
1838 	if (tsk == current)
1839 		speculation_ctrl_update_current();
1840 }
1841 
l1d_flush_prctl_set(struct task_struct * task,unsigned long ctrl)1842 static int l1d_flush_prctl_set(struct task_struct *task, unsigned long ctrl)
1843 {
1844 
1845 	if (!static_branch_unlikely(&switch_mm_cond_l1d_flush))
1846 		return -EPERM;
1847 
1848 	switch (ctrl) {
1849 	case PR_SPEC_ENABLE:
1850 		set_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH);
1851 		return 0;
1852 	case PR_SPEC_DISABLE:
1853 		clear_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH);
1854 		return 0;
1855 	default:
1856 		return -ERANGE;
1857 	}
1858 }
1859 
ssb_prctl_set(struct task_struct * task,unsigned long ctrl)1860 static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
1861 {
1862 	if (ssb_mode != SPEC_STORE_BYPASS_PRCTL &&
1863 	    ssb_mode != SPEC_STORE_BYPASS_SECCOMP)
1864 		return -ENXIO;
1865 
1866 	switch (ctrl) {
1867 	case PR_SPEC_ENABLE:
1868 		/* If speculation is force disabled, enable is not allowed */
1869 		if (task_spec_ssb_force_disable(task))
1870 			return -EPERM;
1871 		task_clear_spec_ssb_disable(task);
1872 		task_clear_spec_ssb_noexec(task);
1873 		task_update_spec_tif(task);
1874 		break;
1875 	case PR_SPEC_DISABLE:
1876 		task_set_spec_ssb_disable(task);
1877 		task_clear_spec_ssb_noexec(task);
1878 		task_update_spec_tif(task);
1879 		break;
1880 	case PR_SPEC_FORCE_DISABLE:
1881 		task_set_spec_ssb_disable(task);
1882 		task_set_spec_ssb_force_disable(task);
1883 		task_clear_spec_ssb_noexec(task);
1884 		task_update_spec_tif(task);
1885 		break;
1886 	case PR_SPEC_DISABLE_NOEXEC:
1887 		if (task_spec_ssb_force_disable(task))
1888 			return -EPERM;
1889 		task_set_spec_ssb_disable(task);
1890 		task_set_spec_ssb_noexec(task);
1891 		task_update_spec_tif(task);
1892 		break;
1893 	default:
1894 		return -ERANGE;
1895 	}
1896 	return 0;
1897 }
1898 
is_spec_ib_user_controlled(void)1899 static bool is_spec_ib_user_controlled(void)
1900 {
1901 	return spectre_v2_user_ibpb == SPECTRE_V2_USER_PRCTL ||
1902 		spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP ||
1903 		spectre_v2_user_stibp == SPECTRE_V2_USER_PRCTL ||
1904 		spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP;
1905 }
1906 
ib_prctl_set(struct task_struct * task,unsigned long ctrl)1907 static int ib_prctl_set(struct task_struct *task, unsigned long ctrl)
1908 {
1909 	switch (ctrl) {
1910 	case PR_SPEC_ENABLE:
1911 		if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1912 		    spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1913 			return 0;
1914 
1915 		/*
1916 		 * With strict mode for both IBPB and STIBP, the instruction
1917 		 * code paths avoid checking this task flag and instead,
1918 		 * unconditionally run the instruction. However, STIBP and IBPB
1919 		 * are independent and either can be set to conditionally
1920 		 * enabled regardless of the mode of the other.
1921 		 *
1922 		 * If either is set to conditional, allow the task flag to be
1923 		 * updated, unless it was force-disabled by a previous prctl
1924 		 * call. Currently, this is possible on an AMD CPU which has the
1925 		 * feature X86_FEATURE_AMD_STIBP_ALWAYS_ON. In this case, if the
1926 		 * kernel is booted with 'spectre_v2_user=seccomp', then
1927 		 * spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP and
1928 		 * spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED.
1929 		 */
1930 		if (!is_spec_ib_user_controlled() ||
1931 		    task_spec_ib_force_disable(task))
1932 			return -EPERM;
1933 
1934 		task_clear_spec_ib_disable(task);
1935 		task_update_spec_tif(task);
1936 		break;
1937 	case PR_SPEC_DISABLE:
1938 	case PR_SPEC_FORCE_DISABLE:
1939 		/*
1940 		 * Indirect branch speculation is always allowed when
1941 		 * mitigation is force disabled.
1942 		 */
1943 		if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1944 		    spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1945 			return -EPERM;
1946 
1947 		if (!is_spec_ib_user_controlled())
1948 			return 0;
1949 
1950 		task_set_spec_ib_disable(task);
1951 		if (ctrl == PR_SPEC_FORCE_DISABLE)
1952 			task_set_spec_ib_force_disable(task);
1953 		task_update_spec_tif(task);
1954 		if (task == current)
1955 			indirect_branch_prediction_barrier();
1956 		break;
1957 	default:
1958 		return -ERANGE;
1959 	}
1960 	return 0;
1961 }
1962 
arch_prctl_spec_ctrl_set(struct task_struct * task,unsigned long which,unsigned long ctrl)1963 int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which,
1964 			     unsigned long ctrl)
1965 {
1966 	switch (which) {
1967 	case PR_SPEC_STORE_BYPASS:
1968 		return ssb_prctl_set(task, ctrl);
1969 	case PR_SPEC_INDIRECT_BRANCH:
1970 		return ib_prctl_set(task, ctrl);
1971 	case PR_SPEC_L1D_FLUSH:
1972 		return l1d_flush_prctl_set(task, ctrl);
1973 	default:
1974 		return -ENODEV;
1975 	}
1976 }
1977 
1978 #ifdef CONFIG_SECCOMP
arch_seccomp_spec_mitigate(struct task_struct * task)1979 void arch_seccomp_spec_mitigate(struct task_struct *task)
1980 {
1981 	if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP)
1982 		ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE);
1983 	if (spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP ||
1984 	    spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP)
1985 		ib_prctl_set(task, PR_SPEC_FORCE_DISABLE);
1986 }
1987 #endif
1988 
l1d_flush_prctl_get(struct task_struct * task)1989 static int l1d_flush_prctl_get(struct task_struct *task)
1990 {
1991 	if (!static_branch_unlikely(&switch_mm_cond_l1d_flush))
1992 		return PR_SPEC_FORCE_DISABLE;
1993 
1994 	if (test_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH))
1995 		return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
1996 	else
1997 		return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
1998 }
1999 
ssb_prctl_get(struct task_struct * task)2000 static int ssb_prctl_get(struct task_struct *task)
2001 {
2002 	switch (ssb_mode) {
2003 	case SPEC_STORE_BYPASS_DISABLE:
2004 		return PR_SPEC_DISABLE;
2005 	case SPEC_STORE_BYPASS_SECCOMP:
2006 	case SPEC_STORE_BYPASS_PRCTL:
2007 		if (task_spec_ssb_force_disable(task))
2008 			return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
2009 		if (task_spec_ssb_noexec(task))
2010 			return PR_SPEC_PRCTL | PR_SPEC_DISABLE_NOEXEC;
2011 		if (task_spec_ssb_disable(task))
2012 			return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
2013 		return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
2014 	default:
2015 		if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
2016 			return PR_SPEC_ENABLE;
2017 		return PR_SPEC_NOT_AFFECTED;
2018 	}
2019 }
2020 
ib_prctl_get(struct task_struct * task)2021 static int ib_prctl_get(struct task_struct *task)
2022 {
2023 	if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
2024 		return PR_SPEC_NOT_AFFECTED;
2025 
2026 	if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
2027 	    spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
2028 		return PR_SPEC_ENABLE;
2029 	else if (is_spec_ib_user_controlled()) {
2030 		if (task_spec_ib_force_disable(task))
2031 			return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
2032 		if (task_spec_ib_disable(task))
2033 			return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
2034 		return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
2035 	} else if (spectre_v2_user_ibpb == SPECTRE_V2_USER_STRICT ||
2036 	    spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT ||
2037 	    spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED)
2038 		return PR_SPEC_DISABLE;
2039 	else
2040 		return PR_SPEC_NOT_AFFECTED;
2041 }
2042 
arch_prctl_spec_ctrl_get(struct task_struct * task,unsigned long which)2043 int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
2044 {
2045 	switch (which) {
2046 	case PR_SPEC_STORE_BYPASS:
2047 		return ssb_prctl_get(task);
2048 	case PR_SPEC_INDIRECT_BRANCH:
2049 		return ib_prctl_get(task);
2050 	case PR_SPEC_L1D_FLUSH:
2051 		return l1d_flush_prctl_get(task);
2052 	default:
2053 		return -ENODEV;
2054 	}
2055 }
2056 
x86_spec_ctrl_setup_ap(void)2057 void x86_spec_ctrl_setup_ap(void)
2058 {
2059 	if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
2060 		update_spec_ctrl(x86_spec_ctrl_base);
2061 
2062 	if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
2063 		x86_amd_ssb_disable();
2064 }
2065 
2066 bool itlb_multihit_kvm_mitigation;
2067 EXPORT_SYMBOL_GPL(itlb_multihit_kvm_mitigation);
2068 
2069 #undef pr_fmt
2070 #define pr_fmt(fmt)	"L1TF: " fmt
2071 
2072 /* Default mitigation for L1TF-affected CPUs */
2073 enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH;
2074 #if IS_ENABLED(CONFIG_KVM_INTEL)
2075 EXPORT_SYMBOL_GPL(l1tf_mitigation);
2076 #endif
2077 enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
2078 EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation);
2079 
2080 /*
2081  * These CPUs all support 44bits physical address space internally in the
2082  * cache but CPUID can report a smaller number of physical address bits.
2083  *
2084  * The L1TF mitigation uses the top most address bit for the inversion of
2085  * non present PTEs. When the installed memory reaches into the top most
2086  * address bit due to memory holes, which has been observed on machines
2087  * which report 36bits physical address bits and have 32G RAM installed,
2088  * then the mitigation range check in l1tf_select_mitigation() triggers.
2089  * This is a false positive because the mitigation is still possible due to
2090  * the fact that the cache uses 44bit internally. Use the cache bits
2091  * instead of the reported physical bits and adjust them on the affected
2092  * machines to 44bit if the reported bits are less than 44.
2093  */
override_cache_bits(struct cpuinfo_x86 * c)2094 static void override_cache_bits(struct cpuinfo_x86 *c)
2095 {
2096 	if (c->x86 != 6)
2097 		return;
2098 
2099 	switch (c->x86_model) {
2100 	case INTEL_FAM6_NEHALEM:
2101 	case INTEL_FAM6_WESTMERE:
2102 	case INTEL_FAM6_SANDYBRIDGE:
2103 	case INTEL_FAM6_IVYBRIDGE:
2104 	case INTEL_FAM6_HASWELL:
2105 	case INTEL_FAM6_HASWELL_L:
2106 	case INTEL_FAM6_HASWELL_G:
2107 	case INTEL_FAM6_BROADWELL:
2108 	case INTEL_FAM6_BROADWELL_G:
2109 	case INTEL_FAM6_SKYLAKE_L:
2110 	case INTEL_FAM6_SKYLAKE:
2111 	case INTEL_FAM6_KABYLAKE_L:
2112 	case INTEL_FAM6_KABYLAKE:
2113 		if (c->x86_cache_bits < 44)
2114 			c->x86_cache_bits = 44;
2115 		break;
2116 	}
2117 }
2118 
l1tf_select_mitigation(void)2119 static void __init l1tf_select_mitigation(void)
2120 {
2121 	u64 half_pa;
2122 
2123 	if (!boot_cpu_has_bug(X86_BUG_L1TF))
2124 		return;
2125 
2126 	if (cpu_mitigations_off())
2127 		l1tf_mitigation = L1TF_MITIGATION_OFF;
2128 	else if (cpu_mitigations_auto_nosmt())
2129 		l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
2130 
2131 	override_cache_bits(&boot_cpu_data);
2132 
2133 	switch (l1tf_mitigation) {
2134 	case L1TF_MITIGATION_OFF:
2135 	case L1TF_MITIGATION_FLUSH_NOWARN:
2136 	case L1TF_MITIGATION_FLUSH:
2137 		break;
2138 	case L1TF_MITIGATION_FLUSH_NOSMT:
2139 	case L1TF_MITIGATION_FULL:
2140 		cpu_smt_disable(false);
2141 		break;
2142 	case L1TF_MITIGATION_FULL_FORCE:
2143 		cpu_smt_disable(true);
2144 		break;
2145 	}
2146 
2147 #if CONFIG_PGTABLE_LEVELS == 2
2148 	pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n");
2149 	return;
2150 #endif
2151 
2152 	half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT;
2153 	if (l1tf_mitigation != L1TF_MITIGATION_OFF &&
2154 			e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) {
2155 		pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n");
2156 		pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n",
2157 				half_pa);
2158 		pr_info("However, doing so will make a part of your RAM unusable.\n");
2159 		pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html might help you decide.\n");
2160 		return;
2161 	}
2162 
2163 	setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV);
2164 }
2165 
l1tf_cmdline(char * str)2166 static int __init l1tf_cmdline(char *str)
2167 {
2168 	if (!boot_cpu_has_bug(X86_BUG_L1TF))
2169 		return 0;
2170 
2171 	if (!str)
2172 		return -EINVAL;
2173 
2174 	if (!strcmp(str, "off"))
2175 		l1tf_mitigation = L1TF_MITIGATION_OFF;
2176 	else if (!strcmp(str, "flush,nowarn"))
2177 		l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN;
2178 	else if (!strcmp(str, "flush"))
2179 		l1tf_mitigation = L1TF_MITIGATION_FLUSH;
2180 	else if (!strcmp(str, "flush,nosmt"))
2181 		l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
2182 	else if (!strcmp(str, "full"))
2183 		l1tf_mitigation = L1TF_MITIGATION_FULL;
2184 	else if (!strcmp(str, "full,force"))
2185 		l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE;
2186 
2187 	return 0;
2188 }
2189 early_param("l1tf", l1tf_cmdline);
2190 
2191 #undef pr_fmt
2192 #define pr_fmt(fmt) fmt
2193 
2194 #ifdef CONFIG_SYSFS
2195 
2196 #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion"
2197 
2198 #if IS_ENABLED(CONFIG_KVM_INTEL)
2199 static const char * const l1tf_vmx_states[] = {
2200 	[VMENTER_L1D_FLUSH_AUTO]		= "auto",
2201 	[VMENTER_L1D_FLUSH_NEVER]		= "vulnerable",
2202 	[VMENTER_L1D_FLUSH_COND]		= "conditional cache flushes",
2203 	[VMENTER_L1D_FLUSH_ALWAYS]		= "cache flushes",
2204 	[VMENTER_L1D_FLUSH_EPT_DISABLED]	= "EPT disabled",
2205 	[VMENTER_L1D_FLUSH_NOT_REQUIRED]	= "flush not necessary"
2206 };
2207 
l1tf_show_state(char * buf)2208 static ssize_t l1tf_show_state(char *buf)
2209 {
2210 	if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO)
2211 		return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
2212 
2213 	if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED ||
2214 	    (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER &&
2215 	     sched_smt_active())) {
2216 		return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG,
2217 			       l1tf_vmx_states[l1tf_vmx_mitigation]);
2218 	}
2219 
2220 	return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG,
2221 		       l1tf_vmx_states[l1tf_vmx_mitigation],
2222 		       sched_smt_active() ? "vulnerable" : "disabled");
2223 }
2224 
itlb_multihit_show_state(char * buf)2225 static ssize_t itlb_multihit_show_state(char *buf)
2226 {
2227 	if (!boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
2228 	    !boot_cpu_has(X86_FEATURE_VMX))
2229 		return sprintf(buf, "KVM: Mitigation: VMX unsupported\n");
2230 	else if (!(cr4_read_shadow() & X86_CR4_VMXE))
2231 		return sprintf(buf, "KVM: Mitigation: VMX disabled\n");
2232 	else if (itlb_multihit_kvm_mitigation)
2233 		return sprintf(buf, "KVM: Mitigation: Split huge pages\n");
2234 	else
2235 		return sprintf(buf, "KVM: Vulnerable\n");
2236 }
2237 #else
l1tf_show_state(char * buf)2238 static ssize_t l1tf_show_state(char *buf)
2239 {
2240 	return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
2241 }
2242 
itlb_multihit_show_state(char * buf)2243 static ssize_t itlb_multihit_show_state(char *buf)
2244 {
2245 	return sprintf(buf, "Processor vulnerable\n");
2246 }
2247 #endif
2248 
mds_show_state(char * buf)2249 static ssize_t mds_show_state(char *buf)
2250 {
2251 	if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
2252 		return sprintf(buf, "%s; SMT Host state unknown\n",
2253 			       mds_strings[mds_mitigation]);
2254 	}
2255 
2256 	if (boot_cpu_has(X86_BUG_MSBDS_ONLY)) {
2257 		return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation],
2258 			       (mds_mitigation == MDS_MITIGATION_OFF ? "vulnerable" :
2259 			        sched_smt_active() ? "mitigated" : "disabled"));
2260 	}
2261 
2262 	return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation],
2263 		       sched_smt_active() ? "vulnerable" : "disabled");
2264 }
2265 
tsx_async_abort_show_state(char * buf)2266 static ssize_t tsx_async_abort_show_state(char *buf)
2267 {
2268 	if ((taa_mitigation == TAA_MITIGATION_TSX_DISABLED) ||
2269 	    (taa_mitigation == TAA_MITIGATION_OFF))
2270 		return sprintf(buf, "%s\n", taa_strings[taa_mitigation]);
2271 
2272 	if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
2273 		return sprintf(buf, "%s; SMT Host state unknown\n",
2274 			       taa_strings[taa_mitigation]);
2275 	}
2276 
2277 	return sprintf(buf, "%s; SMT %s\n", taa_strings[taa_mitigation],
2278 		       sched_smt_active() ? "vulnerable" : "disabled");
2279 }
2280 
mmio_stale_data_show_state(char * buf)2281 static ssize_t mmio_stale_data_show_state(char *buf)
2282 {
2283 	if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN))
2284 		return sysfs_emit(buf, "Unknown: No mitigations\n");
2285 
2286 	if (mmio_mitigation == MMIO_MITIGATION_OFF)
2287 		return sysfs_emit(buf, "%s\n", mmio_strings[mmio_mitigation]);
2288 
2289 	if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
2290 		return sysfs_emit(buf, "%s; SMT Host state unknown\n",
2291 				  mmio_strings[mmio_mitigation]);
2292 	}
2293 
2294 	return sysfs_emit(buf, "%s; SMT %s\n", mmio_strings[mmio_mitigation],
2295 			  sched_smt_active() ? "vulnerable" : "disabled");
2296 }
2297 
stibp_state(void)2298 static char *stibp_state(void)
2299 {
2300 	if (spectre_v2_in_ibrs_mode(spectre_v2_enabled))
2301 		return "";
2302 
2303 	switch (spectre_v2_user_stibp) {
2304 	case SPECTRE_V2_USER_NONE:
2305 		return ", STIBP: disabled";
2306 	case SPECTRE_V2_USER_STRICT:
2307 		return ", STIBP: forced";
2308 	case SPECTRE_V2_USER_STRICT_PREFERRED:
2309 		return ", STIBP: always-on";
2310 	case SPECTRE_V2_USER_PRCTL:
2311 	case SPECTRE_V2_USER_SECCOMP:
2312 		if (static_key_enabled(&switch_to_cond_stibp))
2313 			return ", STIBP: conditional";
2314 	}
2315 	return "";
2316 }
2317 
ibpb_state(void)2318 static char *ibpb_state(void)
2319 {
2320 	if (boot_cpu_has(X86_FEATURE_IBPB)) {
2321 		if (static_key_enabled(&switch_mm_always_ibpb))
2322 			return ", IBPB: always-on";
2323 		if (static_key_enabled(&switch_mm_cond_ibpb))
2324 			return ", IBPB: conditional";
2325 		return ", IBPB: disabled";
2326 	}
2327 	return "";
2328 }
2329 
pbrsb_eibrs_state(void)2330 static char *pbrsb_eibrs_state(void)
2331 {
2332 	if (boot_cpu_has_bug(X86_BUG_EIBRS_PBRSB)) {
2333 		if (boot_cpu_has(X86_FEATURE_RSB_VMEXIT_LITE) ||
2334 		    boot_cpu_has(X86_FEATURE_RSB_VMEXIT))
2335 			return ", PBRSB-eIBRS: SW sequence";
2336 		else
2337 			return ", PBRSB-eIBRS: Vulnerable";
2338 	} else {
2339 		return ", PBRSB-eIBRS: Not affected";
2340 	}
2341 }
2342 
spectre_v2_show_state(char * buf)2343 static ssize_t spectre_v2_show_state(char *buf)
2344 {
2345 	if (spectre_v2_enabled == SPECTRE_V2_LFENCE)
2346 		return sprintf(buf, "Vulnerable: LFENCE\n");
2347 
2348 	if (spectre_v2_enabled == SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled())
2349 		return sprintf(buf, "Vulnerable: eIBRS with unprivileged eBPF\n");
2350 
2351 	if (sched_smt_active() && unprivileged_ebpf_enabled() &&
2352 	    spectre_v2_enabled == SPECTRE_V2_EIBRS_LFENCE)
2353 		return sprintf(buf, "Vulnerable: eIBRS+LFENCE with unprivileged eBPF and SMT\n");
2354 
2355 	return sprintf(buf, "%s%s%s%s%s%s%s\n",
2356 		       spectre_v2_strings[spectre_v2_enabled],
2357 		       ibpb_state(),
2358 		       boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "",
2359 		       stibp_state(),
2360 		       boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "",
2361 		       pbrsb_eibrs_state(),
2362 		       spectre_v2_module_string());
2363 }
2364 
srbds_show_state(char * buf)2365 static ssize_t srbds_show_state(char *buf)
2366 {
2367 	return sprintf(buf, "%s\n", srbds_strings[srbds_mitigation]);
2368 }
2369 
retbleed_show_state(char * buf)2370 static ssize_t retbleed_show_state(char *buf)
2371 {
2372 	if (retbleed_mitigation == RETBLEED_MITIGATION_UNRET ||
2373 	    retbleed_mitigation == RETBLEED_MITIGATION_IBPB) {
2374 	    if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
2375 		boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
2376 		    return sprintf(buf, "Vulnerable: untrained return thunk / IBPB on non-AMD based uarch\n");
2377 
2378 	    return sprintf(buf, "%s; SMT %s\n",
2379 			   retbleed_strings[retbleed_mitigation],
2380 			   !sched_smt_active() ? "disabled" :
2381 			   spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT ||
2382 			   spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED ?
2383 			   "enabled with STIBP protection" : "vulnerable");
2384 	}
2385 
2386 	return sprintf(buf, "%s\n", retbleed_strings[retbleed_mitigation]);
2387 }
2388 
cpu_show_common(struct device * dev,struct device_attribute * attr,char * buf,unsigned int bug)2389 static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
2390 			       char *buf, unsigned int bug)
2391 {
2392 	if (!boot_cpu_has_bug(bug))
2393 		return sprintf(buf, "Not affected\n");
2394 
2395 	switch (bug) {
2396 	case X86_BUG_CPU_MELTDOWN:
2397 		if (boot_cpu_has(X86_FEATURE_PTI))
2398 			return sprintf(buf, "Mitigation: PTI\n");
2399 
2400 		if (hypervisor_is_type(X86_HYPER_XEN_PV))
2401 			return sprintf(buf, "Unknown (XEN PV detected, hypervisor mitigation required)\n");
2402 
2403 		break;
2404 
2405 	case X86_BUG_SPECTRE_V1:
2406 		return sprintf(buf, "%s\n", spectre_v1_strings[spectre_v1_mitigation]);
2407 
2408 	case X86_BUG_SPECTRE_V2:
2409 		return spectre_v2_show_state(buf);
2410 
2411 	case X86_BUG_SPEC_STORE_BYPASS:
2412 		return sprintf(buf, "%s\n", ssb_strings[ssb_mode]);
2413 
2414 	case X86_BUG_L1TF:
2415 		if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV))
2416 			return l1tf_show_state(buf);
2417 		break;
2418 
2419 	case X86_BUG_MDS:
2420 		return mds_show_state(buf);
2421 
2422 	case X86_BUG_TAA:
2423 		return tsx_async_abort_show_state(buf);
2424 
2425 	case X86_BUG_ITLB_MULTIHIT:
2426 		return itlb_multihit_show_state(buf);
2427 
2428 	case X86_BUG_SRBDS:
2429 		return srbds_show_state(buf);
2430 
2431 	case X86_BUG_MMIO_STALE_DATA:
2432 	case X86_BUG_MMIO_UNKNOWN:
2433 		return mmio_stale_data_show_state(buf);
2434 
2435 	case X86_BUG_RETBLEED:
2436 		return retbleed_show_state(buf);
2437 
2438 	default:
2439 		break;
2440 	}
2441 
2442 	return sprintf(buf, "Vulnerable\n");
2443 }
2444 
cpu_show_meltdown(struct device * dev,struct device_attribute * attr,char * buf)2445 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf)
2446 {
2447 	return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN);
2448 }
2449 
cpu_show_spectre_v1(struct device * dev,struct device_attribute * attr,char * buf)2450 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf)
2451 {
2452 	return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1);
2453 }
2454 
cpu_show_spectre_v2(struct device * dev,struct device_attribute * attr,char * buf)2455 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf)
2456 {
2457 	return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2);
2458 }
2459 
cpu_show_spec_store_bypass(struct device * dev,struct device_attribute * attr,char * buf)2460 ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
2461 {
2462 	return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS);
2463 }
2464 
cpu_show_l1tf(struct device * dev,struct device_attribute * attr,char * buf)2465 ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf)
2466 {
2467 	return cpu_show_common(dev, attr, buf, X86_BUG_L1TF);
2468 }
2469 
cpu_show_mds(struct device * dev,struct device_attribute * attr,char * buf)2470 ssize_t cpu_show_mds(struct device *dev, struct device_attribute *attr, char *buf)
2471 {
2472 	return cpu_show_common(dev, attr, buf, X86_BUG_MDS);
2473 }
2474 
cpu_show_tsx_async_abort(struct device * dev,struct device_attribute * attr,char * buf)2475 ssize_t cpu_show_tsx_async_abort(struct device *dev, struct device_attribute *attr, char *buf)
2476 {
2477 	return cpu_show_common(dev, attr, buf, X86_BUG_TAA);
2478 }
2479 
cpu_show_itlb_multihit(struct device * dev,struct device_attribute * attr,char * buf)2480 ssize_t cpu_show_itlb_multihit(struct device *dev, struct device_attribute *attr, char *buf)
2481 {
2482 	return cpu_show_common(dev, attr, buf, X86_BUG_ITLB_MULTIHIT);
2483 }
2484 
cpu_show_srbds(struct device * dev,struct device_attribute * attr,char * buf)2485 ssize_t cpu_show_srbds(struct device *dev, struct device_attribute *attr, char *buf)
2486 {
2487 	return cpu_show_common(dev, attr, buf, X86_BUG_SRBDS);
2488 }
2489 
cpu_show_mmio_stale_data(struct device * dev,struct device_attribute * attr,char * buf)2490 ssize_t cpu_show_mmio_stale_data(struct device *dev, struct device_attribute *attr, char *buf)
2491 {
2492 	if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN))
2493 		return cpu_show_common(dev, attr, buf, X86_BUG_MMIO_UNKNOWN);
2494 	else
2495 		return cpu_show_common(dev, attr, buf, X86_BUG_MMIO_STALE_DATA);
2496 }
2497 
cpu_show_retbleed(struct device * dev,struct device_attribute * attr,char * buf)2498 ssize_t cpu_show_retbleed(struct device *dev, struct device_attribute *attr, char *buf)
2499 {
2500 	return cpu_show_common(dev, attr, buf, X86_BUG_RETBLEED);
2501 }
2502 #endif
2503