1 #include <linux/gfp.h>
2 #include <linux/initrd.h>
3 #include <linux/ioport.h>
4 #include <linux/swap.h>
5 #include <linux/memblock.h>
6 #include <linux/swapfile.h>
7 #include <linux/swapops.h>
8 #include <linux/kmemleak.h>
9 #include <linux/sched/task.h>
10
11 #include <asm/set_memory.h>
12 #include <asm/e820/api.h>
13 #include <asm/init.h>
14 #include <asm/page.h>
15 #include <asm/page_types.h>
16 #include <asm/sections.h>
17 #include <asm/setup.h>
18 #include <asm/tlbflush.h>
19 #include <asm/tlb.h>
20 #include <asm/proto.h>
21 #include <asm/dma.h> /* for MAX_DMA_PFN */
22 #include <asm/microcode.h>
23 #include <asm/kaslr.h>
24 #include <asm/hypervisor.h>
25 #include <asm/cpufeature.h>
26 #include <asm/pti.h>
27 #include <asm/text-patching.h>
28 #include <asm/memtype.h>
29
30 /*
31 * We need to define the tracepoints somewhere, and tlb.c
32 * is only compiled when SMP=y.
33 */
34 #include <trace/events/tlb.h>
35
36 #include "mm_internal.h"
37
38 /*
39 * Tables translating between page_cache_type_t and pte encoding.
40 *
41 * The default values are defined statically as minimal supported mode;
42 * WC and WT fall back to UC-. pat_init() updates these values to support
43 * more cache modes, WC and WT, when it is safe to do so. See pat_init()
44 * for the details. Note, __early_ioremap() used during early boot-time
45 * takes pgprot_t (pte encoding) and does not use these tables.
46 *
47 * Index into __cachemode2pte_tbl[] is the cachemode.
48 *
49 * Index into __pte2cachemode_tbl[] are the caching attribute bits of the pte
50 * (_PAGE_PWT, _PAGE_PCD, _PAGE_PAT) at index bit positions 0, 1, 2.
51 */
52 static uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM] = {
53 [_PAGE_CACHE_MODE_WB ] = 0 | 0 ,
54 [_PAGE_CACHE_MODE_WC ] = 0 | _PAGE_PCD,
55 [_PAGE_CACHE_MODE_UC_MINUS] = 0 | _PAGE_PCD,
56 [_PAGE_CACHE_MODE_UC ] = _PAGE_PWT | _PAGE_PCD,
57 [_PAGE_CACHE_MODE_WT ] = 0 | _PAGE_PCD,
58 [_PAGE_CACHE_MODE_WP ] = 0 | _PAGE_PCD,
59 };
60
cachemode2protval(enum page_cache_mode pcm)61 unsigned long cachemode2protval(enum page_cache_mode pcm)
62 {
63 if (likely(pcm == 0))
64 return 0;
65 return __cachemode2pte_tbl[pcm];
66 }
67 EXPORT_SYMBOL(cachemode2protval);
68
69 static uint8_t __pte2cachemode_tbl[8] = {
70 [__pte2cm_idx( 0 | 0 | 0 )] = _PAGE_CACHE_MODE_WB,
71 [__pte2cm_idx(_PAGE_PWT | 0 | 0 )] = _PAGE_CACHE_MODE_UC_MINUS,
72 [__pte2cm_idx( 0 | _PAGE_PCD | 0 )] = _PAGE_CACHE_MODE_UC_MINUS,
73 [__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | 0 )] = _PAGE_CACHE_MODE_UC,
74 [__pte2cm_idx( 0 | 0 | _PAGE_PAT)] = _PAGE_CACHE_MODE_WB,
75 [__pte2cm_idx(_PAGE_PWT | 0 | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC_MINUS,
76 [__pte2cm_idx(0 | _PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC_MINUS,
77 [__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC,
78 };
79
80 /*
81 * Check that the write-protect PAT entry is set for write-protect.
82 * To do this without making assumptions how PAT has been set up (Xen has
83 * another layout than the kernel), translate the _PAGE_CACHE_MODE_WP cache
84 * mode via the __cachemode2pte_tbl[] into protection bits (those protection
85 * bits will select a cache mode of WP or better), and then translate the
86 * protection bits back into the cache mode using __pte2cm_idx() and the
87 * __pte2cachemode_tbl[] array. This will return the really used cache mode.
88 */
x86_has_pat_wp(void)89 bool x86_has_pat_wp(void)
90 {
91 uint16_t prot = __cachemode2pte_tbl[_PAGE_CACHE_MODE_WP];
92
93 return __pte2cachemode_tbl[__pte2cm_idx(prot)] == _PAGE_CACHE_MODE_WP;
94 }
95
pgprot2cachemode(pgprot_t pgprot)96 enum page_cache_mode pgprot2cachemode(pgprot_t pgprot)
97 {
98 unsigned long masked;
99
100 masked = pgprot_val(pgprot) & _PAGE_CACHE_MASK;
101 if (likely(masked == 0))
102 return 0;
103 return __pte2cachemode_tbl[__pte2cm_idx(masked)];
104 }
105
106 static unsigned long __initdata pgt_buf_start;
107 static unsigned long __initdata pgt_buf_end;
108 static unsigned long __initdata pgt_buf_top;
109
110 static unsigned long min_pfn_mapped;
111
112 static bool __initdata can_use_brk_pgt = true;
113
114 /*
115 * Pages returned are already directly mapped.
116 *
117 * Changing that is likely to break Xen, see commit:
118 *
119 * 279b706 x86,xen: introduce x86_init.mapping.pagetable_reserve
120 *
121 * for detailed information.
122 */
alloc_low_pages(unsigned int num)123 __ref void *alloc_low_pages(unsigned int num)
124 {
125 unsigned long pfn;
126 int i;
127
128 if (after_bootmem) {
129 unsigned int order;
130
131 order = get_order((unsigned long)num << PAGE_SHIFT);
132 return (void *)__get_free_pages(GFP_ATOMIC | __GFP_ZERO, order);
133 }
134
135 if ((pgt_buf_end + num) > pgt_buf_top || !can_use_brk_pgt) {
136 unsigned long ret = 0;
137
138 if (min_pfn_mapped < max_pfn_mapped) {
139 ret = memblock_phys_alloc_range(
140 PAGE_SIZE * num, PAGE_SIZE,
141 min_pfn_mapped << PAGE_SHIFT,
142 max_pfn_mapped << PAGE_SHIFT);
143 }
144 if (!ret && can_use_brk_pgt)
145 ret = __pa(extend_brk(PAGE_SIZE * num, PAGE_SIZE));
146
147 if (!ret)
148 panic("alloc_low_pages: can not alloc memory");
149
150 pfn = ret >> PAGE_SHIFT;
151 } else {
152 pfn = pgt_buf_end;
153 pgt_buf_end += num;
154 }
155
156 for (i = 0; i < num; i++) {
157 void *adr;
158
159 adr = __va((pfn + i) << PAGE_SHIFT);
160 clear_page(adr);
161 }
162
163 return __va(pfn << PAGE_SHIFT);
164 }
165
166 /*
167 * By default need to be able to allocate page tables below PGD firstly for
168 * the 0-ISA_END_ADDRESS range and secondly for the initial PMD_SIZE mapping.
169 * With KASLR memory randomization, depending on the machine e820 memory and the
170 * PUD alignment, twice that many pages may be needed when KASLR memory
171 * randomization is enabled.
172 */
173
174 #ifndef CONFIG_X86_5LEVEL
175 #define INIT_PGD_PAGE_TABLES 3
176 #else
177 #define INIT_PGD_PAGE_TABLES 4
178 #endif
179
180 #ifndef CONFIG_RANDOMIZE_MEMORY
181 #define INIT_PGD_PAGE_COUNT (2 * INIT_PGD_PAGE_TABLES)
182 #else
183 #define INIT_PGD_PAGE_COUNT (4 * INIT_PGD_PAGE_TABLES)
184 #endif
185
186 #define INIT_PGT_BUF_SIZE (INIT_PGD_PAGE_COUNT * PAGE_SIZE)
187 RESERVE_BRK(early_pgt_alloc, INIT_PGT_BUF_SIZE);
early_alloc_pgt_buf(void)188 void __init early_alloc_pgt_buf(void)
189 {
190 unsigned long tables = INIT_PGT_BUF_SIZE;
191 phys_addr_t base;
192
193 base = __pa(extend_brk(tables, PAGE_SIZE));
194
195 pgt_buf_start = base >> PAGE_SHIFT;
196 pgt_buf_end = pgt_buf_start;
197 pgt_buf_top = pgt_buf_start + (tables >> PAGE_SHIFT);
198 }
199
200 int after_bootmem;
201
202 early_param_on_off("gbpages", "nogbpages", direct_gbpages, CONFIG_X86_DIRECT_GBPAGES);
203
204 struct map_range {
205 unsigned long start;
206 unsigned long end;
207 unsigned page_size_mask;
208 };
209
210 static int page_size_mask;
211
212 /*
213 * Save some of cr4 feature set we're using (e.g. Pentium 4MB
214 * enable and PPro Global page enable), so that any CPU's that boot
215 * up after us can get the correct flags. Invoked on the boot CPU.
216 */
cr4_set_bits_and_update_boot(unsigned long mask)217 static inline void cr4_set_bits_and_update_boot(unsigned long mask)
218 {
219 mmu_cr4_features |= mask;
220 if (trampoline_cr4_features)
221 *trampoline_cr4_features = mmu_cr4_features;
222 cr4_set_bits(mask);
223 }
224
probe_page_size_mask(void)225 static void __init probe_page_size_mask(void)
226 {
227 /*
228 * For pagealloc debugging, identity mapping will use small pages.
229 * This will simplify cpa(), which otherwise needs to support splitting
230 * large pages into small in interrupt context, etc.
231 */
232 if (boot_cpu_has(X86_FEATURE_PSE) && !debug_pagealloc_enabled())
233 page_size_mask |= 1 << PG_LEVEL_2M;
234 else
235 direct_gbpages = 0;
236
237 /* Enable PSE if available */
238 if (boot_cpu_has(X86_FEATURE_PSE))
239 cr4_set_bits_and_update_boot(X86_CR4_PSE);
240
241 /* Enable PGE if available */
242 __supported_pte_mask &= ~_PAGE_GLOBAL;
243 if (boot_cpu_has(X86_FEATURE_PGE)) {
244 cr4_set_bits_and_update_boot(X86_CR4_PGE);
245 __supported_pte_mask |= _PAGE_GLOBAL;
246 }
247
248 /* By the default is everything supported: */
249 __default_kernel_pte_mask = __supported_pte_mask;
250 /* Except when with PTI where the kernel is mostly non-Global: */
251 if (cpu_feature_enabled(X86_FEATURE_PTI))
252 __default_kernel_pte_mask &= ~_PAGE_GLOBAL;
253
254 /* Enable 1 GB linear kernel mappings if available: */
255 if (direct_gbpages && boot_cpu_has(X86_FEATURE_GBPAGES)) {
256 printk(KERN_INFO "Using GB pages for direct mapping\n");
257 page_size_mask |= 1 << PG_LEVEL_1G;
258 } else {
259 direct_gbpages = 0;
260 }
261 }
262
setup_pcid(void)263 static void setup_pcid(void)
264 {
265 if (!IS_ENABLED(CONFIG_X86_64))
266 return;
267
268 if (!boot_cpu_has(X86_FEATURE_PCID))
269 return;
270
271 if (boot_cpu_has(X86_FEATURE_PGE)) {
272 /*
273 * This can't be cr4_set_bits_and_update_boot() -- the
274 * trampoline code can't handle CR4.PCIDE and it wouldn't
275 * do any good anyway. Despite the name,
276 * cr4_set_bits_and_update_boot() doesn't actually cause
277 * the bits in question to remain set all the way through
278 * the secondary boot asm.
279 *
280 * Instead, we brute-force it and set CR4.PCIDE manually in
281 * start_secondary().
282 */
283 cr4_set_bits(X86_CR4_PCIDE);
284
285 /*
286 * INVPCID's single-context modes (2/3) only work if we set
287 * X86_CR4_PCIDE, *and* we INVPCID support. It's unusable
288 * on systems that have X86_CR4_PCIDE clear, or that have
289 * no INVPCID support at all.
290 */
291 if (boot_cpu_has(X86_FEATURE_INVPCID))
292 setup_force_cpu_cap(X86_FEATURE_INVPCID_SINGLE);
293 } else {
294 /*
295 * flush_tlb_all(), as currently implemented, won't work if
296 * PCID is on but PGE is not. Since that combination
297 * doesn't exist on real hardware, there's no reason to try
298 * to fully support it, but it's polite to avoid corrupting
299 * data if we're on an improperly configured VM.
300 */
301 setup_clear_cpu_cap(X86_FEATURE_PCID);
302 }
303 }
304
305 #ifdef CONFIG_X86_32
306 #define NR_RANGE_MR 3
307 #else /* CONFIG_X86_64 */
308 #define NR_RANGE_MR 5
309 #endif
310
save_mr(struct map_range * mr,int nr_range,unsigned long start_pfn,unsigned long end_pfn,unsigned long page_size_mask)311 static int __meminit save_mr(struct map_range *mr, int nr_range,
312 unsigned long start_pfn, unsigned long end_pfn,
313 unsigned long page_size_mask)
314 {
315 if (start_pfn < end_pfn) {
316 if (nr_range >= NR_RANGE_MR)
317 panic("run out of range for init_memory_mapping\n");
318 mr[nr_range].start = start_pfn<<PAGE_SHIFT;
319 mr[nr_range].end = end_pfn<<PAGE_SHIFT;
320 mr[nr_range].page_size_mask = page_size_mask;
321 nr_range++;
322 }
323
324 return nr_range;
325 }
326
327 /*
328 * adjust the page_size_mask for small range to go with
329 * big page size instead small one if nearby are ram too.
330 */
adjust_range_page_size_mask(struct map_range * mr,int nr_range)331 static void __ref adjust_range_page_size_mask(struct map_range *mr,
332 int nr_range)
333 {
334 int i;
335
336 for (i = 0; i < nr_range; i++) {
337 if ((page_size_mask & (1<<PG_LEVEL_2M)) &&
338 !(mr[i].page_size_mask & (1<<PG_LEVEL_2M))) {
339 unsigned long start = round_down(mr[i].start, PMD_SIZE);
340 unsigned long end = round_up(mr[i].end, PMD_SIZE);
341
342 #ifdef CONFIG_X86_32
343 if ((end >> PAGE_SHIFT) > max_low_pfn)
344 continue;
345 #endif
346
347 if (memblock_is_region_memory(start, end - start))
348 mr[i].page_size_mask |= 1<<PG_LEVEL_2M;
349 }
350 if ((page_size_mask & (1<<PG_LEVEL_1G)) &&
351 !(mr[i].page_size_mask & (1<<PG_LEVEL_1G))) {
352 unsigned long start = round_down(mr[i].start, PUD_SIZE);
353 unsigned long end = round_up(mr[i].end, PUD_SIZE);
354
355 if (memblock_is_region_memory(start, end - start))
356 mr[i].page_size_mask |= 1<<PG_LEVEL_1G;
357 }
358 }
359 }
360
page_size_string(struct map_range * mr)361 static const char *page_size_string(struct map_range *mr)
362 {
363 static const char str_1g[] = "1G";
364 static const char str_2m[] = "2M";
365 static const char str_4m[] = "4M";
366 static const char str_4k[] = "4k";
367
368 if (mr->page_size_mask & (1<<PG_LEVEL_1G))
369 return str_1g;
370 /*
371 * 32-bit without PAE has a 4M large page size.
372 * PG_LEVEL_2M is misnamed, but we can at least
373 * print out the right size in the string.
374 */
375 if (IS_ENABLED(CONFIG_X86_32) &&
376 !IS_ENABLED(CONFIG_X86_PAE) &&
377 mr->page_size_mask & (1<<PG_LEVEL_2M))
378 return str_4m;
379
380 if (mr->page_size_mask & (1<<PG_LEVEL_2M))
381 return str_2m;
382
383 return str_4k;
384 }
385
split_mem_range(struct map_range * mr,int nr_range,unsigned long start,unsigned long end)386 static int __meminit split_mem_range(struct map_range *mr, int nr_range,
387 unsigned long start,
388 unsigned long end)
389 {
390 unsigned long start_pfn, end_pfn, limit_pfn;
391 unsigned long pfn;
392 int i;
393
394 limit_pfn = PFN_DOWN(end);
395
396 /* head if not big page alignment ? */
397 pfn = start_pfn = PFN_DOWN(start);
398 #ifdef CONFIG_X86_32
399 /*
400 * Don't use a large page for the first 2/4MB of memory
401 * because there are often fixed size MTRRs in there
402 * and overlapping MTRRs into large pages can cause
403 * slowdowns.
404 */
405 if (pfn == 0)
406 end_pfn = PFN_DOWN(PMD_SIZE);
407 else
408 end_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE));
409 #else /* CONFIG_X86_64 */
410 end_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE));
411 #endif
412 if (end_pfn > limit_pfn)
413 end_pfn = limit_pfn;
414 if (start_pfn < end_pfn) {
415 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0);
416 pfn = end_pfn;
417 }
418
419 /* big page (2M) range */
420 start_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE));
421 #ifdef CONFIG_X86_32
422 end_pfn = round_down(limit_pfn, PFN_DOWN(PMD_SIZE));
423 #else /* CONFIG_X86_64 */
424 end_pfn = round_up(pfn, PFN_DOWN(PUD_SIZE));
425 if (end_pfn > round_down(limit_pfn, PFN_DOWN(PMD_SIZE)))
426 end_pfn = round_down(limit_pfn, PFN_DOWN(PMD_SIZE));
427 #endif
428
429 if (start_pfn < end_pfn) {
430 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn,
431 page_size_mask & (1<<PG_LEVEL_2M));
432 pfn = end_pfn;
433 }
434
435 #ifdef CONFIG_X86_64
436 /* big page (1G) range */
437 start_pfn = round_up(pfn, PFN_DOWN(PUD_SIZE));
438 end_pfn = round_down(limit_pfn, PFN_DOWN(PUD_SIZE));
439 if (start_pfn < end_pfn) {
440 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn,
441 page_size_mask &
442 ((1<<PG_LEVEL_2M)|(1<<PG_LEVEL_1G)));
443 pfn = end_pfn;
444 }
445
446 /* tail is not big page (1G) alignment */
447 start_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE));
448 end_pfn = round_down(limit_pfn, PFN_DOWN(PMD_SIZE));
449 if (start_pfn < end_pfn) {
450 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn,
451 page_size_mask & (1<<PG_LEVEL_2M));
452 pfn = end_pfn;
453 }
454 #endif
455
456 /* tail is not big page (2M) alignment */
457 start_pfn = pfn;
458 end_pfn = limit_pfn;
459 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0);
460
461 if (!after_bootmem)
462 adjust_range_page_size_mask(mr, nr_range);
463
464 /* try to merge same page size and continuous */
465 for (i = 0; nr_range > 1 && i < nr_range - 1; i++) {
466 unsigned long old_start;
467 if (mr[i].end != mr[i+1].start ||
468 mr[i].page_size_mask != mr[i+1].page_size_mask)
469 continue;
470 /* move it */
471 old_start = mr[i].start;
472 memmove(&mr[i], &mr[i+1],
473 (nr_range - 1 - i) * sizeof(struct map_range));
474 mr[i--].start = old_start;
475 nr_range--;
476 }
477
478 for (i = 0; i < nr_range; i++)
479 pr_debug(" [mem %#010lx-%#010lx] page %s\n",
480 mr[i].start, mr[i].end - 1,
481 page_size_string(&mr[i]));
482
483 return nr_range;
484 }
485
486 struct range pfn_mapped[E820_MAX_ENTRIES];
487 int nr_pfn_mapped;
488
add_pfn_range_mapped(unsigned long start_pfn,unsigned long end_pfn)489 static void add_pfn_range_mapped(unsigned long start_pfn, unsigned long end_pfn)
490 {
491 nr_pfn_mapped = add_range_with_merge(pfn_mapped, E820_MAX_ENTRIES,
492 nr_pfn_mapped, start_pfn, end_pfn);
493 nr_pfn_mapped = clean_sort_range(pfn_mapped, E820_MAX_ENTRIES);
494
495 max_pfn_mapped = max(max_pfn_mapped, end_pfn);
496
497 if (start_pfn < (1UL<<(32-PAGE_SHIFT)))
498 max_low_pfn_mapped = max(max_low_pfn_mapped,
499 min(end_pfn, 1UL<<(32-PAGE_SHIFT)));
500 }
501
pfn_range_is_mapped(unsigned long start_pfn,unsigned long end_pfn)502 bool pfn_range_is_mapped(unsigned long start_pfn, unsigned long end_pfn)
503 {
504 int i;
505
506 for (i = 0; i < nr_pfn_mapped; i++)
507 if ((start_pfn >= pfn_mapped[i].start) &&
508 (end_pfn <= pfn_mapped[i].end))
509 return true;
510
511 return false;
512 }
513
514 /*
515 * Setup the direct mapping of the physical memory at PAGE_OFFSET.
516 * This runs before bootmem is initialized and gets pages directly from
517 * the physical memory. To access them they are temporarily mapped.
518 */
init_memory_mapping(unsigned long start,unsigned long end,pgprot_t prot)519 unsigned long __ref init_memory_mapping(unsigned long start,
520 unsigned long end, pgprot_t prot)
521 {
522 struct map_range mr[NR_RANGE_MR];
523 unsigned long ret = 0;
524 int nr_range, i;
525
526 pr_debug("init_memory_mapping: [mem %#010lx-%#010lx]\n",
527 start, end - 1);
528
529 memset(mr, 0, sizeof(mr));
530 nr_range = split_mem_range(mr, 0, start, end);
531
532 for (i = 0; i < nr_range; i++)
533 ret = kernel_physical_mapping_init(mr[i].start, mr[i].end,
534 mr[i].page_size_mask,
535 prot);
536
537 add_pfn_range_mapped(start >> PAGE_SHIFT, ret >> PAGE_SHIFT);
538
539 return ret >> PAGE_SHIFT;
540 }
541
542 /*
543 * We need to iterate through the E820 memory map and create direct mappings
544 * for only E820_TYPE_RAM and E820_KERN_RESERVED regions. We cannot simply
545 * create direct mappings for all pfns from [0 to max_low_pfn) and
546 * [4GB to max_pfn) because of possible memory holes in high addresses
547 * that cannot be marked as UC by fixed/variable range MTRRs.
548 * Depending on the alignment of E820 ranges, this may possibly result
549 * in using smaller size (i.e. 4K instead of 2M or 1G) page tables.
550 *
551 * init_mem_mapping() calls init_range_memory_mapping() with big range.
552 * That range would have hole in the middle or ends, and only ram parts
553 * will be mapped in init_range_memory_mapping().
554 */
init_range_memory_mapping(unsigned long r_start,unsigned long r_end)555 static unsigned long __init init_range_memory_mapping(
556 unsigned long r_start,
557 unsigned long r_end)
558 {
559 unsigned long start_pfn, end_pfn;
560 unsigned long mapped_ram_size = 0;
561 int i;
562
563 for_each_mem_pfn_range(i, MAX_NUMNODES, &start_pfn, &end_pfn, NULL) {
564 u64 start = clamp_val(PFN_PHYS(start_pfn), r_start, r_end);
565 u64 end = clamp_val(PFN_PHYS(end_pfn), r_start, r_end);
566 if (start >= end)
567 continue;
568
569 /*
570 * if it is overlapping with brk pgt, we need to
571 * alloc pgt buf from memblock instead.
572 */
573 can_use_brk_pgt = max(start, (u64)pgt_buf_end<<PAGE_SHIFT) >=
574 min(end, (u64)pgt_buf_top<<PAGE_SHIFT);
575 init_memory_mapping(start, end, PAGE_KERNEL);
576 mapped_ram_size += end - start;
577 can_use_brk_pgt = true;
578 }
579
580 return mapped_ram_size;
581 }
582
get_new_step_size(unsigned long step_size)583 static unsigned long __init get_new_step_size(unsigned long step_size)
584 {
585 /*
586 * Initial mapped size is PMD_SIZE (2M).
587 * We can not set step_size to be PUD_SIZE (1G) yet.
588 * In worse case, when we cross the 1G boundary, and
589 * PG_LEVEL_2M is not set, we will need 1+1+512 pages (2M + 8k)
590 * to map 1G range with PTE. Hence we use one less than the
591 * difference of page table level shifts.
592 *
593 * Don't need to worry about overflow in the top-down case, on 32bit,
594 * when step_size is 0, round_down() returns 0 for start, and that
595 * turns it into 0x100000000ULL.
596 * In the bottom-up case, round_up(x, 0) returns 0 though too, which
597 * needs to be taken into consideration by the code below.
598 */
599 return step_size << (PMD_SHIFT - PAGE_SHIFT - 1);
600 }
601
602 /**
603 * memory_map_top_down - Map [map_start, map_end) top down
604 * @map_start: start address of the target memory range
605 * @map_end: end address of the target memory range
606 *
607 * This function will setup direct mapping for memory range
608 * [map_start, map_end) in top-down. That said, the page tables
609 * will be allocated at the end of the memory, and we map the
610 * memory in top-down.
611 */
memory_map_top_down(unsigned long map_start,unsigned long map_end)612 static void __init memory_map_top_down(unsigned long map_start,
613 unsigned long map_end)
614 {
615 unsigned long real_end, last_start;
616 unsigned long step_size;
617 unsigned long addr;
618 unsigned long mapped_ram_size = 0;
619
620 /*
621 * Systems that have many reserved areas near top of the memory,
622 * e.g. QEMU with less than 1G RAM and EFI enabled, or Xen, will
623 * require lots of 4K mappings which may exhaust pgt_buf.
624 * Start with top-most PMD_SIZE range aligned at PMD_SIZE to ensure
625 * there is enough mapped memory that can be allocated from
626 * memblock.
627 */
628 addr = memblock_phys_alloc_range(PMD_SIZE, PMD_SIZE, map_start,
629 map_end);
630 memblock_phys_free(addr, PMD_SIZE);
631 real_end = addr + PMD_SIZE;
632
633 /* step_size need to be small so pgt_buf from BRK could cover it */
634 step_size = PMD_SIZE;
635 max_pfn_mapped = 0; /* will get exact value next */
636 min_pfn_mapped = real_end >> PAGE_SHIFT;
637 last_start = real_end;
638
639 /*
640 * We start from the top (end of memory) and go to the bottom.
641 * The memblock_find_in_range() gets us a block of RAM from the
642 * end of RAM in [min_pfn_mapped, max_pfn_mapped) used as new pages
643 * for page table.
644 */
645 while (last_start > map_start) {
646 unsigned long start;
647
648 if (last_start > step_size) {
649 start = round_down(last_start - 1, step_size);
650 if (start < map_start)
651 start = map_start;
652 } else
653 start = map_start;
654 mapped_ram_size += init_range_memory_mapping(start,
655 last_start);
656 last_start = start;
657 min_pfn_mapped = last_start >> PAGE_SHIFT;
658 if (mapped_ram_size >= step_size)
659 step_size = get_new_step_size(step_size);
660 }
661
662 if (real_end < map_end)
663 init_range_memory_mapping(real_end, map_end);
664 }
665
666 /**
667 * memory_map_bottom_up - Map [map_start, map_end) bottom up
668 * @map_start: start address of the target memory range
669 * @map_end: end address of the target memory range
670 *
671 * This function will setup direct mapping for memory range
672 * [map_start, map_end) in bottom-up. Since we have limited the
673 * bottom-up allocation above the kernel, the page tables will
674 * be allocated just above the kernel and we map the memory
675 * in [map_start, map_end) in bottom-up.
676 */
memory_map_bottom_up(unsigned long map_start,unsigned long map_end)677 static void __init memory_map_bottom_up(unsigned long map_start,
678 unsigned long map_end)
679 {
680 unsigned long next, start;
681 unsigned long mapped_ram_size = 0;
682 /* step_size need to be small so pgt_buf from BRK could cover it */
683 unsigned long step_size = PMD_SIZE;
684
685 start = map_start;
686 min_pfn_mapped = start >> PAGE_SHIFT;
687
688 /*
689 * We start from the bottom (@map_start) and go to the top (@map_end).
690 * The memblock_find_in_range() gets us a block of RAM from the
691 * end of RAM in [min_pfn_mapped, max_pfn_mapped) used as new pages
692 * for page table.
693 */
694 while (start < map_end) {
695 if (step_size && map_end - start > step_size) {
696 next = round_up(start + 1, step_size);
697 if (next > map_end)
698 next = map_end;
699 } else {
700 next = map_end;
701 }
702
703 mapped_ram_size += init_range_memory_mapping(start, next);
704 start = next;
705
706 if (mapped_ram_size >= step_size)
707 step_size = get_new_step_size(step_size);
708 }
709 }
710
711 /*
712 * The real mode trampoline, which is required for bootstrapping CPUs
713 * occupies only a small area under the low 1MB. See reserve_real_mode()
714 * for details.
715 *
716 * If KASLR is disabled the first PGD entry of the direct mapping is copied
717 * to map the real mode trampoline.
718 *
719 * If KASLR is enabled, copy only the PUD which covers the low 1MB
720 * area. This limits the randomization granularity to 1GB for both 4-level
721 * and 5-level paging.
722 */
init_trampoline(void)723 static void __init init_trampoline(void)
724 {
725 #ifdef CONFIG_X86_64
726 /*
727 * The code below will alias kernel page-tables in the user-range of the
728 * address space, including the Global bit. So global TLB entries will
729 * be created when using the trampoline page-table.
730 */
731 if (!kaslr_memory_enabled())
732 trampoline_pgd_entry = init_top_pgt[pgd_index(__PAGE_OFFSET)];
733 else
734 init_trampoline_kaslr();
735 #endif
736 }
737
init_mem_mapping(void)738 void __init init_mem_mapping(void)
739 {
740 unsigned long end;
741
742 pti_check_boottime_disable();
743 probe_page_size_mask();
744 setup_pcid();
745
746 #ifdef CONFIG_X86_64
747 end = max_pfn << PAGE_SHIFT;
748 #else
749 end = max_low_pfn << PAGE_SHIFT;
750 #endif
751
752 /* the ISA range is always mapped regardless of memory holes */
753 init_memory_mapping(0, ISA_END_ADDRESS, PAGE_KERNEL);
754
755 /* Init the trampoline, possibly with KASLR memory offset */
756 init_trampoline();
757
758 /*
759 * If the allocation is in bottom-up direction, we setup direct mapping
760 * in bottom-up, otherwise we setup direct mapping in top-down.
761 */
762 if (memblock_bottom_up()) {
763 unsigned long kernel_end = __pa_symbol(_end);
764
765 /*
766 * we need two separate calls here. This is because we want to
767 * allocate page tables above the kernel. So we first map
768 * [kernel_end, end) to make memory above the kernel be mapped
769 * as soon as possible. And then use page tables allocated above
770 * the kernel to map [ISA_END_ADDRESS, kernel_end).
771 */
772 memory_map_bottom_up(kernel_end, end);
773 memory_map_bottom_up(ISA_END_ADDRESS, kernel_end);
774 } else {
775 memory_map_top_down(ISA_END_ADDRESS, end);
776 }
777
778 #ifdef CONFIG_X86_64
779 if (max_pfn > max_low_pfn) {
780 /* can we preserve max_low_pfn ?*/
781 max_low_pfn = max_pfn;
782 }
783 #else
784 early_ioremap_page_table_range_init();
785 #endif
786
787 load_cr3(swapper_pg_dir);
788 __flush_tlb_all();
789
790 x86_init.hyper.init_mem_mapping();
791
792 early_memtest(0, max_pfn_mapped << PAGE_SHIFT);
793 }
794
795 /*
796 * Initialize an mm_struct to be used during poking and a pointer to be used
797 * during patching.
798 */
poking_init(void)799 void __init poking_init(void)
800 {
801 spinlock_t *ptl;
802 pte_t *ptep;
803
804 poking_mm = copy_init_mm();
805 BUG_ON(!poking_mm);
806
807 /*
808 * Randomize the poking address, but make sure that the following page
809 * will be mapped at the same PMD. We need 2 pages, so find space for 3,
810 * and adjust the address if the PMD ends after the first one.
811 */
812 poking_addr = TASK_UNMAPPED_BASE;
813 if (IS_ENABLED(CONFIG_RANDOMIZE_BASE))
814 poking_addr += (kaslr_get_random_long("Poking") & PAGE_MASK) %
815 (TASK_SIZE - TASK_UNMAPPED_BASE - 3 * PAGE_SIZE);
816
817 if (((poking_addr + PAGE_SIZE) & ~PMD_MASK) == 0)
818 poking_addr += PAGE_SIZE;
819
820 /*
821 * We need to trigger the allocation of the page-tables that will be
822 * needed for poking now. Later, poking may be performed in an atomic
823 * section, which might cause allocation to fail.
824 */
825 ptep = get_locked_pte(poking_mm, poking_addr, &ptl);
826 BUG_ON(!ptep);
827 pte_unmap_unlock(ptep, ptl);
828 }
829
830 /*
831 * devmem_is_allowed() checks to see if /dev/mem access to a certain address
832 * is valid. The argument is a physical page number.
833 *
834 * On x86, access has to be given to the first megabyte of RAM because that
835 * area traditionally contains BIOS code and data regions used by X, dosemu,
836 * and similar apps. Since they map the entire memory range, the whole range
837 * must be allowed (for mapping), but any areas that would otherwise be
838 * disallowed are flagged as being "zero filled" instead of rejected.
839 * Access has to be given to non-kernel-ram areas as well, these contain the
840 * PCI mmio resources as well as potential bios/acpi data regions.
841 */
devmem_is_allowed(unsigned long pagenr)842 int devmem_is_allowed(unsigned long pagenr)
843 {
844 if (region_intersects(PFN_PHYS(pagenr), PAGE_SIZE,
845 IORESOURCE_SYSTEM_RAM, IORES_DESC_NONE)
846 != REGION_DISJOINT) {
847 /*
848 * For disallowed memory regions in the low 1MB range,
849 * request that the page be shown as all zeros.
850 */
851 if (pagenr < 256)
852 return 2;
853
854 return 0;
855 }
856
857 /*
858 * This must follow RAM test, since System RAM is considered a
859 * restricted resource under CONFIG_STRICT_IOMEM.
860 */
861 if (iomem_is_exclusive(pagenr << PAGE_SHIFT)) {
862 /* Low 1MB bypasses iomem restrictions. */
863 if (pagenr < 256)
864 return 1;
865
866 return 0;
867 }
868
869 return 1;
870 }
871
free_init_pages(const char * what,unsigned long begin,unsigned long end)872 void free_init_pages(const char *what, unsigned long begin, unsigned long end)
873 {
874 unsigned long begin_aligned, end_aligned;
875
876 /* Make sure boundaries are page aligned */
877 begin_aligned = PAGE_ALIGN(begin);
878 end_aligned = end & PAGE_MASK;
879
880 if (WARN_ON(begin_aligned != begin || end_aligned != end)) {
881 begin = begin_aligned;
882 end = end_aligned;
883 }
884
885 if (begin >= end)
886 return;
887
888 /*
889 * If debugging page accesses then do not free this memory but
890 * mark them not present - any buggy init-section access will
891 * create a kernel page fault:
892 */
893 if (debug_pagealloc_enabled()) {
894 pr_info("debug: unmapping init [mem %#010lx-%#010lx]\n",
895 begin, end - 1);
896 /*
897 * Inform kmemleak about the hole in the memory since the
898 * corresponding pages will be unmapped.
899 */
900 kmemleak_free_part((void *)begin, end - begin);
901 set_memory_np(begin, (end - begin) >> PAGE_SHIFT);
902 } else {
903 /*
904 * We just marked the kernel text read only above, now that
905 * we are going to free part of that, we need to make that
906 * writeable and non-executable first.
907 */
908 set_memory_nx(begin, (end - begin) >> PAGE_SHIFT);
909 set_memory_rw(begin, (end - begin) >> PAGE_SHIFT);
910
911 free_reserved_area((void *)begin, (void *)end,
912 POISON_FREE_INITMEM, what);
913 }
914 }
915
916 /*
917 * begin/end can be in the direct map or the "high kernel mapping"
918 * used for the kernel image only. free_init_pages() will do the
919 * right thing for either kind of address.
920 */
free_kernel_image_pages(const char * what,void * begin,void * end)921 void free_kernel_image_pages(const char *what, void *begin, void *end)
922 {
923 unsigned long begin_ul = (unsigned long)begin;
924 unsigned long end_ul = (unsigned long)end;
925 unsigned long len_pages = (end_ul - begin_ul) >> PAGE_SHIFT;
926
927 free_init_pages(what, begin_ul, end_ul);
928
929 /*
930 * PTI maps some of the kernel into userspace. For performance,
931 * this includes some kernel areas that do not contain secrets.
932 * Those areas might be adjacent to the parts of the kernel image
933 * being freed, which may contain secrets. Remove the "high kernel
934 * image mapping" for these freed areas, ensuring they are not even
935 * potentially vulnerable to Meltdown regardless of the specific
936 * optimizations PTI is currently using.
937 *
938 * The "noalias" prevents unmapping the direct map alias which is
939 * needed to access the freed pages.
940 *
941 * This is only valid for 64bit kernels. 32bit has only one mapping
942 * which can't be treated in this way for obvious reasons.
943 */
944 if (IS_ENABLED(CONFIG_X86_64) && cpu_feature_enabled(X86_FEATURE_PTI))
945 set_memory_np_noalias(begin_ul, len_pages);
946 }
947
free_initmem(void)948 void __ref free_initmem(void)
949 {
950 e820__reallocate_tables();
951
952 mem_encrypt_free_decrypted_mem();
953
954 free_kernel_image_pages("unused kernel image (initmem)",
955 &__init_begin, &__init_end);
956 }
957
958 #ifdef CONFIG_BLK_DEV_INITRD
free_initrd_mem(unsigned long start,unsigned long end)959 void __init free_initrd_mem(unsigned long start, unsigned long end)
960 {
961 /*
962 * end could be not aligned, and We can not align that,
963 * decompressor could be confused by aligned initrd_end
964 * We already reserve the end partial page before in
965 * - i386_start_kernel()
966 * - x86_64_start_kernel()
967 * - relocate_initrd()
968 * So here We can do PAGE_ALIGN() safely to get partial page to be freed
969 */
970 free_init_pages("initrd", start, PAGE_ALIGN(end));
971 }
972 #endif
973
974 /*
975 * Calculate the precise size of the DMA zone (first 16 MB of RAM),
976 * and pass it to the MM layer - to help it set zone watermarks more
977 * accurately.
978 *
979 * Done on 64-bit systems only for the time being, although 32-bit systems
980 * might benefit from this as well.
981 */
memblock_find_dma_reserve(void)982 void __init memblock_find_dma_reserve(void)
983 {
984 #ifdef CONFIG_X86_64
985 u64 nr_pages = 0, nr_free_pages = 0;
986 unsigned long start_pfn, end_pfn;
987 phys_addr_t start_addr, end_addr;
988 int i;
989 u64 u;
990
991 /*
992 * Iterate over all memory ranges (free and reserved ones alike),
993 * to calculate the total number of pages in the first 16 MB of RAM:
994 */
995 nr_pages = 0;
996 for_each_mem_pfn_range(i, MAX_NUMNODES, &start_pfn, &end_pfn, NULL) {
997 start_pfn = min(start_pfn, MAX_DMA_PFN);
998 end_pfn = min(end_pfn, MAX_DMA_PFN);
999
1000 nr_pages += end_pfn - start_pfn;
1001 }
1002
1003 /*
1004 * Iterate over free memory ranges to calculate the number of free
1005 * pages in the DMA zone, while not counting potential partial
1006 * pages at the beginning or the end of the range:
1007 */
1008 nr_free_pages = 0;
1009 for_each_free_mem_range(u, NUMA_NO_NODE, MEMBLOCK_NONE, &start_addr, &end_addr, NULL) {
1010 start_pfn = min_t(unsigned long, PFN_UP(start_addr), MAX_DMA_PFN);
1011 end_pfn = min_t(unsigned long, PFN_DOWN(end_addr), MAX_DMA_PFN);
1012
1013 if (start_pfn < end_pfn)
1014 nr_free_pages += end_pfn - start_pfn;
1015 }
1016
1017 set_dma_reserve(nr_pages - nr_free_pages);
1018 #endif
1019 }
1020
zone_sizes_init(void)1021 void __init zone_sizes_init(void)
1022 {
1023 unsigned long max_zone_pfns[MAX_NR_ZONES];
1024
1025 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
1026
1027 #ifdef CONFIG_ZONE_DMA
1028 max_zone_pfns[ZONE_DMA] = min(MAX_DMA_PFN, max_low_pfn);
1029 #endif
1030 #ifdef CONFIG_ZONE_DMA32
1031 max_zone_pfns[ZONE_DMA32] = min(MAX_DMA32_PFN, max_low_pfn);
1032 #endif
1033 max_zone_pfns[ZONE_NORMAL] = max_low_pfn;
1034 #ifdef CONFIG_HIGHMEM
1035 max_zone_pfns[ZONE_HIGHMEM] = max_pfn;
1036 #endif
1037
1038 free_area_init(max_zone_pfns);
1039 }
1040
1041 __visible DEFINE_PER_CPU_ALIGNED(struct tlb_state, cpu_tlbstate) = {
1042 .loaded_mm = &init_mm,
1043 .next_asid = 1,
1044 .cr4 = ~0UL, /* fail hard if we screw up cr4 shadow initialization */
1045 };
1046
update_cache_mode_entry(unsigned entry,enum page_cache_mode cache)1047 void update_cache_mode_entry(unsigned entry, enum page_cache_mode cache)
1048 {
1049 /* entry 0 MUST be WB (hardwired to speed up translations) */
1050 BUG_ON(!entry && cache != _PAGE_CACHE_MODE_WB);
1051
1052 __cachemode2pte_tbl[cache] = __cm_idx2pte(entry);
1053 __pte2cachemode_tbl[entry] = cache;
1054 }
1055
1056 #ifdef CONFIG_SWAP
max_swapfile_size(void)1057 unsigned long max_swapfile_size(void)
1058 {
1059 unsigned long pages;
1060
1061 pages = generic_max_swapfile_size();
1062
1063 if (boot_cpu_has_bug(X86_BUG_L1TF) && l1tf_mitigation != L1TF_MITIGATION_OFF) {
1064 /* Limit the swap file size to MAX_PA/2 for L1TF workaround */
1065 unsigned long long l1tf_limit = l1tf_pfn_limit();
1066 /*
1067 * We encode swap offsets also with 3 bits below those for pfn
1068 * which makes the usable limit higher.
1069 */
1070 #if CONFIG_PGTABLE_LEVELS > 2
1071 l1tf_limit <<= PAGE_SHIFT - SWP_OFFSET_FIRST_BIT;
1072 #endif
1073 pages = min_t(unsigned long long, l1tf_limit, pages);
1074 }
1075 return pages;
1076 }
1077 #endif
1078