1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * SGI UV APIC functions (note: not an Intel compatible APIC)
7  *
8  * (C) Copyright 2020 Hewlett Packard Enterprise Development LP
9  * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
10  */
11 #include <linux/crash_dump.h>
12 #include <linux/cpuhotplug.h>
13 #include <linux/cpumask.h>
14 #include <linux/proc_fs.h>
15 #include <linux/memory.h>
16 #include <linux/export.h>
17 #include <linux/pci.h>
18 #include <linux/acpi.h>
19 #include <linux/efi.h>
20 
21 #include <asm/e820/api.h>
22 #include <asm/uv/uv_mmrs.h>
23 #include <asm/uv/uv_hub.h>
24 #include <asm/uv/bios.h>
25 #include <asm/uv/uv.h>
26 #include <asm/apic.h>
27 
28 #include "local.h"
29 
30 static enum uv_system_type	uv_system_type;
31 static int			uv_hubbed_system;
32 static int			uv_hubless_system;
33 static u64			gru_start_paddr, gru_end_paddr;
34 static union uvh_apicid		uvh_apicid;
35 static int			uv_node_id;
36 
37 /* Unpack AT/OEM/TABLE ID's to be NULL terminated strings */
38 static u8 uv_archtype[UV_AT_SIZE + 1];
39 static u8 oem_id[ACPI_OEM_ID_SIZE + 1];
40 static u8 oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
41 
42 /* Information derived from CPUID and some UV MMRs */
43 static struct {
44 	unsigned int apicid_shift;
45 	unsigned int apicid_mask;
46 	unsigned int socketid_shift;	/* aka pnode_shift for UV2/3 */
47 	unsigned int pnode_mask;
48 	unsigned int nasid_shift;
49 	unsigned int gpa_shift;
50 	unsigned int gnode_shift;
51 	unsigned int m_skt;
52 	unsigned int n_skt;
53 } uv_cpuid;
54 
55 static int uv_min_hub_revision_id;
56 
57 static struct apic apic_x2apic_uv_x;
58 static struct uv_hub_info_s uv_hub_info_node0;
59 
60 /* Set this to use hardware error handler instead of kernel panic: */
61 static int disable_uv_undefined_panic = 1;
62 
uv_undefined(char * str)63 unsigned long uv_undefined(char *str)
64 {
65 	if (likely(!disable_uv_undefined_panic))
66 		panic("UV: error: undefined MMR: %s\n", str);
67 	else
68 		pr_crit("UV: error: undefined MMR: %s\n", str);
69 
70 	/* Cause a machine fault: */
71 	return ~0ul;
72 }
73 EXPORT_SYMBOL(uv_undefined);
74 
uv_early_read_mmr(unsigned long addr)75 static unsigned long __init uv_early_read_mmr(unsigned long addr)
76 {
77 	unsigned long val, *mmr;
78 
79 	mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr));
80 	val = *mmr;
81 	early_iounmap(mmr, sizeof(*mmr));
82 
83 	return val;
84 }
85 
is_GRU_range(u64 start,u64 end)86 static inline bool is_GRU_range(u64 start, u64 end)
87 {
88 	if (!gru_start_paddr)
89 		return false;
90 
91 	return start >= gru_start_paddr && end <= gru_end_paddr;
92 }
93 
uv_is_untracked_pat_range(u64 start,u64 end)94 static bool uv_is_untracked_pat_range(u64 start, u64 end)
95 {
96 	return is_ISA_range(start, end) || is_GRU_range(start, end);
97 }
98 
early_get_pnodeid(void)99 static void __init early_get_pnodeid(void)
100 {
101 	int pnode;
102 
103 	uv_cpuid.m_skt = 0;
104 	if (UVH_RH10_GAM_ADDR_MAP_CONFIG) {
105 		union uvh_rh10_gam_addr_map_config_u  m_n_config;
106 
107 		m_n_config.v = uv_early_read_mmr(UVH_RH10_GAM_ADDR_MAP_CONFIG);
108 		uv_cpuid.n_skt = m_n_config.s.n_skt;
109 		uv_cpuid.nasid_shift = 0;
110 	} else if (UVH_RH_GAM_ADDR_MAP_CONFIG) {
111 		union uvh_rh_gam_addr_map_config_u  m_n_config;
112 
113 	m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_ADDR_MAP_CONFIG);
114 		uv_cpuid.n_skt = m_n_config.s.n_skt;
115 		if (is_uv(UV3))
116 			uv_cpuid.m_skt = m_n_config.s3.m_skt;
117 		if (is_uv(UV2))
118 			uv_cpuid.m_skt = m_n_config.s2.m_skt;
119 		uv_cpuid.nasid_shift = 1;
120 	} else {
121 		unsigned long GAM_ADDR_MAP_CONFIG = 0;
122 
123 		WARN(GAM_ADDR_MAP_CONFIG == 0,
124 			"UV: WARN: GAM_ADDR_MAP_CONFIG is not available\n");
125 		uv_cpuid.n_skt = 0;
126 		uv_cpuid.nasid_shift = 0;
127 	}
128 
129 	if (is_uv(UV4|UVY))
130 		uv_cpuid.gnode_shift = 2; /* min partition is 4 sockets */
131 
132 	uv_cpuid.pnode_mask = (1 << uv_cpuid.n_skt) - 1;
133 	pnode = (uv_node_id >> uv_cpuid.nasid_shift) & uv_cpuid.pnode_mask;
134 	uv_cpuid.gpa_shift = 46;	/* Default unless changed */
135 
136 	pr_info("UV: n_skt:%d pnmsk:%x pn:%x\n",
137 		uv_cpuid.n_skt, uv_cpuid.pnode_mask, pnode);
138 }
139 
140 /* Running on a UV Hubbed system, determine which UV Hub Type it is */
early_set_hub_type(void)141 static int __init early_set_hub_type(void)
142 {
143 	union uvh_node_id_u node_id;
144 
145 	/*
146 	 * The NODE_ID MMR is always at offset 0.
147 	 * Contains the chip part # + revision.
148 	 * Node_id field started with 15 bits,
149 	 * ... now 7 but upper 8 are masked to 0.
150 	 * All blades/nodes have the same part # and hub revision.
151 	 */
152 	node_id.v = uv_early_read_mmr(UVH_NODE_ID);
153 	uv_node_id = node_id.sx.node_id;
154 
155 	switch (node_id.s.part_number) {
156 
157 	case UV5_HUB_PART_NUMBER:
158 		uv_min_hub_revision_id = node_id.s.revision
159 					 + UV5_HUB_REVISION_BASE;
160 		uv_hub_type_set(UV5);
161 		break;
162 
163 	/* UV4/4A only have a revision difference */
164 	case UV4_HUB_PART_NUMBER:
165 		uv_min_hub_revision_id = node_id.s.revision
166 					 + UV4_HUB_REVISION_BASE - 1;
167 		uv_hub_type_set(UV4);
168 		if (uv_min_hub_revision_id == UV4A_HUB_REVISION_BASE)
169 			uv_hub_type_set(UV4|UV4A);
170 		break;
171 
172 	case UV3_HUB_PART_NUMBER:
173 	case UV3_HUB_PART_NUMBER_X:
174 		uv_min_hub_revision_id = node_id.s.revision
175 					 + UV3_HUB_REVISION_BASE;
176 		uv_hub_type_set(UV3);
177 		break;
178 
179 	case UV2_HUB_PART_NUMBER:
180 	case UV2_HUB_PART_NUMBER_X:
181 		uv_min_hub_revision_id = node_id.s.revision
182 					 + UV2_HUB_REVISION_BASE - 1;
183 		uv_hub_type_set(UV2);
184 		break;
185 
186 	default:
187 		return 0;
188 	}
189 
190 	pr_info("UV: part#:%x rev:%d rev_id:%d UVtype:0x%x\n",
191 		node_id.s.part_number, node_id.s.revision,
192 		uv_min_hub_revision_id, is_uv(~0));
193 
194 	return 1;
195 }
196 
uv_tsc_check_sync(void)197 static void __init uv_tsc_check_sync(void)
198 {
199 	u64 mmr;
200 	int sync_state;
201 	int mmr_shift;
202 	char *state;
203 
204 	/* UV5 guarantees synced TSCs; do not zero TSC_ADJUST */
205 	if (!is_uv(UV2|UV3|UV4)) {
206 		mark_tsc_async_resets("UV5+");
207 		return;
208 	}
209 
210 	/* UV2,3,4, UV BIOS TSC sync state available */
211 	mmr = uv_early_read_mmr(UVH_TSC_SYNC_MMR);
212 	mmr_shift =
213 		is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT;
214 	sync_state = (mmr >> mmr_shift) & UVH_TSC_SYNC_MASK;
215 
216 	/* Check if TSC is valid for all sockets */
217 	switch (sync_state) {
218 	case UVH_TSC_SYNC_VALID:
219 		state = "in sync";
220 		mark_tsc_async_resets("UV BIOS");
221 		break;
222 
223 	/* If BIOS state unknown, don't do anything */
224 	case UVH_TSC_SYNC_UNKNOWN:
225 		state = "unknown";
226 		break;
227 
228 	/* Otherwise, BIOS indicates problem with TSC */
229 	default:
230 		state = "unstable";
231 		mark_tsc_unstable("UV BIOS");
232 		break;
233 	}
234 	pr_info("UV: TSC sync state from BIOS:0%d(%s)\n", sync_state, state);
235 }
236 
237 /* Selector for (4|4A|5) structs */
238 #define uvxy_field(sname, field, undef) (	\
239 	is_uv(UV4A) ? sname.s4a.field :		\
240 	is_uv(UV4) ? sname.s4.field :		\
241 	is_uv(UV3) ? sname.s3.field :		\
242 	undef)
243 
244 /* [Copied from arch/x86/kernel/cpu/topology.c:detect_extended_topology()] */
245 
246 #define SMT_LEVEL			0	/* Leaf 0xb SMT level */
247 #define INVALID_TYPE			0	/* Leaf 0xb sub-leaf types */
248 #define SMT_TYPE			1
249 #define CORE_TYPE			2
250 #define LEAFB_SUBTYPE(ecx)		(((ecx) >> 8) & 0xff)
251 #define BITS_SHIFT_NEXT_LEVEL(eax)	((eax) & 0x1f)
252 
set_x2apic_bits(void)253 static void set_x2apic_bits(void)
254 {
255 	unsigned int eax, ebx, ecx, edx, sub_index;
256 	unsigned int sid_shift;
257 
258 	cpuid(0, &eax, &ebx, &ecx, &edx);
259 	if (eax < 0xb) {
260 		pr_info("UV: CPU does not have CPUID.11\n");
261 		return;
262 	}
263 
264 	cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx);
265 	if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE)) {
266 		pr_info("UV: CPUID.11 not implemented\n");
267 		return;
268 	}
269 
270 	sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
271 	sub_index = 1;
272 	do {
273 		cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx);
274 		if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) {
275 			sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
276 			break;
277 		}
278 		sub_index++;
279 	} while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE);
280 
281 	uv_cpuid.apicid_shift	= 0;
282 	uv_cpuid.apicid_mask	= (~(-1 << sid_shift));
283 	uv_cpuid.socketid_shift = sid_shift;
284 }
285 
early_get_apic_socketid_shift(void)286 static void __init early_get_apic_socketid_shift(void)
287 {
288 	if (is_uv2_hub() || is_uv3_hub())
289 		uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
290 
291 	set_x2apic_bits();
292 
293 	pr_info("UV: apicid_shift:%d apicid_mask:0x%x\n", uv_cpuid.apicid_shift, uv_cpuid.apicid_mask);
294 	pr_info("UV: socketid_shift:%d pnode_mask:0x%x\n", uv_cpuid.socketid_shift, uv_cpuid.pnode_mask);
295 }
296 
uv_stringify(int len,char * to,char * from)297 static void __init uv_stringify(int len, char *to, char *from)
298 {
299 	strscpy(to, from, len);
300 
301 	/* Trim trailing spaces */
302 	(void)strim(to);
303 }
304 
305 /* Find UV arch type entry in UVsystab */
early_find_archtype(struct uv_systab * st)306 static unsigned long __init early_find_archtype(struct uv_systab *st)
307 {
308 	int i;
309 
310 	for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) {
311 		unsigned long ptr = st->entry[i].offset;
312 
313 		if (!ptr)
314 			continue;
315 		ptr += (unsigned long)st;
316 		if (st->entry[i].type == UV_SYSTAB_TYPE_ARCH_TYPE)
317 			return ptr;
318 	}
319 	return 0;
320 }
321 
322 /* Validate UV arch type field in UVsystab */
decode_arch_type(unsigned long ptr)323 static int __init decode_arch_type(unsigned long ptr)
324 {
325 	struct uv_arch_type_entry *uv_ate = (struct uv_arch_type_entry *)ptr;
326 	int n = strlen(uv_ate->archtype);
327 
328 	if (n > 0 && n < sizeof(uv_ate->archtype)) {
329 		pr_info("UV: UVarchtype received from BIOS\n");
330 		uv_stringify(sizeof(uv_archtype), uv_archtype, uv_ate->archtype);
331 		return 1;
332 	}
333 	return 0;
334 }
335 
336 /* Determine if UV arch type entry might exist in UVsystab */
early_get_arch_type(void)337 static int __init early_get_arch_type(void)
338 {
339 	unsigned long uvst_physaddr, uvst_size, ptr;
340 	struct uv_systab *st;
341 	u32 rev;
342 	int ret;
343 
344 	uvst_physaddr = get_uv_systab_phys(0);
345 	if (!uvst_physaddr)
346 		return 0;
347 
348 	st = early_memremap_ro(uvst_physaddr, sizeof(struct uv_systab));
349 	if (!st) {
350 		pr_err("UV: Cannot access UVsystab, remap failed\n");
351 		return 0;
352 	}
353 
354 	rev = st->revision;
355 	if (rev < UV_SYSTAB_VERSION_UV5) {
356 		early_memunmap(st, sizeof(struct uv_systab));
357 		return 0;
358 	}
359 
360 	uvst_size = st->size;
361 	early_memunmap(st, sizeof(struct uv_systab));
362 	st = early_memremap_ro(uvst_physaddr, uvst_size);
363 	if (!st) {
364 		pr_err("UV: Cannot access UVarchtype, remap failed\n");
365 		return 0;
366 	}
367 
368 	ptr = early_find_archtype(st);
369 	if (!ptr) {
370 		early_memunmap(st, uvst_size);
371 		return 0;
372 	}
373 
374 	ret = decode_arch_type(ptr);
375 	early_memunmap(st, uvst_size);
376 	return ret;
377 }
378 
379 /* UV system found, check which APIC MODE BIOS already selected */
early_set_apic_mode(void)380 static void __init early_set_apic_mode(void)
381 {
382 	if (x2apic_enabled())
383 		uv_system_type = UV_X2APIC;
384 	else
385 		uv_system_type = UV_LEGACY_APIC;
386 }
387 
uv_set_system_type(char * _oem_id,char * _oem_table_id)388 static int __init uv_set_system_type(char *_oem_id, char *_oem_table_id)
389 {
390 	/* Save OEM_ID passed from ACPI MADT */
391 	uv_stringify(sizeof(oem_id), oem_id, _oem_id);
392 
393 	/* Check if BIOS sent us a UVarchtype */
394 	if (!early_get_arch_type())
395 
396 		/* If not use OEM ID for UVarchtype */
397 		uv_stringify(sizeof(uv_archtype), uv_archtype, oem_id);
398 
399 	/* Check if not hubbed */
400 	if (strncmp(uv_archtype, "SGI", 3) != 0) {
401 
402 		/* (Not hubbed), check if not hubless */
403 		if (strncmp(uv_archtype, "NSGI", 4) != 0)
404 
405 			/* (Not hubless), not a UV */
406 			return 0;
407 
408 		/* Is UV hubless system */
409 		uv_hubless_system = 0x01;
410 
411 		/* UV5 Hubless */
412 		if (strncmp(uv_archtype, "NSGI5", 5) == 0)
413 			uv_hubless_system |= 0x20;
414 
415 		/* UV4 Hubless: CH */
416 		else if (strncmp(uv_archtype, "NSGI4", 5) == 0)
417 			uv_hubless_system |= 0x10;
418 
419 		/* UV3 Hubless: UV300/MC990X w/o hub */
420 		else
421 			uv_hubless_system |= 0x8;
422 
423 		/* Copy OEM Table ID */
424 		uv_stringify(sizeof(oem_table_id), oem_table_id, _oem_table_id);
425 
426 		pr_info("UV: OEM IDs %s/%s, SystemType %d, HUBLESS ID %x\n",
427 			oem_id, oem_table_id, uv_system_type, uv_hubless_system);
428 
429 		return 0;
430 	}
431 
432 	if (numa_off) {
433 		pr_err("UV: NUMA is off, disabling UV support\n");
434 		return 0;
435 	}
436 
437 	/* Set hubbed type if true */
438 	uv_hub_info->hub_revision =
439 		!strncmp(uv_archtype, "SGI5", 4) ? UV5_HUB_REVISION_BASE :
440 		!strncmp(uv_archtype, "SGI4", 4) ? UV4_HUB_REVISION_BASE :
441 		!strncmp(uv_archtype, "SGI3", 4) ? UV3_HUB_REVISION_BASE :
442 		!strcmp(uv_archtype, "SGI2") ? UV2_HUB_REVISION_BASE : 0;
443 
444 	switch (uv_hub_info->hub_revision) {
445 	case UV5_HUB_REVISION_BASE:
446 		uv_hubbed_system = 0x21;
447 		uv_hub_type_set(UV5);
448 		break;
449 
450 	case UV4_HUB_REVISION_BASE:
451 		uv_hubbed_system = 0x11;
452 		uv_hub_type_set(UV4);
453 		break;
454 
455 	case UV3_HUB_REVISION_BASE:
456 		uv_hubbed_system = 0x9;
457 		uv_hub_type_set(UV3);
458 		break;
459 
460 	case UV2_HUB_REVISION_BASE:
461 		uv_hubbed_system = 0x5;
462 		uv_hub_type_set(UV2);
463 		break;
464 
465 	default:
466 		return 0;
467 	}
468 
469 	/* Get UV hub chip part number & revision */
470 	early_set_hub_type();
471 
472 	/* Other UV setup functions */
473 	early_set_apic_mode();
474 	early_get_pnodeid();
475 	early_get_apic_socketid_shift();
476 	x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range;
477 	x86_platform.nmi_init = uv_nmi_init;
478 	uv_tsc_check_sync();
479 
480 	return 1;
481 }
482 
483 /* Called early to probe for the correct APIC driver */
uv_acpi_madt_oem_check(char * _oem_id,char * _oem_table_id)484 static int __init uv_acpi_madt_oem_check(char *_oem_id, char *_oem_table_id)
485 {
486 	/* Set up early hub info fields for Node 0 */
487 	uv_cpu_info->p_uv_hub_info = &uv_hub_info_node0;
488 
489 	/* If not UV, return. */
490 	if (uv_set_system_type(_oem_id, _oem_table_id) == 0)
491 		return 0;
492 
493 	/* Save for display of the OEM Table ID */
494 	uv_stringify(sizeof(oem_table_id), oem_table_id, _oem_table_id);
495 
496 	pr_info("UV: OEM IDs %s/%s, System/UVType %d/0x%x, HUB RevID %d\n",
497 		oem_id, oem_table_id, uv_system_type, is_uv(UV_ANY),
498 		uv_min_hub_revision_id);
499 
500 	return 0;
501 }
502 
get_uv_system_type(void)503 enum uv_system_type get_uv_system_type(void)
504 {
505 	return uv_system_type;
506 }
507 
uv_get_hubless_system(void)508 int uv_get_hubless_system(void)
509 {
510 	return uv_hubless_system;
511 }
512 EXPORT_SYMBOL_GPL(uv_get_hubless_system);
513 
uv_get_archtype(char * buf,int len)514 ssize_t uv_get_archtype(char *buf, int len)
515 {
516 	return scnprintf(buf, len, "%s/%s", uv_archtype, oem_table_id);
517 }
518 EXPORT_SYMBOL_GPL(uv_get_archtype);
519 
is_uv_system(void)520 int is_uv_system(void)
521 {
522 	return uv_system_type != UV_NONE;
523 }
524 EXPORT_SYMBOL_GPL(is_uv_system);
525 
is_uv_hubbed(int uvtype)526 int is_uv_hubbed(int uvtype)
527 {
528 	return (uv_hubbed_system & uvtype);
529 }
530 EXPORT_SYMBOL_GPL(is_uv_hubbed);
531 
is_uv_hubless(int uvtype)532 static int is_uv_hubless(int uvtype)
533 {
534 	return (uv_hubless_system & uvtype);
535 }
536 
537 void **__uv_hub_info_list;
538 EXPORT_SYMBOL_GPL(__uv_hub_info_list);
539 
540 DEFINE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info);
541 EXPORT_PER_CPU_SYMBOL_GPL(__uv_cpu_info);
542 
543 short uv_possible_blades;
544 EXPORT_SYMBOL_GPL(uv_possible_blades);
545 
546 unsigned long sn_rtc_cycles_per_second;
547 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
548 
549 /* The following values are used for the per node hub info struct */
550 static __initdata unsigned short		_min_socket, _max_socket;
551 static __initdata unsigned short		_min_pnode, _max_pnode, _gr_table_len;
552 static __initdata struct uv_gam_range_entry	*uv_gre_table;
553 static __initdata struct uv_gam_parameters	*uv_gp_table;
554 static __initdata unsigned short		*_socket_to_node;
555 static __initdata unsigned short		*_socket_to_pnode;
556 static __initdata unsigned short		*_pnode_to_socket;
557 static __initdata unsigned short		*_node_to_socket;
558 
559 static __initdata struct uv_gam_range_s		*_gr_table;
560 
561 #define	SOCK_EMPTY	((unsigned short)~0)
562 
563 /* Default UV memory block size is 2GB */
564 static unsigned long mem_block_size __initdata = (2UL << 30);
565 
566 /* Kernel parameter to specify UV mem block size */
parse_mem_block_size(char * ptr)567 static int __init parse_mem_block_size(char *ptr)
568 {
569 	unsigned long size = memparse(ptr, NULL);
570 
571 	/* Size will be rounded down by set_block_size() below */
572 	mem_block_size = size;
573 	return 0;
574 }
575 early_param("uv_memblksize", parse_mem_block_size);
576 
adj_blksize(u32 lgre)577 static __init int adj_blksize(u32 lgre)
578 {
579 	unsigned long base = (unsigned long)lgre << UV_GAM_RANGE_SHFT;
580 	unsigned long size;
581 
582 	for (size = mem_block_size; size > MIN_MEMORY_BLOCK_SIZE; size >>= 1)
583 		if (IS_ALIGNED(base, size))
584 			break;
585 
586 	if (size >= mem_block_size)
587 		return 0;
588 
589 	mem_block_size = size;
590 	return 1;
591 }
592 
set_block_size(void)593 static __init void set_block_size(void)
594 {
595 	unsigned int order = ffs(mem_block_size);
596 
597 	if (order) {
598 		/* adjust for ffs return of 1..64 */
599 		set_memory_block_size_order(order - 1);
600 		pr_info("UV: mem_block_size set to 0x%lx\n", mem_block_size);
601 	} else {
602 		/* bad or zero value, default to 1UL << 31 (2GB) */
603 		pr_err("UV: mem_block_size error with 0x%lx\n", mem_block_size);
604 		set_memory_block_size_order(31);
605 	}
606 }
607 
608 /* Build GAM range lookup table: */
build_uv_gr_table(void)609 static __init void build_uv_gr_table(void)
610 {
611 	struct uv_gam_range_entry *gre = uv_gre_table;
612 	struct uv_gam_range_s *grt;
613 	unsigned long last_limit = 0, ram_limit = 0;
614 	int bytes, i, sid, lsid = -1, indx = 0, lindx = -1;
615 
616 	if (!gre)
617 		return;
618 
619 	bytes = _gr_table_len * sizeof(struct uv_gam_range_s);
620 	grt = kzalloc(bytes, GFP_KERNEL);
621 	if (WARN_ON_ONCE(!grt))
622 		return;
623 	_gr_table = grt;
624 
625 	for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
626 		if (gre->type == UV_GAM_RANGE_TYPE_HOLE) {
627 			if (!ram_limit) {
628 				/* Mark hole between RAM/non-RAM: */
629 				ram_limit = last_limit;
630 				last_limit = gre->limit;
631 				lsid++;
632 				continue;
633 			}
634 			last_limit = gre->limit;
635 			pr_info("UV: extra hole in GAM RE table @%d\n", (int)(gre - uv_gre_table));
636 			continue;
637 		}
638 		if (_max_socket < gre->sockid) {
639 			pr_err("UV: GAM table sockid(%d) too large(>%d) @%d\n", gre->sockid, _max_socket, (int)(gre - uv_gre_table));
640 			continue;
641 		}
642 		sid = gre->sockid - _min_socket;
643 		if (lsid < sid) {
644 			/* New range: */
645 			grt = &_gr_table[indx];
646 			grt->base = lindx;
647 			grt->nasid = gre->nasid;
648 			grt->limit = last_limit = gre->limit;
649 			lsid = sid;
650 			lindx = indx++;
651 			continue;
652 		}
653 		/* Update range: */
654 		if (lsid == sid && !ram_limit) {
655 			/* .. if contiguous: */
656 			if (grt->limit == last_limit) {
657 				grt->limit = last_limit = gre->limit;
658 				continue;
659 			}
660 		}
661 		/* Non-contiguous RAM range: */
662 		if (!ram_limit) {
663 			grt++;
664 			grt->base = lindx;
665 			grt->nasid = gre->nasid;
666 			grt->limit = last_limit = gre->limit;
667 			continue;
668 		}
669 		/* Non-contiguous/non-RAM: */
670 		grt++;
671 		/* base is this entry */
672 		grt->base = grt - _gr_table;
673 		grt->nasid = gre->nasid;
674 		grt->limit = last_limit = gre->limit;
675 		lsid++;
676 	}
677 
678 	/* Shorten table if possible */
679 	grt++;
680 	i = grt - _gr_table;
681 	if (i < _gr_table_len) {
682 		void *ret;
683 
684 		bytes = i * sizeof(struct uv_gam_range_s);
685 		ret = krealloc(_gr_table, bytes, GFP_KERNEL);
686 		if (ret) {
687 			_gr_table = ret;
688 			_gr_table_len = i;
689 		}
690 	}
691 
692 	/* Display resultant GAM range table: */
693 	for (i = 0, grt = _gr_table; i < _gr_table_len; i++, grt++) {
694 		unsigned long start, end;
695 		int gb = grt->base;
696 
697 		start = gb < 0 ?  0 : (unsigned long)_gr_table[gb].limit << UV_GAM_RANGE_SHFT;
698 		end = (unsigned long)grt->limit << UV_GAM_RANGE_SHFT;
699 
700 		pr_info("UV: GAM Range %2d %04x 0x%013lx-0x%013lx (%d)\n", i, grt->nasid, start, end, gb);
701 	}
702 }
703 
uv_wakeup_secondary(int phys_apicid,unsigned long start_rip)704 static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
705 {
706 	unsigned long val;
707 	int pnode;
708 
709 	pnode = uv_apicid_to_pnode(phys_apicid);
710 
711 	val = (1UL << UVH_IPI_INT_SEND_SHFT) |
712 	    (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
713 	    ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
714 	    APIC_DM_INIT;
715 
716 	uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
717 
718 	val = (1UL << UVH_IPI_INT_SEND_SHFT) |
719 	    (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
720 	    ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
721 	    APIC_DM_STARTUP;
722 
723 	uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
724 
725 	return 0;
726 }
727 
uv_send_IPI_one(int cpu,int vector)728 static void uv_send_IPI_one(int cpu, int vector)
729 {
730 	unsigned long apicid = per_cpu(x86_cpu_to_apicid, cpu);
731 	int pnode = uv_apicid_to_pnode(apicid);
732 	unsigned long dmode, val;
733 
734 	if (vector == NMI_VECTOR)
735 		dmode = APIC_DELIVERY_MODE_NMI;
736 	else
737 		dmode = APIC_DELIVERY_MODE_FIXED;
738 
739 	val = (1UL << UVH_IPI_INT_SEND_SHFT) |
740 		(apicid << UVH_IPI_INT_APIC_ID_SHFT) |
741 		(dmode << UVH_IPI_INT_DELIVERY_MODE_SHFT) |
742 		(vector << UVH_IPI_INT_VECTOR_SHFT);
743 
744 	uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
745 }
746 
uv_send_IPI_mask(const struct cpumask * mask,int vector)747 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
748 {
749 	unsigned int cpu;
750 
751 	for_each_cpu(cpu, mask)
752 		uv_send_IPI_one(cpu, vector);
753 }
754 
uv_send_IPI_mask_allbutself(const struct cpumask * mask,int vector)755 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
756 {
757 	unsigned int this_cpu = smp_processor_id();
758 	unsigned int cpu;
759 
760 	for_each_cpu(cpu, mask) {
761 		if (cpu != this_cpu)
762 			uv_send_IPI_one(cpu, vector);
763 	}
764 }
765 
uv_send_IPI_allbutself(int vector)766 static void uv_send_IPI_allbutself(int vector)
767 {
768 	unsigned int this_cpu = smp_processor_id();
769 	unsigned int cpu;
770 
771 	for_each_online_cpu(cpu) {
772 		if (cpu != this_cpu)
773 			uv_send_IPI_one(cpu, vector);
774 	}
775 }
776 
uv_send_IPI_all(int vector)777 static void uv_send_IPI_all(int vector)
778 {
779 	uv_send_IPI_mask(cpu_online_mask, vector);
780 }
781 
set_apic_id(unsigned int id)782 static u32 set_apic_id(unsigned int id)
783 {
784 	return id;
785 }
786 
uv_read_apic_id(void)787 static unsigned int uv_read_apic_id(void)
788 {
789 	return x2apic_get_apic_id(apic_read(APIC_ID));
790 }
791 
uv_phys_pkg_id(int initial_apicid,int index_msb)792 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
793 {
794 	return uv_read_apic_id() >> index_msb;
795 }
796 
uv_probe(void)797 static int uv_probe(void)
798 {
799 	return apic == &apic_x2apic_uv_x;
800 }
801 
802 static struct apic apic_x2apic_uv_x __ro_after_init = {
803 
804 	.name				= "UV large system",
805 	.probe				= uv_probe,
806 	.acpi_madt_oem_check		= uv_acpi_madt_oem_check,
807 
808 	.delivery_mode			= APIC_DELIVERY_MODE_FIXED,
809 	.dest_mode_logical		= false,
810 
811 	.disable_esr			= 0,
812 
813 	.cpu_present_to_apicid		= default_cpu_present_to_apicid,
814 	.phys_pkg_id			= uv_phys_pkg_id,
815 
816 	.max_apic_id			= UINT_MAX,
817 	.get_apic_id			= x2apic_get_apic_id,
818 	.set_apic_id			= set_apic_id,
819 
820 	.calc_dest_apicid		= apic_default_calc_apicid,
821 
822 	.send_IPI			= uv_send_IPI_one,
823 	.send_IPI_mask			= uv_send_IPI_mask,
824 	.send_IPI_mask_allbutself	= uv_send_IPI_mask_allbutself,
825 	.send_IPI_allbutself		= uv_send_IPI_allbutself,
826 	.send_IPI_all			= uv_send_IPI_all,
827 	.send_IPI_self			= x2apic_send_IPI_self,
828 
829 	.wakeup_secondary_cpu		= uv_wakeup_secondary,
830 
831 	.read				= native_apic_msr_read,
832 	.write				= native_apic_msr_write,
833 	.eoi				= native_apic_msr_eoi,
834 	.icr_read			= native_x2apic_icr_read,
835 	.icr_write			= native_x2apic_icr_write,
836 };
837 
838 #define	UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH	3
839 #define DEST_SHIFT UVXH_RH_GAM_ALIAS_0_REDIRECT_CONFIG_DEST_BASE_SHFT
840 
get_lowmem_redirect(unsigned long * base,unsigned long * size)841 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
842 {
843 	union uvh_rh_gam_alias_2_overlay_config_u alias;
844 	union uvh_rh_gam_alias_2_redirect_config_u redirect;
845 	unsigned long m_redirect;
846 	unsigned long m_overlay;
847 	int i;
848 
849 	for (i = 0; i < UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH; i++) {
850 		switch (i) {
851 		case 0:
852 			m_redirect = UVH_RH_GAM_ALIAS_0_REDIRECT_CONFIG;
853 			m_overlay  = UVH_RH_GAM_ALIAS_0_OVERLAY_CONFIG;
854 			break;
855 		case 1:
856 			m_redirect = UVH_RH_GAM_ALIAS_1_REDIRECT_CONFIG;
857 			m_overlay  = UVH_RH_GAM_ALIAS_1_OVERLAY_CONFIG;
858 			break;
859 		case 2:
860 			m_redirect = UVH_RH_GAM_ALIAS_2_REDIRECT_CONFIG;
861 			m_overlay  = UVH_RH_GAM_ALIAS_2_OVERLAY_CONFIG;
862 			break;
863 		}
864 		alias.v = uv_read_local_mmr(m_overlay);
865 		if (alias.s.enable && alias.s.base == 0) {
866 			*size = (1UL << alias.s.m_alias);
867 			redirect.v = uv_read_local_mmr(m_redirect);
868 			*base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
869 			return;
870 		}
871 	}
872 	*base = *size = 0;
873 }
874 
875 enum map_type {map_wb, map_uc};
876 static const char * const mt[] = { "WB", "UC" };
877 
map_high(char * id,unsigned long base,int pshift,int bshift,int max_pnode,enum map_type map_type)878 static __init void map_high(char *id, unsigned long base, int pshift, int bshift, int max_pnode, enum map_type map_type)
879 {
880 	unsigned long bytes, paddr;
881 
882 	paddr = base << pshift;
883 	bytes = (1UL << bshift) * (max_pnode + 1);
884 	if (!paddr) {
885 		pr_info("UV: Map %s_HI base address NULL\n", id);
886 		return;
887 	}
888 	if (map_type == map_uc)
889 		init_extra_mapping_uc(paddr, bytes);
890 	else
891 		init_extra_mapping_wb(paddr, bytes);
892 
893 	pr_info("UV: Map %s_HI 0x%lx - 0x%lx %s (%d segments)\n",
894 		id, paddr, paddr + bytes, mt[map_type], max_pnode + 1);
895 }
896 
map_gru_high(int max_pnode)897 static __init void map_gru_high(int max_pnode)
898 {
899 	union uvh_rh_gam_gru_overlay_config_u gru;
900 	unsigned long mask, base;
901 	int shift;
902 
903 	if (UVH_RH_GAM_GRU_OVERLAY_CONFIG) {
904 		gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG);
905 		shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT;
906 		mask = UVH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_MASK;
907 	} else if (UVH_RH10_GAM_GRU_OVERLAY_CONFIG) {
908 		gru.v = uv_read_local_mmr(UVH_RH10_GAM_GRU_OVERLAY_CONFIG);
909 		shift = UVH_RH10_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT;
910 		mask = UVH_RH10_GAM_GRU_OVERLAY_CONFIG_BASE_MASK;
911 	} else {
912 		pr_err("UV: GRU unavailable (no MMR)\n");
913 		return;
914 	}
915 
916 	if (!gru.s.enable) {
917 		pr_info("UV: GRU disabled (by BIOS)\n");
918 		return;
919 	}
920 
921 	base = (gru.v & mask) >> shift;
922 	map_high("GRU", base, shift, shift, max_pnode, map_wb);
923 	gru_start_paddr = ((u64)base << shift);
924 	gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
925 }
926 
map_mmr_high(int max_pnode)927 static __init void map_mmr_high(int max_pnode)
928 {
929 	unsigned long base;
930 	int shift;
931 	bool enable;
932 
933 	if (UVH_RH10_GAM_MMR_OVERLAY_CONFIG) {
934 		union uvh_rh10_gam_mmr_overlay_config_u mmr;
935 
936 		mmr.v = uv_read_local_mmr(UVH_RH10_GAM_MMR_OVERLAY_CONFIG);
937 		enable = mmr.s.enable;
938 		base = mmr.s.base;
939 		shift = UVH_RH10_GAM_MMR_OVERLAY_CONFIG_BASE_SHFT;
940 	} else if (UVH_RH_GAM_MMR_OVERLAY_CONFIG) {
941 		union uvh_rh_gam_mmr_overlay_config_u mmr;
942 
943 		mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG);
944 		enable = mmr.s.enable;
945 		base = mmr.s.base;
946 		shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_BASE_SHFT;
947 	} else {
948 		pr_err("UV:%s:RH_GAM_MMR_OVERLAY_CONFIG MMR undefined?\n",
949 			__func__);
950 		return;
951 	}
952 
953 	if (enable)
954 		map_high("MMR", base, shift, shift, max_pnode, map_uc);
955 	else
956 		pr_info("UV: MMR disabled\n");
957 }
958 
959 /* Arch specific ENUM cases */
960 enum mmioh_arch {
961 	UV2_MMIOH = -1,
962 	UVY_MMIOH0, UVY_MMIOH1,
963 	UVX_MMIOH0, UVX_MMIOH1,
964 };
965 
966 /* Calculate and Map MMIOH Regions */
calc_mmioh_map(enum mmioh_arch index,int min_pnode,int max_pnode,int shift,unsigned long base,int m_io,int n_io)967 static void __init calc_mmioh_map(enum mmioh_arch index,
968 	int min_pnode, int max_pnode,
969 	int shift, unsigned long base, int m_io, int n_io)
970 {
971 	unsigned long mmr, nasid_mask;
972 	int nasid, min_nasid, max_nasid, lnasid, mapped;
973 	int i, fi, li, n, max_io;
974 	char id[8];
975 
976 	/* One (UV2) mapping */
977 	if (index == UV2_MMIOH) {
978 		strscpy(id, "MMIOH", sizeof(id));
979 		max_io = max_pnode;
980 		mapped = 0;
981 		goto map_exit;
982 	}
983 
984 	/* small and large MMIOH mappings */
985 	switch (index) {
986 	case UVY_MMIOH0:
987 		mmr = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG0;
988 		nasid_mask = UVYH_RH10_GAM_MMIOH_REDIRECT_CONFIG0_NASID_MASK;
989 		n = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG0_DEPTH;
990 		min_nasid = min_pnode;
991 		max_nasid = max_pnode;
992 		mapped = 1;
993 		break;
994 	case UVY_MMIOH1:
995 		mmr = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG1;
996 		nasid_mask = UVYH_RH10_GAM_MMIOH_REDIRECT_CONFIG1_NASID_MASK;
997 		n = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG1_DEPTH;
998 		min_nasid = min_pnode;
999 		max_nasid = max_pnode;
1000 		mapped = 1;
1001 		break;
1002 	case UVX_MMIOH0:
1003 		mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0;
1004 		nasid_mask = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_NASID_MASK;
1005 		n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_DEPTH;
1006 		min_nasid = min_pnode * 2;
1007 		max_nasid = max_pnode * 2;
1008 		mapped = 1;
1009 		break;
1010 	case UVX_MMIOH1:
1011 		mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1;
1012 		nasid_mask = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_NASID_MASK;
1013 		n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_DEPTH;
1014 		min_nasid = min_pnode * 2;
1015 		max_nasid = max_pnode * 2;
1016 		mapped = 1;
1017 		break;
1018 	default:
1019 		pr_err("UV:%s:Invalid mapping type:%d\n", __func__, index);
1020 		return;
1021 	}
1022 
1023 	/* enum values chosen so (index mod 2) is MMIOH 0/1 (low/high) */
1024 	snprintf(id, sizeof(id), "MMIOH%d", index%2);
1025 
1026 	max_io = lnasid = fi = li = -1;
1027 	for (i = 0; i < n; i++) {
1028 		unsigned long m_redirect = mmr + i * 8;
1029 		unsigned long redirect = uv_read_local_mmr(m_redirect);
1030 
1031 		nasid = redirect & nasid_mask;
1032 		if (i == 0)
1033 			pr_info("UV: %s redirect base 0x%lx(@0x%lx) 0x%04x\n",
1034 				id, redirect, m_redirect, nasid);
1035 
1036 		/* Invalid NASID check */
1037 		if (nasid < min_nasid || max_nasid < nasid) {
1038 			/* Not an error: unused table entries get "poison" values */
1039 			pr_debug("UV:%s:Invalid NASID(%x):%x (range:%x..%x)\n",
1040 			       __func__, index, nasid, min_nasid, max_nasid);
1041 			nasid = -1;
1042 		}
1043 
1044 		if (nasid == lnasid) {
1045 			li = i;
1046 			/* Last entry check: */
1047 			if (i != n-1)
1048 				continue;
1049 		}
1050 
1051 		/* Check if we have a cached (or last) redirect to print: */
1052 		if (lnasid != -1 || (i == n-1 && nasid != -1))  {
1053 			unsigned long addr1, addr2;
1054 			int f, l;
1055 
1056 			if (lnasid == -1) {
1057 				f = l = i;
1058 				lnasid = nasid;
1059 			} else {
1060 				f = fi;
1061 				l = li;
1062 			}
1063 			addr1 = (base << shift) + f * (1ULL << m_io);
1064 			addr2 = (base << shift) + (l + 1) * (1ULL << m_io);
1065 			pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n",
1066 				id, fi, li, lnasid, addr1, addr2);
1067 			if (max_io < l)
1068 				max_io = l;
1069 		}
1070 		fi = li = i;
1071 		lnasid = nasid;
1072 	}
1073 
1074 map_exit:
1075 	pr_info("UV: %s base:0x%lx shift:%d m_io:%d max_io:%d max_pnode:0x%x\n",
1076 		id, base, shift, m_io, max_io, max_pnode);
1077 
1078 	if (max_io >= 0 && !mapped)
1079 		map_high(id, base, shift, m_io, max_io, map_uc);
1080 }
1081 
map_mmioh_high(int min_pnode,int max_pnode)1082 static __init void map_mmioh_high(int min_pnode, int max_pnode)
1083 {
1084 	/* UVY flavor */
1085 	if (UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0) {
1086 		union uvh_rh10_gam_mmioh_overlay_config0_u mmioh0;
1087 		union uvh_rh10_gam_mmioh_overlay_config1_u mmioh1;
1088 
1089 		mmioh0.v = uv_read_local_mmr(UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0);
1090 		if (unlikely(mmioh0.s.enable == 0))
1091 			pr_info("UV: MMIOH0 disabled\n");
1092 		else
1093 			calc_mmioh_map(UVY_MMIOH0, min_pnode, max_pnode,
1094 				UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT,
1095 				mmioh0.s.base, mmioh0.s.m_io, mmioh0.s.n_io);
1096 
1097 		mmioh1.v = uv_read_local_mmr(UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1);
1098 		if (unlikely(mmioh1.s.enable == 0))
1099 			pr_info("UV: MMIOH1 disabled\n");
1100 		else
1101 			calc_mmioh_map(UVY_MMIOH1, min_pnode, max_pnode,
1102 				UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT,
1103 				mmioh1.s.base, mmioh1.s.m_io, mmioh1.s.n_io);
1104 		return;
1105 	}
1106 	/* UVX flavor */
1107 	if (UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0) {
1108 		union uvh_rh_gam_mmioh_overlay_config0_u mmioh0;
1109 		union uvh_rh_gam_mmioh_overlay_config1_u mmioh1;
1110 
1111 		mmioh0.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0);
1112 		if (unlikely(mmioh0.s.enable == 0))
1113 			pr_info("UV: MMIOH0 disabled\n");
1114 		else {
1115 			unsigned long base = uvxy_field(mmioh0, base, 0);
1116 			int m_io = uvxy_field(mmioh0, m_io, 0);
1117 			int n_io = uvxy_field(mmioh0, n_io, 0);
1118 
1119 			calc_mmioh_map(UVX_MMIOH0, min_pnode, max_pnode,
1120 				UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT,
1121 				base, m_io, n_io);
1122 		}
1123 
1124 		mmioh1.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1);
1125 		if (unlikely(mmioh1.s.enable == 0))
1126 			pr_info("UV: MMIOH1 disabled\n");
1127 		else {
1128 			unsigned long base = uvxy_field(mmioh1, base, 0);
1129 			int m_io = uvxy_field(mmioh1, m_io, 0);
1130 			int n_io = uvxy_field(mmioh1, n_io, 0);
1131 
1132 			calc_mmioh_map(UVX_MMIOH1, min_pnode, max_pnode,
1133 				UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT,
1134 				base, m_io, n_io);
1135 		}
1136 		return;
1137 	}
1138 
1139 	/* UV2 flavor */
1140 	if (UVH_RH_GAM_MMIOH_OVERLAY_CONFIG) {
1141 		union uvh_rh_gam_mmioh_overlay_config_u mmioh;
1142 
1143 		mmioh.v	= uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG);
1144 		if (unlikely(mmioh.s2.enable == 0))
1145 			pr_info("UV: MMIOH disabled\n");
1146 		else
1147 			calc_mmioh_map(UV2_MMIOH, min_pnode, max_pnode,
1148 				UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_BASE_SHFT,
1149 				mmioh.s2.base, mmioh.s2.m_io, mmioh.s2.n_io);
1150 		return;
1151 	}
1152 }
1153 
map_low_mmrs(void)1154 static __init void map_low_mmrs(void)
1155 {
1156 	if (UV_GLOBAL_MMR32_BASE)
1157 		init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
1158 
1159 	if (UV_LOCAL_MMR_BASE)
1160 		init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
1161 }
1162 
uv_rtc_init(void)1163 static __init void uv_rtc_init(void)
1164 {
1165 	long status;
1166 	u64 ticks_per_sec;
1167 
1168 	status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec);
1169 
1170 	if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
1171 		pr_warn("UV: unable to determine platform RTC clock frequency, guessing.\n");
1172 
1173 		/* BIOS gives wrong value for clock frequency, so guess: */
1174 		sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
1175 	} else {
1176 		sn_rtc_cycles_per_second = ticks_per_sec;
1177 	}
1178 }
1179 
1180 /* Direct Legacy VGA I/O traffic to designated IOH */
uv_set_vga_state(struct pci_dev * pdev,bool decode,unsigned int command_bits,u32 flags)1181 static int uv_set_vga_state(struct pci_dev *pdev, bool decode, unsigned int command_bits, u32 flags)
1182 {
1183 	int domain, bus, rc;
1184 
1185 	if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
1186 		return 0;
1187 
1188 	if ((command_bits & PCI_COMMAND_IO) == 0)
1189 		return 0;
1190 
1191 	domain = pci_domain_nr(pdev->bus);
1192 	bus = pdev->bus->number;
1193 
1194 	rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
1195 
1196 	return rc;
1197 }
1198 
1199 /*
1200  * Called on each CPU to initialize the per_cpu UV data area.
1201  * FIXME: hotplug not supported yet
1202  */
uv_cpu_init(void)1203 void uv_cpu_init(void)
1204 {
1205 	/* CPU 0 initialization will be done via uv_system_init. */
1206 	if (smp_processor_id() == 0)
1207 		return;
1208 
1209 	uv_hub_info->nr_online_cpus++;
1210 }
1211 
1212 struct mn {
1213 	unsigned char	m_val;
1214 	unsigned char	n_val;
1215 	unsigned char	m_shift;
1216 	unsigned char	n_lshift;
1217 };
1218 
1219 /* Initialize caller's MN struct and fill in values */
get_mn(struct mn * mnp)1220 static void get_mn(struct mn *mnp)
1221 {
1222 	memset(mnp, 0, sizeof(*mnp));
1223 	mnp->n_val	= uv_cpuid.n_skt;
1224 	if (is_uv(UV4|UVY)) {
1225 		mnp->m_val	= 0;
1226 		mnp->n_lshift	= 0;
1227 	} else if (is_uv3_hub()) {
1228 		union uvyh_gr0_gam_gr_config_u m_gr_config;
1229 
1230 		mnp->m_val	= uv_cpuid.m_skt;
1231 		m_gr_config.v	= uv_read_local_mmr(UVH_GR0_GAM_GR_CONFIG);
1232 		mnp->n_lshift	= m_gr_config.s3.m_skt;
1233 	} else if (is_uv2_hub()) {
1234 		mnp->m_val	= uv_cpuid.m_skt;
1235 		mnp->n_lshift	= mnp->m_val == 40 ? 40 : 39;
1236 	}
1237 	mnp->m_shift = mnp->m_val ? 64 - mnp->m_val : 0;
1238 }
1239 
uv_init_hub_info(struct uv_hub_info_s * hi)1240 static void __init uv_init_hub_info(struct uv_hub_info_s *hi)
1241 {
1242 	struct mn mn;
1243 
1244 	get_mn(&mn);
1245 	hi->gpa_mask = mn.m_val ?
1246 		(1UL << (mn.m_val + mn.n_val)) - 1 :
1247 		(1UL << uv_cpuid.gpa_shift) - 1;
1248 
1249 	hi->m_val		= mn.m_val;
1250 	hi->n_val		= mn.n_val;
1251 	hi->m_shift		= mn.m_shift;
1252 	hi->n_lshift		= mn.n_lshift ? mn.n_lshift : 0;
1253 	hi->hub_revision	= uv_hub_info->hub_revision;
1254 	hi->hub_type		= uv_hub_info->hub_type;
1255 	hi->pnode_mask		= uv_cpuid.pnode_mask;
1256 	hi->nasid_shift		= uv_cpuid.nasid_shift;
1257 	hi->min_pnode		= _min_pnode;
1258 	hi->min_socket		= _min_socket;
1259 	hi->node_to_socket	= _node_to_socket;
1260 	hi->pnode_to_socket	= _pnode_to_socket;
1261 	hi->socket_to_node	= _socket_to_node;
1262 	hi->socket_to_pnode	= _socket_to_pnode;
1263 	hi->gr_table_len	= _gr_table_len;
1264 	hi->gr_table		= _gr_table;
1265 
1266 	uv_cpuid.gnode_shift	= max_t(unsigned int, uv_cpuid.gnode_shift, mn.n_val);
1267 	hi->gnode_extra		= (uv_node_id & ~((1 << uv_cpuid.gnode_shift) - 1)) >> 1;
1268 	if (mn.m_val)
1269 		hi->gnode_upper	= (u64)hi->gnode_extra << mn.m_val;
1270 
1271 	if (uv_gp_table) {
1272 		hi->global_mmr_base	= uv_gp_table->mmr_base;
1273 		hi->global_mmr_shift	= uv_gp_table->mmr_shift;
1274 		hi->global_gru_base	= uv_gp_table->gru_base;
1275 		hi->global_gru_shift	= uv_gp_table->gru_shift;
1276 		hi->gpa_shift		= uv_gp_table->gpa_shift;
1277 		hi->gpa_mask		= (1UL << hi->gpa_shift) - 1;
1278 	} else {
1279 		hi->global_mmr_base	=
1280 			uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG) &
1281 			~UV_MMR_ENABLE;
1282 		hi->global_mmr_shift	= _UV_GLOBAL_MMR64_PNODE_SHIFT;
1283 	}
1284 
1285 	get_lowmem_redirect(&hi->lowmem_remap_base, &hi->lowmem_remap_top);
1286 
1287 	hi->apic_pnode_shift = uv_cpuid.socketid_shift;
1288 
1289 	/* Show system specific info: */
1290 	pr_info("UV: N:%d M:%d m_shift:%d n_lshift:%d\n", hi->n_val, hi->m_val, hi->m_shift, hi->n_lshift);
1291 	pr_info("UV: gpa_mask/shift:0x%lx/%d pnode_mask:0x%x apic_pns:%d\n", hi->gpa_mask, hi->gpa_shift, hi->pnode_mask, hi->apic_pnode_shift);
1292 	pr_info("UV: mmr_base/shift:0x%lx/%ld\n", hi->global_mmr_base, hi->global_mmr_shift);
1293 	if (hi->global_gru_base)
1294 		pr_info("UV: gru_base/shift:0x%lx/%ld\n",
1295 			hi->global_gru_base, hi->global_gru_shift);
1296 
1297 	pr_info("UV: gnode_upper:0x%lx gnode_extra:0x%x\n", hi->gnode_upper, hi->gnode_extra);
1298 }
1299 
decode_gam_params(unsigned long ptr)1300 static void __init decode_gam_params(unsigned long ptr)
1301 {
1302 	uv_gp_table = (struct uv_gam_parameters *)ptr;
1303 
1304 	pr_info("UV: GAM Params...\n");
1305 	pr_info("UV: mmr_base/shift:0x%llx/%d gru_base/shift:0x%llx/%d gpa_shift:%d\n",
1306 		uv_gp_table->mmr_base, uv_gp_table->mmr_shift,
1307 		uv_gp_table->gru_base, uv_gp_table->gru_shift,
1308 		uv_gp_table->gpa_shift);
1309 }
1310 
decode_gam_rng_tbl(unsigned long ptr)1311 static void __init decode_gam_rng_tbl(unsigned long ptr)
1312 {
1313 	struct uv_gam_range_entry *gre = (struct uv_gam_range_entry *)ptr;
1314 	unsigned long lgre = 0, gend = 0;
1315 	int index = 0;
1316 	int sock_min = INT_MAX, pnode_min = INT_MAX;
1317 	int sock_max = -1, pnode_max = -1;
1318 
1319 	uv_gre_table = gre;
1320 	for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1321 		unsigned long size = ((unsigned long)(gre->limit - lgre)
1322 					<< UV_GAM_RANGE_SHFT);
1323 		int order = 0;
1324 		char suffix[] = " KMGTPE";
1325 		int flag = ' ';
1326 
1327 		while (size > 9999 && order < sizeof(suffix)) {
1328 			size /= 1024;
1329 			order++;
1330 		}
1331 
1332 		/* adjust max block size to current range start */
1333 		if (gre->type == 1 || gre->type == 2)
1334 			if (adj_blksize(lgre))
1335 				flag = '*';
1336 
1337 		if (!index) {
1338 			pr_info("UV: GAM Range Table...\n");
1339 			pr_info("UV:  # %20s %14s %6s %4s %5s %3s %2s\n", "Range", "", "Size", "Type", "NASID", "SID", "PN");
1340 		}
1341 		pr_info("UV: %2d: 0x%014lx-0x%014lx%c %5lu%c %3d   %04x  %02x %02x\n",
1342 			index++,
1343 			(unsigned long)lgre << UV_GAM_RANGE_SHFT,
1344 			(unsigned long)gre->limit << UV_GAM_RANGE_SHFT,
1345 			flag, size, suffix[order],
1346 			gre->type, gre->nasid, gre->sockid, gre->pnode);
1347 
1348 		if (gre->type == UV_GAM_RANGE_TYPE_HOLE)
1349 			gend = (unsigned long)gre->limit << UV_GAM_RANGE_SHFT;
1350 
1351 		/* update to next range start */
1352 		lgre = gre->limit;
1353 		if (sock_min > gre->sockid)
1354 			sock_min = gre->sockid;
1355 		if (sock_max < gre->sockid)
1356 			sock_max = gre->sockid;
1357 		if (pnode_min > gre->pnode)
1358 			pnode_min = gre->pnode;
1359 		if (pnode_max < gre->pnode)
1360 			pnode_max = gre->pnode;
1361 	}
1362 	_min_socket	= sock_min;
1363 	_max_socket	= sock_max;
1364 	_min_pnode	= pnode_min;
1365 	_max_pnode	= pnode_max;
1366 	_gr_table_len	= index;
1367 
1368 	pr_info("UV: GRT: %d entries, sockets(min:%x,max:%x), pnodes(min:%x,max:%x), gap_end(%d)\n",
1369 	  index, _min_socket, _max_socket, _min_pnode, _max_pnode, fls64(gend));
1370 }
1371 
1372 /* Walk through UVsystab decoding the fields */
decode_uv_systab(void)1373 static int __init decode_uv_systab(void)
1374 {
1375 	struct uv_systab *st;
1376 	int i;
1377 
1378 	/* Get mapped UVsystab pointer */
1379 	st = uv_systab;
1380 
1381 	/* If UVsystab is version 1, there is no extended UVsystab */
1382 	if (st && st->revision == UV_SYSTAB_VERSION_1)
1383 		return 0;
1384 
1385 	if ((!st) || (st->revision < UV_SYSTAB_VERSION_UV4_LATEST)) {
1386 		int rev = st ? st->revision : 0;
1387 
1388 		pr_err("UV: BIOS UVsystab mismatch, (%x < %x)\n",
1389 			rev, UV_SYSTAB_VERSION_UV4_LATEST);
1390 		pr_err("UV: Does not support UV, switch to non-UV x86_64\n");
1391 		uv_system_type = UV_NONE;
1392 
1393 		return -EINVAL;
1394 	}
1395 
1396 	for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) {
1397 		unsigned long ptr = st->entry[i].offset;
1398 
1399 		if (!ptr)
1400 			continue;
1401 
1402 		/* point to payload */
1403 		ptr += (unsigned long)st;
1404 
1405 		switch (st->entry[i].type) {
1406 		case UV_SYSTAB_TYPE_GAM_PARAMS:
1407 			decode_gam_params(ptr);
1408 			break;
1409 
1410 		case UV_SYSTAB_TYPE_GAM_RNG_TBL:
1411 			decode_gam_rng_tbl(ptr);
1412 			break;
1413 
1414 		case UV_SYSTAB_TYPE_ARCH_TYPE:
1415 			/* already processed in early startup */
1416 			break;
1417 
1418 		default:
1419 			pr_err("UV:%s:Unrecognized UV_SYSTAB_TYPE:%d, skipped\n",
1420 				__func__, st->entry[i].type);
1421 			break;
1422 		}
1423 	}
1424 	return 0;
1425 }
1426 
1427 /*
1428  * Given a bitmask 'bits' representing presnt blades, numbered
1429  * starting at 'base', masking off unused high bits of blade number
1430  * with 'mask', update the minimum and maximum blade numbers that we
1431  * have found.  (Masking with 'mask' necessary because of BIOS
1432  * treatment of system partitioning when creating this table we are
1433  * interpreting.)
1434  */
blade_update_min_max(unsigned long bits,int base,int mask,int * min,int * max)1435 static inline void blade_update_min_max(unsigned long bits, int base, int mask, int *min, int *max)
1436 {
1437 	int first, last;
1438 
1439 	if (!bits)
1440 		return;
1441 	first = (base + __ffs(bits)) & mask;
1442 	last =  (base + __fls(bits)) & mask;
1443 
1444 	if (*min > first)
1445 		*min = first;
1446 	if (*max < last)
1447 		*max = last;
1448 }
1449 
1450 /* Set up physical blade translations from UVH_NODE_PRESENT_TABLE */
boot_init_possible_blades(struct uv_hub_info_s * hub_info)1451 static __init void boot_init_possible_blades(struct uv_hub_info_s *hub_info)
1452 {
1453 	unsigned long np;
1454 	int i, uv_pb = 0;
1455 	int sock_min = INT_MAX, sock_max = -1, s_mask;
1456 
1457 	s_mask = (1 << uv_cpuid.n_skt) - 1;
1458 
1459 	if (UVH_NODE_PRESENT_TABLE) {
1460 		pr_info("UV: NODE_PRESENT_DEPTH = %d\n",
1461 			UVH_NODE_PRESENT_TABLE_DEPTH);
1462 		for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
1463 			np = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
1464 			pr_info("UV: NODE_PRESENT(%d) = 0x%016lx\n", i, np);
1465 			blade_update_min_max(np, i * 64, s_mask, &sock_min, &sock_max);
1466 		}
1467 	}
1468 	if (UVH_NODE_PRESENT_0) {
1469 		np = uv_read_local_mmr(UVH_NODE_PRESENT_0);
1470 		pr_info("UV: NODE_PRESENT_0 = 0x%016lx\n", np);
1471 		blade_update_min_max(np, 0, s_mask, &sock_min, &sock_max);
1472 	}
1473 	if (UVH_NODE_PRESENT_1) {
1474 		np = uv_read_local_mmr(UVH_NODE_PRESENT_1);
1475 		pr_info("UV: NODE_PRESENT_1 = 0x%016lx\n", np);
1476 		blade_update_min_max(np, 64, s_mask, &sock_min, &sock_max);
1477 	}
1478 
1479 	/* Only update if we actually found some bits indicating blades present */
1480 	if (sock_max >= sock_min) {
1481 		_min_socket = sock_min;
1482 		_max_socket = sock_max;
1483 		uv_pb = sock_max - sock_min + 1;
1484 	}
1485 	if (uv_possible_blades != uv_pb)
1486 		uv_possible_blades = uv_pb;
1487 
1488 	pr_info("UV: number nodes/possible blades %d (%d - %d)\n",
1489 		uv_pb, sock_min, sock_max);
1490 }
1491 
alloc_conv_table(int num_elem,unsigned short ** table)1492 static int __init alloc_conv_table(int num_elem, unsigned short **table)
1493 {
1494 	int i;
1495 	size_t bytes;
1496 
1497 	bytes = num_elem * sizeof(*table[0]);
1498 	*table = kmalloc(bytes, GFP_KERNEL);
1499 	if (WARN_ON_ONCE(!*table))
1500 		return -ENOMEM;
1501 	for (i = 0; i < num_elem; i++)
1502 		((unsigned short *)*table)[i] = SOCK_EMPTY;
1503 	return 0;
1504 }
1505 
1506 /* Remove conversion table if it's 1:1 */
1507 #define FREE_1_TO_1_TABLE(tbl, min, max, max2) free_1_to_1_table(&tbl, #tbl, min, max, max2)
1508 
free_1_to_1_table(unsigned short ** tp,char * tname,int min,int max,int max2)1509 static void __init free_1_to_1_table(unsigned short **tp, char *tname, int min, int max, int max2)
1510 {
1511 	int i;
1512 	unsigned short *table = *tp;
1513 
1514 	if (table == NULL)
1515 		return;
1516 	if (max != max2)
1517 		return;
1518 	for (i = 0; i < max; i++) {
1519 		if (i != table[i])
1520 			return;
1521 	}
1522 	kfree(table);
1523 	*tp = NULL;
1524 	pr_info("UV: %s is 1:1, conversion table removed\n", tname);
1525 }
1526 
1527 /*
1528  * Build Socket Tables
1529  * If the number of nodes is >1 per socket, socket to node table will
1530  * contain lowest node number on that socket.
1531  */
build_socket_tables(void)1532 static void __init build_socket_tables(void)
1533 {
1534 	struct uv_gam_range_entry *gre = uv_gre_table;
1535 	int nums, numn, nump;
1536 	int i, lnid, apicid;
1537 	int minsock = _min_socket;
1538 	int maxsock = _max_socket;
1539 	int minpnode = _min_pnode;
1540 	int maxpnode = _max_pnode;
1541 
1542 	if (!gre) {
1543 		if (is_uv2_hub() || is_uv3_hub()) {
1544 			pr_info("UV: No UVsystab socket table, ignoring\n");
1545 			return;
1546 		}
1547 		pr_err("UV: Error: UVsystab address translations not available!\n");
1548 		WARN_ON_ONCE(!gre);
1549 		return;
1550 	}
1551 
1552 	numn = num_possible_nodes();
1553 	nump = maxpnode - minpnode + 1;
1554 	nums = maxsock - minsock + 1;
1555 
1556 	/* Allocate and clear tables */
1557 	if ((alloc_conv_table(nump, &_pnode_to_socket) < 0)
1558 	    || (alloc_conv_table(nums, &_socket_to_pnode) < 0)
1559 	    || (alloc_conv_table(numn, &_node_to_socket) < 0)
1560 	    || (alloc_conv_table(nums, &_socket_to_node) < 0)) {
1561 		kfree(_pnode_to_socket);
1562 		kfree(_socket_to_pnode);
1563 		kfree(_node_to_socket);
1564 		return;
1565 	}
1566 
1567 	/* Fill in pnode/node/addr conversion list values: */
1568 	for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1569 		if (gre->type == UV_GAM_RANGE_TYPE_HOLE)
1570 			continue;
1571 		i = gre->sockid - minsock;
1572 		if (_socket_to_pnode[i] == SOCK_EMPTY)
1573 			_socket_to_pnode[i] = gre->pnode;
1574 
1575 		i = gre->pnode - minpnode;
1576 		if (_pnode_to_socket[i] == SOCK_EMPTY)
1577 			_pnode_to_socket[i] = gre->sockid;
1578 
1579 		pr_info("UV: sid:%02x type:%d nasid:%04x pn:%02x pn2s:%2x\n",
1580 			gre->sockid, gre->type, gre->nasid,
1581 			_socket_to_pnode[gre->sockid - minsock],
1582 			_pnode_to_socket[gre->pnode - minpnode]);
1583 	}
1584 
1585 	/* Set socket -> node values: */
1586 	lnid = NUMA_NO_NODE;
1587 	for (apicid = 0; apicid < ARRAY_SIZE(__apicid_to_node); apicid++) {
1588 		int nid = __apicid_to_node[apicid];
1589 		int sockid;
1590 
1591 		if ((nid == NUMA_NO_NODE) || (lnid == nid))
1592 			continue;
1593 		lnid = nid;
1594 
1595 		sockid = apicid >> uv_cpuid.socketid_shift;
1596 
1597 		if (_socket_to_node[sockid - minsock] == SOCK_EMPTY)
1598 			_socket_to_node[sockid - minsock] = nid;
1599 
1600 		if (_node_to_socket[nid] == SOCK_EMPTY)
1601 			_node_to_socket[nid] = sockid;
1602 
1603 		pr_info("UV: sid:%02x: apicid:%04x socket:%02d node:%03x s2n:%03x\n",
1604 			sockid,
1605 			apicid,
1606 			_node_to_socket[nid],
1607 			nid,
1608 			_socket_to_node[sockid - minsock]);
1609 	}
1610 
1611 	/*
1612 	 * If e.g. socket id == pnode for all pnodes,
1613 	 *   system runs faster by removing corresponding conversion table.
1614 	 */
1615 	FREE_1_TO_1_TABLE(_socket_to_node, _min_socket, nums, numn);
1616 	FREE_1_TO_1_TABLE(_node_to_socket, _min_socket, nums, numn);
1617 	FREE_1_TO_1_TABLE(_socket_to_pnode, _min_pnode, nums, nump);
1618 	FREE_1_TO_1_TABLE(_pnode_to_socket, _min_pnode, nums, nump);
1619 }
1620 
1621 /* Check which reboot to use */
check_efi_reboot(void)1622 static void check_efi_reboot(void)
1623 {
1624 	/* If EFI reboot not available, use ACPI reboot */
1625 	if (!efi_enabled(EFI_BOOT))
1626 		reboot_type = BOOT_ACPI;
1627 }
1628 
1629 /*
1630  * User proc fs file handling now deprecated.
1631  * Recommend using /sys/firmware/sgi_uv/... instead.
1632  */
proc_hubbed_show(struct seq_file * file,void * data)1633 static int __maybe_unused proc_hubbed_show(struct seq_file *file, void *data)
1634 {
1635 	pr_notice_once("%s: using deprecated /proc/sgi_uv/hubbed, use /sys/firmware/sgi_uv/hub_type\n",
1636 		       current->comm);
1637 	seq_printf(file, "0x%x\n", uv_hubbed_system);
1638 	return 0;
1639 }
1640 
proc_hubless_show(struct seq_file * file,void * data)1641 static int __maybe_unused proc_hubless_show(struct seq_file *file, void *data)
1642 {
1643 	pr_notice_once("%s: using deprecated /proc/sgi_uv/hubless, use /sys/firmware/sgi_uv/hubless\n",
1644 		       current->comm);
1645 	seq_printf(file, "0x%x\n", uv_hubless_system);
1646 	return 0;
1647 }
1648 
proc_archtype_show(struct seq_file * file,void * data)1649 static int __maybe_unused proc_archtype_show(struct seq_file *file, void *data)
1650 {
1651 	pr_notice_once("%s: using deprecated /proc/sgi_uv/archtype, use /sys/firmware/sgi_uv/archtype\n",
1652 		       current->comm);
1653 	seq_printf(file, "%s/%s\n", uv_archtype, oem_table_id);
1654 	return 0;
1655 }
1656 
uv_setup_proc_files(int hubless)1657 static __init void uv_setup_proc_files(int hubless)
1658 {
1659 	struct proc_dir_entry *pde;
1660 
1661 	pde = proc_mkdir(UV_PROC_NODE, NULL);
1662 	proc_create_single("archtype", 0, pde, proc_archtype_show);
1663 	if (hubless)
1664 		proc_create_single("hubless", 0, pde, proc_hubless_show);
1665 	else
1666 		proc_create_single("hubbed", 0, pde, proc_hubbed_show);
1667 }
1668 
1669 /* Initialize UV hubless systems */
uv_system_init_hubless(void)1670 static __init int uv_system_init_hubless(void)
1671 {
1672 	int rc;
1673 
1674 	/* Setup PCH NMI handler */
1675 	uv_nmi_setup_hubless();
1676 
1677 	/* Init kernel/BIOS interface */
1678 	rc = uv_bios_init();
1679 	if (rc < 0)
1680 		return rc;
1681 
1682 	/* Process UVsystab */
1683 	rc = decode_uv_systab();
1684 	if (rc < 0)
1685 		return rc;
1686 
1687 	/* Set section block size for current node memory */
1688 	set_block_size();
1689 
1690 	/* Create user access node */
1691 	if (rc >= 0)
1692 		uv_setup_proc_files(1);
1693 
1694 	check_efi_reboot();
1695 
1696 	return rc;
1697 }
1698 
uv_system_init_hub(void)1699 static void __init uv_system_init_hub(void)
1700 {
1701 	struct uv_hub_info_s hub_info = {0};
1702 	int bytes, cpu, nodeid, bid;
1703 	unsigned short min_pnode = USHRT_MAX, max_pnode = 0;
1704 	char *hub = is_uv5_hub() ? "UV500" :
1705 		    is_uv4_hub() ? "UV400" :
1706 		    is_uv3_hub() ? "UV300" :
1707 		    is_uv2_hub() ? "UV2000/3000" : NULL;
1708 	struct uv_hub_info_s **uv_hub_info_list_blade;
1709 
1710 	if (!hub) {
1711 		pr_err("UV: Unknown/unsupported UV hub\n");
1712 		return;
1713 	}
1714 	pr_info("UV: Found %s hub\n", hub);
1715 
1716 	map_low_mmrs();
1717 
1718 	/* Get uv_systab for decoding, setup UV BIOS calls */
1719 	uv_bios_init();
1720 
1721 	/* If there's an UVsystab problem then abort UV init: */
1722 	if (decode_uv_systab() < 0) {
1723 		pr_err("UV: Mangled UVsystab format\n");
1724 		return;
1725 	}
1726 
1727 	build_socket_tables();
1728 	build_uv_gr_table();
1729 	set_block_size();
1730 	uv_init_hub_info(&hub_info);
1731 	/* If UV2 or UV3 may need to get # blades from HW */
1732 	if (is_uv(UV2|UV3) && !uv_gre_table)
1733 		boot_init_possible_blades(&hub_info);
1734 	else
1735 		/* min/max sockets set in decode_gam_rng_tbl */
1736 		uv_possible_blades = (_max_socket - _min_socket) + 1;
1737 
1738 	/* uv_num_possible_blades() is really the hub count: */
1739 	pr_info("UV: Found %d hubs, %d nodes, %d CPUs\n", uv_num_possible_blades(), num_possible_nodes(), num_possible_cpus());
1740 
1741 	uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id, &sn_region_size, &system_serial_number);
1742 	hub_info.coherency_domain_number = sn_coherency_id;
1743 	uv_rtc_init();
1744 
1745 	/*
1746 	 * __uv_hub_info_list[] is indexed by node, but there is only
1747 	 * one hub_info structure per blade.  First, allocate one
1748 	 * structure per blade.  Further down we create a per-node
1749 	 * table (__uv_hub_info_list[]) pointing to hub_info
1750 	 * structures for the correct blade.
1751 	 */
1752 
1753 	bytes = sizeof(void *) * uv_num_possible_blades();
1754 	uv_hub_info_list_blade = kzalloc(bytes, GFP_KERNEL);
1755 	if (WARN_ON_ONCE(!uv_hub_info_list_blade))
1756 		return;
1757 
1758 	bytes = sizeof(struct uv_hub_info_s);
1759 	for_each_possible_blade(bid) {
1760 		struct uv_hub_info_s *new_hub;
1761 
1762 		/* Allocate & fill new per hub info list */
1763 		new_hub = (bid == 0) ?  &uv_hub_info_node0
1764 			: kzalloc_node(bytes, GFP_KERNEL, uv_blade_to_node(bid));
1765 		if (WARN_ON_ONCE(!new_hub)) {
1766 			/* do not kfree() bid 0, which is statically allocated */
1767 			while (--bid > 0)
1768 				kfree(uv_hub_info_list_blade[bid]);
1769 			kfree(uv_hub_info_list_blade);
1770 			return;
1771 		}
1772 
1773 		uv_hub_info_list_blade[bid] = new_hub;
1774 		*new_hub = hub_info;
1775 
1776 		/* Use information from GAM table if available: */
1777 		if (uv_gre_table)
1778 			new_hub->pnode = uv_blade_to_pnode(bid);
1779 		else /* Or fill in during CPU loop: */
1780 			new_hub->pnode = 0xffff;
1781 
1782 		new_hub->numa_blade_id = bid;
1783 		new_hub->memory_nid = NUMA_NO_NODE;
1784 		new_hub->nr_possible_cpus = 0;
1785 		new_hub->nr_online_cpus = 0;
1786 	}
1787 
1788 	/*
1789 	 * Now populate __uv_hub_info_list[] for each node with the
1790 	 * pointer to the struct for the blade it resides on.
1791 	 */
1792 
1793 	bytes = sizeof(void *) * num_possible_nodes();
1794 	__uv_hub_info_list = kzalloc(bytes, GFP_KERNEL);
1795 	if (WARN_ON_ONCE(!__uv_hub_info_list)) {
1796 		for_each_possible_blade(bid)
1797 			/* bid 0 is statically allocated */
1798 			if (bid != 0)
1799 				kfree(uv_hub_info_list_blade[bid]);
1800 		kfree(uv_hub_info_list_blade);
1801 		return;
1802 	}
1803 
1804 	for_each_node(nodeid)
1805 		__uv_hub_info_list[nodeid] = uv_hub_info_list_blade[uv_node_to_blade_id(nodeid)];
1806 
1807 	/* Initialize per CPU info: */
1808 	for_each_possible_cpu(cpu) {
1809 		int apicid = per_cpu(x86_cpu_to_apicid, cpu);
1810 		unsigned short bid;
1811 		unsigned short pnode;
1812 
1813 		pnode = uv_apicid_to_pnode(apicid);
1814 		bid = uv_pnode_to_socket(pnode) - _min_socket;
1815 
1816 		uv_cpu_info_per(cpu)->p_uv_hub_info = uv_hub_info_list_blade[bid];
1817 		uv_cpu_info_per(cpu)->blade_cpu_id = uv_cpu_hub_info(cpu)->nr_possible_cpus++;
1818 		if (uv_cpu_hub_info(cpu)->memory_nid == NUMA_NO_NODE)
1819 			uv_cpu_hub_info(cpu)->memory_nid = cpu_to_node(cpu);
1820 
1821 		if (uv_cpu_hub_info(cpu)->pnode == 0xffff)
1822 			uv_cpu_hub_info(cpu)->pnode = pnode;
1823 	}
1824 
1825 	for_each_possible_blade(bid) {
1826 		unsigned short pnode = uv_hub_info_list_blade[bid]->pnode;
1827 
1828 		if (pnode == 0xffff)
1829 			continue;
1830 
1831 		min_pnode = min(pnode, min_pnode);
1832 		max_pnode = max(pnode, max_pnode);
1833 		pr_info("UV: HUB:%2d pn:%02x nrcpus:%d\n",
1834 			bid,
1835 			uv_hub_info_list_blade[bid]->pnode,
1836 			uv_hub_info_list_blade[bid]->nr_possible_cpus);
1837 	}
1838 
1839 	pr_info("UV: min_pnode:%02x max_pnode:%02x\n", min_pnode, max_pnode);
1840 	map_gru_high(max_pnode);
1841 	map_mmr_high(max_pnode);
1842 	map_mmioh_high(min_pnode, max_pnode);
1843 
1844 	kfree(uv_hub_info_list_blade);
1845 	uv_hub_info_list_blade = NULL;
1846 
1847 	uv_nmi_setup();
1848 	uv_cpu_init();
1849 	uv_setup_proc_files(0);
1850 
1851 	/* Register Legacy VGA I/O redirection handler: */
1852 	pci_register_set_vga_state(uv_set_vga_state);
1853 
1854 	check_efi_reboot();
1855 }
1856 
1857 /*
1858  * There is a different code path needed to initialize a UV system that does
1859  * not have a "UV HUB" (referred to as "hubless").
1860  */
uv_system_init(void)1861 void __init uv_system_init(void)
1862 {
1863 	if (likely(!is_uv_system() && !is_uv_hubless(1)))
1864 		return;
1865 
1866 	if (is_uv_system())
1867 		uv_system_init_hub();
1868 	else
1869 		uv_system_init_hubless();
1870 }
1871 
1872 apic_driver(apic_x2apic_uv_x);
1873