1 /****************************************************************************** 2 * 3 * (C)Copyright 1998,1999 SysKonnect, 4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * The information in this file is provided "AS IS" without warranty. 12 * 13 ******************************************************************************/ 14 15 /* 16 * AMD Fplus in tag mode data structs 17 * defs for fplustm.c 18 */ 19 20 #ifndef _FPLUS_ 21 #define _FPLUS_ 22 23 #ifndef HW_PTR 24 #ifdef MEM_MAPPED_IO 25 #define HW_PTR u_long 26 #else 27 #define HW_PTR u_short 28 #endif 29 #endif 30 31 /* 32 * fplus error statistic structure 33 */ 34 struct err_st { 35 u_long err_valid ; /* memory status valid */ 36 u_long err_abort ; /* memory status receive abort */ 37 u_long err_e_indicator ; /* error indicator */ 38 u_long err_crc ; /* error detected (CRC or length) */ 39 u_long err_llc_frame ; /* LLC frame */ 40 u_long err_mac_frame ; /* MAC frame */ 41 u_long err_smt_frame ; /* SMT frame */ 42 u_long err_imp_frame ; /* implementer frame */ 43 u_long err_no_buf ; /* no buffer available */ 44 u_long err_too_long ; /* longer than max. buffer */ 45 u_long err_bec_stat ; /* beacon state entered */ 46 u_long err_clm_stat ; /* claim state entered */ 47 u_long err_sifg_det ; /* short interframe gap detect */ 48 u_long err_phinv ; /* PHY invalid */ 49 u_long err_tkiss ; /* token issued */ 50 u_long err_tkerr ; /* token error */ 51 } ; 52 53 #define SK_XD_ALIGN (size_t) 32 54 55 /* 56 * Transmit Descriptor struct 57 */ 58 struct s_dummy_txd { 59 u_int txd_tbctrl ; /* transmit buffer control */ 60 u_int txd_txdscr ; /* transmit frame status word */ 61 u_int txd_tbadr ; /* physical tx buffer address */ 62 u_int txd_ntdadr ; /* physical pointer to the next TxD */ 63 #ifdef ENA_64BIT_SUP 64 u_int txd_tbadr_hi ; /* physical tx buffer addr(high dword)*/ 65 #endif 66 caddr_t txd_virt ; /* virtual pointer to the data frag */ 67 /* virt pointer to the next TxD */ 68 struct s_smt_fp_txd volatile far *txd_next ; 69 struct s_txd_os txd_os ; /* OS - specific struct */ 70 /* No padding here! */ 71 } ; 72 73 #define SK_DUMMY_TXD sizeof(struct s_dummy_txd) 74 #define SK_TXD_PAD (((SK_DUMMY_TXD+SK_XD_ALIGN-1) \ 75 & ~(SK_XD_ALIGN-1))-SK_DUMMY_TXD) 76 struct s_smt_fp_txd { 77 u_int txd_tbctrl ; /* transmit buffer control */ 78 u_int txd_txdscr ; /* transmit frame status word */ 79 u_int txd_tbadr ; /* physical tx buffer address */ 80 u_int txd_ntdadr ; /* physical pointer to the next TxD */ 81 #ifdef ENA_64BIT_SUP 82 u_int txd_tbadr_hi ; /* physical tx buffer addr(high dword)*/ 83 #endif 84 caddr_t txd_virt ; /* virtual pointer to the data frag */ 85 /* virt pointer to the next TxD */ 86 struct s_smt_fp_txd volatile far *txd_next ; 87 struct s_txd_os txd_os ; /* OS - specific struct */ 88 char padding[SK_TXD_PAD]; /* padding */ 89 } ; 90 91 92 93 /* 94 * Receive Descriptor struct 95 */ 96 97 struct s_dummy_rxd { 98 u_int rxd_rbctrl ; /* receive buffer control */ 99 u_int rxd_rfsw ; /* receive frame status word */ 100 u_int rxd_rbadr ; /* physical rx buffer address */ 101 u_int rxd_nrdadr ; /* physical pointer to the next RxD */ 102 #ifdef ENA_64BIT_SUP 103 u_int rxd_rbadr_hi ; /* physical tx buffer addr(high dword)*/ 104 #endif 105 caddr_t rxd_virt ; /* virtual pointer to the data frag */ 106 /* virt pointer to the next RxD */ 107 struct s_smt_fp_rxd volatile far *rxd_next ; 108 struct s_rxd_os rxd_os ; /* OS - specific struct */ 109 /* No padding here! */ 110 } ; 111 112 #define SK_DUMMY_RXD sizeof(struct s_dummy_rxd) 113 #define SK_RXD_PAD (((SK_DUMMY_RXD+SK_XD_ALIGN-1) \ 114 & ~(SK_XD_ALIGN-1))-SK_DUMMY_RXD) 115 116 struct s_smt_fp_rxd { 117 u_int rxd_rbctrl ; /* receive buffer control */ 118 u_int rxd_rfsw ; /* receive frame status word */ 119 u_int rxd_rbadr ; /* physical rx buffer address */ 120 u_int rxd_nrdadr ; /* physical pointer to the next RxD */ 121 #ifdef ENA_64BIT_SUP 122 u_int rxd_rbadr_hi ; /* physical tx buffer addr(high dword)*/ 123 #endif 124 caddr_t rxd_virt ; /* virtual pointer to the data frag */ 125 /* virt pointer to the next RxD */ 126 struct s_smt_fp_rxd volatile far *rxd_next ; 127 struct s_rxd_os rxd_os ; /* OS - specific struct */ 128 char padding[SK_RXD_PAD] ; 129 } ; 130 131 /* 132 * Descriptor Union Definition 133 */ 134 union s_fp_descr { 135 struct s_smt_fp_txd t ; /* pointer to the TxD */ 136 struct s_smt_fp_rxd r ; /* pointer to the RxD */ 137 } ; 138 139 /* 140 * TxD Ring Control struct 141 */ 142 struct s_smt_tx_queue { 143 struct s_smt_fp_txd volatile *tx_curr_put ; /* next free TxD */ 144 struct s_smt_fp_txd volatile *tx_prev_put ; /* shadow put pointer */ 145 struct s_smt_fp_txd volatile *tx_curr_get ; /* next TxD to release*/ 146 u_short tx_free ; /* count of free TxD's */ 147 u_short tx_used ; /* count of used TxD's */ 148 HW_PTR tx_bmu_ctl ; /* BMU addr for tx start */ 149 HW_PTR tx_bmu_dsc ; /* BMU addr for curr dsc. */ 150 } ; 151 152 /* 153 * RxD Ring Control struct 154 */ 155 struct s_smt_rx_queue { 156 struct s_smt_fp_rxd volatile *rx_curr_put ; /* next RxD to queue into */ 157 struct s_smt_fp_rxd volatile *rx_prev_put ; /* shadow put pointer */ 158 struct s_smt_fp_rxd volatile *rx_curr_get ; /* next RxD to fill */ 159 u_short rx_free ; /* count of free RxD's */ 160 u_short rx_used ; /* count of used RxD's */ 161 HW_PTR rx_bmu_ctl ; /* BMU addr for rx start */ 162 HW_PTR rx_bmu_dsc ; /* BMU addr for curr dsc. */ 163 } ; 164 165 #define VOID_FRAME_OFF 0x00 166 #define CLAIM_FRAME_OFF 0x08 167 #define BEACON_FRAME_OFF 0x10 168 #define DBEACON_FRAME_OFF 0x18 169 #define RX_FIFO_OFF 0x21 /* to get a prime number for */ 170 /* the RX_FIFO_SPACE */ 171 172 #define RBC_MEM_SIZE 0x8000 173 #define SEND_ASYNC_AS_SYNC 0x1 174 #define SYNC_TRAFFIC_ON 0x2 175 176 /* big FIFO memory */ 177 #define RX_FIFO_SPACE 0x4000 - RX_FIFO_OFF 178 #define TX_FIFO_SPACE 0x4000 179 180 #define TX_SMALL_FIFO 0x0900 181 #define TX_MEDIUM_FIFO TX_FIFO_SPACE / 2 182 #define TX_LARGE_FIFO TX_FIFO_SPACE - TX_SMALL_FIFO 183 184 #define RX_SMALL_FIFO 0x0900 185 #define RX_LARGE_FIFO RX_FIFO_SPACE - RX_SMALL_FIFO 186 187 struct s_smt_fifo_conf { 188 u_short rbc_ram_start ; /* FIFO start address */ 189 u_short rbc_ram_end ; /* FIFO size */ 190 u_short rx1_fifo_start ; /* rx queue start address */ 191 u_short rx1_fifo_size ; /* rx queue size */ 192 u_short rx2_fifo_start ; /* rx queue start address */ 193 u_short rx2_fifo_size ; /* rx queue size */ 194 u_short tx_s_start ; /* sync queue start address */ 195 u_short tx_s_size ; /* sync queue size */ 196 u_short tx_a0_start ; /* async queue A0 start address */ 197 u_short tx_a0_size ; /* async queue A0 size */ 198 u_short fifo_config_mode ; /* FIFO configuration mode */ 199 } ; 200 201 #define FM_ADDRX (FM_ADDET|FM_EXGPA0|FM_EXGPA1) 202 203 struct s_smt_fp { 204 u_short mdr2init ; /* mode register 2 init value */ 205 u_short mdr3init ; /* mode register 3 init value */ 206 u_short frselreg_init ; /* frame selection register init val */ 207 u_short rx_mode ; /* address mode broad/multi/promisc */ 208 u_short nsa_mode ; 209 u_short rx_prom ; 210 u_short exgpa ; 211 212 struct err_st err_stats ; /* error statistics */ 213 214 /* 215 * MAC buffers 216 */ 217 struct fddi_mac_sf { /* special frame build buffer */ 218 u_char mac_fc ; 219 struct fddi_addr mac_dest ; 220 struct fddi_addr mac_source ; 221 u_char mac_info[0x20] ; 222 } mac_sfb ; 223 224 225 /* 226 * queues 227 */ 228 #define QUEUE_S 0 229 #define QUEUE_A0 1 230 #define QUEUE_R1 0 231 #define QUEUE_R2 1 232 #define USED_QUEUES 2 233 234 /* 235 * queue pointers; points to the queue dependent variables 236 */ 237 struct s_smt_tx_queue *tx[USED_QUEUES] ; 238 struct s_smt_rx_queue *rx[USED_QUEUES] ; 239 240 /* 241 * queue dependent variables 242 */ 243 struct s_smt_tx_queue tx_q[USED_QUEUES] ; 244 struct s_smt_rx_queue rx_q[USED_QUEUES] ; 245 246 /* 247 * FIFO configuration struct 248 */ 249 struct s_smt_fifo_conf fifo ; 250 251 /* last formac status */ 252 u_short s2u ; 253 u_short s2l ; 254 255 /* calculated FORMAC+ reg.addr. */ 256 HW_PTR fm_st1u ; 257 HW_PTR fm_st1l ; 258 HW_PTR fm_st2u ; 259 HW_PTR fm_st2l ; 260 HW_PTR fm_st3u ; 261 HW_PTR fm_st3l ; 262 263 264 /* 265 * multicast table 266 */ 267 #define FPMAX_MULTICAST 32 268 #define SMT_MAX_MULTI 4 269 struct { 270 struct s_fpmc { 271 struct fddi_addr a ; /* mc address */ 272 u_char n ; /* usage counter */ 273 u_char perm ; /* flag: permanent */ 274 } table[FPMAX_MULTICAST] ; 275 } mc ; 276 struct fddi_addr group_addr ; 277 u_long func_addr ; /* functional address */ 278 int smt_slots_used ; /* count of table entries for the SMT */ 279 int os_slots_used ; /* count of table entries */ 280 /* used by the os-specific module */ 281 } ; 282 283 /* 284 * modes for mac_set_rx_mode() 285 */ 286 #define RX_ENABLE_ALLMULTI 1 /* enable all multicasts */ 287 #define RX_DISABLE_ALLMULTI 2 /* disable "enable all multicasts" */ 288 #define RX_ENABLE_PROMISC 3 /* enable promiscous */ 289 #define RX_DISABLE_PROMISC 4 /* disable promiscous */ 290 #define RX_ENABLE_NSA 5 /* enable reception of NSA frames */ 291 #define RX_DISABLE_NSA 6 /* disable reception of NSA frames */ 292 293 294 /* 295 * support for byte reversal in AIX 296 * (descriptors and pointers must be byte reversed in memory 297 * CPU is big endian; M-Channel is little endian) 298 */ 299 #ifdef AIX 300 #define MDR_REV 301 #define AIX_REVERSE(x) ((((x)<<24L)&0xff000000L) + \ 302 (((x)<< 8L)&0x00ff0000L) + \ 303 (((x)>> 8L)&0x0000ff00L) + \ 304 (((x)>>24L)&0x000000ffL)) 305 #else 306 #ifndef AIX_REVERSE 307 #define AIX_REVERSE(x) (x) 308 #endif 309 #endif 310 311 #ifdef MDR_REV 312 #define MDR_REVERSE(x) ((((x)<<24L)&0xff000000L) + \ 313 (((x)<< 8L)&0x00ff0000L) + \ 314 (((x)>> 8L)&0x0000ff00L) + \ 315 (((x)>>24L)&0x000000ffL)) 316 #else 317 #ifndef MDR_REVERSE 318 #define MDR_REVERSE(x) (x) 319 #endif 320 #endif 321 322 #endif 323