1 /*
2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 #ifndef __MLX5_EN_H__
33 #define __MLX5_EN_H__
34 
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/crash_dump.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/qp.h>
42 #include <linux/mlx5/cq.h>
43 #include <linux/mlx5/port.h>
44 #include <linux/mlx5/vport.h>
45 #include <linux/mlx5/transobj.h>
46 #include <linux/mlx5/fs.h>
47 #include <linux/rhashtable.h>
48 #include <net/udp_tunnel.h>
49 #include <net/switchdev.h>
50 #include <net/xdp.h>
51 #include <linux/dim.h>
52 #include <linux/bits.h>
53 #include "wq.h"
54 #include "mlx5_core.h"
55 #include "en_stats.h"
56 #include "en/dcbnl.h"
57 #include "en/fs.h"
58 #include "en/qos.h"
59 #include "lib/hv_vhca.h"
60 #include "lib/clock.h"
61 #include "en/rx_res.h"
62 #include "en/selq.h"
63 
64 extern const struct net_device_ops mlx5e_netdev_ops;
65 struct page_pool;
66 
67 #define MLX5E_METADATA_ETHER_TYPE (0x8CE4)
68 #define MLX5E_METADATA_ETHER_LEN 8
69 
70 #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
71 
72 #define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu))
73 #define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu))
74 
75 #define MLX5E_MAX_NUM_TC	8
76 #define MLX5E_MAX_NUM_MQPRIO_CH_TC TC_QOPT_MAX_QUEUE
77 
78 #define MLX5_RX_HEADROOM NET_SKB_PAD
79 #define MLX5_SKB_FRAG_SZ(len)	(SKB_DATA_ALIGN(len) +	\
80 				 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
81 
82 #define MLX5E_RX_MAX_HEAD (256)
83 #define MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE (9)
84 #define MLX5E_SHAMPO_WQ_HEADER_PER_PAGE (PAGE_SIZE >> MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE)
85 #define MLX5E_SHAMPO_WQ_BASE_HEAD_ENTRY_SIZE (64)
86 #define MLX5E_SHAMPO_WQ_RESRV_SIZE (64 * 1024)
87 #define MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE (4096)
88 
89 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \
90 	(6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */
91 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \
92 	max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req)
93 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) \
94 	MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, order_base_2(MLX5E_RX_MAX_HEAD))
95 
96 #define MLX5_MPWRQ_MAX_LOG_WQE_SZ 18
97 
98 /* Keep in sync with mlx5e_mpwrq_log_wqe_sz.
99  * These are theoretical maximums, which can be further restricted by
100  * capabilities. These values are used for static resource allocations and
101  * sanity checks.
102  * MLX5_SEND_WQE_MAX_SIZE is a bit bigger than the maximum cacheline-aligned WQE
103  * size actually used at runtime, but it's not a problem when calculating static
104  * array sizes.
105  */
106 #define MLX5_UMR_MAX_MTT_SPACE \
107 	(ALIGN_DOWN(MLX5_SEND_WQE_MAX_SIZE - sizeof(struct mlx5e_umr_wqe), \
108 		    MLX5_UMR_MTT_ALIGNMENT))
109 #define MLX5_MPWRQ_MAX_PAGES_PER_WQE \
110 	rounddown_pow_of_two(MLX5_UMR_MAX_MTT_SPACE / sizeof(struct mlx5_mtt))
111 
112 #define MLX5E_MAX_RQ_NUM_MTTS	\
113 	(ALIGN_DOWN(U16_MAX, 4) * 2) /* Fits into u16 and aligned by WQEBB. */
114 #define MLX5E_MAX_RQ_NUM_KSMS (U16_MAX - 1) /* So that num_ksms fits into u16. */
115 #define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024))
116 
117 #define MLX5E_MIN_SKB_FRAG_SZ		(MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM))
118 #define MLX5E_LOG_MAX_RX_WQE_BULK	\
119 	(ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ)))
120 
121 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE                0x6
122 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE                0xa
123 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE                0xd
124 
125 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK)
126 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE                0xa
127 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE		0xd
128 
129 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW            0x2
130 
131 #define MLX5E_DEFAULT_LRO_TIMEOUT                       32
132 #define MLX5E_LRO_TIMEOUT_ARR_SIZE                      4
133 
134 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC      0x10
135 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
136 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS      0x20
137 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC      0x10
138 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10
139 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS      0x20
140 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES                0x80
141 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW            0x2
142 
143 #define MLX5E_MIN_NUM_CHANNELS         0x1
144 #define MLX5E_MAX_NUM_CHANNELS         (MLX5E_INDIR_RQT_SIZE / 2)
145 #define MLX5E_TX_CQ_POLL_BUDGET        128
146 #define MLX5E_TX_XSK_POLL_BUDGET       64
147 #define MLX5E_SQ_RECOVER_MIN_INTERVAL  500 /* msecs */
148 
149 #define MLX5E_KLM_UMR_WQE_SZ(sgl_len)\
150 	(sizeof(struct mlx5e_umr_wqe) +\
151 	(sizeof(struct mlx5_klm) * (sgl_len)))
152 
153 #define MLX5E_KLM_UMR_WQEBBS(klm_entries) \
154 	(DIV_ROUND_UP(MLX5E_KLM_UMR_WQE_SZ(klm_entries), MLX5_SEND_WQE_BB))
155 
156 #define MLX5E_KLM_UMR_DS_CNT(klm_entries)\
157 	(DIV_ROUND_UP(MLX5E_KLM_UMR_WQE_SZ(klm_entries), MLX5_SEND_WQE_DS))
158 
159 #define MLX5E_KLM_MAX_ENTRIES_PER_WQE(wqe_size)\
160 	(((wqe_size) - sizeof(struct mlx5e_umr_wqe)) / sizeof(struct mlx5_klm))
161 
162 #define MLX5E_KLM_ENTRIES_PER_WQE(wqe_size)\
163 	ALIGN_DOWN(MLX5E_KLM_MAX_ENTRIES_PER_WQE(wqe_size), MLX5_UMR_KLM_ALIGNMENT)
164 
165 #define MLX5E_MAX_KLM_PER_WQE(mdev) \
166 	MLX5E_KLM_ENTRIES_PER_WQE(MLX5_SEND_WQE_BB * mlx5e_get_max_sq_aligned_wqebbs(mdev))
167 
168 #define MLX5E_MSG_LEVEL			NETIF_MSG_LINK
169 
170 #define mlx5e_dbg(mlevel, priv, format, ...)                    \
171 do {                                                            \
172 	if (NETIF_MSG_##mlevel & (priv)->msglevel)              \
173 		netdev_warn(priv->netdev, format,               \
174 			    ##__VA_ARGS__);                     \
175 } while (0)
176 
177 #define mlx5e_state_dereference(priv, p) \
178 	rcu_dereference_protected((p), lockdep_is_held(&(priv)->state_lock))
179 
mlx5e_get_num_lag_ports(struct mlx5_core_dev * mdev)180 static inline u8 mlx5e_get_num_lag_ports(struct mlx5_core_dev *mdev)
181 {
182 	if (mlx5_lag_is_lacp_owner(mdev))
183 		return 1;
184 
185 	return clamp_t(u8, MLX5_CAP_GEN(mdev, num_lag_ports), 1, MLX5_MAX_PORTS);
186 }
187 
mlx5_min_rx_wqes(int wq_type,u32 wq_size)188 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
189 {
190 	switch (wq_type) {
191 	case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
192 		return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
193 			     wq_size / 2);
194 	default:
195 		return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
196 			     wq_size / 2);
197 	}
198 }
199 
200 /* Use this function to get max num channels (rxqs/txqs) only to create netdev */
mlx5e_get_max_num_channels(struct mlx5_core_dev * mdev)201 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
202 {
203 	return is_kdump_kernel() ?
204 		MLX5E_MIN_NUM_CHANNELS :
205 		min_t(int, mlx5_comp_vectors_count(mdev), MLX5E_MAX_NUM_CHANNELS);
206 }
207 
208 /* The maximum WQE size can be retrieved by max_wqe_sz_sq in
209  * bytes units. Driver hardens the limitation to 1KB (16
210  * WQEBBs), unless firmware capability is stricter.
211  */
mlx5e_get_max_sq_wqebbs(struct mlx5_core_dev * mdev)212 static inline u8 mlx5e_get_max_sq_wqebbs(struct mlx5_core_dev *mdev)
213 {
214 	BUILD_BUG_ON(MLX5_SEND_WQE_MAX_WQEBBS > U8_MAX);
215 
216 	return (u8)min_t(u16, MLX5_SEND_WQE_MAX_WQEBBS,
217 			 MLX5_CAP_GEN(mdev, max_wqe_sz_sq) / MLX5_SEND_WQE_BB);
218 }
219 
mlx5e_get_max_sq_aligned_wqebbs(struct mlx5_core_dev * mdev)220 static inline u8 mlx5e_get_max_sq_aligned_wqebbs(struct mlx5_core_dev *mdev)
221 {
222 /* The return value will be multiplied by MLX5_SEND_WQEBB_NUM_DS.
223  * Since max_sq_wqebbs may be up to MLX5_SEND_WQE_MAX_WQEBBS == 16,
224  * see mlx5e_get_max_sq_wqebbs(), the multiplication (16 * 4 == 64)
225  * overflows the 6-bit DS field of Ctrl Segment. Use a bound lower
226  * than MLX5_SEND_WQE_MAX_WQEBBS to let a full-session WQE be
227  * cache-aligned.
228  */
229 	u8 wqebbs = mlx5e_get_max_sq_wqebbs(mdev);
230 
231 	wqebbs = min_t(u8, wqebbs, MLX5_SEND_WQE_MAX_WQEBBS - 1);
232 #if L1_CACHE_BYTES >= 128
233 	wqebbs = ALIGN_DOWN(wqebbs, 2);
234 #endif
235 	return wqebbs;
236 }
237 
238 struct mlx5e_tx_wqe {
239 	struct mlx5_wqe_ctrl_seg ctrl;
240 	struct mlx5_wqe_eth_seg  eth;
241 	struct mlx5_wqe_data_seg data[];
242 };
243 
244 struct mlx5e_rx_wqe_ll {
245 	struct mlx5_wqe_srq_next_seg  next;
246 	struct mlx5_wqe_data_seg      data[];
247 };
248 
249 struct mlx5e_rx_wqe_cyc {
250 	struct mlx5_wqe_data_seg      data[0];
251 };
252 
253 struct mlx5e_umr_wqe {
254 	struct mlx5_wqe_ctrl_seg       ctrl;
255 	struct mlx5_wqe_umr_ctrl_seg   uctrl;
256 	struct mlx5_mkey_seg           mkc;
257 	union {
258 		DECLARE_FLEX_ARRAY(struct mlx5_mtt, inline_mtts);
259 		DECLARE_FLEX_ARRAY(struct mlx5_klm, inline_klms);
260 		DECLARE_FLEX_ARRAY(struct mlx5_ksm, inline_ksms);
261 	};
262 };
263 
264 enum mlx5e_priv_flag {
265 	MLX5E_PFLAG_RX_CQE_BASED_MODER,
266 	MLX5E_PFLAG_TX_CQE_BASED_MODER,
267 	MLX5E_PFLAG_RX_CQE_COMPRESS,
268 	MLX5E_PFLAG_RX_STRIDING_RQ,
269 	MLX5E_PFLAG_RX_NO_CSUM_COMPLETE,
270 	MLX5E_PFLAG_XDP_TX_MPWQE,
271 	MLX5E_PFLAG_SKB_TX_MPWQE,
272 	MLX5E_PFLAG_TX_PORT_TS,
273 	MLX5E_NUM_PFLAGS, /* Keep last */
274 };
275 
276 #define MLX5E_SET_PFLAG(params, pflag, enable)			\
277 	do {							\
278 		if (enable)					\
279 			(params)->pflags |= BIT(pflag);		\
280 		else						\
281 			(params)->pflags &= ~(BIT(pflag));	\
282 	} while (0)
283 
284 #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (BIT(pflag))))
285 
286 enum packet_merge {
287 	MLX5E_PACKET_MERGE_NONE,
288 	MLX5E_PACKET_MERGE_LRO,
289 	MLX5E_PACKET_MERGE_SHAMPO,
290 };
291 
292 struct mlx5e_packet_merge_param {
293 	enum packet_merge type;
294 	u32 timeout;
295 	struct {
296 		u8 match_criteria_type;
297 		u8 alignment_granularity;
298 	} shampo;
299 };
300 
301 struct mlx5e_params {
302 	u8  log_sq_size;
303 	u8  rq_wq_type;
304 	u8  log_rq_mtu_frames;
305 	u16 num_channels;
306 	struct {
307 		u16 mode;
308 		u8 num_tc;
309 		struct netdev_tc_txq tc_to_txq[TC_MAX_QUEUE];
310 		struct {
311 			u64 max_rate[TC_MAX_QUEUE];
312 			u32 hw_id[TC_MAX_QUEUE];
313 		} channel;
314 	} mqprio;
315 	bool rx_cqe_compress_def;
316 	bool tunneled_offload_en;
317 	struct dim_cq_moder rx_cq_moderation;
318 	struct dim_cq_moder tx_cq_moderation;
319 	struct mlx5e_packet_merge_param packet_merge;
320 	u8  tx_min_inline_mode;
321 	bool vlan_strip_disable;
322 	bool scatter_fcs_en;
323 	bool rx_dim_enabled;
324 	bool tx_dim_enabled;
325 	u32 pflags;
326 	struct bpf_prog *xdp_prog;
327 	struct mlx5e_xsk *xsk;
328 	unsigned int sw_mtu;
329 	int hard_mtu;
330 	bool ptp_rx;
331 };
332 
mlx5e_get_dcb_num_tc(struct mlx5e_params * params)333 static inline u8 mlx5e_get_dcb_num_tc(struct mlx5e_params *params)
334 {
335 	return params->mqprio.mode == TC_MQPRIO_MODE_DCB ?
336 		params->mqprio.num_tc : 1;
337 }
338 
339 enum {
340 	MLX5E_RQ_STATE_ENABLED,
341 	MLX5E_RQ_STATE_RECOVERING,
342 	MLX5E_RQ_STATE_AM,
343 	MLX5E_RQ_STATE_NO_CSUM_COMPLETE,
344 	MLX5E_RQ_STATE_CSUM_FULL, /* cqe_csum_full hw bit is set */
345 	MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, /* set when mini_cqe_resp_stride_index cap is used */
346 	MLX5E_RQ_STATE_SHAMPO, /* set when SHAMPO cap is used */
347 };
348 
349 struct mlx5e_cq {
350 	/* data path - accessed per cqe */
351 	struct mlx5_cqwq           wq;
352 
353 	/* data path - accessed per napi poll */
354 	u16                        event_ctr;
355 	struct napi_struct        *napi;
356 	struct mlx5_core_cq        mcq;
357 	struct mlx5e_ch_stats     *ch_stats;
358 
359 	/* control */
360 	struct net_device         *netdev;
361 	struct mlx5_core_dev      *mdev;
362 	struct mlx5e_priv         *priv;
363 	struct mlx5_wq_ctrl        wq_ctrl;
364 } ____cacheline_aligned_in_smp;
365 
366 struct mlx5e_cq_decomp {
367 	/* cqe decompression */
368 	struct mlx5_cqe64          title;
369 	struct mlx5_mini_cqe8      mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
370 	u8                         mini_arr_idx;
371 	u16                        left;
372 	u16                        wqe_counter;
373 } ____cacheline_aligned_in_smp;
374 
375 enum mlx5e_dma_map_type {
376 	MLX5E_DMA_MAP_SINGLE,
377 	MLX5E_DMA_MAP_PAGE
378 };
379 
380 struct mlx5e_sq_dma {
381 	dma_addr_t              addr;
382 	u32                     size;
383 	enum mlx5e_dma_map_type type;
384 };
385 
386 enum {
387 	MLX5E_SQ_STATE_ENABLED,
388 	MLX5E_SQ_STATE_MPWQE,
389 	MLX5E_SQ_STATE_RECOVERING,
390 	MLX5E_SQ_STATE_IPSEC,
391 	MLX5E_SQ_STATE_AM,
392 	MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE,
393 	MLX5E_SQ_STATE_PENDING_XSK_TX,
394 	MLX5E_SQ_STATE_PENDING_TLS_RX_RESYNC,
395 	MLX5E_SQ_STATE_XDP_MULTIBUF,
396 };
397 
398 struct mlx5e_tx_mpwqe {
399 	/* Current MPWQE session */
400 	struct mlx5e_tx_wqe *wqe;
401 	u32 bytes_count;
402 	u8 ds_count;
403 	u8 pkt_count;
404 	u8 inline_on;
405 };
406 
407 struct mlx5e_skb_fifo {
408 	struct sk_buff **fifo;
409 	u16 *pc;
410 	u16 *cc;
411 	u16 mask;
412 };
413 
414 struct mlx5e_ptpsq;
415 
416 struct mlx5e_txqsq {
417 	/* data path */
418 
419 	/* dirtied @completion */
420 	u16                        cc;
421 	u16                        skb_fifo_cc;
422 	u32                        dma_fifo_cc;
423 	struct dim                 dim; /* Adaptive Moderation */
424 
425 	/* dirtied @xmit */
426 	u16                        pc ____cacheline_aligned_in_smp;
427 	u16                        skb_fifo_pc;
428 	u32                        dma_fifo_pc;
429 	struct mlx5e_tx_mpwqe      mpwqe;
430 
431 	struct mlx5e_cq            cq;
432 
433 	/* read only */
434 	struct mlx5_wq_cyc         wq;
435 	u32                        dma_fifo_mask;
436 	struct mlx5e_sq_stats     *stats;
437 	struct {
438 		struct mlx5e_sq_dma       *dma_fifo;
439 		struct mlx5e_skb_fifo      skb_fifo;
440 		struct mlx5e_tx_wqe_info  *wqe_info;
441 	} db;
442 	void __iomem              *uar_map;
443 	struct netdev_queue       *txq;
444 	u32                        sqn;
445 	u16                        stop_room;
446 	u8                         max_sq_mpw_wqebbs;
447 	u8                         min_inline_mode;
448 	struct device             *pdev;
449 	__be32                     mkey_be;
450 	unsigned long              state;
451 	unsigned int               hw_mtu;
452 	struct mlx5_clock         *clock;
453 	struct net_device         *netdev;
454 	struct mlx5_core_dev      *mdev;
455 	struct mlx5e_priv         *priv;
456 
457 	/* control path */
458 	struct mlx5_wq_ctrl        wq_ctrl;
459 	int                        ch_ix;
460 	int                        txq_ix;
461 	u32                        rate_limit;
462 	struct work_struct         recover_work;
463 	struct mlx5e_ptpsq        *ptpsq;
464 	cqe_ts_to_ns               ptp_cyc2time;
465 } ____cacheline_aligned_in_smp;
466 
467 union mlx5e_alloc_unit {
468 	struct page *page;
469 	struct xdp_buff *xsk;
470 };
471 
472 /* XDP packets can be transmitted in different ways. On completion, we need to
473  * distinguish between them to clean up things in a proper way.
474  */
475 enum mlx5e_xdp_xmit_mode {
476 	/* An xdp_frame was transmitted due to either XDP_REDIRECT from another
477 	 * device or XDP_TX from an XSK RQ. The frame has to be unmapped and
478 	 * returned.
479 	 */
480 	MLX5E_XDP_XMIT_MODE_FRAME,
481 
482 	/* The xdp_frame was created in place as a result of XDP_TX from a
483 	 * regular RQ. No DMA remapping happened, and the page belongs to us.
484 	 */
485 	MLX5E_XDP_XMIT_MODE_PAGE,
486 
487 	/* No xdp_frame was created at all, the transmit happened from a UMEM
488 	 * page. The UMEM Completion Ring producer pointer has to be increased.
489 	 */
490 	MLX5E_XDP_XMIT_MODE_XSK,
491 };
492 
493 struct mlx5e_xdp_info {
494 	enum mlx5e_xdp_xmit_mode mode;
495 	union {
496 		struct {
497 			struct xdp_frame *xdpf;
498 			dma_addr_t dma_addr;
499 		} frame;
500 		struct {
501 			struct mlx5e_rq *rq;
502 			struct page *page;
503 		} page;
504 	};
505 };
506 
507 struct mlx5e_xmit_data {
508 	dma_addr_t  dma_addr;
509 	void       *data;
510 	u32         len;
511 };
512 
513 struct mlx5e_xdp_info_fifo {
514 	struct mlx5e_xdp_info *xi;
515 	u32 *cc;
516 	u32 *pc;
517 	u32 mask;
518 };
519 
520 struct mlx5e_xdpsq;
521 typedef int (*mlx5e_fp_xmit_xdp_frame_check)(struct mlx5e_xdpsq *);
522 typedef bool (*mlx5e_fp_xmit_xdp_frame)(struct mlx5e_xdpsq *,
523 					struct mlx5e_xmit_data *,
524 					struct skb_shared_info *,
525 					int);
526 
527 struct mlx5e_xdpsq {
528 	/* data path */
529 
530 	/* dirtied @completion */
531 	u32                        xdpi_fifo_cc;
532 	u16                        cc;
533 
534 	/* dirtied @xmit */
535 	u32                        xdpi_fifo_pc ____cacheline_aligned_in_smp;
536 	u16                        pc;
537 	struct mlx5_wqe_ctrl_seg   *doorbell_cseg;
538 	struct mlx5e_tx_mpwqe      mpwqe;
539 
540 	struct mlx5e_cq            cq;
541 
542 	/* read only */
543 	struct xsk_buff_pool      *xsk_pool;
544 	struct mlx5_wq_cyc         wq;
545 	struct mlx5e_xdpsq_stats  *stats;
546 	mlx5e_fp_xmit_xdp_frame_check xmit_xdp_frame_check;
547 	mlx5e_fp_xmit_xdp_frame    xmit_xdp_frame;
548 	struct {
549 		struct mlx5e_xdp_wqe_info *wqe_info;
550 		struct mlx5e_xdp_info_fifo xdpi_fifo;
551 	} db;
552 	void __iomem              *uar_map;
553 	u32                        sqn;
554 	struct device             *pdev;
555 	__be32                     mkey_be;
556 	u16                        stop_room;
557 	u8                         max_sq_mpw_wqebbs;
558 	u8                         min_inline_mode;
559 	unsigned long              state;
560 	unsigned int               hw_mtu;
561 
562 	/* control path */
563 	struct mlx5_wq_ctrl        wq_ctrl;
564 	struct mlx5e_channel      *channel;
565 } ____cacheline_aligned_in_smp;
566 
567 struct mlx5e_ktls_resync_resp;
568 
569 struct mlx5e_icosq {
570 	/* data path */
571 	u16                        cc;
572 	u16                        pc;
573 
574 	struct mlx5_wqe_ctrl_seg  *doorbell_cseg;
575 	struct mlx5e_cq            cq;
576 
577 	/* write@xmit, read@completion */
578 	struct {
579 		struct mlx5e_icosq_wqe_info *wqe_info;
580 	} db;
581 
582 	/* read only */
583 	struct mlx5_wq_cyc         wq;
584 	void __iomem              *uar_map;
585 	u32                        sqn;
586 	u16                        reserved_room;
587 	unsigned long              state;
588 	struct mlx5e_ktls_resync_resp *ktls_resync;
589 
590 	/* control path */
591 	struct mlx5_wq_ctrl        wq_ctrl;
592 	struct mlx5e_channel      *channel;
593 
594 	struct work_struct         recover_work;
595 } ____cacheline_aligned_in_smp;
596 
597 struct mlx5e_wqe_frag_info {
598 	union mlx5e_alloc_unit *au;
599 	u32 offset;
600 	bool last_in_page;
601 };
602 
603 struct mlx5e_mpw_info {
604 	u16 consumed_strides;
605 	DECLARE_BITMAP(xdp_xmit_bitmap, MLX5_MPWRQ_MAX_PAGES_PER_WQE);
606 	union mlx5e_alloc_unit alloc_units[];
607 };
608 
609 #define MLX5E_MAX_RX_FRAGS 4
610 
611 /* a single cache unit is capable to serve one napi call (for non-striding rq)
612  * or a MPWQE (for striding rq).
613  */
614 #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_MAX_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \
615 			  MLX5_MPWRQ_MAX_PAGES_PER_WQE : NAPI_POLL_WEIGHT)
616 #define MLX5E_CACHE_SIZE	(4 * roundup_pow_of_two(MLX5E_CACHE_UNIT))
617 struct mlx5e_page_cache {
618 	u32 head;
619 	u32 tail;
620 	struct page *page_cache[MLX5E_CACHE_SIZE];
621 };
622 
623 struct mlx5e_rq;
624 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*);
625 typedef struct sk_buff *
626 (*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
627 			       u16 cqe_bcnt, u32 head_offset, u32 page_idx);
628 typedef struct sk_buff *
629 (*mlx5e_fp_skb_from_cqe)(struct mlx5e_rq *rq, struct mlx5e_wqe_frag_info *wi,
630 			 u32 cqe_bcnt);
631 typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq);
632 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16);
633 typedef void (*mlx5e_fp_shampo_dealloc_hd)(struct mlx5e_rq*, u16, u16, bool);
634 
635 int mlx5e_rq_set_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params, bool xsk);
636 void mlx5e_rq_set_trap_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params);
637 
638 enum mlx5e_rq_flag {
639 	MLX5E_RQ_FLAG_XDP_XMIT,
640 	MLX5E_RQ_FLAG_XDP_REDIRECT,
641 };
642 
643 struct mlx5e_rq_frag_info {
644 	int frag_size;
645 	int frag_stride;
646 };
647 
648 struct mlx5e_rq_frags_info {
649 	struct mlx5e_rq_frag_info arr[MLX5E_MAX_RX_FRAGS];
650 	u8 num_frags;
651 	u8 log_num_frags;
652 	u8 wqe_bulk;
653 	u8 wqe_index_mask;
654 };
655 
656 struct mlx5e_dma_info {
657 	dma_addr_t addr;
658 	struct page *page;
659 };
660 
661 struct mlx5e_shampo_hd {
662 	u32 mkey;
663 	struct mlx5e_dma_info *info;
664 	struct page *last_page;
665 	u16 hd_per_wq;
666 	u16 hd_per_wqe;
667 	unsigned long *bitmap;
668 	u16 pi;
669 	u16 ci;
670 	__be32 key;
671 	u64 last_addr;
672 };
673 
674 struct mlx5e_hw_gro_data {
675 	struct sk_buff *skb;
676 	struct flow_keys fk;
677 	int second_ip_id;
678 };
679 
680 enum mlx5e_mpwrq_umr_mode {
681 	MLX5E_MPWRQ_UMR_MODE_ALIGNED,
682 	MLX5E_MPWRQ_UMR_MODE_UNALIGNED,
683 	MLX5E_MPWRQ_UMR_MODE_OVERSIZED,
684 	MLX5E_MPWRQ_UMR_MODE_TRIPLE,
685 };
686 
687 struct mlx5e_rq {
688 	/* data path */
689 	union {
690 		struct {
691 			struct mlx5_wq_cyc          wq;
692 			struct mlx5e_wqe_frag_info *frags;
693 			union mlx5e_alloc_unit     *alloc_units;
694 			struct mlx5e_rq_frags_info  info;
695 			mlx5e_fp_skb_from_cqe       skb_from_cqe;
696 		} wqe;
697 		struct {
698 			struct mlx5_wq_ll      wq;
699 			struct mlx5e_umr_wqe   umr_wqe;
700 			struct mlx5e_mpw_info *info;
701 			mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq;
702 			__be32                 umr_mkey_be;
703 			u16                    num_strides;
704 			u16                    actual_wq_head;
705 			u8                     log_stride_sz;
706 			u8                     umr_in_progress;
707 			u8                     umr_last_bulk;
708 			u8                     umr_completed;
709 			u8                     min_wqe_bulk;
710 			u8                     page_shift;
711 			u8                     pages_per_wqe;
712 			u8                     umr_wqebbs;
713 			u8                     mtts_per_wqe;
714 			u8                     umr_mode;
715 			struct mlx5e_shampo_hd *shampo;
716 		} mpwqe;
717 	};
718 	struct {
719 		u16            headroom;
720 		u32            frame0_sz;
721 		u8             map_dir;   /* dma map direction */
722 	} buff;
723 
724 	struct device         *pdev;
725 	struct net_device     *netdev;
726 	struct mlx5e_rq_stats *stats;
727 	struct mlx5e_cq        cq;
728 	struct mlx5e_cq_decomp cqd;
729 	struct mlx5e_page_cache page_cache;
730 	struct hwtstamp_config *tstamp;
731 	struct mlx5_clock      *clock;
732 	struct mlx5e_icosq    *icosq;
733 	struct mlx5e_priv     *priv;
734 
735 	struct mlx5e_hw_gro_data *hw_gro_data;
736 
737 	mlx5e_fp_handle_rx_cqe handle_rx_cqe;
738 	mlx5e_fp_post_rx_wqes  post_wqes;
739 	mlx5e_fp_dealloc_wqe   dealloc_wqe;
740 
741 	unsigned long          state;
742 	int                    ix;
743 	unsigned int           hw_mtu;
744 
745 	struct dim         dim; /* Dynamic Interrupt Moderation */
746 
747 	/* XDP */
748 	struct bpf_prog __rcu *xdp_prog;
749 	struct mlx5e_xdpsq    *xdpsq;
750 	DECLARE_BITMAP(flags, 8);
751 	struct page_pool      *page_pool;
752 
753 	/* AF_XDP zero-copy */
754 	struct xsk_buff_pool  *xsk_pool;
755 
756 	struct work_struct     recover_work;
757 
758 	/* control */
759 	struct mlx5_wq_ctrl    wq_ctrl;
760 	__be32                 mkey_be;
761 	u8                     wq_type;
762 	u32                    rqn;
763 	struct mlx5_core_dev  *mdev;
764 	struct mlx5e_channel  *channel;
765 	struct mlx5e_dma_info  wqe_overflow;
766 
767 	/* XDP read-mostly */
768 	struct xdp_rxq_info    xdp_rxq;
769 	cqe_ts_to_ns           ptp_cyc2time;
770 } ____cacheline_aligned_in_smp;
771 
772 enum mlx5e_channel_state {
773 	MLX5E_CHANNEL_STATE_XSK,
774 	MLX5E_CHANNEL_NUM_STATES
775 };
776 
777 struct mlx5e_channel {
778 	/* data path */
779 	struct mlx5e_rq            rq;
780 	struct mlx5e_xdpsq         rq_xdpsq;
781 	struct mlx5e_txqsq         sq[MLX5E_MAX_NUM_TC];
782 	struct mlx5e_icosq         icosq;   /* internal control operations */
783 	struct mlx5e_txqsq __rcu * __rcu *qos_sqs;
784 	bool                       xdp;
785 	struct napi_struct         napi;
786 	struct device             *pdev;
787 	struct net_device         *netdev;
788 	__be32                     mkey_be;
789 	u16                        qos_sqs_size;
790 	u8                         num_tc;
791 	u8                         lag_port;
792 
793 	/* XDP_REDIRECT */
794 	struct mlx5e_xdpsq         xdpsq;
795 
796 	/* AF_XDP zero-copy */
797 	struct mlx5e_rq            xskrq;
798 	struct mlx5e_xdpsq         xsksq;
799 
800 	/* Async ICOSQ */
801 	struct mlx5e_icosq         async_icosq;
802 	/* async_icosq can be accessed from any CPU - the spinlock protects it. */
803 	spinlock_t                 async_icosq_lock;
804 
805 	/* data path - accessed per napi poll */
806 	const struct cpumask	  *aff_mask;
807 	struct mlx5e_ch_stats     *stats;
808 
809 	/* control */
810 	struct mlx5e_priv         *priv;
811 	struct mlx5_core_dev      *mdev;
812 	struct hwtstamp_config    *tstamp;
813 	DECLARE_BITMAP(state, MLX5E_CHANNEL_NUM_STATES);
814 	int                        ix;
815 	int                        cpu;
816 	/* Sync between icosq recovery and XSK enable/disable. */
817 	struct mutex               icosq_recovery_lock;
818 };
819 
820 struct mlx5e_ptp;
821 
822 struct mlx5e_channels {
823 	struct mlx5e_channel **c;
824 	struct mlx5e_ptp      *ptp;
825 	unsigned int           num;
826 	struct mlx5e_params    params;
827 };
828 
829 struct mlx5e_channel_stats {
830 	struct mlx5e_ch_stats ch;
831 	struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC];
832 	struct mlx5e_rq_stats rq;
833 	struct mlx5e_rq_stats xskrq;
834 	struct mlx5e_xdpsq_stats rq_xdpsq;
835 	struct mlx5e_xdpsq_stats xdpsq;
836 	struct mlx5e_xdpsq_stats xsksq;
837 } ____cacheline_aligned_in_smp;
838 
839 struct mlx5e_ptp_stats {
840 	struct mlx5e_ch_stats ch;
841 	struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC];
842 	struct mlx5e_ptp_cq_stats cq[MLX5E_MAX_NUM_TC];
843 	struct mlx5e_rq_stats rq;
844 } ____cacheline_aligned_in_smp;
845 
846 enum {
847 	MLX5E_STATE_OPENED,
848 	MLX5E_STATE_DESTROYING,
849 	MLX5E_STATE_XDP_TX_ENABLED,
850 	MLX5E_STATE_XDP_ACTIVE,
851 };
852 
853 struct mlx5e_modify_sq_param {
854 	int curr_state;
855 	int next_state;
856 	int rl_update;
857 	int rl_index;
858 	bool qos_update;
859 	u16 qos_queue_group_id;
860 };
861 
862 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE)
863 struct mlx5e_hv_vhca_stats_agent {
864 	struct mlx5_hv_vhca_agent *agent;
865 	struct delayed_work        work;
866 	u16                        delay;
867 	void                      *buf;
868 };
869 #endif
870 
871 struct mlx5e_xsk {
872 	/* XSK buffer pools are stored separately from channels,
873 	 * because we don't want to lose them when channels are
874 	 * recreated. The kernel also stores buffer pool, but it doesn't
875 	 * distinguish between zero-copy and non-zero-copy UMEMs, so
876 	 * rely on our mechanism.
877 	 */
878 	struct xsk_buff_pool **pools;
879 	u16 refcnt;
880 	bool ever_used;
881 };
882 
883 /* Temporary storage for variables that are allocated when struct mlx5e_priv is
884  * initialized, and used where we can't allocate them because that functions
885  * must not fail. Use with care and make sure the same variable is not used
886  * simultaneously by multiple users.
887  */
888 struct mlx5e_scratchpad {
889 	cpumask_var_t cpumask;
890 };
891 
892 struct mlx5e_trap;
893 struct mlx5e_htb;
894 
895 struct mlx5e_priv {
896 	/* priv data path fields - start */
897 	struct mlx5e_selq selq;
898 	struct mlx5e_txqsq **txq2sq;
899 #ifdef CONFIG_MLX5_CORE_EN_DCB
900 	struct mlx5e_dcbx_dp       dcbx_dp;
901 #endif
902 	/* priv data path fields - end */
903 
904 	u32                        msglevel;
905 	unsigned long              state;
906 	struct mutex               state_lock; /* Protects Interface state */
907 	struct mlx5e_rq            drop_rq;
908 
909 	struct mlx5e_channels      channels;
910 	u32                        tisn[MLX5_MAX_PORTS][MLX5E_MAX_NUM_TC];
911 	struct mlx5e_rx_res       *rx_res;
912 	u32                       *tx_rates;
913 
914 	struct mlx5e_flow_steering *fs;
915 
916 	struct workqueue_struct    *wq;
917 	struct work_struct         update_carrier_work;
918 	struct work_struct         set_rx_mode_work;
919 	struct work_struct         tx_timeout_work;
920 	struct work_struct         update_stats_work;
921 	struct work_struct         monitor_counters_work;
922 	struct mlx5_nb             monitor_counters_nb;
923 
924 	struct mlx5_core_dev      *mdev;
925 	struct net_device         *netdev;
926 	struct mlx5e_trap         *en_trap;
927 	struct mlx5e_stats         stats;
928 	struct mlx5e_channel_stats **channel_stats;
929 	struct mlx5e_channel_stats trap_stats;
930 	struct mlx5e_ptp_stats     ptp_stats;
931 	struct mlx5e_sq_stats      **htb_qos_sq_stats;
932 	u16                        htb_max_qos_sqs;
933 	u16                        stats_nch;
934 	u16                        max_nch;
935 	u8                         max_opened_tc;
936 	bool                       tx_ptp_opened;
937 	bool                       rx_ptp_opened;
938 	struct hwtstamp_config     tstamp;
939 	u16                        q_counter;
940 	u16                        drop_rq_q_counter;
941 	struct notifier_block      events_nb;
942 	struct notifier_block      blocking_events_nb;
943 
944 	struct udp_tunnel_nic_info nic_info;
945 #ifdef CONFIG_MLX5_CORE_EN_DCB
946 	struct mlx5e_dcbx          dcbx;
947 #endif
948 
949 	const struct mlx5e_profile *profile;
950 	void                      *ppriv;
951 #ifdef CONFIG_MLX5_EN_MACSEC
952 	struct mlx5e_macsec       *macsec;
953 #endif
954 #ifdef CONFIG_MLX5_EN_IPSEC
955 	struct mlx5e_ipsec        *ipsec;
956 #endif
957 #ifdef CONFIG_MLX5_EN_TLS
958 	struct mlx5e_tls          *tls;
959 #endif
960 	struct devlink_health_reporter *tx_reporter;
961 	struct devlink_health_reporter *rx_reporter;
962 	struct mlx5e_xsk           xsk;
963 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE)
964 	struct mlx5e_hv_vhca_stats_agent stats_agent;
965 #endif
966 	struct mlx5e_scratchpad    scratchpad;
967 	struct mlx5e_htb          *htb;
968 	struct mlx5e_mqprio_rl    *mqprio_rl;
969 };
970 
971 struct mlx5e_rx_handlers {
972 	mlx5e_fp_handle_rx_cqe handle_rx_cqe;
973 	mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe;
974 	mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe_shampo;
975 };
976 
977 extern const struct mlx5e_rx_handlers mlx5e_rx_handlers_nic;
978 
979 enum mlx5e_profile_feature {
980 	MLX5E_PROFILE_FEATURE_PTP_RX,
981 	MLX5E_PROFILE_FEATURE_PTP_TX,
982 	MLX5E_PROFILE_FEATURE_QOS_HTB,
983 	MLX5E_PROFILE_FEATURE_FS_VLAN,
984 	MLX5E_PROFILE_FEATURE_FS_TC,
985 };
986 
987 struct mlx5e_profile {
988 	int	(*init)(struct mlx5_core_dev *mdev,
989 			struct net_device *netdev);
990 	void	(*cleanup)(struct mlx5e_priv *priv);
991 	int	(*init_rx)(struct mlx5e_priv *priv);
992 	void	(*cleanup_rx)(struct mlx5e_priv *priv);
993 	int	(*init_tx)(struct mlx5e_priv *priv);
994 	void	(*cleanup_tx)(struct mlx5e_priv *priv);
995 	void	(*enable)(struct mlx5e_priv *priv);
996 	void	(*disable)(struct mlx5e_priv *priv);
997 	int	(*update_rx)(struct mlx5e_priv *priv);
998 	void	(*update_stats)(struct mlx5e_priv *priv);
999 	void	(*update_carrier)(struct mlx5e_priv *priv);
1000 	int	(*max_nch_limit)(struct mlx5_core_dev *mdev);
1001 	unsigned int (*stats_grps_num)(struct mlx5e_priv *priv);
1002 	mlx5e_stats_grp_t *stats_grps;
1003 	const struct mlx5e_rx_handlers *rx_handlers;
1004 	int	max_tc;
1005 	u32     features;
1006 };
1007 
1008 #define mlx5e_profile_feature_cap(profile, feature)	\
1009 	((profile)->features & BIT(MLX5E_PROFILE_FEATURE_##feature))
1010 
1011 void mlx5e_build_ptys2ethtool_map(void);
1012 
1013 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev, u8 page_shift,
1014 					    enum mlx5e_mpwrq_umr_mode umr_mode);
1015 
1016 void mlx5e_shampo_dealloc_hd(struct mlx5e_rq *rq, u16 len, u16 start, bool close);
1017 void mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats);
1018 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s);
1019 
1020 int mlx5e_self_test_num(struct mlx5e_priv *priv);
1021 int mlx5e_self_test_fill_strings(struct mlx5e_priv *priv, u8 *data);
1022 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest,
1023 		     u64 *buf);
1024 void mlx5e_set_rx_mode_work(struct work_struct *work);
1025 
1026 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr);
1027 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr);
1028 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val, bool rx_filter);
1029 
1030 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
1031 			  u16 vid);
1032 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
1033 			   u16 vid);
1034 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
1035 
1036 struct mlx5e_xsk_param;
1037 
1038 struct mlx5e_rq_param;
1039 int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param,
1040 		  struct mlx5e_xsk_param *xsk, int node,
1041 		  struct mlx5e_rq *rq);
1042 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */
1043 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time);
1044 void mlx5e_close_rq(struct mlx5e_rq *rq);
1045 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param);
1046 void mlx5e_destroy_rq(struct mlx5e_rq *rq);
1047 
1048 struct mlx5e_sq_param;
1049 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1050 		     struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool,
1051 		     struct mlx5e_xdpsq *sq, bool is_redirect);
1052 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq);
1053 
1054 struct mlx5e_create_cq_param {
1055 	struct napi_struct *napi;
1056 	struct mlx5e_ch_stats *ch_stats;
1057 	int node;
1058 	int ix;
1059 };
1060 
1061 struct mlx5e_cq_param;
1062 int mlx5e_open_cq(struct mlx5e_priv *priv, struct dim_cq_moder moder,
1063 		  struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp,
1064 		  struct mlx5e_cq *cq);
1065 void mlx5e_close_cq(struct mlx5e_cq *cq);
1066 
1067 int mlx5e_open_locked(struct net_device *netdev);
1068 int mlx5e_close_locked(struct net_device *netdev);
1069 
1070 void mlx5e_trigger_napi_icosq(struct mlx5e_channel *c);
1071 void mlx5e_trigger_napi_sched(struct napi_struct *napi);
1072 
1073 int mlx5e_open_channels(struct mlx5e_priv *priv,
1074 			struct mlx5e_channels *chs);
1075 void mlx5e_close_channels(struct mlx5e_channels *chs);
1076 
1077 /* Function pointer to be used to modify HW or kernel settings while
1078  * switching channels
1079  */
1080 typedef int (*mlx5e_fp_preactivate)(struct mlx5e_priv *priv, void *context);
1081 #define MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(fn) \
1082 int fn##_ctx(struct mlx5e_priv *priv, void *context) \
1083 { \
1084 	return fn(priv); \
1085 }
1086 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv);
1087 int mlx5e_safe_switch_params(struct mlx5e_priv *priv,
1088 			     struct mlx5e_params *new_params,
1089 			     mlx5e_fp_preactivate preactivate,
1090 			     void *context, bool reset);
1091 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv);
1092 int mlx5e_num_channels_changed_ctx(struct mlx5e_priv *priv, void *context);
1093 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv);
1094 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv);
1095 int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx);
1096 
1097 int mlx5e_flush_rq(struct mlx5e_rq *rq, int curr_state);
1098 void mlx5e_activate_rq(struct mlx5e_rq *rq);
1099 void mlx5e_deactivate_rq(struct mlx5e_rq *rq);
1100 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq);
1101 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq);
1102 
1103 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1104 		    struct mlx5e_modify_sq_param *p);
1105 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix,
1106 		     struct mlx5e_params *params, struct mlx5e_sq_param *param,
1107 		     struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id,
1108 		     struct mlx5e_sq_stats *sq_stats);
1109 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq);
1110 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq);
1111 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq);
1112 void mlx5e_tx_disable_queue(struct netdev_queue *txq);
1113 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa);
1114 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq);
1115 struct mlx5e_create_sq_param;
1116 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1117 			struct mlx5e_sq_param *param,
1118 			struct mlx5e_create_sq_param *csp,
1119 			u16 qos_queue_group_id,
1120 			u32 *sqn);
1121 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work);
1122 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq);
1123 
mlx5_tx_swp_supported(struct mlx5_core_dev * mdev)1124 static inline bool mlx5_tx_swp_supported(struct mlx5_core_dev *mdev)
1125 {
1126 	return MLX5_CAP_ETH(mdev, swp) &&
1127 		MLX5_CAP_ETH(mdev, swp_csum) && MLX5_CAP_ETH(mdev, swp_lso);
1128 }
1129 
1130 extern const struct ethtool_ops mlx5e_ethtool_ops;
1131 
1132 int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, u32 *mkey);
1133 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev);
1134 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);
1135 int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb,
1136 		       bool enable_mc_lb);
1137 void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc);
1138 
1139 /* common netdev helpers */
1140 void mlx5e_create_q_counters(struct mlx5e_priv *priv);
1141 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv);
1142 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
1143 		       struct mlx5e_rq *drop_rq);
1144 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq);
1145 
1146 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn);
1147 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn);
1148 
1149 int mlx5e_create_tises(struct mlx5e_priv *priv);
1150 void mlx5e_destroy_tises(struct mlx5e_priv *priv);
1151 int mlx5e_update_nic_rx(struct mlx5e_priv *priv);
1152 void mlx5e_update_carrier(struct mlx5e_priv *priv);
1153 int mlx5e_close(struct net_device *netdev);
1154 int mlx5e_open(struct net_device *netdev);
1155 
1156 void mlx5e_queue_update_stats(struct mlx5e_priv *priv);
1157 
1158 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv);
1159 int mlx5e_set_dev_port_mtu_ctx(struct mlx5e_priv *priv, void *context);
1160 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
1161 		     mlx5e_fp_preactivate preactivate);
1162 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv);
1163 
1164 /* ethtool helpers */
1165 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
1166 			       struct ethtool_drvinfo *drvinfo);
1167 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv,
1168 			       uint32_t stringset, uint8_t *data);
1169 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset);
1170 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
1171 				     struct ethtool_stats *stats, u64 *data);
1172 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
1173 				 struct ethtool_ringparam *param,
1174 				 struct kernel_ethtool_ringparam *kernel_param);
1175 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
1176 				struct ethtool_ringparam *param);
1177 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
1178 				struct ethtool_channels *ch);
1179 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
1180 			       struct ethtool_channels *ch);
1181 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
1182 			       struct ethtool_coalesce *coal,
1183 			       struct kernel_ethtool_coalesce *kernel_coal);
1184 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
1185 			       struct ethtool_coalesce *coal,
1186 			       struct kernel_ethtool_coalesce *kernel_coal,
1187 			       struct netlink_ext_ack *extack);
1188 int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv,
1189 				     struct ethtool_link_ksettings *link_ksettings);
1190 int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv,
1191 				     const struct ethtool_link_ksettings *link_ksettings);
1192 int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, u8 *hfunc);
1193 int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir, const u8 *key,
1194 		   const u8 hfunc);
1195 int mlx5e_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
1196 		    u32 *rule_locs);
1197 int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd);
1198 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv);
1199 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv);
1200 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1201 			      struct ethtool_ts_info *info);
1202 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1203 			       struct ethtool_flash *flash);
1204 void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv,
1205 				  struct ethtool_pauseparam *pauseparam);
1206 int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv,
1207 				 struct ethtool_pauseparam *pauseparam);
1208 
1209 /* mlx5e generic netdev management API */
1210 static inline bool
mlx5e_tx_mpwqe_supported(struct mlx5_core_dev * mdev)1211 mlx5e_tx_mpwqe_supported(struct mlx5_core_dev *mdev)
1212 {
1213 	return !is_kdump_kernel() &&
1214 		MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe);
1215 }
1216 
1217 int mlx5e_get_pf_num_tirs(struct mlx5_core_dev *mdev);
1218 int mlx5e_priv_init(struct mlx5e_priv *priv,
1219 		    const struct mlx5e_profile *profile,
1220 		    struct net_device *netdev,
1221 		    struct mlx5_core_dev *mdev);
1222 void mlx5e_priv_cleanup(struct mlx5e_priv *priv);
1223 struct net_device *
1224 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile);
1225 int mlx5e_attach_netdev(struct mlx5e_priv *priv);
1226 void mlx5e_detach_netdev(struct mlx5e_priv *priv);
1227 void mlx5e_destroy_netdev(struct mlx5e_priv *priv);
1228 int mlx5e_netdev_change_profile(struct mlx5e_priv *priv,
1229 				const struct mlx5e_profile *new_profile, void *new_ppriv);
1230 void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv);
1231 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv);
1232 void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu);
1233 void mlx5e_rx_dim_work(struct work_struct *work);
1234 void mlx5e_tx_dim_work(struct work_struct *work);
1235 
1236 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
1237 				       struct net_device *netdev,
1238 				       netdev_features_t features);
1239 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features);
1240 #ifdef CONFIG_MLX5_ESWITCH
1241 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac);
1242 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, int max_tx_rate);
1243 int mlx5e_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivi);
1244 int mlx5e_get_vf_stats(struct net_device *dev, int vf, struct ifla_vf_stats *vf_stats);
1245 #endif
1246 #endif /* __MLX5_EN_H__ */
1247