1 /*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc.
4 * ahennessy@mvista.com
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 * Copyright (C) 2000-2001 Toshiba Corporation
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 */
32 #include <linux/config.h>
33 #include <linux/init.h>
34
35 #include <linux/errno.h>
36 #include <linux/irq.h>
37 #include <linux/kernel_stat.h>
38 #include <linux/signal.h>
39 #include <linux/sched.h>
40 #include <linux/types.h>
41 #include <linux/interrupt.h>
42 #include <linux/ioport.h>
43 #include <linux/timex.h>
44 #include <linux/slab.h>
45 #include <linux/random.h>
46 #include <linux/smp.h>
47 #include <linux/smp_lock.h>
48
49 #include <asm/bitops.h>
50 #include <asm/io.h>
51 #include <asm/mipsregs.h>
52 #include <asm/system.h>
53
54 #include <asm/ptrace.h>
55 #include <asm/processor.h>
56 #include <asm/jmr3927/irq.h>
57 #include <asm/debug.h>
58 #include <asm/jmr3927/jmr3927.h>
59
60 #if JMR3927_IRQ_END > NR_IRQS
61 #error JMR3927_IRQ_END > NR_IRQS
62 #endif
63
64 struct tb_irq_space* tb_irq_spaces;
65
66 unsigned int local_bh_count[NR_CPUS];
67 unsigned int local_irq_count[NR_CPUS];
68
69 static int jmr3927_irq_base=-1;
70
71 #ifdef CONFIG_PCI
jmr3927_gen_iack(void)72 static int jmr3927_gen_iack(void)
73 {
74 /* generate ACK cycle */
75 #ifdef __BIG_ENDIAN
76 return (tx3927_pcicptr->iiadp >> 24) & 0xff;
77 #else
78 return tx3927_pcicptr->iiadp & 0xff;
79 #endif
80 }
81 #endif
82
83 extern asmlinkage void jmr3927_IRQ(void);
84
85 #define irc_dlevel 0
86 #define irc_elevel 1
87 static unsigned char irc_level[TX3927_NUM_IR] = {
88 5, 5, 5, 5, 5, 5, /* INT[5:0] */
89 7, 7, /* SIO */
90 5, 5, 5, 0, 0, /* DMA, PIO, PCI */
91 6, 6, 6 /* TMR */
92 };
93
mask_irq(unsigned int irq_nr)94 static inline void mask_irq(unsigned int irq_nr)
95 {
96 struct tb_irq_space* sp;
97 for (sp = tb_irq_spaces; sp; sp = sp->next) {
98 if (sp->start_irqno <= irq_nr &&
99 irq_nr < sp->start_irqno + sp->nr_irqs) {
100 if (sp->mask_func)
101 sp->mask_func(irq_nr - sp->start_irqno,
102 sp->space_id);
103 break;
104 }
105 }
106 }
107
unmask_irq(unsigned int irq_nr)108 static inline void unmask_irq(unsigned int irq_nr)
109 {
110 struct tb_irq_space* sp;
111 for (sp = tb_irq_spaces; sp; sp = sp->next) {
112 if (sp->start_irqno <= irq_nr &&
113 irq_nr < sp->start_irqno + sp->nr_irqs) {
114 if (sp->unmask_func)
115 sp->unmask_func(irq_nr - sp->start_irqno,
116 sp->space_id);
117 break;
118 }
119 }
120 }
121
122 static void jmr3927_irq_disable(unsigned int irq_nr);
123 static void jmr3927_irq_enable(unsigned int irq_nr);
124
jmr3927_irq_startup(unsigned int irq)125 static unsigned int jmr3927_irq_startup(unsigned int irq)
126 {
127 jmr3927_irq_enable(irq);
128 return 0;
129 }
130
131 #define jmr3927_irq_shutdown jmr3927_irq_disable
132
jmr3927_irq_ack(unsigned int irq)133 static void jmr3927_irq_ack(unsigned int irq)
134 {
135 db_assert(jmr3927_irq_base != -1);
136 db_assert(irq >= jmr3927_irq_base);
137 db_assert(irq < jmr3927_irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC);
138
139 if (irq == JMR3927_IRQ_IRC_TMR0) {
140 jmr3927_tmrptr->tisr = 0; /* ack interrupt */
141 }
142
143 jmr3927_irq_disable(irq);
144 }
145
jmr3927_irq_end(unsigned int irq)146 static void jmr3927_irq_end(unsigned int irq)
147 {
148 db_assert(jmr3927_irq_base != -1);
149 db_assert(irq >= jmr3927_irq_base);
150 db_assert(irq < jmr3927_irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC);
151
152 jmr3927_irq_enable(irq);
153 }
154
jmr3927_irq_disable(unsigned int irq_nr)155 static void jmr3927_irq_disable(unsigned int irq_nr)
156 {
157 unsigned long flags;
158
159 db_assert(jmr3927_irq_base != -1);
160 db_assert(irq >= jmr3927_irq_base);
161 db_assert(irq < jmr3927_irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC);
162
163 save_and_cli(flags);
164 mask_irq(irq_nr);
165 restore_flags(flags);
166 }
167
jmr3927_irq_enable(unsigned int irq_nr)168 static void jmr3927_irq_enable(unsigned int irq_nr)
169 {
170 unsigned long flags;
171
172 db_assert(jmr3927_irq_base != -1);
173 db_assert(irq >= jmr3927_irq_base);
174 db_assert(irq < jmr3927_irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC);
175
176 save_and_cli(flags);
177 unmask_irq(irq_nr);
178 restore_flags(flags);
179 }
180
181 /*
182 * CP0_STATUS is a thread's resource (saved/restored on context switch).
183 * So disable_irq/enable_irq MUST handle IOC/ISAC/IRC registers.
184 */
mask_irq_isac(int irq_nr,int space_id)185 static void mask_irq_isac(int irq_nr, int space_id)
186 {
187 /* 0: mask */
188 unsigned char imask =
189 jmr3927_isac_reg_in(JMR3927_ISAC_INTM_ADDR);
190 unsigned int bit = 1 << irq_nr;
191 jmr3927_isac_reg_out(imask & ~bit, JMR3927_ISAC_INTM_ADDR);
192 /* flush write buffer */
193 (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
194 }
unmask_irq_isac(int irq_nr,int space_id)195 static void unmask_irq_isac(int irq_nr, int space_id)
196 {
197 /* 0: mask */
198 unsigned char imask =
199 jmr3927_isac_reg_in(JMR3927_ISAC_INTM_ADDR);
200 unsigned int bit = 1 << irq_nr;
201 jmr3927_isac_reg_out(imask | bit, JMR3927_ISAC_INTM_ADDR);
202 /* flush write buffer */
203 (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
204 }
205
mask_irq_ioc(int irq_nr,int space_id)206 static void mask_irq_ioc(int irq_nr, int space_id)
207 {
208 /* 0: mask */
209 unsigned char imask =
210 jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
211 unsigned int bit = 1 << irq_nr;
212 jmr3927_ioc_reg_out(imask & ~bit, JMR3927_IOC_INTM_ADDR);
213 /* flush write buffer */
214 (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
215 }
unmask_irq_ioc(int irq_nr,int space_id)216 static void unmask_irq_ioc(int irq_nr, int space_id)
217 {
218 /* 0: mask */
219 unsigned char imask =
220 jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
221 unsigned int bit = 1 << irq_nr;
222 jmr3927_ioc_reg_out(imask | bit, JMR3927_IOC_INTM_ADDR);
223 /* flush write buffer */
224 (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
225 }
226
mask_irq_irc(int irq_nr,int space_id)227 static void mask_irq_irc(int irq_nr, int space_id)
228 {
229 volatile unsigned long *ilrp = &tx3927_ircptr->ilr[irq_nr / 2];
230 if (irq_nr & 1)
231 *ilrp = (*ilrp & 0x00ff) | (irc_dlevel << 8);
232 else
233 *ilrp = (*ilrp & 0xff00) | irc_dlevel;
234 /* update IRCSR */
235 tx3927_ircptr->imr = 0;
236 tx3927_ircptr->imr = irc_elevel;
237 }
unmask_irq_irc(int irq_nr,int space_id)238 static void unmask_irq_irc(int irq_nr, int space_id)
239 {
240 volatile unsigned long *ilrp = &tx3927_ircptr->ilr[irq_nr / 2];
241 if (irq_nr & 1)
242 *ilrp = (*ilrp & 0x00ff) | (irc_level[irq_nr] << 8);
243 else
244 *ilrp = (*ilrp & 0xff00) | irc_level[irq_nr];
245 /* update IRCSR */
246 tx3927_ircptr->imr = 0;
247 tx3927_ircptr->imr = irc_elevel;
248 }
249
250 struct tb_irq_space jmr3927_isac_irqspace = {
251 .next = NULL,
252 .start_irqno = JMR3927_IRQ_ISAC,
253 nr_irqs : JMR3927_NR_IRQ_ISAC,
254 .mask_func = mask_irq_isac,
255 .unmask_func = unmask_irq_isac,
256 .name = "ISAC",
257 .space_id = 0,
258 can_share : 0
259 };
260 struct tb_irq_space jmr3927_ioc_irqspace = {
261 .next = NULL,
262 .start_irqno = JMR3927_IRQ_IOC,
263 nr_irqs : JMR3927_NR_IRQ_IOC,
264 .mask_func = mask_irq_ioc,
265 .unmask_func = unmask_irq_ioc,
266 .name = "IOC",
267 .space_id = 0,
268 can_share : 1
269 };
270 struct tb_irq_space jmr3927_irc_irqspace = {
271 .next = NULL,
272 .start_irqno = JMR3927_IRQ_IRC,
273 nr_irqs : JMR3927_NR_IRQ_IRC,
274 .mask_func = mask_irq_irc,
275 .unmask_func = unmask_irq_irc,
276 .name = "on-chip",
277 .space_id = 0,
278 can_share : 0
279 };
280
jmr3927_spurious(struct pt_regs * regs)281 void jmr3927_spurious(struct pt_regs *regs)
282 {
283 #ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
284 tx_branch_likely_bug_fixup(regs);
285 #endif
286 printk(KERN_WARNING "spurious interrupt (cause 0x%lx, pc 0x%lx, ra 0x%lx).\n",
287 regs->cp0_cause, regs->cp0_epc, regs->regs[31]);
288 }
289
jmr3927_irc_irqdispatch(struct pt_regs * regs)290 void jmr3927_irc_irqdispatch(struct pt_regs *regs)
291 {
292 int irq;
293
294 #ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
295 tx_branch_likely_bug_fixup(regs);
296 #endif
297 if ((regs->cp0_cause & CAUSEF_IP7) == 0) {
298 #if 0
299 jmr3927_spurious(regs);
300 #endif
301 return;
302 }
303 irq = (regs->cp0_cause >> CAUSEB_IP2) & 0x0f;
304
305 do_IRQ(irq + JMR3927_IRQ_IRC, regs);
306 }
307
jmr3927_ioc_interrupt(int irq,void * dev_id,struct pt_regs * regs)308 static void jmr3927_ioc_interrupt(int irq, void *dev_id, struct pt_regs *regs)
309 {
310 unsigned char istat = jmr3927_ioc_reg_in(JMR3927_IOC_INTS2_ADDR);
311 int i;
312
313 for (i = 0; i < JMR3927_NR_IRQ_IOC; i++) {
314 if (istat & (1 << i)) {
315 irq = JMR3927_IRQ_IOC + i;
316 do_IRQ(irq, regs);
317 }
318 }
319 }
320
321 static struct irqaction ioc_action = {
322 jmr3927_ioc_interrupt, 0, 0, "IOC", NULL, NULL,
323 };
324
jmr3927_isac_interrupt(int irq,void * dev_id,struct pt_regs * regs)325 static void jmr3927_isac_interrupt(int irq, void *dev_id, struct pt_regs *regs)
326 {
327 unsigned char istat = jmr3927_isac_reg_in(JMR3927_ISAC_INTS2_ADDR);
328 int i;
329
330 for (i = 0; i < JMR3927_NR_IRQ_ISAC; i++) {
331 if (istat & (1 << i)) {
332 irq = JMR3927_IRQ_ISAC + i;
333 do_IRQ(irq, regs);
334 }
335 }
336 }
337
338 static struct irqaction isac_action = {
339 jmr3927_isac_interrupt, 0, 0, "ISAC", NULL, NULL,
340 };
341
342
jmr3927_isaerr_interrupt(int irq,void * dev_id,struct pt_regs * regs)343 static void jmr3927_isaerr_interrupt(int irq, void * dev_id, struct pt_regs * regs)
344 {
345 printk(KERN_WARNING "ISA error interrupt (irq 0x%x).\n", irq);
346 }
347 static struct irqaction isaerr_action = {
348 jmr3927_isaerr_interrupt, 0, 0, "ISA error", NULL, NULL,
349 };
350
jmr3927_pcierr_interrupt(int irq,void * dev_id,struct pt_regs * regs)351 static void jmr3927_pcierr_interrupt(int irq, void * dev_id, struct pt_regs * regs)
352 {
353 printk(KERN_WARNING "PCI error interrupt (irq 0x%x).\n", irq);
354 printk(KERN_WARNING "pcistat:%02x, lbstat:%04lx\n",
355 tx3927_pcicptr->pcistat, tx3927_pcicptr->lbstat);
356 }
357 static struct irqaction pcierr_action = {
358 jmr3927_pcierr_interrupt, 0, 0, "PCI error", NULL, NULL,
359 };
360
361 int jmr3927_ether1_irq = 0;
362
363 void jmr3927_irq_init(u32 irq_base);
jmr3927_irq_setup(void)364 void jmr3927_irq_setup(void)
365 {
366 /* look for io board's presence */
367 int have_isac = jmr3927_have_isac();
368
369 /* Now, interrupt control disabled, */
370 /* all IRC interrupts are masked, */
371 /* all IRC interrupt mode are Low Active. */
372
373 if (have_isac) {
374
375 /* ETHER1 (NE2000 compatible 10M-Ether) parameter setup */
376 /* temporary enable interrupt control */
377 tx3927_ircptr->cer = 1;
378 /* ETHER1 Int. Is High-Active. */
379 if (tx3927_ircptr->ssr & (1 << 0))
380 jmr3927_ether1_irq = JMR3927_IRQ_IRC_INT0;
381 #if 0 /* INT3 may be asserted by ether0 (even after reboot...) */
382 else if (tx3927_ircptr->ssr & (1 << 3))
383 jmr3927_ether1_irq = JMR3927_IRQ_IRC_INT3;
384 #endif
385 /* disable interrupt control */
386 tx3927_ircptr->cer = 0;
387
388 /* Ether1: High Active */
389 if (jmr3927_ether1_irq) {
390 int ether1_irc = jmr3927_ether1_irq - JMR3927_IRQ_IRC;
391 tx3927_ircptr->cr[ether1_irc / 8] |=
392 TX3927_IRCR_HIGH << ((ether1_irc % 8) * 2);
393 }
394 }
395
396 /* mask all IOC interrupts */
397 jmr3927_ioc_reg_out(0, JMR3927_IOC_INTM_ADDR);
398 /* setup IOC interrupt mode (SOFT:High Active, Others:Low Active) */
399 jmr3927_ioc_reg_out(JMR3927_IOC_INTF_SOFT, JMR3927_IOC_INTP_ADDR);
400
401 if (have_isac) {
402 /* mask all ISAC interrupts */
403 jmr3927_isac_reg_out(0, JMR3927_ISAC_INTM_ADDR);
404 /* setup ISAC interrupt mode (ISAIRQ3,ISAIRQ5:Low Active ???) */
405 jmr3927_isac_reg_out(JMR3927_ISAC_INTF_IRQ3|JMR3927_ISAC_INTF_IRQ5, JMR3927_ISAC_INTP_ADDR);
406 }
407
408 /* clear PCI Soft interrupts */
409 jmr3927_ioc_reg_out(0, JMR3927_IOC_INTS1_ADDR);
410 /* clear PCI Reset interrupts */
411 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
412
413 /* enable interrupt control */
414 tx3927_ircptr->cer = TX3927_IRCER_ICE;
415 tx3927_ircptr->imr = irc_elevel;
416
417 jmr3927_irq_init(NR_ISA_IRQS);
418
419 set_except_vector(0, jmr3927_IRQ);
420
421 /* setup irq space */
422 add_tb_irq_space(&jmr3927_isac_irqspace);
423 add_tb_irq_space(&jmr3927_ioc_irqspace);
424 add_tb_irq_space(&jmr3927_irc_irqspace);
425
426 /* setup IOC interrupt 1 (PCI, MODEM) */
427 setup_irq(JMR3927_IRQ_IOCINT, &ioc_action);
428
429 if (have_isac) {
430 setup_irq(JMR3927_IRQ_ISACINT, &isac_action);
431 setup_irq(JMR3927_IRQ_ISAC_ISAER, &isaerr_action);
432 }
433
434 #ifdef CONFIG_PCI
435 setup_irq(JMR3927_IRQ_IRC_PCI, &pcierr_action);
436 #endif
437
438 /* enable all CPU interrupt bits. */
439 set_c0_status(ST0_IM); /* IE bit is still 0. */
440 }
441
442 void (*irq_setup)(void);
init_IRQ(void)443 void __init init_IRQ(void)
444 {
445
446 #ifdef CONFIG_KGDB
447 extern void breakpoint(void);
448 extern void set_debug_traps(void);
449
450 puts("Wait for gdb client connection ...\n");
451 set_debug_traps();
452 breakpoint();
453 #endif
454
455 /* invoke board-specific irq setup */
456 irq_setup();
457 }
458
459 hw_irq_controller jmr3927_irq_controller = {
460 "jmr3927_irq",
461 jmr3927_irq_startup,
462 jmr3927_irq_shutdown,
463 jmr3927_irq_enable,
464 jmr3927_irq_disable,
465 jmr3927_irq_ack,
466 jmr3927_irq_end,
467 NULL /* no affinity stuff for UP */
468 };
469
470 void
jmr3927_irq_init(u32 irq_base)471 jmr3927_irq_init(u32 irq_base)
472 {
473 extern irq_desc_t irq_desc[];
474 u32 i;
475
476 for (i= irq_base; i< irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC; i++) {
477 irq_desc[i].status = IRQ_DISABLED;
478 irq_desc[i].action = NULL;
479 irq_desc[i].depth = 1;
480 irq_desc[i].handler = &jmr3927_irq_controller;
481 }
482
483 jmr3927_irq_base = irq_base;
484 }
485
486 #ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
487 static int tx_branch_likely_bug_count = 0;
488 static int have_tx_branch_likely_bug = 0;
tx_branch_likely_bug_fixup(struct pt_regs * regs)489 void tx_branch_likely_bug_fixup(struct pt_regs *regs)
490 {
491 /* TX39/49-BUG: Under this condition, the insn in delay slot
492 of the branch likely insn is executed (not nullified) even
493 the branch condition is false. */
494 if (!have_tx_branch_likely_bug)
495 return;
496 if ((regs->cp0_epc & 0xfff) == 0xffc &&
497 KSEGX(regs->cp0_epc) != KSEG0 &&
498 KSEGX(regs->cp0_epc) != KSEG1) {
499 unsigned int insn = *(unsigned int*)(regs->cp0_epc - 4);
500 /* beql,bnel,blezl,bgtzl */
501 /* bltzl,bgezl,blezall,bgezall */
502 /* bczfl, bcztl */
503 if ((insn & 0xf0000000) == 0x50000000 ||
504 (insn & 0xfc0e0000) == 0x04020000 ||
505 (insn & 0xf3fe0000) == 0x41020000) {
506 regs->cp0_epc -= 4;
507 tx_branch_likely_bug_count++;
508 printk(KERN_INFO
509 "fix branch-likery bug in %s (insn %08x)\n",
510 current->comm, insn);
511 }
512 }
513 }
514 #endif
515