1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * twl_core.c - driver for TWL4030/TWL5030/TWL60X0/TPS659x0 PM
4  * and audio CODEC devices
5  *
6  * Copyright (C) 2005-2006 Texas Instruments, Inc.
7  *
8  * Modifications to defer interrupt handling to a kernel thread:
9  * Copyright (C) 2006 MontaVista Software, Inc.
10  *
11  * Based on tlv320aic23.c:
12  * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
13  *
14  * Code cleanup and modifications to IRQ handler.
15  * by syed khasim <x0khasim@ti.com>
16  */
17 
18 #include <linux/init.h>
19 #include <linux/mutex.h>
20 #include <linux/platform_device.h>
21 #include <linux/regmap.h>
22 #include <linux/clk.h>
23 #include <linux/err.h>
24 #include <linux/device.h>
25 #include <linux/of.h>
26 #include <linux/of_irq.h>
27 #include <linux/of_platform.h>
28 #include <linux/irq.h>
29 #include <linux/irqdomain.h>
30 
31 #include <linux/regulator/machine.h>
32 
33 #include <linux/i2c.h>
34 #include <linux/mfd/twl.h>
35 
36 /* Register descriptions for audio */
37 #include <linux/mfd/twl4030-audio.h>
38 
39 #include "twl-core.h"
40 
41 /*
42  * The TWL4030 "Triton 2" is one of a family of a multi-function "Power
43  * Management and System Companion Device" chips originally designed for
44  * use in OMAP2 and OMAP 3 based systems.  Its control interfaces use I2C,
45  * often at around 3 Mbit/sec, including for interrupt handling.
46  *
47  * This driver core provides genirq support for the interrupts emitted,
48  * by the various modules, and exports register access primitives.
49  *
50  * FIXME this driver currently requires use of the first interrupt line
51  * (and associated registers).
52  */
53 
54 #define DRIVER_NAME			"twl"
55 
56 /* Triton Core internal information (BEGIN) */
57 
58 /* Base Address defns for twl4030_map[] */
59 
60 /* subchip/slave 0 - USB ID */
61 #define TWL4030_BASEADD_USB		0x0000
62 
63 /* subchip/slave 1 - AUD ID */
64 #define TWL4030_BASEADD_AUDIO_VOICE	0x0000
65 #define TWL4030_BASEADD_GPIO		0x0098
66 #define TWL4030_BASEADD_INTBR		0x0085
67 #define TWL4030_BASEADD_PIH		0x0080
68 #define TWL4030_BASEADD_TEST		0x004C
69 
70 /* subchip/slave 2 - AUX ID */
71 #define TWL4030_BASEADD_INTERRUPTS	0x00B9
72 #define TWL4030_BASEADD_LED		0x00EE
73 #define TWL4030_BASEADD_MADC		0x0000
74 #define TWL4030_BASEADD_MAIN_CHARGE	0x0074
75 #define TWL4030_BASEADD_PRECHARGE	0x00AA
76 #define TWL4030_BASEADD_PWM		0x00F8
77 #define TWL4030_BASEADD_KEYPAD		0x00D2
78 
79 #define TWL5031_BASEADD_ACCESSORY	0x0074 /* Replaces Main Charge */
80 #define TWL5031_BASEADD_INTERRUPTS	0x00B9 /* Different than TWL4030's
81 						  one */
82 
83 /* subchip/slave 3 - POWER ID */
84 #define TWL4030_BASEADD_BACKUP		0x0014
85 #define TWL4030_BASEADD_INT		0x002E
86 #define TWL4030_BASEADD_PM_MASTER	0x0036
87 
88 #define TWL4030_BASEADD_PM_RECEIVER	0x005B
89 #define TWL4030_DCDC_GLOBAL_CFG		0x06
90 #define SMARTREFLEX_ENABLE		BIT(3)
91 
92 #define TWL4030_BASEADD_RTC		0x001C
93 #define TWL4030_BASEADD_SECURED_REG	0x0000
94 
95 /* Triton Core internal information (END) */
96 
97 
98 /* subchip/slave 0 0x48 - POWER */
99 #define TWL6030_BASEADD_RTC		0x0000
100 #define TWL6030_BASEADD_SECURED_REG	0x0017
101 #define TWL6030_BASEADD_PM_MASTER	0x001F
102 #define TWL6030_BASEADD_PM_SLAVE_MISC	0x0030 /* PM_RECEIVER */
103 #define TWL6030_BASEADD_PM_MISC		0x00E2
104 #define TWL6030_BASEADD_PM_PUPD		0x00F0
105 
106 /* subchip/slave 1 0x49 - FEATURE */
107 #define TWL6030_BASEADD_USB		0x0000
108 #define TWL6030_BASEADD_GPADC_CTRL	0x002E
109 #define TWL6030_BASEADD_AUX		0x0090
110 #define TWL6030_BASEADD_PWM		0x00BA
111 #define TWL6030_BASEADD_GASGAUGE	0x00C0
112 #define TWL6030_BASEADD_PIH		0x00D0
113 #define TWL6032_BASEADD_CHARGER		0x00DA
114 #define TWL6030_BASEADD_CHARGER		0x00E0
115 #define TWL6030_BASEADD_LED		0x00F4
116 
117 /* subchip/slave 2 0x4A - DFT */
118 #define TWL6030_BASEADD_DIEID		0x00C0
119 
120 /* subchip/slave 3 0x4B - AUDIO */
121 #define TWL6030_BASEADD_AUDIO		0x0000
122 #define TWL6030_BASEADD_RSV		0x0000
123 #define TWL6030_BASEADD_ZERO		0x0000
124 
125 /* Few power values */
126 #define R_CFG_BOOT			0x05
127 
128 /* some fields in R_CFG_BOOT */
129 #define HFCLK_FREQ_19p2_MHZ		(1 << 0)
130 #define HFCLK_FREQ_26_MHZ		(2 << 0)
131 #define HFCLK_FREQ_38p4_MHZ		(3 << 0)
132 #define HIGH_PERF_SQ			(1 << 3)
133 #define CK32K_LOWPWR_EN			(1 << 7)
134 
135 /*----------------------------------------------------------------------*/
136 
137 /* Structure for each TWL4030/TWL6030 Slave */
138 struct twl_client {
139 	struct i2c_client *client;
140 	struct regmap *regmap;
141 };
142 
143 /* mapping the module id to slave id and base address */
144 struct twl_mapping {
145 	unsigned char sid;	/* Slave ID */
146 	unsigned char base;	/* base address */
147 };
148 
149 struct twl_private {
150 	bool ready; /* The core driver is ready to be used */
151 	u32 twl_idcode; /* TWL IDCODE Register value */
152 	unsigned int twl_id;
153 
154 	struct twl_mapping *twl_map;
155 	struct twl_client *twl_modules;
156 };
157 
158 static struct twl_private *twl_priv;
159 
160 static struct twl_mapping twl4030_map[] = {
161 	/*
162 	 * NOTE:  don't change this table without updating the
163 	 * <linux/mfd/twl.h> defines for TWL4030_MODULE_*
164 	 * so they continue to match the order in this table.
165 	 */
166 
167 	/* Common IPs */
168 	{ 0, TWL4030_BASEADD_USB },
169 	{ 1, TWL4030_BASEADD_PIH },
170 	{ 2, TWL4030_BASEADD_MAIN_CHARGE },
171 	{ 3, TWL4030_BASEADD_PM_MASTER },
172 	{ 3, TWL4030_BASEADD_PM_RECEIVER },
173 
174 	{ 3, TWL4030_BASEADD_RTC },
175 	{ 2, TWL4030_BASEADD_PWM },
176 	{ 2, TWL4030_BASEADD_LED },
177 	{ 3, TWL4030_BASEADD_SECURED_REG },
178 
179 	/* TWL4030 specific IPs */
180 	{ 1, TWL4030_BASEADD_AUDIO_VOICE },
181 	{ 1, TWL4030_BASEADD_GPIO },
182 	{ 1, TWL4030_BASEADD_INTBR },
183 	{ 1, TWL4030_BASEADD_TEST },
184 	{ 2, TWL4030_BASEADD_KEYPAD },
185 
186 	{ 2, TWL4030_BASEADD_MADC },
187 	{ 2, TWL4030_BASEADD_INTERRUPTS },
188 	{ 2, TWL4030_BASEADD_PRECHARGE },
189 	{ 3, TWL4030_BASEADD_BACKUP },
190 	{ 3, TWL4030_BASEADD_INT },
191 
192 	{ 2, TWL5031_BASEADD_ACCESSORY },
193 	{ 2, TWL5031_BASEADD_INTERRUPTS },
194 };
195 
196 static const struct reg_default twl4030_49_defaults[] = {
197 	/* Audio Registers */
198 	{ 0x01, 0x00}, /* CODEC_MODE	*/
199 	{ 0x02, 0x00}, /* OPTION	*/
200 	/* 0x03  Unused	*/
201 	{ 0x04, 0x00}, /* MICBIAS_CTL	*/
202 	{ 0x05, 0x00}, /* ANAMICL	*/
203 	{ 0x06, 0x00}, /* ANAMICR	*/
204 	{ 0x07, 0x00}, /* AVADC_CTL	*/
205 	{ 0x08, 0x00}, /* ADCMICSEL	*/
206 	{ 0x09, 0x00}, /* DIGMIXING	*/
207 	{ 0x0a, 0x0f}, /* ATXL1PGA	*/
208 	{ 0x0b, 0x0f}, /* ATXR1PGA	*/
209 	{ 0x0c, 0x0f}, /* AVTXL2PGA	*/
210 	{ 0x0d, 0x0f}, /* AVTXR2PGA	*/
211 	{ 0x0e, 0x00}, /* AUDIO_IF	*/
212 	{ 0x0f, 0x00}, /* VOICE_IF	*/
213 	{ 0x10, 0x3f}, /* ARXR1PGA	*/
214 	{ 0x11, 0x3f}, /* ARXL1PGA	*/
215 	{ 0x12, 0x3f}, /* ARXR2PGA	*/
216 	{ 0x13, 0x3f}, /* ARXL2PGA	*/
217 	{ 0x14, 0x25}, /* VRXPGA	*/
218 	{ 0x15, 0x00}, /* VSTPGA	*/
219 	{ 0x16, 0x00}, /* VRX2ARXPGA	*/
220 	{ 0x17, 0x00}, /* AVDAC_CTL	*/
221 	{ 0x18, 0x00}, /* ARX2VTXPGA	*/
222 	{ 0x19, 0x32}, /* ARXL1_APGA_CTL*/
223 	{ 0x1a, 0x32}, /* ARXR1_APGA_CTL*/
224 	{ 0x1b, 0x32}, /* ARXL2_APGA_CTL*/
225 	{ 0x1c, 0x32}, /* ARXR2_APGA_CTL*/
226 	{ 0x1d, 0x00}, /* ATX2ARXPGA	*/
227 	{ 0x1e, 0x00}, /* BT_IF		*/
228 	{ 0x1f, 0x55}, /* BTPGA		*/
229 	{ 0x20, 0x00}, /* BTSTPGA	*/
230 	{ 0x21, 0x00}, /* EAR_CTL	*/
231 	{ 0x22, 0x00}, /* HS_SEL	*/
232 	{ 0x23, 0x00}, /* HS_GAIN_SET	*/
233 	{ 0x24, 0x00}, /* HS_POPN_SET	*/
234 	{ 0x25, 0x00}, /* PREDL_CTL	*/
235 	{ 0x26, 0x00}, /* PREDR_CTL	*/
236 	{ 0x27, 0x00}, /* PRECKL_CTL	*/
237 	{ 0x28, 0x00}, /* PRECKR_CTL	*/
238 	{ 0x29, 0x00}, /* HFL_CTL	*/
239 	{ 0x2a, 0x00}, /* HFR_CTL	*/
240 	{ 0x2b, 0x05}, /* ALC_CTL	*/
241 	{ 0x2c, 0x00}, /* ALC_SET1	*/
242 	{ 0x2d, 0x00}, /* ALC_SET2	*/
243 	{ 0x2e, 0x00}, /* BOOST_CTL	*/
244 	{ 0x2f, 0x00}, /* SOFTVOL_CTL	*/
245 	{ 0x30, 0x13}, /* DTMF_FREQSEL	*/
246 	{ 0x31, 0x00}, /* DTMF_TONEXT1H	*/
247 	{ 0x32, 0x00}, /* DTMF_TONEXT1L	*/
248 	{ 0x33, 0x00}, /* DTMF_TONEXT2H	*/
249 	{ 0x34, 0x00}, /* DTMF_TONEXT2L	*/
250 	{ 0x35, 0x79}, /* DTMF_TONOFF	*/
251 	{ 0x36, 0x11}, /* DTMF_WANONOFF	*/
252 	{ 0x37, 0x00}, /* I2S_RX_SCRAMBLE_H */
253 	{ 0x38, 0x00}, /* I2S_RX_SCRAMBLE_M */
254 	{ 0x39, 0x00}, /* I2S_RX_SCRAMBLE_L */
255 	{ 0x3a, 0x06}, /* APLL_CTL */
256 	{ 0x3b, 0x00}, /* DTMF_CTL */
257 	{ 0x3c, 0x44}, /* DTMF_PGA_CTL2	(0x3C) */
258 	{ 0x3d, 0x69}, /* DTMF_PGA_CTL1	(0x3D) */
259 	{ 0x3e, 0x00}, /* MISC_SET_1 */
260 	{ 0x3f, 0x00}, /* PCMBTMUX */
261 	/* 0x40 - 0x42  Unused */
262 	{ 0x43, 0x00}, /* RX_PATH_SEL */
263 	{ 0x44, 0x32}, /* VDL_APGA_CTL */
264 	{ 0x45, 0x00}, /* VIBRA_CTL */
265 	{ 0x46, 0x00}, /* VIBRA_SET */
266 	{ 0x47, 0x00}, /* VIBRA_PWM_SET	*/
267 	{ 0x48, 0x00}, /* ANAMIC_GAIN	*/
268 	{ 0x49, 0x00}, /* MISC_SET_2	*/
269 	/* End of Audio Registers */
270 };
271 
twl4030_49_nop_reg(struct device * dev,unsigned int reg)272 static bool twl4030_49_nop_reg(struct device *dev, unsigned int reg)
273 {
274 	switch (reg) {
275 	case 0x00:
276 	case 0x03:
277 	case 0x40:
278 	case 0x41:
279 	case 0x42:
280 		return false;
281 	default:
282 		return true;
283 	}
284 }
285 
286 static const struct regmap_range twl4030_49_volatile_ranges[] = {
287 	regmap_reg_range(TWL4030_BASEADD_TEST, 0xff),
288 };
289 
290 static const struct regmap_access_table twl4030_49_volatile_table = {
291 	.yes_ranges = twl4030_49_volatile_ranges,
292 	.n_yes_ranges = ARRAY_SIZE(twl4030_49_volatile_ranges),
293 };
294 
295 static const struct regmap_config twl4030_regmap_config[4] = {
296 	{
297 		/* Address 0x48 */
298 		.reg_bits = 8,
299 		.val_bits = 8,
300 		.max_register = 0xff,
301 	},
302 	{
303 		/* Address 0x49 */
304 		.reg_bits = 8,
305 		.val_bits = 8,
306 		.max_register = 0xff,
307 
308 		.readable_reg = twl4030_49_nop_reg,
309 		.writeable_reg = twl4030_49_nop_reg,
310 
311 		.volatile_table = &twl4030_49_volatile_table,
312 
313 		.reg_defaults = twl4030_49_defaults,
314 		.num_reg_defaults = ARRAY_SIZE(twl4030_49_defaults),
315 		.cache_type = REGCACHE_RBTREE,
316 	},
317 	{
318 		/* Address 0x4a */
319 		.reg_bits = 8,
320 		.val_bits = 8,
321 		.max_register = 0xff,
322 	},
323 	{
324 		/* Address 0x4b */
325 		.reg_bits = 8,
326 		.val_bits = 8,
327 		.max_register = 0xff,
328 	},
329 };
330 
331 static struct twl_mapping twl6030_map[] = {
332 	/*
333 	 * NOTE:  don't change this table without updating the
334 	 * <linux/mfd/twl.h> defines for TWL4030_MODULE_*
335 	 * so they continue to match the order in this table.
336 	 */
337 
338 	/* Common IPs */
339 	{ 1, TWL6030_BASEADD_USB },
340 	{ 1, TWL6030_BASEADD_PIH },
341 	{ 1, TWL6030_BASEADD_CHARGER },
342 	{ 0, TWL6030_BASEADD_PM_MASTER },
343 	{ 0, TWL6030_BASEADD_PM_SLAVE_MISC },
344 
345 	{ 0, TWL6030_BASEADD_RTC },
346 	{ 1, TWL6030_BASEADD_PWM },
347 	{ 1, TWL6030_BASEADD_LED },
348 	{ 0, TWL6030_BASEADD_SECURED_REG },
349 
350 	/* TWL6030 specific IPs */
351 	{ 0, TWL6030_BASEADD_ZERO },
352 	{ 1, TWL6030_BASEADD_ZERO },
353 	{ 2, TWL6030_BASEADD_ZERO },
354 	{ 1, TWL6030_BASEADD_GPADC_CTRL },
355 	{ 1, TWL6030_BASEADD_GASGAUGE },
356 
357 	/* TWL6032 specific charger registers */
358 	{ 1, TWL6032_BASEADD_CHARGER },
359 };
360 
361 static const struct regmap_config twl6030_regmap_config[3] = {
362 	{
363 		/* Address 0x48 */
364 		.reg_bits = 8,
365 		.val_bits = 8,
366 		.max_register = 0xff,
367 	},
368 	{
369 		/* Address 0x49 */
370 		.reg_bits = 8,
371 		.val_bits = 8,
372 		.max_register = 0xff,
373 	},
374 	{
375 		/* Address 0x4a */
376 		.reg_bits = 8,
377 		.val_bits = 8,
378 		.max_register = 0xff,
379 	},
380 };
381 
382 /*----------------------------------------------------------------------*/
383 
twl_get_num_slaves(void)384 static inline int twl_get_num_slaves(void)
385 {
386 	if (twl_class_is_4030())
387 		return 4; /* TWL4030 class have four slave address */
388 	else
389 		return 3; /* TWL6030 class have three slave address */
390 }
391 
twl_get_last_module(void)392 static inline int twl_get_last_module(void)
393 {
394 	if (twl_class_is_4030())
395 		return TWL4030_MODULE_LAST;
396 	else
397 		return TWL6030_MODULE_LAST;
398 }
399 
400 /* Exported Functions */
401 
twl_rev(void)402 unsigned int twl_rev(void)
403 {
404 	return twl_priv ? twl_priv->twl_id : 0;
405 }
406 EXPORT_SYMBOL(twl_rev);
407 
408 /**
409  * twl_get_regmap - Get the regmap associated with the given module
410  * @mod_no: module number
411  *
412  * Returns the regmap pointer or NULL in case of failure.
413  */
twl_get_regmap(u8 mod_no)414 static struct regmap *twl_get_regmap(u8 mod_no)
415 {
416 	int sid;
417 	struct twl_client *twl;
418 
419 	if (unlikely(!twl_priv || !twl_priv->ready)) {
420 		pr_err("%s: not initialized\n", DRIVER_NAME);
421 		return NULL;
422 	}
423 	if (unlikely(mod_no >= twl_get_last_module())) {
424 		pr_err("%s: invalid module number %d\n", DRIVER_NAME, mod_no);
425 		return NULL;
426 	}
427 
428 	sid = twl_priv->twl_map[mod_no].sid;
429 	twl = &twl_priv->twl_modules[sid];
430 
431 	return twl->regmap;
432 }
433 
434 /**
435  * twl_i2c_write - Writes a n bit register in TWL4030/TWL5030/TWL60X0
436  * @mod_no: module number
437  * @value: an array of num_bytes+1 containing data to write
438  * @reg: register address (just offset will do)
439  * @num_bytes: number of bytes to transfer
440  *
441  * Returns 0 on success or else a negative error code.
442  */
twl_i2c_write(u8 mod_no,u8 * value,u8 reg,unsigned num_bytes)443 int twl_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes)
444 {
445 	struct regmap *regmap = twl_get_regmap(mod_no);
446 	int ret;
447 
448 	if (!regmap)
449 		return -EPERM;
450 
451 	ret = regmap_bulk_write(regmap, twl_priv->twl_map[mod_no].base + reg,
452 				value, num_bytes);
453 
454 	if (ret)
455 		pr_err("%s: Write failed (mod %d, reg 0x%02x count %d)\n",
456 		       DRIVER_NAME, mod_no, reg, num_bytes);
457 
458 	return ret;
459 }
460 EXPORT_SYMBOL(twl_i2c_write);
461 
462 /**
463  * twl_i2c_read - Reads a n bit register in TWL4030/TWL5030/TWL60X0
464  * @mod_no: module number
465  * @value: an array of num_bytes containing data to be read
466  * @reg: register address (just offset will do)
467  * @num_bytes: number of bytes to transfer
468  *
469  * Returns 0 on success or else a negative error code.
470  */
twl_i2c_read(u8 mod_no,u8 * value,u8 reg,unsigned num_bytes)471 int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes)
472 {
473 	struct regmap *regmap = twl_get_regmap(mod_no);
474 	int ret;
475 
476 	if (!regmap)
477 		return -EPERM;
478 
479 	ret = regmap_bulk_read(regmap, twl_priv->twl_map[mod_no].base + reg,
480 			       value, num_bytes);
481 
482 	if (ret)
483 		pr_err("%s: Read failed (mod %d, reg 0x%02x count %d)\n",
484 		       DRIVER_NAME, mod_no, reg, num_bytes);
485 
486 	return ret;
487 }
488 EXPORT_SYMBOL(twl_i2c_read);
489 
490 /**
491  * twl_set_regcache_bypass - Configure the regcache bypass for the regmap associated
492  *			 with the module
493  * @mod_no: module number
494  * @enable: Regcache bypass state
495  *
496  * Returns 0 else failure.
497  */
twl_set_regcache_bypass(u8 mod_no,bool enable)498 int twl_set_regcache_bypass(u8 mod_no, bool enable)
499 {
500 	struct regmap *regmap = twl_get_regmap(mod_no);
501 
502 	if (!regmap)
503 		return -EPERM;
504 
505 	regcache_cache_bypass(regmap, enable);
506 
507 	return 0;
508 }
509 EXPORT_SYMBOL(twl_set_regcache_bypass);
510 
511 /*----------------------------------------------------------------------*/
512 
513 /**
514  * twl_read_idcode_register - API to read the IDCODE register.
515  *
516  * Unlocks the IDCODE register and read the 32 bit value.
517  */
twl_read_idcode_register(void)518 static int twl_read_idcode_register(void)
519 {
520 	int err;
521 
522 	err = twl_i2c_write_u8(TWL4030_MODULE_INTBR, TWL_EEPROM_R_UNLOCK,
523 						REG_UNLOCK_TEST_REG);
524 	if (err) {
525 		pr_err("TWL4030 Unable to unlock IDCODE registers -%d\n", err);
526 		goto fail;
527 	}
528 
529 	err = twl_i2c_read(TWL4030_MODULE_INTBR, (u8 *)(&twl_priv->twl_idcode),
530 						REG_IDCODE_7_0, 4);
531 	if (err) {
532 		pr_err("TWL4030: unable to read IDCODE -%d\n", err);
533 		goto fail;
534 	}
535 
536 	err = twl_i2c_write_u8(TWL4030_MODULE_INTBR, 0x0, REG_UNLOCK_TEST_REG);
537 	if (err)
538 		pr_err("TWL4030 Unable to relock IDCODE registers -%d\n", err);
539 fail:
540 	return err;
541 }
542 
543 /**
544  * twl_get_type - API to get TWL Si type.
545  *
546  * Api to get the TWL Si type from IDCODE value.
547  */
twl_get_type(void)548 int twl_get_type(void)
549 {
550 	return TWL_SIL_TYPE(twl_priv->twl_idcode);
551 }
552 EXPORT_SYMBOL_GPL(twl_get_type);
553 
554 /**
555  * twl_get_version - API to get TWL Si version.
556  *
557  * Api to get the TWL Si version from IDCODE value.
558  */
twl_get_version(void)559 int twl_get_version(void)
560 {
561 	return TWL_SIL_REV(twl_priv->twl_idcode);
562 }
563 EXPORT_SYMBOL_GPL(twl_get_version);
564 
565 /**
566  * twl_get_hfclk_rate - API to get TWL external HFCLK clock rate.
567  *
568  * Api to get the TWL HFCLK rate based on BOOT_CFG register.
569  */
twl_get_hfclk_rate(void)570 int twl_get_hfclk_rate(void)
571 {
572 	u8 ctrl;
573 	int rate;
574 
575 	twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &ctrl, R_CFG_BOOT);
576 
577 	switch (ctrl & 0x3) {
578 	case HFCLK_FREQ_19p2_MHZ:
579 		rate = 19200000;
580 		break;
581 	case HFCLK_FREQ_26_MHZ:
582 		rate = 26000000;
583 		break;
584 	case HFCLK_FREQ_38p4_MHZ:
585 		rate = 38400000;
586 		break;
587 	default:
588 		pr_err("TWL4030: HFCLK is not configured\n");
589 		rate = -EINVAL;
590 		break;
591 	}
592 
593 	return rate;
594 }
595 EXPORT_SYMBOL_GPL(twl_get_hfclk_rate);
596 
597 /*----------------------------------------------------------------------*/
598 
599 /*
600  * These three functions initialize the on-chip clock framework,
601  * letting it generate the right frequencies for USB, MADC, and
602  * other purposes.
603  */
protect_pm_master(void)604 static inline int protect_pm_master(void)
605 {
606 	int e = 0;
607 
608 	e = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0,
609 			     TWL4030_PM_MASTER_PROTECT_KEY);
610 	return e;
611 }
612 
unprotect_pm_master(void)613 static inline int unprotect_pm_master(void)
614 {
615 	int e = 0;
616 
617 	e |= twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1,
618 			      TWL4030_PM_MASTER_PROTECT_KEY);
619 	e |= twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG2,
620 			      TWL4030_PM_MASTER_PROTECT_KEY);
621 
622 	return e;
623 }
624 
clocks_init(struct device * dev)625 static void clocks_init(struct device *dev)
626 {
627 	int e = 0;
628 	struct clk *osc;
629 	u32 rate;
630 	u8 ctrl = HFCLK_FREQ_26_MHZ;
631 
632 	osc = clk_get(dev, "fck");
633 	if (IS_ERR(osc)) {
634 		printk(KERN_WARNING "Skipping twl internal clock init and "
635 				"using bootloader value (unknown osc rate)\n");
636 		return;
637 	}
638 
639 	rate = clk_get_rate(osc);
640 	clk_put(osc);
641 
642 	switch (rate) {
643 	case 19200000:
644 		ctrl = HFCLK_FREQ_19p2_MHZ;
645 		break;
646 	case 26000000:
647 		ctrl = HFCLK_FREQ_26_MHZ;
648 		break;
649 	case 38400000:
650 		ctrl = HFCLK_FREQ_38p4_MHZ;
651 		break;
652 	}
653 
654 	ctrl |= HIGH_PERF_SQ;
655 
656 	e |= unprotect_pm_master();
657 	/* effect->MADC+USB ck en */
658 	e |= twl_i2c_write_u8(TWL_MODULE_PM_MASTER, ctrl, R_CFG_BOOT);
659 	e |= protect_pm_master();
660 
661 	if (e < 0)
662 		pr_err("%s: clock init err [%d]\n", DRIVER_NAME, e);
663 }
664 
665 /*----------------------------------------------------------------------*/
666 
667 
twl_remove(struct i2c_client * client)668 static void twl_remove(struct i2c_client *client)
669 {
670 	unsigned i, num_slaves;
671 
672 	if (twl_class_is_4030())
673 		twl4030_exit_irq();
674 	else
675 		twl6030_exit_irq();
676 
677 	num_slaves = twl_get_num_slaves();
678 	for (i = 0; i < num_slaves; i++) {
679 		struct twl_client	*twl = &twl_priv->twl_modules[i];
680 
681 		if (twl->client && twl->client != client)
682 			i2c_unregister_device(twl->client);
683 		twl->client = NULL;
684 	}
685 	twl_priv->ready = false;
686 }
687 
688 static struct of_dev_auxdata twl_auxdata_lookup[] = {
689 	OF_DEV_AUXDATA("ti,twl4030-gpio", 0, "twl4030-gpio", NULL),
690 	{ /* sentinel */ },
691 };
692 
693 /* NOTE: This driver only handles a single twl4030/tps659x0 chip */
694 static int
twl_probe(struct i2c_client * client)695 twl_probe(struct i2c_client *client)
696 {
697 	const struct i2c_device_id *id = i2c_client_get_device_id(client);
698 	struct device_node		*node = client->dev.of_node;
699 	struct platform_device		*pdev;
700 	const struct regmap_config	*twl_regmap_config;
701 	int				irq_base = 0;
702 	int				status;
703 	unsigned			i, num_slaves;
704 
705 	if (!node) {
706 		dev_err(&client->dev, "no platform data\n");
707 		return -EINVAL;
708 	}
709 
710 	if (twl_priv) {
711 		dev_dbg(&client->dev, "only one instance of %s allowed\n",
712 			DRIVER_NAME);
713 		return -EBUSY;
714 	}
715 
716 	pdev = platform_device_alloc(DRIVER_NAME, -1);
717 	if (!pdev) {
718 		dev_err(&client->dev, "can't alloc pdev\n");
719 		return -ENOMEM;
720 	}
721 
722 	status = platform_device_add(pdev);
723 	if (status) {
724 		platform_device_put(pdev);
725 		return status;
726 	}
727 
728 	if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C) == 0) {
729 		dev_dbg(&client->dev, "can't talk I2C?\n");
730 		status = -EIO;
731 		goto free;
732 	}
733 
734 	twl_priv = devm_kzalloc(&client->dev, sizeof(struct twl_private),
735 				GFP_KERNEL);
736 	if (!twl_priv) {
737 		status = -ENOMEM;
738 		goto free;
739 	}
740 
741 	if ((id->driver_data) & TWL6030_CLASS) {
742 		twl_priv->twl_id = TWL6030_CLASS_ID;
743 		twl_priv->twl_map = &twl6030_map[0];
744 		twl_regmap_config = twl6030_regmap_config;
745 	} else {
746 		twl_priv->twl_id = TWL4030_CLASS_ID;
747 		twl_priv->twl_map = &twl4030_map[0];
748 		twl_regmap_config = twl4030_regmap_config;
749 	}
750 
751 	num_slaves = twl_get_num_slaves();
752 	twl_priv->twl_modules = devm_kcalloc(&client->dev,
753 					 num_slaves,
754 					 sizeof(struct twl_client),
755 					 GFP_KERNEL);
756 	if (!twl_priv->twl_modules) {
757 		status = -ENOMEM;
758 		goto free;
759 	}
760 
761 	for (i = 0; i < num_slaves; i++) {
762 		struct twl_client *twl = &twl_priv->twl_modules[i];
763 
764 		if (i == 0) {
765 			twl->client = client;
766 		} else {
767 			twl->client = i2c_new_dummy_device(client->adapter,
768 						    client->addr + i);
769 			if (IS_ERR(twl->client)) {
770 				dev_err(&client->dev,
771 					"can't attach client %d\n", i);
772 				status = PTR_ERR(twl->client);
773 				goto fail;
774 			}
775 		}
776 
777 		twl->regmap = devm_regmap_init_i2c(twl->client,
778 						   &twl_regmap_config[i]);
779 		if (IS_ERR(twl->regmap)) {
780 			status = PTR_ERR(twl->regmap);
781 			dev_err(&client->dev,
782 				"Failed to allocate regmap %d, err: %d\n", i,
783 				status);
784 			goto fail;
785 		}
786 	}
787 
788 	twl_priv->ready = true;
789 
790 	/* setup clock framework */
791 	clocks_init(&client->dev);
792 
793 	/* read TWL IDCODE Register */
794 	if (twl_class_is_4030()) {
795 		status = twl_read_idcode_register();
796 		WARN(status < 0, "Error: reading twl_idcode register value\n");
797 	}
798 
799 	/* Maybe init the T2 Interrupt subsystem */
800 	if (client->irq) {
801 		if (twl_class_is_4030()) {
802 			twl4030_init_chip_irq(id->name);
803 			irq_base = twl4030_init_irq(&client->dev, client->irq);
804 		} else {
805 			irq_base = twl6030_init_irq(&client->dev, client->irq);
806 		}
807 
808 		if (irq_base < 0) {
809 			status = irq_base;
810 			goto fail;
811 		}
812 	}
813 
814 	/*
815 	 * Disable TWL4030/TWL5030 I2C Pull-up on I2C1 and I2C4(SR) interface.
816 	 * Program I2C_SCL_CTRL_PU(bit 0)=0, I2C_SDA_CTRL_PU (bit 2)=0,
817 	 * SR_I2C_SCL_CTRL_PU(bit 4)=0 and SR_I2C_SDA_CTRL_PU(bit 6)=0.
818 	 *
819 	 * Also, always enable SmartReflex bit as that's needed for omaps to
820 	 * do anything over I2C4 for voltage scaling even if SmartReflex
821 	 * is disabled. Without the SmartReflex bit omap sys_clkreq idle
822 	 * signal will never trigger for retention idle.
823 	 */
824 	if (twl_class_is_4030()) {
825 		u8 temp;
826 
827 		twl_i2c_read_u8(TWL4030_MODULE_INTBR, &temp, REG_GPPUPDCTR1);
828 		temp &= ~(SR_I2C_SDA_CTRL_PU | SR_I2C_SCL_CTRL_PU | \
829 			I2C_SDA_CTRL_PU | I2C_SCL_CTRL_PU);
830 		twl_i2c_write_u8(TWL4030_MODULE_INTBR, temp, REG_GPPUPDCTR1);
831 
832 		twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &temp,
833 				TWL4030_DCDC_GLOBAL_CFG);
834 		temp |= SMARTREFLEX_ENABLE;
835 		twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, temp,
836 				 TWL4030_DCDC_GLOBAL_CFG);
837 	}
838 
839 	status = of_platform_populate(node, NULL, twl_auxdata_lookup,
840 				      &client->dev);
841 
842 fail:
843 	if (status < 0)
844 		twl_remove(client);
845 free:
846 	if (status < 0)
847 		platform_device_unregister(pdev);
848 
849 	return status;
850 }
851 
twl_suspend(struct device * dev)852 static int __maybe_unused twl_suspend(struct device *dev)
853 {
854 	struct i2c_client *client = to_i2c_client(dev);
855 
856 	if (client->irq)
857 		disable_irq(client->irq);
858 
859 	return 0;
860 }
861 
twl_resume(struct device * dev)862 static int __maybe_unused twl_resume(struct device *dev)
863 {
864 	struct i2c_client *client = to_i2c_client(dev);
865 
866 	if (client->irq)
867 		enable_irq(client->irq);
868 
869 	return 0;
870 }
871 
872 static SIMPLE_DEV_PM_OPS(twl_dev_pm_ops, twl_suspend, twl_resume);
873 
874 static const struct i2c_device_id twl_ids[] = {
875 	{ "twl4030", TWL4030_VAUX2 },	/* "Triton 2" */
876 	{ "twl5030", 0 },		/* T2 updated */
877 	{ "twl5031", TWL5031 },		/* TWL5030 updated */
878 	{ "tps65950", 0 },		/* catalog version of twl5030 */
879 	{ "tps65930", TPS_SUBSET },	/* fewer LDOs and DACs; no charger */
880 	{ "tps65920", TPS_SUBSET },	/* fewer LDOs; no codec or charger */
881 	{ "tps65921", TPS_SUBSET },	/* fewer LDOs; no codec, no LED
882 					   and vibrator. Charger in USB module*/
883 	{ "twl6030", TWL6030_CLASS },	/* "Phoenix power chip" */
884 	{ "twl6032", TWL6030_CLASS | TWL6032_SUBCLASS }, /* "Phoenix lite" */
885 	{ /* end of list */ },
886 };
887 
888 /* One Client Driver , 4 Clients */
889 static struct i2c_driver twl_driver = {
890 	.driver.name	= DRIVER_NAME,
891 	.driver.pm	= &twl_dev_pm_ops,
892 	.id_table	= twl_ids,
893 	.probe		= twl_probe,
894 	.remove		= twl_remove,
895 };
896 builtin_i2c_driver(twl_driver);
897