1 /* 2 * epson1356fb.h -- Epson SED1356 Framebuffer Driver 3 * 4 * Copyright 2001, 2002, 2003 MontaVista Software Inc. 5 * Author: MontaVista Software, Inc. 6 * stevel@mvista.com or source@mvista.com 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 * 24 * You should have received a copy of the GNU General Public License along 25 * with this program; if not, write to the Free Software Foundation, Inc., 26 * 675 Mass Ave, Cambridge, MA 02139, USA. 27 * 28 */ 29 30 #ifdef E1356FB_DEBUG 31 #define DPRINTK(a,b...) printk(KERN_DEBUG "e1356fb: %s: " a, __FUNCTION__ , ## b) 32 #else 33 #define DPRINTK(a,b...) 34 #endif 35 36 #define E1356_REG_SIZE 0x200000 37 38 #define PICOS2KHZ(a) (1000000000UL/(a)) 39 #define KHZ2PICOS(a) (1000000000UL/(a)) 40 41 #define MAX_PIXCLOCK 40000 // KHz 42 #define NTSC_PIXCLOCK 14318 // KHz 43 #define PAL_PIXCLOCK 17734 // KHz 44 45 /* 46 * Maximum percent errors between desired pixel clock and 47 * supported pixel clock. Lower-than and higher-than desired 48 * clock percent errors. 49 */ 50 #define MAX_PCLK_ERROR_LOWER 10 51 #define MAX_PCLK_ERROR_HIGHER -1 52 53 #define fontwidth_x8(p) (((fontwidth(p) + 7) >> 3) << 3) 54 55 /* 56 * Register Structures 57 */ 58 59 // Basic 60 #define REG_BASE_BASIC 0x00 61 typedef struct { 62 u8 rev_code; // 00 63 u8 misc; // 01 64 } reg_basic_t; 65 66 // General IO Pins 67 #define REG_BASE_GENIO 0x04 68 typedef struct { 69 u8 gpio_cfg; // 04 70 u8 gpio_cfg2; // 05 SED13806 71 u8 spacer[2]; // 06 72 u8 gpio_ctrl; // 08 73 u8 gpio_ctrl2; // 09 SED13806 74 } reg_genio_t; 75 76 // MD Config Readback 77 #define REG_BASE_MDCFG 0x0c 78 typedef struct { 79 u8 md_cfg_stat0; // 0C 80 u8 md_cfg_stat1; // 0D 81 } reg_mdcfg_t; 82 83 // Clock Config 84 #define REG_BASE_CLKCFG 0x10 85 typedef struct { 86 u8 mem_clk_cfg; // 10 87 u8 spacer1[3]; // 11 88 u8 lcd_pclk_cfg; // 14 89 u8 spacer2[3]; // 15 90 u8 crttv_pclk_cfg; // 18 91 u8 spacer3[3]; // 19 92 u8 mpclk_cfg; // 1C 93 u8 spacer4; // 1D 94 u8 cpu2mem_wait_sel; // 1E 95 } reg_clkcfg_t; 96 97 // Memory Config 98 #define REG_BASE_MEMCFG 0x20 99 typedef struct { 100 u8 mem_cfg; // 20 101 u8 dram_refresh; // 21 102 u8 spacer[8]; // 22 103 u8 dram_timings_ctrl0; // 2A 104 u8 dram_timings_ctrl1; // 2B 105 } reg_memcfg_t; 106 107 // Panel Config 108 #define REG_BASE_PANELCFG 0x30 109 typedef struct { 110 u8 panel_type; // 30 111 u8 mod_rate; // 31 112 } reg_panelcfg_t; 113 114 // LCD and CRTTV Display Config 115 #define REG_BASE_LCD_DISPCFG 0x32 116 #define REG_BASE_CRTTV_DISPCFG 0x50 117 typedef struct { 118 u8 hdw; // 32 or 50 119 u8 spacer1; // 33 or 51 120 u8 hndp; // 34 or 52 121 u8 hsync_start; // 35 or 53 122 u8 hsync_pulse; // 36 or 54 123 u8 spacer2; // 37 or 55 124 u8 vdh0; // 38 or 56 125 u8 vdh1; // 39 or 57 126 u8 vndp; // 3A or 58 127 u8 vsync_start; // 3B or 59 128 u8 vsync_pulse; // 3C or 5A 129 u8 tv_output_ctrl; // 5B (TV only) 130 } reg_dispcfg_t; 131 132 // LCD and CRTTV Display Mode 133 #define REG_BASE_LCD_DISPMODE 0x40 134 #define REG_BASE_CRTTV_DISPMODE 0x60 135 typedef struct { 136 u8 disp_mode; // 40 or 60 137 u8 lcd_misc; // 41 (LCD only) 138 u8 start_addr0; // 42 or 62 139 u8 start_addr1; // 43 or 63 140 u8 start_addr2; // 44 or 64 141 u8 spacer1; // 45 or 65 142 u8 mem_addr_offset0; // 46 or 66 143 u8 mem_addr_offset1; // 47 or 67 144 u8 pixel_panning; // 48 or 68 145 u8 spacer2; // 49 or 69 146 u8 fifo_high_thresh; // 4A or 6A 147 u8 fifo_low_thresh; // 4B or 6B 148 } reg_dispmode_t; 149 150 // LCD and CRTTV Ink/Cursor 151 #define REG_BASE_LCD_INKCURS 0x70 152 #define REG_BASE_CRTTV_INKCURS 0x80 153 typedef struct { 154 u8 ctrl; // 70 or 80 155 u8 start_addr; // 71 or 81 156 u8 x_pos0; // 72 or 82 157 u8 x_pos1; // 73 or 83 158 u8 y_pos0; // 74 or 84 159 u8 y_pos1; // 75 or 85 160 u8 blue0; // 76 or 86 161 u8 green0; // 77 or 87 162 u8 red0; // 78 or 88 163 u8 spacer1; // 79 or 89 164 u8 blue1; // 7A or 8A 165 u8 green1; // 7B or 8B 166 u8 red1; // 7C or 8C 167 u8 spacer2; // 7D or 8D 168 u8 fifo; // 7E or 8E 169 } reg_inkcurs_t; 170 171 // BitBlt Config 172 #define REG_BASE_BITBLT 0x100 173 typedef struct { 174 u8 ctrl0; // 100 175 u8 ctrl1; // 101 176 u8 rop_code; // 102 177 u8 operation; // 103 178 u8 src_start_addr0; // 104 179 u8 src_start_addr1; // 105 180 u8 src_start_addr2; // 106 181 u8 spacer1; // 107 182 u8 dest_start_addr0; // 108 183 u8 dest_start_addr1; // 109 184 u8 dest_start_addr2; // 10A 185 u8 spacer2; // 10B 186 u8 mem_addr_offset0; // 10C 187 u8 mem_addr_offset1; // 10D 188 u8 spacer3[2]; // 10E 189 u8 width0; // 110 190 u8 width1; // 111 191 u8 height0; // 112 192 u8 height1; // 113 193 u8 bg_color0; // 114 194 u8 bg_color1; // 115 195 u8 spacer4[2]; // 116 196 u8 fg_color0; // 118 197 u8 fg_color1; // 119 198 } reg_bitblt_t; 199 200 // LUT 201 #define REG_BASE_LUT 0x1e0 202 typedef struct { 203 u8 mode; // 1E0 204 u8 spacer1; // 1E1 205 u8 addr; // 1E2 206 u8 spacer2; // 1E3 207 u8 data; // 1E4 208 } reg_lut_t; 209 210 // Power Save Config 211 #define REG_BASE_PWRSAVE 0x1f0 212 typedef struct { 213 u8 cfg; // 1F0 214 u8 status; // 1F1 215 } reg_pwrsave_t; 216 217 // Misc 218 #define REG_BASE_MISC 0x1f4 219 typedef struct { 220 u8 cpu2mem_watchdog; // 1F4 221 u8 spacer[7]; // 1F5 222 u8 disp_mode; // 1FC 223 } reg_misc_t; 224 225 // MediaPlug 226 #define REG_BASE_MEDIAPLUG 0x1000 227 typedef struct { 228 u8 lcmd; // 1000 229 u8 spacer1; // 1001 230 u8 reserved_lcmd; // 1002 231 u8 spacer2; // 1003 232 u8 cmd; // 1004 233 u8 spacer3; // 1005 234 u8 reserved_cmd; // 1006 235 u8 spacer4; // 1007 236 u8 data; // 1008 237 } reg_mediaplug_t; 238 239 // BitBlt data register. 16-bit access only 240 #define REG_BASE_BITBLT_DATA 0x100000 241 242 typedef struct { 243 reg_basic_t* basic; 244 reg_genio_t* genio; 245 reg_mdcfg_t* md_cfg; 246 reg_clkcfg_t* clk_cfg; 247 reg_memcfg_t* mem_cfg; 248 reg_panelcfg_t* panel_cfg; 249 reg_dispcfg_t* lcd_cfg; 250 reg_dispcfg_t* crttv_cfg; 251 reg_dispmode_t* lcd_mode; 252 reg_dispmode_t* crttv_mode; 253 reg_inkcurs_t* lcd_inkcurs; 254 reg_inkcurs_t* crttv_inkcurs; 255 reg_bitblt_t* bitblt; 256 reg_lut_t* lut; 257 reg_pwrsave_t* pwr_save; 258 reg_misc_t* misc; 259 reg_mediaplug_t* mediaplug; 260 u16* bitblt_data; 261 } e1356_reg_t; 262 263 264 /*--------------------------------------------------------*/ 265 266 enum mem_type_t { 267 MEM_TYPE_EDO_2CAS = 0, 268 MEM_TYPE_FPM_2CAS, 269 MEM_TYPE_EDO_2WE, 270 MEM_TYPE_FPM_2WE, 271 MEM_TYPE_EMBEDDED_SDRAM = 0x80 272 }; 273 274 enum mem_smr_t { 275 MEM_SMR_CBR = 0, 276 MEM_SMR_SELF, 277 MEM_SMR_NONE 278 }; 279 280 enum disp_type_t { 281 DISP_TYPE_LCD = 0, 282 DISP_TYPE_TFT, 283 DISP_TYPE_CRT, 284 DISP_TYPE_PAL, 285 DISP_TYPE_NTSC 286 }; 287 288 /* 289 * Maximum timing values, as determined by the SED1356 register 290 * field sizes. All are indexed by display type, except 291 * max_hsync_start which is first indexed by color depth, 292 * then by display type. 293 */ 294 static const int max_hndp[5] = {256, 256, 512, 511, 510}; 295 static const int max_hsync_start[2][5] = { 296 {0, 252, 507, 505, 505}, // 8 bpp 297 {0, 254, 509, 507, 507} // 16 bpp 298 }; 299 static const int max_hsync_width[5] = {0, 128, 128, 0, 0}; 300 static const int max_vndp[5] = {64, 64, 128, 128, 128}; 301 static const int max_vsync_start[5] = {0, 64, 128, 128, 128}; 302 static const int max_vsync_width[5] = {0, 8, 8, 0, 0}; 303 304 #define IS_PANEL(disp_type) \ 305 (disp_type == DISP_TYPE_LCD || disp_type == DISP_TYPE_TFT) 306 #define IS_CRT(disp_type) (disp_type == DISP_TYPE_CRT) 307 #define IS_TV(disp_type) \ 308 (disp_type == DISP_TYPE_NTSC || disp_type == DISP_TYPE_PAL) 309 310 311 enum tv_filters_t { 312 TV_FILT_LUM = 1, 313 TV_FILT_CHROM = 2, 314 TV_FILT_FLICKER = 4 315 }; 316 317 enum tv_format_t { 318 TV_FMT_COMPOSITE = 0, 319 TV_FMT_S_VIDEO 320 }; 321 322 323 struct e1356fb_fix { 324 int system; // the number of a pre-packaged system 325 phys_t regbase_phys; // phys start address of registers 326 phys_t membase_phys; // phys start address of fb memory 327 328 // Memory parameters 329 int mem_speed; // speed: 50, 60, 70, or 80 (nsec) 330 int mem_type; // mem type: EDO-2CAS, FPM-2CAS, EDO-2WE, FPM-2WE 331 int mem_refresh; // refresh rate in KHz 332 int mem_smr; // suspend mode refresh: CAS_BEFORE_RAS, SELF, or NONE 333 // Clocks 334 int busclk; // BUSCLK frequency, in KHz 335 int mclk; // MCLK freq, in KHz, will either be BUSCLK or BUSCLK/2 336 int clki; // CLKI frequency, in KHz 337 int clki2; // CLKI2 frequency, in KHz 338 339 int disp_type; // LCD, TFT, CRT, PAL, or NTSC 340 341 // TV Options 342 u8 tv_filt; // TV Filter mask, LUM, CHROM, and FLICKER 343 int tv_fmt; // TV output format, COMPOSITE or S_VIDEO 344 345 // Panel (LCD,TFT) Options 346 int panel_el; // enable support for EL-type panels 347 int panel_width; // Panel data width: LCD: 4/8/16, TFT: 9/12/18 348 349 // Misc 350 int noaccel; 351 int nopan; 352 #ifdef CONFIG_MTRR 353 int nomtrr; 354 #endif 355 int nohwcursor; 356 int mmunalign; // force unaligned returned VA in mmap() 357 char fontname[40]; 358 359 char *mode_option; 360 }; 361 362 363 typedef struct { 364 int pixclk_d; // Desired Pixel Clock, KHz 365 int pixclk; // Closest supported clock to desired clock, KHz 366 int error; // percent error between pixclock and pixclock_d 367 int clksrc; // equal to busclk, mclk, clki, or clki2, KHz 368 int divisor; // pixclk = clksrc/divisor, where divisor = 1,2,3, or 4 369 u8 pixclk_bits; // pixclock register value for above settings 370 } pixclock_info_t; 371 372 373 struct e1356fb_par { 374 int width; 375 int height; 376 int width_virt; // Width in pixels 377 int height_virt; // Height in lines 378 int bpp; // bits-per-pixel 379 int Bpp; // Bytes-per-pixel 380 381 // Timing 382 pixclock_info_t ipclk; 383 int horiz_ndp; // Horiz. Non-Display Period, pixels 384 int vert_ndp; // Vert. Non-Display Period, lines 385 int hsync_pol; // Polarity of horiz. sync signal (HRTC for CRT/TV, 386 // FPLINE for TFT). 0=active lo, 1=active hi 387 int hsync_start; // Horiz. Sync Start position, pixels 388 int hsync_width; // Horiz. Sync Pulse width, pixels 389 int hsync_freq; // calculated horizontal sync frequency 390 int vsync_pol; // Polarity of vert. sync signal (VRTC for CRT/TV, 391 // FPFRAME for TFT). 0=active lo, 1=active hi 392 int vsync_start; // Vert. Sync Start position, lines 393 int vsync_width; // Vert. Sync Pulse width, lines 394 int vsync_freq; // calculated vertical sync frequency 395 396 int cmap_len; // color-map length 397 }; 398 399 400 401 struct fb_info_e1356 { 402 struct fb_info fb_info; 403 404 void *regbase_virt; 405 unsigned long regbase_size; 406 void *membase_virt; 407 unsigned long fb_size; 408 409 e1356_reg_t reg; 410 411 void* putcs_buffer; 412 413 int max_pixclock; // Max supported pixel clock, KHz 414 int open, mmaped; // open count, is mmap'ed 415 416 u8 chip_rev; 417 418 #ifdef CONFIG_MTRR 419 int mtrr_idx; 420 #endif 421 422 #ifdef SHADOW_FRAME_BUFFER 423 struct { 424 void* fb; 425 struct timer_list timer; 426 } shadow; 427 #endif 428 429 struct { unsigned red, green, blue, pad; } palette[256]; 430 struct display disp; 431 432 #if defined(FBCON_HAS_CFB16) 433 u16 fbcon_cmap16[16]; 434 #endif 435 436 struct { 437 int type; 438 int state; 439 int w,h,u; 440 int x,y,redraw; 441 unsigned long enable,disable; 442 struct timer_list timer; 443 spinlock_t lock; 444 } cursor; 445 446 struct e1356fb_fix fix; 447 struct e1356fb_par default_par; 448 struct e1356fb_par current_par; 449 }; 450 451 452 // The following are boot options for particular SED1356-based target systems 453 454 enum { 455 SYS_NULL, 456 SYS_PB1000, 457 SYS_PB1500, 458 SYS_SDU1356, 459 SYS_CLIO1050, 460 NUM_SYSTEMS // must be last 461 }; 462 463 static struct { 464 struct e1356fb_fix fix; 465 struct e1356fb_par par; 466 } systems[NUM_SYSTEMS] = { 467 468 /* 469 * NULL system to help us detect missing options 470 * when the driver is compiled as a module. 471 */ 472 { 473 { // fix 474 SYS_NULL, 475 }, 476 { // par 477 } 478 }, 479 480 /* 481 * Alchemy Pb1000 evaluation board, SED1356 482 */ 483 { 484 { // fix 485 SYS_PB1000, 486 0xE00000000, 0xE00200000, 487 60, MEM_TYPE_EDO_2CAS, 64, MEM_SMR_CBR, 488 0, 0, // BUSCLK and MCLK are calculated at run-time 489 40000, 14318, // CLKI, CLKI2 490 #ifdef CONFIG_PB1000_CRT 491 DISP_TYPE_CRT, 492 0, 0, // TV Options 493 0, 0, // Panel options 494 #elif defined (CONFIG_PB1000_NTSC) 495 DISP_TYPE_NTSC, 496 TV_FILT_FLICKER|TV_FILT_LUM|TV_FILT_CHROM, 497 TV_FMT_COMPOSITE, 498 0, 0, // Panel options 499 #elif defined (CONFIG_PB1000_TFT) 500 DISP_TYPE_TFT, 501 0, 0, // TV Options 502 0, 12, // Panel options, EL panel?, data width? 503 #else 504 DISP_TYPE_PAL, 505 TV_FILT_FLICKER|TV_FILT_LUM|TV_FILT_CHROM, 506 TV_FMT_COMPOSITE, 507 0, 0, // Panel options 508 #endif 509 0, 0, 510 #ifdef CONFIG_MTRR 511 0, 512 #endif 513 0, 514 0, 515 {0}, 516 "800x600@60" 517 }, 518 { // par 519 0, 0, 800, 600, 8, 1, 520 // timings will be set by modedb 521 {0}, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 522 256 523 } 524 }, 525 526 /* 527 * Alchemy Pb1500 evaluation board, SED13806 528 */ 529 { 530 { // fix 531 SYS_PB1500, 532 0xE1B000000, 0xE1B200000, 533 50, MEM_TYPE_EMBEDDED_SDRAM, 64, MEM_SMR_CBR, 534 0, 0, // BUSCLK and MCLK are calculated at run-time 535 40000, 14318, // CLKI, CLKI2 536 #ifdef CONFIG_PB1500_CRT 537 DISP_TYPE_CRT, 538 0, 0, // TV Options 539 0, 0, // Panel options 540 #else 541 DISP_TYPE_TFT, 542 0, 0, // TV Options 543 0, 12, // Panel options, EL panel?, data width? 544 #endif 545 0, 0, 546 #ifdef CONFIG_MTRR 547 0, 548 #endif 549 0, 550 0, 551 {0}, 552 "800x600@60" 553 }, 554 { // par 555 0, 0, 800, 600, 8, 1, 556 // timings will be set by modedb 557 {0}, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 558 256 559 } 560 }, 561 562 /* 563 * Epson SDU1356B0C PCI eval card. These settings assume the 564 * card is configured for PCI, the MediaPlug is disabled, 565 * and the onboard clock synthesizer is at the power-up 566 * clock settings. 567 */ 568 { 569 { // fix 570 SYS_SDU1356, 571 0x0, 0x0, // addresses obtained from PCI config space 572 // FIXME: just guess for now 573 60, MEM_TYPE_EDO_2CAS, 64, MEM_SMR_CBR, 574 33000, 0, 40000, 25175, // BUSCLK, MCLK, CLKI, CLKI2 575 DISP_TYPE_CRT, 576 0, 0, 577 0, 0, 578 0, 0, 579 #ifdef CONFIG_MTRR 580 0, 581 #endif 582 0, 583 0, 584 {0}, 585 "800x600@60" 586 }, 587 { // par 588 0, 0, 1024, 768, 8, 1, 589 // timings will be set by modedb 590 {0}, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 591 256 592 } 593 }, 594 595 /* 596 * Vadem Clio 1050 - this is for the benefit of the Linux-VR project. 597 * FIXME: Most of these settings are just guesses, until I can get a 598 * Clio 1050 and dump the registers that WinCE has setup. 599 */ 600 { 601 { // fix 602 SYS_CLIO1050, 603 0x0a000000, 0x0a200000, 604 60, MEM_TYPE_EDO_2CAS, 64, MEM_SMR_CBR, 605 40000, 40000, 14318, 14318, 606 DISP_TYPE_TFT, 607 0, 0, 608 0, 16, 609 0, 0, 610 #ifdef CONFIG_MTRR 611 0, 612 #endif 613 0, 614 0, 615 {0}, 616 "640x480@85" 617 }, 618 { // par 619 0, 0, 1024, 768, 16, 2, 620 // timings will be set by modedb 621 {0}, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 622 16 623 } 624 } 625 }; 626