1 /* 2 * Miscellaneous IOCTL commands for Dynamic Power Management Controller Driver 3 * 4 * Copyright (C) 2004-2009 Analog Device Inc. 5 * 6 * Licensed under the GPL-2 7 */ 8 9 #ifndef _BLACKFIN_DPMC_H_ 10 #define _BLACKFIN_DPMC_H_ 11 12 #include <mach/pll.h> 13 14 /* PLL_CTL Masks */ 15 #define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */ 16 #define PLL_OFF 0x0002 /* PLL Not Powered */ 17 #define STOPCK 0x0008 /* Core Clock Off */ 18 #define PDWN 0x0020 /* Enter Deep Sleep Mode */ 19 #ifdef __ADSPBF539__ 20 # define IN_DELAY 0x0014 /* Add 200ps Delay To EBIU Input Latches */ 21 # define OUT_DELAY 0x00C0 /* Add 200ps Delay To EBIU Output Signals */ 22 #else 23 # define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */ 24 # define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */ 25 #endif 26 #define BYPASS 0x0100 /* Bypass the PLL */ 27 #define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */ 28 #define SPORT_HYST 0x8000 /* Enable Additional Hysteresis on SPORT Input Pins */ 29 #define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */ 30 31 /* PLL_DIV Masks */ 32 #define SSEL 0x000F /* System Select */ 33 #define CSEL 0x0030 /* Core Select */ 34 #define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */ 35 #define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */ 36 #define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */ 37 #define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */ 38 39 #define CCLK_DIV1 CSEL_DIV1 40 #define CCLK_DIV2 CSEL_DIV2 41 #define CCLK_DIV4 CSEL_DIV4 42 #define CCLK_DIV8 CSEL_DIV8 43 44 #define SET_SSEL(x) ((x) & 0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */ 45 #define SCLK_DIV(x) (x) /* SCLK = VCO / x */ 46 47 /* PLL_STAT Masks */ 48 #define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */ 49 #define FULL_ON 0x0002 /* Processor In Full On Mode */ 50 #define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */ 51 #define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ 52 53 #define RTCWS 0x0400 /* RTC/Reset Wake-Up Status */ 54 #define CANWS 0x0800 /* CAN Wake-Up Status */ 55 #define USBWS 0x2000 /* USB Wake-Up Status */ 56 #define KPADWS 0x4000 /* Keypad Wake-Up Status */ 57 #define ROTWS 0x8000 /* Rotary Wake-Up Status */ 58 #define GPWS 0x1000 /* General-Purpose Wake-Up Status */ 59 60 /* VR_CTL Masks */ 61 #if defined(__ADSPBF52x__) || defined(__ADSPBF51x__) 62 #define FREQ 0x3000 /* Switching Oscillator Frequency For Regulator */ 63 #define FREQ_1000 0x3000 /* Switching Frequency Is 1 MHz */ 64 #else 65 #define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */ 66 #define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */ 67 #define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */ 68 #define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */ 69 #endif 70 #define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */ 71 72 #define GAIN 0x000C /* Voltage Level Gain */ 73 #define GAIN_5 0x0000 /* GAIN = 5 */ 74 #define GAIN_10 0x0004 /* GAIN = 1 */ 75 #define GAIN_20 0x0008 /* GAIN = 2 */ 76 #define GAIN_50 0x000C /* GAIN = 5 */ 77 78 #define VLEV 0x00F0 /* Internal Voltage Level */ 79 #ifdef __ADSPBF52x__ 80 #define VLEV_085 0x0040 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ 81 #define VLEV_090 0x0050 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ 82 #define VLEV_095 0x0060 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ 83 #define VLEV_100 0x0070 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ 84 #define VLEV_105 0x0080 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ 85 #define VLEV_110 0x0090 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ 86 #define VLEV_115 0x00A0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ 87 #define VLEV_120 0x00B0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ 88 #else 89 #define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ 90 #define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ 91 #define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ 92 #define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ 93 #define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ 94 #define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ 95 #define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ 96 #define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ 97 #define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ 98 #define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ 99 #endif 100 101 #define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ 102 #define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */ 103 #define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */ 104 #define GPWE 0x0400 /* General-Purpose Wake-Up Enable */ 105 #define MXVRWE 0x0400 /* Enable MXVR Wakeup From Hibernate */ 106 #define KPADWE 0x1000 /* Keypad Wake-Up Enable */ 107 #define ROTWE 0x2000 /* Rotary Wake-Up Enable */ 108 #define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */ 109 #define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */ 110 111 #if defined(__ADSPBF52x__) || defined(__ADSPBF51x__) 112 #define USBWE 0x0200 /* Enable USB Wakeup From Hibernate */ 113 #else 114 #define USBWE 0x0800 /* Enable USB Wakeup From Hibernate */ 115 #endif 116 117 #ifndef __ASSEMBLY__ 118 119 void sleep_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2); 120 void sleep_deeper(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2); 121 void do_hibernate(int wakeup); 122 void set_dram_srfs(void); 123 void unset_dram_srfs(void); 124 125 #define VRPAIR(vlev, freq) (((vlev) << 16) | ((freq) >> 16)) 126 127 #ifdef CONFIG_CPU_FREQ 128 #define CPUFREQ_CPU 0 129 #endif 130 struct bfin_dpmc_platform_data { 131 const unsigned int *tuple_tab; 132 unsigned short tabsize; 133 unsigned short vr_settling_time; /* in us */ 134 }; 135 136 #endif 137 138 #endif /*_BLACKFIN_DPMC_H_*/ 139