1 #ifndef __SPARC64_MMU_CONTEXT_H
2 #define __SPARC64_MMU_CONTEXT_H
3
4 /* Derived heavily from Linus's Alpha/AXP ASN code... */
5
6 #ifndef __ASSEMBLY__
7
8 #include <linux/spinlock.h>
9 #include <asm/system.h>
10 #include <asm/spitfire.h>
11 #include <asm-generic/mm_hooks.h>
12
enter_lazy_tlb(struct mm_struct * mm,struct task_struct * tsk)13 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
14 {
15 }
16
17 extern spinlock_t ctx_alloc_lock;
18 extern unsigned long tlb_context_cache;
19 extern unsigned long mmu_context_bmap[];
20
21 extern void get_new_mmu_context(struct mm_struct *mm);
22 #ifdef CONFIG_SMP
23 extern void smp_new_mmu_context_version(void);
24 #else
25 #define smp_new_mmu_context_version() do { } while (0)
26 #endif
27
28 extern int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
29 extern void destroy_context(struct mm_struct *mm);
30
31 extern void __tsb_context_switch(unsigned long pgd_pa,
32 struct tsb_config *tsb_base,
33 struct tsb_config *tsb_huge,
34 unsigned long tsb_descr_pa);
35
tsb_context_switch(struct mm_struct * mm)36 static inline void tsb_context_switch(struct mm_struct *mm)
37 {
38 __tsb_context_switch(__pa(mm->pgd),
39 &mm->context.tsb_block[0],
40 #ifdef CONFIG_HUGETLB_PAGE
41 (mm->context.tsb_block[1].tsb ?
42 &mm->context.tsb_block[1] :
43 NULL)
44 #else
45 NULL
46 #endif
47 , __pa(&mm->context.tsb_descr[0]));
48 }
49
50 extern void tsb_grow(struct mm_struct *mm, unsigned long tsb_index, unsigned long mm_rss);
51 #ifdef CONFIG_SMP
52 extern void smp_tsb_sync(struct mm_struct *mm);
53 #else
54 #define smp_tsb_sync(__mm) do { } while (0)
55 #endif
56
57 /* Set MMU context in the actual hardware. */
58 #define load_secondary_context(__mm) \
59 __asm__ __volatile__( \
60 "\n661: stxa %0, [%1] %2\n" \
61 " .section .sun4v_1insn_patch, \"ax\"\n" \
62 " .word 661b\n" \
63 " stxa %0, [%1] %3\n" \
64 " .previous\n" \
65 " flush %%g6\n" \
66 : /* No outputs */ \
67 : "r" (CTX_HWBITS((__mm)->context)), \
68 "r" (SECONDARY_CONTEXT), "i" (ASI_DMMU), "i" (ASI_MMU))
69
70 extern void __flush_tlb_mm(unsigned long, unsigned long);
71
72 /* Switch the current MM context. Interrupts are disabled. */
switch_mm(struct mm_struct * old_mm,struct mm_struct * mm,struct task_struct * tsk)73 static inline void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, struct task_struct *tsk)
74 {
75 unsigned long ctx_valid, flags;
76 int cpu;
77
78 if (unlikely(mm == &init_mm))
79 return;
80
81 spin_lock_irqsave(&mm->context.lock, flags);
82 ctx_valid = CTX_VALID(mm->context);
83 if (!ctx_valid)
84 get_new_mmu_context(mm);
85
86 /* We have to be extremely careful here or else we will miss
87 * a TSB grow if we switch back and forth between a kernel
88 * thread and an address space which has it's TSB size increased
89 * on another processor.
90 *
91 * It is possible to play some games in order to optimize the
92 * switch, but the safest thing to do is to unconditionally
93 * perform the secondary context load and the TSB context switch.
94 *
95 * For reference the bad case is, for address space "A":
96 *
97 * CPU 0 CPU 1
98 * run address space A
99 * set cpu0's bits in cpu_vm_mask
100 * switch to kernel thread, borrow
101 * address space A via entry_lazy_tlb
102 * run address space A
103 * set cpu1's bit in cpu_vm_mask
104 * flush_tlb_pending()
105 * reset cpu_vm_mask to just cpu1
106 * TSB grow
107 * run address space A
108 * context was valid, so skip
109 * TSB context switch
110 *
111 * At that point cpu0 continues to use a stale TSB, the one from
112 * before the TSB grow performed on cpu1. cpu1 did not cross-call
113 * cpu0 to update it's TSB because at that point the cpu_vm_mask
114 * only had cpu1 set in it.
115 */
116 load_secondary_context(mm);
117 tsb_context_switch(mm);
118
119 /* Any time a processor runs a context on an address space
120 * for the first time, we must flush that context out of the
121 * local TLB.
122 */
123 cpu = smp_processor_id();
124 if (!ctx_valid || !cpumask_test_cpu(cpu, mm_cpumask(mm))) {
125 cpumask_set_cpu(cpu, mm_cpumask(mm));
126 __flush_tlb_mm(CTX_HWBITS(mm->context),
127 SECONDARY_CONTEXT);
128 }
129 spin_unlock_irqrestore(&mm->context.lock, flags);
130 }
131
132 #define deactivate_mm(tsk,mm) do { } while (0)
133
134 /* Activate a new MM instance for the current task. */
activate_mm(struct mm_struct * active_mm,struct mm_struct * mm)135 static inline void activate_mm(struct mm_struct *active_mm, struct mm_struct *mm)
136 {
137 unsigned long flags;
138 int cpu;
139
140 spin_lock_irqsave(&mm->context.lock, flags);
141 if (!CTX_VALID(mm->context))
142 get_new_mmu_context(mm);
143 cpu = smp_processor_id();
144 if (!cpumask_test_cpu(cpu, mm_cpumask(mm)))
145 cpumask_set_cpu(cpu, mm_cpumask(mm));
146
147 load_secondary_context(mm);
148 __flush_tlb_mm(CTX_HWBITS(mm->context), SECONDARY_CONTEXT);
149 tsb_context_switch(mm);
150 spin_unlock_irqrestore(&mm->context.lock, flags);
151 }
152
153 #endif /* !(__ASSEMBLY__) */
154
155 #endif /* !(__SPARC64_MMU_CONTEXT_H) */
156