1 /*
2 * Copyright © 2006-2019 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25 #ifndef _INTEL_DISPLAY_H_
26 #define _INTEL_DISPLAY_H_
27
28 #include <drm/drm_util.h>
29
30 #include "i915_reg_defs.h"
31
32 enum drm_scaling_filter;
33 struct dpll;
34 struct drm_connector;
35 struct drm_device;
36 struct drm_display_mode;
37 struct drm_encoder;
38 struct drm_file;
39 struct drm_format_info;
40 struct drm_framebuffer;
41 struct drm_i915_gem_object;
42 struct drm_i915_private;
43 struct drm_mode_fb_cmd2;
44 struct drm_modeset_acquire_ctx;
45 struct drm_plane;
46 struct drm_plane_state;
47 struct i915_address_space;
48 struct i915_ggtt_view;
49 struct intel_atomic_state;
50 struct intel_crtc;
51 struct intel_crtc_state;
52 struct intel_digital_port;
53 struct intel_dp;
54 struct intel_encoder;
55 struct intel_initial_plane_config;
56 struct intel_load_detect_pipe;
57 struct intel_plane;
58 struct intel_plane_state;
59 struct intel_remapped_info;
60 struct intel_rotation_info;
61 struct pci_dev;
62
63 enum i915_gpio {
64 GPIOA,
65 GPIOB,
66 GPIOC,
67 GPIOD,
68 GPIOE,
69 GPIOF,
70 GPIOG,
71 GPIOH,
72 __GPIOI_UNUSED,
73 GPIOJ,
74 GPIOK,
75 GPIOL,
76 GPIOM,
77 GPION,
78 GPIOO,
79 };
80
81 /*
82 * Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the
83 * rest have consecutive values and match the enum values of transcoders
84 * with a 1:1 transcoder -> pipe mapping.
85 */
86 enum pipe {
87 INVALID_PIPE = -1,
88
89 PIPE_A = 0,
90 PIPE_B,
91 PIPE_C,
92 PIPE_D,
93 _PIPE_EDP,
94
95 I915_MAX_PIPES = _PIPE_EDP
96 };
97
98 #define pipe_name(p) ((p) + 'A')
99
100 enum transcoder {
101 INVALID_TRANSCODER = -1,
102 /*
103 * The following transcoders have a 1:1 transcoder -> pipe mapping,
104 * keep their values fixed: the code assumes that TRANSCODER_A=0, the
105 * rest have consecutive values and match the enum values of the pipes
106 * they map to.
107 */
108 TRANSCODER_A = PIPE_A,
109 TRANSCODER_B = PIPE_B,
110 TRANSCODER_C = PIPE_C,
111 TRANSCODER_D = PIPE_D,
112
113 /*
114 * The following transcoders can map to any pipe, their enum value
115 * doesn't need to stay fixed.
116 */
117 TRANSCODER_EDP,
118 TRANSCODER_DSI_0,
119 TRANSCODER_DSI_1,
120 TRANSCODER_DSI_A = TRANSCODER_DSI_0, /* legacy DSI */
121 TRANSCODER_DSI_C = TRANSCODER_DSI_1, /* legacy DSI */
122
123 I915_MAX_TRANSCODERS
124 };
125
transcoder_name(enum transcoder transcoder)126 static inline const char *transcoder_name(enum transcoder transcoder)
127 {
128 switch (transcoder) {
129 case TRANSCODER_A:
130 return "A";
131 case TRANSCODER_B:
132 return "B";
133 case TRANSCODER_C:
134 return "C";
135 case TRANSCODER_D:
136 return "D";
137 case TRANSCODER_EDP:
138 return "EDP";
139 case TRANSCODER_DSI_A:
140 return "DSI A";
141 case TRANSCODER_DSI_C:
142 return "DSI C";
143 default:
144 return "<invalid>";
145 }
146 }
147
transcoder_is_dsi(enum transcoder transcoder)148 static inline bool transcoder_is_dsi(enum transcoder transcoder)
149 {
150 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
151 }
152
153 /*
154 * Global legacy plane identifier. Valid only for primary/sprite
155 * planes on pre-g4x, and only for primary planes on g4x-bdw.
156 */
157 enum i9xx_plane_id {
158 PLANE_A,
159 PLANE_B,
160 PLANE_C,
161 };
162
163 #define plane_name(p) ((p) + 'A')
164 #define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
165
166 /*
167 * Per-pipe plane identifier.
168 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
169 * number of planes per CRTC. Not all platforms really have this many planes,
170 * which means some arrays of size I915_MAX_PLANES may have unused entries
171 * between the topmost sprite plane and the cursor plane.
172 *
173 * This is expected to be passed to various register macros
174 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
175 */
176 enum plane_id {
177 PLANE_PRIMARY,
178 PLANE_SPRITE0,
179 PLANE_SPRITE1,
180 PLANE_SPRITE2,
181 PLANE_SPRITE3,
182 PLANE_SPRITE4,
183 PLANE_SPRITE5,
184 PLANE_CURSOR,
185
186 I915_MAX_PLANES,
187 };
188
189 #define for_each_plane_id_on_crtc(__crtc, __p) \
190 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
191 for_each_if((__crtc)->plane_ids_mask & BIT(__p))
192
193 #define for_each_dbuf_slice(__dev_priv, __slice) \
194 for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \
195 for_each_if(INTEL_INFO(__dev_priv)->dbuf.slice_mask & BIT(__slice))
196
197 #define for_each_dbuf_slice_in_mask(__dev_priv, __slice, __mask) \
198 for_each_dbuf_slice((__dev_priv), (__slice)) \
199 for_each_if((__mask) & BIT(__slice))
200
201 enum port {
202 PORT_NONE = -1,
203
204 PORT_A = 0,
205 PORT_B,
206 PORT_C,
207 PORT_D,
208 PORT_E,
209 PORT_F,
210 PORT_G,
211 PORT_H,
212 PORT_I,
213
214 /* tgl+ */
215 PORT_TC1 = PORT_D,
216 PORT_TC2,
217 PORT_TC3,
218 PORT_TC4,
219 PORT_TC5,
220 PORT_TC6,
221
222 /* XE_LPD repositions D/E offsets and bitfields */
223 PORT_D_XELPD = PORT_TC5,
224 PORT_E_XELPD,
225
226 I915_MAX_PORTS
227 };
228
229 #define port_name(p) ((p) + 'A')
230
231 /*
232 * Ports identifier referenced from other drivers.
233 * Expected to remain stable over time
234 */
port_identifier(enum port port)235 static inline const char *port_identifier(enum port port)
236 {
237 switch (port) {
238 case PORT_A:
239 return "Port A";
240 case PORT_B:
241 return "Port B";
242 case PORT_C:
243 return "Port C";
244 case PORT_D:
245 return "Port D";
246 case PORT_E:
247 return "Port E";
248 case PORT_F:
249 return "Port F";
250 case PORT_G:
251 return "Port G";
252 case PORT_H:
253 return "Port H";
254 case PORT_I:
255 return "Port I";
256 default:
257 return "<invalid>";
258 }
259 }
260
261 enum tc_port {
262 TC_PORT_NONE = -1,
263
264 TC_PORT_1 = 0,
265 TC_PORT_2,
266 TC_PORT_3,
267 TC_PORT_4,
268 TC_PORT_5,
269 TC_PORT_6,
270
271 I915_MAX_TC_PORTS
272 };
273
274 enum tc_port_mode {
275 TC_PORT_DISCONNECTED,
276 TC_PORT_TBT_ALT,
277 TC_PORT_DP_ALT,
278 TC_PORT_LEGACY,
279 };
280
281 enum dpio_channel {
282 DPIO_CH0,
283 DPIO_CH1
284 };
285
286 enum dpio_phy {
287 DPIO_PHY0,
288 DPIO_PHY1,
289 DPIO_PHY2,
290 };
291
292 enum aux_ch {
293 AUX_CH_A,
294 AUX_CH_B,
295 AUX_CH_C,
296 AUX_CH_D,
297 AUX_CH_E, /* ICL+ */
298 AUX_CH_F,
299 AUX_CH_G,
300 AUX_CH_H,
301 AUX_CH_I,
302
303 /* tgl+ */
304 AUX_CH_USBC1 = AUX_CH_D,
305 AUX_CH_USBC2,
306 AUX_CH_USBC3,
307 AUX_CH_USBC4,
308 AUX_CH_USBC5,
309 AUX_CH_USBC6,
310
311 /* XE_LPD repositions D/E offsets and bitfields */
312 AUX_CH_D_XELPD = AUX_CH_USBC5,
313 AUX_CH_E_XELPD,
314 };
315
316 #define aux_ch_name(a) ((a) + 'A')
317
318 /* Used by dp and fdi links */
319 struct intel_link_m_n {
320 u32 tu;
321 u32 data_m;
322 u32 data_n;
323 u32 link_m;
324 u32 link_n;
325 };
326
327 enum phy {
328 PHY_NONE = -1,
329
330 PHY_A = 0,
331 PHY_B,
332 PHY_C,
333 PHY_D,
334 PHY_E,
335 PHY_F,
336 PHY_G,
337 PHY_H,
338 PHY_I,
339
340 I915_MAX_PHYS
341 };
342
343 #define phy_name(a) ((a) + 'A')
344
345 enum phy_fia {
346 FIA1,
347 FIA2,
348 FIA3,
349 };
350
351 enum hpd_pin {
352 HPD_NONE = 0,
353 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
354 HPD_CRT,
355 HPD_SDVO_B,
356 HPD_SDVO_C,
357 HPD_PORT_A,
358 HPD_PORT_B,
359 HPD_PORT_C,
360 HPD_PORT_D,
361 HPD_PORT_E,
362 HPD_PORT_TC1,
363 HPD_PORT_TC2,
364 HPD_PORT_TC3,
365 HPD_PORT_TC4,
366 HPD_PORT_TC5,
367 HPD_PORT_TC6,
368
369 HPD_NUM_PINS
370 };
371
372 #define for_each_hpd_pin(__pin) \
373 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
374
375 #define for_each_pipe(__dev_priv, __p) \
376 for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \
377 for_each_if(INTEL_INFO(__dev_priv)->display.pipe_mask & BIT(__p))
378
379 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
380 for_each_pipe(__dev_priv, __p) \
381 for_each_if((__mask) & BIT(__p))
382
383 #define for_each_cpu_transcoder(__dev_priv, __t) \
384 for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \
385 for_each_if (INTEL_INFO(__dev_priv)->display.cpu_transcoder_mask & BIT(__t))
386
387 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
388 for_each_cpu_transcoder(__dev_priv, __t) \
389 for_each_if ((__mask) & BIT(__t))
390
391 #define for_each_sprite(__dev_priv, __p, __s) \
392 for ((__s) = 0; \
393 (__s) < RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \
394 (__s)++)
395
396 #define for_each_port(__port) \
397 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)
398
399 #define for_each_port_masked(__port, __ports_mask) \
400 for_each_port(__port) \
401 for_each_if((__ports_mask) & BIT(__port))
402
403 #define for_each_phy_masked(__phy, __phys_mask) \
404 for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \
405 for_each_if((__phys_mask) & BIT(__phy))
406
407 #define for_each_crtc(dev, crtc) \
408 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
409
410 #define for_each_intel_plane(dev, intel_plane) \
411 list_for_each_entry(intel_plane, \
412 &(dev)->mode_config.plane_list, \
413 base.head)
414
415 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
416 list_for_each_entry(intel_plane, \
417 &(dev)->mode_config.plane_list, \
418 base.head) \
419 for_each_if((plane_mask) & \
420 drm_plane_mask(&intel_plane->base))
421
422 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
423 list_for_each_entry(intel_plane, \
424 &(dev)->mode_config.plane_list, \
425 base.head) \
426 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe)
427
428 #define for_each_intel_crtc(dev, intel_crtc) \
429 list_for_each_entry(intel_crtc, \
430 &(dev)->mode_config.crtc_list, \
431 base.head)
432
433 #define for_each_intel_crtc_in_pipe_mask(dev, intel_crtc, pipe_mask) \
434 list_for_each_entry(intel_crtc, \
435 &(dev)->mode_config.crtc_list, \
436 base.head) \
437 for_each_if((pipe_mask) & BIT(intel_crtc->pipe))
438
439 #define for_each_intel_encoder(dev, intel_encoder) \
440 list_for_each_entry(intel_encoder, \
441 &(dev)->mode_config.encoder_list, \
442 base.head)
443
444 #define for_each_intel_encoder_mask(dev, intel_encoder, encoder_mask) \
445 list_for_each_entry(intel_encoder, \
446 &(dev)->mode_config.encoder_list, \
447 base.head) \
448 for_each_if((encoder_mask) & \
449 drm_encoder_mask(&intel_encoder->base))
450
451 #define for_each_intel_encoder_mask_with_psr(dev, intel_encoder, encoder_mask) \
452 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
453 for_each_if(((encoder_mask) & drm_encoder_mask(&(intel_encoder)->base)) && \
454 intel_encoder_can_psr(intel_encoder))
455
456 #define for_each_intel_dp(dev, intel_encoder) \
457 for_each_intel_encoder(dev, intel_encoder) \
458 for_each_if(intel_encoder_is_dp(intel_encoder))
459
460 #define for_each_intel_encoder_with_psr(dev, intel_encoder) \
461 for_each_intel_encoder((dev), (intel_encoder)) \
462 for_each_if(intel_encoder_can_psr(intel_encoder))
463
464 #define for_each_intel_connector_iter(intel_connector, iter) \
465 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
466
467 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
468 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
469 for_each_if((intel_encoder)->base.crtc == (__crtc))
470
471 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
472 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
473 for_each_if((intel_connector)->base.encoder == (__encoder))
474
475 #define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \
476 for ((__i) = 0; \
477 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
478 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
479 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \
480 (__i)++) \
481 for_each_if(plane)
482
483 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \
484 for ((__i) = 0; \
485 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
486 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
487 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
488 (__i)++) \
489 for_each_if(plane)
490
491 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
492 for ((__i) = 0; \
493 (__i) < (__state)->base.dev->mode_config.num_crtc && \
494 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
495 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
496 (__i)++) \
497 for_each_if(crtc)
498
499 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
500 for ((__i) = 0; \
501 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
502 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
503 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
504 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
505 (__i)++) \
506 for_each_if(plane)
507
508 #define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \
509 for ((__i) = 0; \
510 (__i) < (__state)->base.dev->mode_config.num_crtc && \
511 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
512 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
513 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
514 (__i)++) \
515 for_each_if(crtc)
516
517 #define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
518 for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
519 (__i) >= 0 && \
520 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
521 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
522 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
523 (__i)--) \
524 for_each_if(crtc)
525
526 #define intel_atomic_crtc_state_for_each_plane_state( \
527 plane, plane_state, \
528 crtc_state) \
529 for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \
530 ((crtc_state)->uapi.plane_mask)) \
531 for_each_if ((plane_state = \
532 to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base))))
533
534 #define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
535 for ((__i) = 0; \
536 (__i) < (__state)->base.num_connector; \
537 (__i)++) \
538 for_each_if ((__state)->base.connectors[__i].ptr && \
539 ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
540 (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
541
542 int intel_atomic_add_affected_planes(struct intel_atomic_state *state,
543 struct intel_crtc *crtc);
544 u8 intel_calc_active_pipes(struct intel_atomic_state *state,
545 u8 active_pipes);
546 void intel_link_compute_m_n(u16 bpp, int nlanes,
547 int pixel_clock, int link_clock,
548 struct intel_link_m_n *m_n,
549 bool constant_n, bool fec_enable);
550 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
551 u32 pixel_format, u64 modifier);
552 enum drm_mode_status
553 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
554 const struct drm_display_mode *mode,
555 bool bigjoiner);
556 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
557 bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
558 bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state);
559 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state);
560 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state);
561 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state);
562
563 void intel_plane_destroy(struct drm_plane *plane);
564 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state);
565 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state);
566 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
567 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
568 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
569 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
570 const char *name, u32 reg, int ref_freq);
571 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
572 const char *name, u32 reg);
573 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
574 unsigned int intel_fb_xy_to_linear(int x, int y,
575 const struct intel_plane_state *state,
576 int plane);
577 void intel_add_fb_offsets(int *x, int *y,
578 const struct intel_plane_state *state, int plane);
579 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
580 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info);
581 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
582 int intel_display_suspend(struct drm_device *dev);
583 void intel_encoder_destroy(struct drm_encoder *encoder);
584 struct drm_display_mode *
585 intel_encoder_current_mode(struct intel_encoder *encoder);
586 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy);
587 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy);
588 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy);
589 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
590 enum port port);
591 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
592 struct drm_file *file_priv);
593
594 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp);
595 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
596 struct intel_digital_port *dig_port,
597 unsigned int expected_mask);
598 int intel_get_load_detect_pipe(struct drm_connector *connector,
599 struct intel_load_detect_pipe *old,
600 struct drm_modeset_acquire_ctx *ctx);
601 void intel_release_load_detect_pipe(struct drm_connector *connector,
602 struct intel_load_detect_pipe *old,
603 struct drm_modeset_acquire_ctx *ctx);
604 struct drm_framebuffer *
605 intel_framebuffer_create(struct drm_i915_gem_object *obj,
606 struct drm_mode_fb_cmd2 *mode_cmd);
607
608 bool intel_fuzzy_clock_check(int clock1, int clock2);
609
610 void intel_display_prepare_reset(struct drm_i915_private *dev_priv);
611 void intel_display_finish_reset(struct drm_i915_private *dev_priv);
612 void intel_zero_m_n(struct intel_link_m_n *m_n);
613 void intel_set_m_n(struct drm_i915_private *i915,
614 const struct intel_link_m_n *m_n,
615 i915_reg_t data_m_reg, i915_reg_t data_n_reg,
616 i915_reg_t link_m_reg, i915_reg_t link_n_reg);
617 void intel_get_m_n(struct drm_i915_private *i915,
618 struct intel_link_m_n *m_n,
619 i915_reg_t data_m_reg, i915_reg_t data_n_reg,
620 i915_reg_t link_m_reg, i915_reg_t link_n_reg);
621 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
622 enum transcoder transcoder);
623 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
624 enum transcoder cpu_transcoder,
625 const struct intel_link_m_n *m_n);
626 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
627 enum transcoder cpu_transcoder,
628 const struct intel_link_m_n *m_n);
629 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
630 enum transcoder cpu_transcoder,
631 struct intel_link_m_n *m_n);
632 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
633 enum transcoder cpu_transcoder,
634 struct intel_link_m_n *m_n);
635 void i9xx_crtc_clock_get(struct intel_crtc *crtc,
636 struct intel_crtc_state *pipe_config);
637 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
638 enum intel_display_power_domain intel_port_to_power_domain(struct intel_digital_port *dig_port);
639 enum intel_display_power_domain
640 intel_aux_power_domain(struct intel_digital_port *dig_port);
641 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
642 struct intel_crtc_state *crtc_state);
643 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state);
644
645 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc);
646 unsigned int intel_plane_fence_y_offset(const struct intel_plane_state *plane_state);
647
648 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state);
649
650 struct intel_encoder *
651 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
652 const struct intel_crtc_state *crtc_state);
653 void intel_plane_disable_noatomic(struct intel_crtc *crtc,
654 struct intel_plane *plane);
655
656 void intel_display_driver_register(struct drm_i915_private *i915);
657 void intel_display_driver_unregister(struct drm_i915_private *i915);
658
659 /* modesetting */
660 bool intel_modeset_probe_defer(struct pci_dev *pdev);
661 void intel_modeset_init_hw(struct drm_i915_private *i915);
662 int intel_modeset_init_noirq(struct drm_i915_private *i915);
663 int intel_modeset_init_nogem(struct drm_i915_private *i915);
664 int intel_modeset_init(struct drm_i915_private *i915);
665 void intel_modeset_driver_remove(struct drm_i915_private *i915);
666 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915);
667 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915);
668 void intel_display_resume(struct drm_device *dev);
669 int intel_modeset_all_pipes(struct intel_atomic_state *state);
670
671 /* modesetting asserts */
672 void assert_transcoder(struct drm_i915_private *dev_priv,
673 enum transcoder cpu_transcoder, bool state);
674 #define assert_transcoder_enabled(d, t) assert_transcoder(d, t, true)
675 #define assert_transcoder_disabled(d, t) assert_transcoder(d, t, false)
676
677 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
678 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
679 * which may not necessarily be a user visible problem. This will either
680 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
681 * enable distros and users to tailor their preferred amount of i915 abrt
682 * spam.
683 */
684 #define I915_STATE_WARN(condition, format...) ({ \
685 int __ret_warn_on = !!(condition); \
686 if (unlikely(__ret_warn_on)) \
687 if (!WARN(i915_modparams.verbose_state_checks, format)) \
688 DRM_ERROR(format); \
689 unlikely(__ret_warn_on); \
690 })
691
692 #define I915_STATE_WARN_ON(x) \
693 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
694
695 bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915);
696
697 #endif
698