1 /*
2 * arch/ppc/kernel/todc_time.c
3 *
4 * Time of Day Clock support for the M48T35, M48T37, M48T59, and MC146818
5 * Real Time Clocks/Timekeepers.
6 *
7 * Author: Mark A. Greer
8 * mgreer@mvista.com
9 *
10 * 2001 (c) MontaVista, Software, Inc. This file is licensed under
11 * the terms of the GNU General Public License version 2. This program
12 * is licensed "as is" without any warranty of any kind, whether express
13 * or implied.
14 */
15 #include <linux/errno.h>
16 #include <linux/init.h>
17 #include <linux/kernel.h>
18 #include <linux/time.h>
19 #include <linux/timex.h>
20
21 #include <asm/machdep.h>
22 #include <asm/io.h>
23 #include <asm/time.h>
24 #include <asm/todc.h>
25
26 /*
27 * Depending on the hardware on your board and your board design, the
28 * RTC/NVRAM may be accessed either directly (like normal memory) or via
29 * address/data registers. If your board uses the direct method, set
30 * 'nvram_data' to the base address of your nvram and leave 'nvram_as0' and
31 * 'nvram_as1' NULL. If your board uses address/data regs to access nvram,
32 * set 'nvram_as0' to the address of the lower byte, set 'nvram_as1' to the
33 * address of the upper byte (leave NULL if using mv146818), and set
34 * 'nvram_data' to the address of the 8-bit data register.
35 *
36 * You also need to set 'ppc_md.nvram_read_val' and 'ppc_md.nvram_write_val' to
37 * the proper routines. There are standard ones defined further down in
38 * this file that you can use.
39 *
40 * There is a built in assumption that the RTC and NVRAM are accessed by the
41 * same mechanism (i.e., ppc_md.nvram_read_val, etc works for both).
42 *
43 * Note: Even though the documentation for the various RTC chips say that it
44 * take up to a second before it starts updating once the 'R' bit is
45 * cleared, they always seem to update even though we bang on it many
46 * times a second. This is true, except for the Dallas Semi 1746/1747
47 * (possibly others). Those chips seem to have a real problem whenever
48 * we set the 'R' bit before reading them, they basically stop counting.
49 * --MAG
50 */
51
52 extern spinlock_t rtc_lock;
53
54 /*
55 * 'todc_info' should be initialized in your *_setup.c file to
56 * point to a fully initialized 'todc_info_t' structure.
57 * This structure holds all the register offsets for your particular
58 * TODC/RTC chip.
59 * TODC_ALLOC()/TODC_INIT() will allocate and initialize this table for you.
60 */
61
62 #ifdef RTC_FREQ_SELECT
63 #undef RTC_FREQ_SELECT
64 #define RTC_FREQ_SELECT control_b /* Register A */
65 #endif
66
67 #ifdef RTC_CONTROL
68 #undef RTC_CONTROL
69 #define RTC_CONTROL control_a /* Register B */
70 #endif
71
72 #ifdef RTC_INTR_FLAGS
73 #undef RTC_INTR_FLAGS
74 #define RTC_INTR_FLAGS watchdog /* Register C */
75 #endif
76
77 #ifdef RTC_VALID
78 #undef RTC_VALID
79 #define RTC_VALID interrupts /* Register D */
80 #endif
81
82 /* Access routines when RTC accessed directly (like normal memory) */
83 u_char
todc_direct_read_val(int addr)84 todc_direct_read_val(int addr)
85 {
86 return readb(todc_info->nvram_data + addr);
87 }
88
89 void
todc_direct_write_val(int addr,unsigned char val)90 todc_direct_write_val(int addr, unsigned char val)
91 {
92 writeb(val, todc_info->nvram_data + addr);
93 return;
94 }
95
96 /* Access routines for accessing m48txx type chips via addr/data regs */
97 u_char
todc_m48txx_read_val(int addr)98 todc_m48txx_read_val(int addr)
99 {
100 outb(addr, todc_info->nvram_as0);
101 outb(addr>>todc_info->as0_bits, todc_info->nvram_as1);
102 return inb(todc_info->nvram_data);
103 }
104
105 void
todc_m48txx_write_val(int addr,unsigned char val)106 todc_m48txx_write_val(int addr, unsigned char val)
107 {
108 outb(addr, todc_info->nvram_as0);
109 outb(addr>>todc_info->as0_bits, todc_info->nvram_as1);
110 outb(val, todc_info->nvram_data);
111 return;
112 }
113
114 /* Access routines for accessing mc146818 type chips via addr/data regs */
115 u_char
todc_mc146818_read_val(int addr)116 todc_mc146818_read_val(int addr)
117 {
118 outb(addr, todc_info->nvram_as0);
119 return inb(todc_info->nvram_data);
120 }
121
122 void
todc_mc146818_write_val(int addr,unsigned char val)123 todc_mc146818_write_val(int addr, unsigned char val)
124 {
125 outb(addr, todc_info->nvram_as0);
126 outb(val, todc_info->nvram_data);
127 return;
128 }
129
130
131 /*
132 * Routines to make RTC chips with NVRAM buried behind an addr/data pair
133 * have the NVRAM and clock regs appear at the same level.
134 * The NVRAM will appear to start at addr 0 and the clock regs will appear
135 * to start immediately after the NVRAM (actually, start at offset
136 * todc_info->nvram_size).
137 */
138 static inline u_char
todc_read_val(int addr)139 todc_read_val(int addr)
140 {
141 u_char val;
142
143 if (todc_info->sw_flags & TODC_FLAG_2_LEVEL_NVRAM) {
144 if (addr < todc_info->nvram_size) { /* NVRAM */
145 ppc_md.nvram_write_val(todc_info->nvram_addr_reg, addr);
146 val = ppc_md.nvram_read_val(todc_info->nvram_data_reg);
147 }
148 else { /* Clock Reg */
149 addr -= todc_info->nvram_size;
150 val = ppc_md.nvram_read_val(addr);
151 }
152 }
153 else {
154 val = ppc_md.nvram_read_val(addr);
155 }
156
157 return val;
158 }
159
160 static inline void
todc_write_val(int addr,u_char val)161 todc_write_val(int addr, u_char val)
162 {
163 if (todc_info->sw_flags & TODC_FLAG_2_LEVEL_NVRAM) {
164 if (addr < todc_info->nvram_size) { /* NVRAM */
165 ppc_md.nvram_write_val(todc_info->nvram_addr_reg, addr);
166 ppc_md.nvram_write_val(todc_info->nvram_data_reg, val);
167 }
168 else { /* Clock Reg */
169 addr -= todc_info->nvram_size;
170 ppc_md.nvram_write_val(addr, val);
171 }
172 }
173 else {
174 ppc_md.nvram_write_val(addr, val);
175 }
176 }
177
178 /*
179 * TODC routines
180 *
181 * There is some ugly stuff in that there are assumptions for the mc146818.
182 *
183 * Assumptions:
184 * - todc_info->control_a has the offset as mc146818 Register B reg
185 * - todc_info->control_b has the offset as mc146818 Register A reg
186 * - m48txx control reg's write enable or 'W' bit is same as
187 * mc146818 Register B 'SET' bit (i.e., 0x80)
188 *
189 * These assumptions were made to make the code simpler.
190 */
191 long __init
todc_time_init(void)192 todc_time_init(void)
193 {
194 static u_char not_initialized = 1;
195
196 /* Make sure clocks are running */
197 if (not_initialized) {
198 u_char cntl_b;
199
200 cntl_b = todc_read_val(todc_info->control_b);
201
202 if (todc_info->rtc_type == TODC_TYPE_MC146818) {
203 if ((cntl_b & 0x70) != 0x20) {
204 printk(KERN_INFO "TODC %s %s\n",
205 "real-time-clock was stopped.",
206 "Now starting...");
207 cntl_b &= ~0x70;
208 cntl_b |= 0x20;
209 }
210
211 todc_write_val(todc_info->control_b, cntl_b);
212 }
213 else if (todc_info->rtc_type == TODC_TYPE_DS1501) {
214 u_char month;
215
216 todc_info->enable_read = TODC_DS1501_CNTL_B_TE;
217 todc_info->enable_write = TODC_DS1501_CNTL_B_TE;
218
219 month = todc_read_val(todc_info->month);
220
221 if ((month & 0x80) == 0x80) {
222 printk(KERN_INFO "TODC %s %s\n",
223 "real-time-clock was stopped.",
224 "Now starting...");
225 month &= ~0x80;
226 todc_write_val(todc_info->month, month);
227 }
228
229 cntl_b &= ~TODC_DS1501_CNTL_B_TE;
230 todc_write_val(todc_info->control_b, cntl_b);
231 }
232 else { /* must be a m48txx type */
233 u_char cntl_a;
234
235 todc_info->enable_read = TODC_MK48TXX_CNTL_A_R;
236 todc_info->enable_write = TODC_MK48TXX_CNTL_A_W;
237
238 cntl_a = todc_read_val(todc_info->control_a);
239
240 /* Check & clear STOP bit in control B register */
241 if (cntl_b & TODC_MK48TXX_DAY_CB) {
242 printk(KERN_INFO "TODC %s %s\n",
243 "real-time-clock was stopped.",
244 "Now starting...");
245
246 cntl_a |= todc_info->enable_write;
247 cntl_b &= ~TODC_MK48TXX_DAY_CB;/* Start Oscil */
248
249 todc_write_val(todc_info->control_a, cntl_a);
250 todc_write_val(todc_info->control_b, cntl_b);
251 }
252
253 /* Make sure READ & WRITE bits are cleared. */
254 cntl_a &= ~(todc_info->enable_write |
255 todc_info->enable_read);
256 todc_write_val(todc_info->control_a, cntl_a);
257 }
258
259 not_initialized = 0;
260 }
261
262
263 return 0;
264 }
265
266 /*
267 * There is some ugly stuff in that there are assumptions that for a mc146818,
268 * the todc_info->control_a has the offset of the mc146818 Register B reg and
269 * that the register'ss 'SET' bit is the same as the m48txx's write enable
270 * bit in the control register of the m48txx (i.e., 0x80).
271 *
272 * It was done to make the code look simpler.
273 */
274 ulong
todc_get_rtc_time(void)275 todc_get_rtc_time(void)
276 {
277 uint year, mon, day, hour, min, sec;
278 uint limit, i;
279 u_char save_control, uip;
280
281 spin_lock(&rtc_lock);
282 save_control = todc_read_val(todc_info->control_a);
283
284 if (todc_info->rtc_type != TODC_TYPE_MC146818) {
285 limit = 1;
286
287 switch (todc_info->rtc_type) {
288 case TODC_TYPE_DS1557:
289 case TODC_TYPE_DS1743:
290 case TODC_TYPE_DS1746: /* XXXX BAD HACK -> FIX */
291 case TODC_TYPE_DS1747:
292 break;
293 default:
294 todc_write_val(todc_info->control_a,
295 (save_control | todc_info->enable_read));
296 }
297 }
298 else {
299 limit = 100000000;
300 }
301
302 for (i=0; i<limit; i++) {
303 if (todc_info->rtc_type == TODC_TYPE_MC146818) {
304 uip = todc_read_val(todc_info->RTC_FREQ_SELECT);
305 }
306
307 sec = todc_read_val(todc_info->seconds) & 0x7f;
308 min = todc_read_val(todc_info->minutes) & 0x7f;
309 hour = todc_read_val(todc_info->hours) & 0x3f;
310 day = todc_read_val(todc_info->day_of_month) & 0x3f;
311 mon = todc_read_val(todc_info->month) & 0x1f;
312 year = todc_read_val(todc_info->year) & 0xff;
313
314 if (todc_info->rtc_type == TODC_TYPE_MC146818) {
315 uip |= todc_read_val(todc_info->RTC_FREQ_SELECT);
316 if ((uip & RTC_UIP) == 0) break;
317 }
318 }
319
320 if (todc_info->rtc_type != TODC_TYPE_MC146818) {
321 switch (todc_info->rtc_type) {
322 case TODC_TYPE_DS1557:
323 case TODC_TYPE_DS1743:
324 case TODC_TYPE_DS1746: /* XXXX BAD HACK -> FIX */
325 case TODC_TYPE_DS1747:
326 break;
327 default:
328 save_control &= ~(todc_info->enable_read);
329 todc_write_val(todc_info->control_a,
330 save_control);
331 }
332 }
333 spin_unlock(&rtc_lock);
334
335 if ((todc_info->rtc_type != TODC_TYPE_MC146818) ||
336 ((save_control & RTC_DM_BINARY) == 0) ||
337 RTC_ALWAYS_BCD) {
338
339 BCD_TO_BIN(sec);
340 BCD_TO_BIN(min);
341 BCD_TO_BIN(hour);
342 BCD_TO_BIN(day);
343 BCD_TO_BIN(mon);
344 BCD_TO_BIN(year);
345 }
346
347 year = year + 1900;
348 if (year < 1970) {
349 year += 100;
350 }
351
352 return mktime(year, mon, day, hour, min, sec);
353 }
354
355 int
todc_set_rtc_time(unsigned long nowtime)356 todc_set_rtc_time(unsigned long nowtime)
357 {
358 struct rtc_time tm;
359 u_char save_control, save_freq_select;
360
361 spin_lock(&rtc_lock);
362 to_tm(nowtime, &tm);
363
364 save_control = todc_read_val(todc_info->control_a);
365
366 /* Assuming MK48T59_RTC_CA_WRITE & RTC_SET are equal */
367 todc_write_val(todc_info->control_a,
368 (save_control | todc_info->enable_write));
369 save_control &= ~(todc_info->enable_write); /* in case it was set */
370
371 if (todc_info->rtc_type == TODC_TYPE_MC146818) {
372 save_freq_select = todc_read_val(todc_info->RTC_FREQ_SELECT);
373 todc_write_val(todc_info->RTC_FREQ_SELECT,
374 save_freq_select | RTC_DIV_RESET2);
375 }
376
377
378 tm.tm_year = (tm.tm_year - 1900) % 100;
379
380 if ((todc_info->rtc_type != TODC_TYPE_MC146818) ||
381 ((save_control & RTC_DM_BINARY) == 0) ||
382 RTC_ALWAYS_BCD) {
383
384 BIN_TO_BCD(tm.tm_sec);
385 BIN_TO_BCD(tm.tm_min);
386 BIN_TO_BCD(tm.tm_hour);
387 BIN_TO_BCD(tm.tm_mon);
388 BIN_TO_BCD(tm.tm_mday);
389 BIN_TO_BCD(tm.tm_year);
390 }
391
392 todc_write_val(todc_info->seconds, tm.tm_sec);
393 todc_write_val(todc_info->minutes, tm.tm_min);
394 todc_write_val(todc_info->hours, tm.tm_hour);
395 todc_write_val(todc_info->month, tm.tm_mon);
396 todc_write_val(todc_info->day_of_month, tm.tm_mday);
397 todc_write_val(todc_info->year, tm.tm_year);
398
399 todc_write_val(todc_info->control_a, save_control);
400
401 if (todc_info->rtc_type == TODC_TYPE_MC146818) {
402 todc_write_val(todc_info->RTC_FREQ_SELECT, save_freq_select);
403 }
404 spin_unlock(&rtc_lock);
405
406 return 0;
407 }
408
409 /*
410 * Manipulates read bit to reliably read seconds at a high rate.
411 */
todc_read_timereg(int addr)412 static unsigned char __init todc_read_timereg(int addr)
413 {
414 unsigned char save_control, val;
415
416 switch (todc_info->rtc_type) {
417 case TODC_TYPE_DS1557:
418 case TODC_TYPE_DS1746: /* XXXX BAD HACK -> FIX */
419 case TODC_TYPE_DS1747:
420 case TODC_TYPE_MC146818:
421 break;
422 default:
423 save_control = todc_read_val(todc_info->control_a);
424 todc_write_val(todc_info->control_a,
425 (save_control | todc_info->enable_read));
426 }
427 val = todc_read_val(addr);
428
429 switch (todc_info->rtc_type) {
430 case TODC_TYPE_DS1557:
431 case TODC_TYPE_DS1746: /* XXXX BAD HACK -> FIX */
432 case TODC_TYPE_DS1747:
433 case TODC_TYPE_MC146818:
434 break;
435 default:
436 save_control &= ~(todc_info->enable_read);
437 todc_write_val(todc_info->control_a, save_control);
438 }
439
440 return val;
441 }
442
443 /*
444 * This was taken from prep_setup.c
445 * Use the NVRAM RTC to time a second to calibrate the decrementer.
446 */
447 void __init
todc_calibrate_decr(void)448 todc_calibrate_decr(void)
449 {
450 ulong freq;
451 ulong tbl, tbu;
452 long i, loop_count;
453 u_char sec;
454
455 todc_time_init();
456
457 /*
458 * Actually this is bad for precision, we should have a loop in
459 * which we only read the seconds counter. todc_read_val writes
460 * the address bytes on every call and this takes a lot of time.
461 * Perhaps an nvram_wait_change method returning a time
462 * stamp with a loop count as parameter would be the solution.
463 */
464 /*
465 * Need to make sure the tbl doesn't roll over so if tbu increments
466 * during this test, we need to do it again.
467 */
468 loop_count = 0;
469
470 sec = todc_read_timereg(todc_info->seconds) & 0x7f;
471
472 do {
473 tbu = get_tbu();
474
475 for (i = 0 ; i < 10000000 ; i++) {/* may take up to 1 second */
476 tbl = get_tbl();
477
478 if ((todc_read_timereg(todc_info->seconds) & 0x7f) != sec) {
479 break;
480 }
481 }
482
483 sec = todc_read_timereg(todc_info->seconds) & 0x7f;
484
485 for (i = 0 ; i < 10000000 ; i++) { /* Should take 1 second */
486 freq = get_tbl();
487
488 if ((todc_read_timereg(todc_info->seconds) & 0x7f) != sec) {
489 break;
490 }
491 }
492
493 freq -= tbl;
494 } while ((get_tbu() != tbu) && (++loop_count < 2));
495
496 printk("time_init: decrementer frequency = %lu.%.6lu MHz\n",
497 freq/1000000, freq%1000000);
498
499 tb_ticks_per_jiffy = freq / HZ;
500 tb_to_us = mulhwu_scale_factor(freq, 1000000);
501
502 return;
503 }
504