1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * drivers/net/ethernet/ibm/emac/emac.h
4  *
5  * Register definitions for PowerPC 4xx on-chip ethernet contoller
6  *
7  * Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
8  *                <benh@kernel.crashing.org>
9  *
10  * Based on the arch/ppc version of the driver:
11  *
12  * Copyright (c) 2004, 2005 Zultys Technologies.
13  * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
14  *
15  * Based on original work by
16  *      Matt Porter <mporter@kernel.crashing.org>
17  *      Armin Kuster <akuster@mvista.com>
18  * 	Copyright 2002-2004 MontaVista Software Inc.
19  */
20 #ifndef __IBM_NEWEMAC_H
21 #define __IBM_NEWEMAC_H
22 
23 #include <linux/types.h>
24 #include <linux/phy.h>
25 
26 /* EMAC registers 			Write Access rules */
27 struct emac_regs {
28 	/* Common registers across all EMAC implementations. */
29 	u32 mr0;			/* Special 	*/
30 	u32 mr1;			/* Reset 	*/
31 	u32 tmr0;			/* Special 	*/
32 	u32 tmr1;			/* Special 	*/
33 	u32 rmr;			/* Reset 	*/
34 	u32 isr;			/* Always 	*/
35 	u32 iser;			/* Reset 	*/
36 	u32 iahr;			/* Reset, R, T 	*/
37 	u32 ialr;			/* Reset, R, T 	*/
38 	u32 vtpid;			/* Reset, R, T 	*/
39 	u32 vtci;			/* Reset, R, T 	*/
40 	u32 ptr;			/* Reset,    T 	*/
41 	union {
42 		/* Registers unique to EMAC4 implementations */
43 		struct {
44 			u32 iaht1;	/* Reset, R	*/
45 			u32 iaht2;	/* Reset, R	*/
46 			u32 iaht3;	/* Reset, R	*/
47 			u32 iaht4;	/* Reset, R	*/
48 			u32 gaht1;	/* Reset, R	*/
49 			u32 gaht2;	/* Reset, R	*/
50 			u32 gaht3;	/* Reset, R	*/
51 			u32 gaht4;	/* Reset, R	*/
52 		} emac4;
53 		/* Registers unique to EMAC4SYNC implementations */
54 		struct {
55 			u32 mahr;	/* Reset, R, T  */
56 			u32 malr;	/* Reset, R, T  */
57 			u32 mmahr;	/* Reset, R, T  */
58 			u32 mmalr;	/* Reset, R, T  */
59 			u32 rsvd0[4];
60 		} emac4sync;
61 	} u0;
62 	/* Common registers across all EMAC implementations. */
63 	u32 lsah;
64 	u32 lsal;
65 	u32 ipgvr;			/* Reset,    T 	*/
66 	u32 stacr;			/* Special 	*/
67 	u32 trtr;			/* Special 	*/
68 	u32 rwmr;			/* Reset 	*/
69 	u32 octx;
70 	u32 ocrx;
71 	union {
72 		/* Registers unique to EMAC4 implementations */
73 		struct {
74 			u32 ipcr;
75 		} emac4;
76 		/* Registers unique to EMAC4SYNC implementations */
77 		struct {
78 			u32 rsvd1;
79 			u32 revid;
80 			u32 rsvd2[2];
81 			u32 iaht1;	/* Reset, R     */
82 			u32 iaht2;	/* Reset, R     */
83 			u32 iaht3;	/* Reset, R     */
84 			u32 iaht4;	/* Reset, R     */
85 			u32 iaht5;	/* Reset, R     */
86 			u32 iaht6;	/* Reset, R     */
87 			u32 iaht7;	/* Reset, R     */
88 			u32 iaht8;	/* Reset, R     */
89 			u32 gaht1;	/* Reset, R     */
90 			u32 gaht2;	/* Reset, R     */
91 			u32 gaht3;	/* Reset, R     */
92 			u32 gaht4;	/* Reset, R     */
93 			u32 gaht5;	/* Reset, R     */
94 			u32 gaht6;	/* Reset, R     */
95 			u32 gaht7;	/* Reset, R     */
96 			u32 gaht8;	/* Reset, R     */
97 			u32 tpc;	/* Reset, T     */
98 		} emac4sync;
99 	} u1;
100 };
101 
102 /* EMACx_MR0 */
103 #define EMAC_MR0_RXI			0x80000000
104 #define EMAC_MR0_TXI			0x40000000
105 #define EMAC_MR0_SRST			0x20000000
106 #define EMAC_MR0_TXE			0x10000000
107 #define EMAC_MR0_RXE			0x08000000
108 #define EMAC_MR0_WKE			0x04000000
109 
110 /* EMACx_MR1 */
111 #define EMAC_MR1_FDE			0x80000000
112 #define EMAC_MR1_ILE			0x40000000
113 #define EMAC_MR1_VLE			0x20000000
114 #define EMAC_MR1_EIFC			0x10000000
115 #define EMAC_MR1_APP			0x08000000
116 #define EMAC_MR1_IST			0x01000000
117 
118 #define EMAC_MR1_MF_MASK		0x00c00000
119 #define EMAC_MR1_MF_10			0x00000000
120 #define EMAC_MR1_MF_100			0x00400000
121 #define EMAC_MR1_MF_1000		0x00800000
122 #define EMAC_MR1_MF_1000GPCS		0x00c00000
123 #define EMAC_MR1_MF_IPPA(id)		(((id) & 0x1f) << 6)
124 
125 #define EMAC_MR1_RFS_4K			0x00300000
126 #define EMAC_MR1_RFS_16K		0x00000000
127 #define EMAC_MR1_TFS_2K			0x00080000
128 #define EMAC_MR1_TR0_MULT		0x00008000
129 #define EMAC_MR1_JPSM			0x00000000
130 #define EMAC_MR1_MWSW_001		0x00000000
131 #define EMAC_MR1_BASE(opb)		(EMAC_MR1_TFS_2K | EMAC_MR1_TR0_MULT)
132 
133 
134 #define EMAC4_MR1_RFS_2K		0x00100000
135 #define EMAC4_MR1_RFS_4K		0x00180000
136 #define EMAC4_MR1_RFS_8K		0x00200000
137 #define EMAC4_MR1_RFS_16K		0x00280000
138 #define EMAC4_MR1_TFS_2K       		0x00020000
139 #define EMAC4_MR1_TFS_4K		0x00030000
140 #define EMAC4_MR1_TFS_8K		0x00040000
141 #define EMAC4_MR1_TFS_16K		0x00050000
142 #define EMAC4_MR1_TR			0x00008000
143 #define EMAC4_MR1_MWSW_001		0x00001000
144 #define EMAC4_MR1_JPSM			0x00000800
145 #define EMAC4_MR1_OBCI_MASK		0x00000038
146 #define EMAC4_MR1_OBCI_50		0x00000000
147 #define EMAC4_MR1_OBCI_66		0x00000008
148 #define EMAC4_MR1_OBCI_83		0x00000010
149 #define EMAC4_MR1_OBCI_100		0x00000018
150 #define EMAC4_MR1_OBCI_100P		0x00000020
151 #define EMAC4_MR1_OBCI(freq)		((freq) <= 50  ? EMAC4_MR1_OBCI_50 : \
152 					 (freq) <= 66  ? EMAC4_MR1_OBCI_66 : \
153 					 (freq) <= 83  ? EMAC4_MR1_OBCI_83 : \
154 					 (freq) <= 100 ? EMAC4_MR1_OBCI_100 : \
155 						EMAC4_MR1_OBCI_100P)
156 
157 /* EMACx_TMR0 */
158 #define EMAC_TMR0_GNP			0x80000000
159 #define EMAC_TMR0_DEFAULT		0x00000000
160 #define EMAC4_TMR0_TFAE_2_32		0x00000001
161 #define EMAC4_TMR0_TFAE_4_64		0x00000002
162 #define EMAC4_TMR0_TFAE_8_128		0x00000003
163 #define EMAC4_TMR0_TFAE_16_256		0x00000004
164 #define EMAC4_TMR0_TFAE_32_512		0x00000005
165 #define EMAC4_TMR0_TFAE_64_1024		0x00000006
166 #define EMAC4_TMR0_TFAE_128_2048	0x00000007
167 #define EMAC4_TMR0_DEFAULT		EMAC4_TMR0_TFAE_2_32
168 #define EMAC_TMR0_XMIT			(EMAC_TMR0_GNP | EMAC_TMR0_DEFAULT)
169 #define EMAC4_TMR0_XMIT			(EMAC_TMR0_GNP | EMAC4_TMR0_DEFAULT)
170 
171 /* EMACx_TMR1 */
172 
173 #define EMAC_TMR1(l,h)			(((l) << 27) | (((h) & 0xff) << 16))
174 #define EMAC4_TMR1(l,h)			(((l) << 27) | (((h) & 0x3ff) << 14))
175 
176 /* EMACx_RMR */
177 #define EMAC_RMR_SP			0x80000000
178 #define EMAC_RMR_SFCS			0x40000000
179 #define EMAC_RMR_RRP			0x20000000
180 #define EMAC_RMR_RFP			0x10000000
181 #define EMAC_RMR_ROP			0x08000000
182 #define EMAC_RMR_RPIR			0x04000000
183 #define EMAC_RMR_PPP			0x02000000
184 #define EMAC_RMR_PME			0x01000000
185 #define EMAC_RMR_PMME			0x00800000
186 #define EMAC_RMR_IAE			0x00400000
187 #define EMAC_RMR_MIAE			0x00200000
188 #define EMAC_RMR_BAE			0x00100000
189 #define EMAC_RMR_MAE			0x00080000
190 #define EMAC_RMR_BASE			0x00000000
191 #define EMAC4_RMR_RFAF_2_32		0x00000001
192 #define EMAC4_RMR_RFAF_4_64		0x00000002
193 #define EMAC4_RMR_RFAF_8_128		0x00000003
194 #define EMAC4_RMR_RFAF_16_256		0x00000004
195 #define EMAC4_RMR_RFAF_32_512		0x00000005
196 #define EMAC4_RMR_RFAF_64_1024		0x00000006
197 #define EMAC4_RMR_RFAF_128_2048		0x00000007
198 #define EMAC4_RMR_BASE			EMAC4_RMR_RFAF_128_2048
199 #define EMAC4_RMR_MJS_MASK              0x0001fff8
200 #define EMAC4_RMR_MJS(s)                (((s) << 3) & EMAC4_RMR_MJS_MASK)
201 
202 /* EMACx_ISR & EMACx_ISER */
203 #define EMAC4_ISR_TXPE			0x20000000
204 #define EMAC4_ISR_RXPE			0x10000000
205 #define EMAC4_ISR_TXUE			0x08000000
206 #define EMAC4_ISR_RXOE			0x04000000
207 #define EMAC_ISR_OVR			0x02000000
208 #define EMAC_ISR_PP			0x01000000
209 #define EMAC_ISR_BP			0x00800000
210 #define EMAC_ISR_RP			0x00400000
211 #define EMAC_ISR_SE			0x00200000
212 #define EMAC_ISR_ALE			0x00100000
213 #define EMAC_ISR_BFCS			0x00080000
214 #define EMAC_ISR_PTLE			0x00040000
215 #define EMAC_ISR_ORE			0x00020000
216 #define EMAC_ISR_IRE			0x00010000
217 #define EMAC_ISR_SQE			0x00000080
218 #define EMAC_ISR_TE			0x00000040
219 #define EMAC_ISR_MOS			0x00000002
220 #define EMAC_ISR_MOF			0x00000001
221 
222 /* EMACx_STACR */
223 #define EMAC_STACR_PHYD_MASK		0xffff
224 #define EMAC_STACR_PHYD_SHIFT		16
225 #define EMAC_STACR_OC			0x00008000
226 #define EMAC_STACR_PHYE			0x00004000
227 #define EMAC_STACR_STAC_MASK		0x00003000
228 #define EMAC_STACR_STAC_READ		0x00001000
229 #define EMAC_STACR_STAC_WRITE		0x00002000
230 #define EMAC_STACR_OPBC_MASK		0x00000C00
231 #define EMAC_STACR_OPBC_50		0x00000000
232 #define EMAC_STACR_OPBC_66		0x00000400
233 #define EMAC_STACR_OPBC_83		0x00000800
234 #define EMAC_STACR_OPBC_100		0x00000C00
235 #define EMAC_STACR_OPBC(freq)		((freq) <= 50 ? EMAC_STACR_OPBC_50 : \
236 					 (freq) <= 66 ? EMAC_STACR_OPBC_66 : \
237 					 (freq) <= 83 ? EMAC_STACR_OPBC_83 : EMAC_STACR_OPBC_100)
238 #define EMAC_STACR_BASE(opb)		EMAC_STACR_OPBC(opb)
239 #define EMAC4_STACR_BASE(opb)		0x00000000
240 #define EMAC_STACR_PCDA_MASK		0x1f
241 #define EMAC_STACR_PCDA_SHIFT		5
242 #define EMAC_STACR_PRA_MASK		0x1f
243 #define EMACX_STACR_STAC_MASK		0x00003800
244 #define EMACX_STACR_STAC_READ		0x00001000
245 #define EMACX_STACR_STAC_WRITE		0x00000800
246 #define EMACX_STACR_STAC_IND_ADDR	0x00002000
247 #define EMACX_STACR_STAC_IND_READ	0x00003800
248 #define EMACX_STACR_STAC_IND_READINC	0x00003000
249 #define EMACX_STACR_STAC_IND_WRITE	0x00002800
250 
251 
252 /* EMACx_TRTR */
253 #define EMAC_TRTR_SHIFT_EMAC4		24
254 #define EMAC_TRTR_SHIFT		27
255 
256 /* EMAC specific TX descriptor control fields (write access) */
257 #define EMAC_TX_CTRL_GFCS		0x0200
258 #define EMAC_TX_CTRL_GP			0x0100
259 #define EMAC_TX_CTRL_ISA		0x0080
260 #define EMAC_TX_CTRL_RSA		0x0040
261 #define EMAC_TX_CTRL_IVT		0x0020
262 #define EMAC_TX_CTRL_RVT		0x0010
263 #define EMAC_TX_CTRL_TAH_CSUM		0x000e
264 
265 /* EMAC specific TX descriptor status fields (read access) */
266 #define EMAC_TX_ST_BFCS			0x0200
267 #define EMAC_TX_ST_LCS			0x0080
268 #define EMAC_TX_ST_ED			0x0040
269 #define EMAC_TX_ST_EC			0x0020
270 #define EMAC_TX_ST_LC			0x0010
271 #define EMAC_TX_ST_MC			0x0008
272 #define EMAC_TX_ST_SC			0x0004
273 #define EMAC_TX_ST_UR			0x0002
274 #define EMAC_TX_ST_SQE			0x0001
275 #define EMAC_IS_BAD_TX			(EMAC_TX_ST_LCS | EMAC_TX_ST_ED | \
276 					 EMAC_TX_ST_EC | EMAC_TX_ST_LC | \
277 					 EMAC_TX_ST_MC | EMAC_TX_ST_UR)
278 #define EMAC_IS_BAD_TX_TAH		(EMAC_TX_ST_LCS | EMAC_TX_ST_ED | \
279 					 EMAC_TX_ST_EC | EMAC_TX_ST_LC)
280 
281 /* EMAC specific RX descriptor status fields (read access) */
282 #define EMAC_RX_ST_OE			0x0200
283 #define EMAC_RX_ST_PP			0x0100
284 #define EMAC_RX_ST_BP			0x0080
285 #define EMAC_RX_ST_RP			0x0040
286 #define EMAC_RX_ST_SE			0x0020
287 #define EMAC_RX_ST_AE			0x0010
288 #define EMAC_RX_ST_BFCS			0x0008
289 #define EMAC_RX_ST_PTL			0x0004
290 #define EMAC_RX_ST_ORE			0x0002
291 #define EMAC_RX_ST_IRE			0x0001
292 #define EMAC_RX_TAH_BAD_CSUM		0x0003
293 #define EMAC_BAD_RX_MASK		(EMAC_RX_ST_OE | EMAC_RX_ST_BP | \
294 					 EMAC_RX_ST_RP | EMAC_RX_ST_SE | \
295 					 EMAC_RX_ST_AE | EMAC_RX_ST_BFCS | \
296 					 EMAC_RX_ST_PTL | EMAC_RX_ST_ORE | \
297 					 EMAC_RX_ST_IRE )
298 #endif /* __IBM_NEWEMAC_H */
299