1 #ifndef _QIB_KERNEL_H
2 #define _QIB_KERNEL_H
3 /*
4 * Copyright (c) 2006, 2007, 2008, 2009, 2010 QLogic Corporation.
5 * All rights reserved.
6 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
7 *
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
13 *
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
16 * conditions are met:
17 *
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer.
21 *
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
26 *
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 * SOFTWARE.
35 */
36
37 /*
38 * This header file is the base header file for qlogic_ib kernel code
39 * qib_user.h serves a similar purpose for user code.
40 */
41
42 #include <linux/interrupt.h>
43 #include <linux/pci.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/mutex.h>
46 #include <linux/list.h>
47 #include <linux/scatterlist.h>
48 #include <linux/slab.h>
49 #include <linux/io.h>
50 #include <linux/fs.h>
51 #include <linux/completion.h>
52 #include <linux/kref.h>
53 #include <linux/sched.h>
54
55 #include "qib_common.h"
56 #include "qib_verbs.h"
57
58 /* only s/w major version of QLogic_IB we can handle */
59 #define QIB_CHIP_VERS_MAJ 2U
60
61 /* don't care about this except printing */
62 #define QIB_CHIP_VERS_MIN 0U
63
64 /* The Organization Unique Identifier (Mfg code), and its position in GUID */
65 #define QIB_OUI 0x001175
66 #define QIB_OUI_LSB 40
67
68 /*
69 * per driver stats, either not device nor port-specific, or
70 * summed over all of the devices and ports.
71 * They are described by name via ipathfs filesystem, so layout
72 * and number of elements can change without breaking compatibility.
73 * If members are added or deleted qib_statnames[] in qib_fs.c must
74 * change to match.
75 */
76 struct qlogic_ib_stats {
77 __u64 sps_ints; /* number of interrupts handled */
78 __u64 sps_errints; /* number of error interrupts */
79 __u64 sps_txerrs; /* tx-related packet errors */
80 __u64 sps_rcverrs; /* non-crc rcv packet errors */
81 __u64 sps_hwerrs; /* hardware errors reported (parity, etc.) */
82 __u64 sps_nopiobufs; /* no pio bufs avail from kernel */
83 __u64 sps_ctxts; /* number of contexts currently open */
84 __u64 sps_lenerrs; /* number of kernel packets where RHF != LRH len */
85 __u64 sps_buffull;
86 __u64 sps_hdrfull;
87 };
88
89 extern struct qlogic_ib_stats qib_stats;
90 extern struct pci_error_handlers qib_pci_err_handler;
91 extern struct pci_driver qib_driver;
92
93 #define QIB_CHIP_SWVERSION QIB_CHIP_VERS_MAJ
94 /*
95 * First-cut critierion for "device is active" is
96 * two thousand dwords combined Tx, Rx traffic per
97 * 5-second interval. SMA packets are 64 dwords,
98 * and occur "a few per second", presumably each way.
99 */
100 #define QIB_TRAFFIC_ACTIVE_THRESHOLD (2000)
101
102 /*
103 * Struct used to indicate which errors are logged in each of the
104 * error-counters that are logged to EEPROM. A counter is incremented
105 * _once_ (saturating at 255) for each event with any bits set in
106 * the error or hwerror register masks below.
107 */
108 #define QIB_EEP_LOG_CNT (4)
109 struct qib_eep_log_mask {
110 u64 errs_to_log;
111 u64 hwerrs_to_log;
112 };
113
114 /*
115 * Below contains all data related to a single context (formerly called port).
116 */
117 struct qib_ctxtdata {
118 void **rcvegrbuf;
119 dma_addr_t *rcvegrbuf_phys;
120 /* rcvhdrq base, needs mmap before useful */
121 void *rcvhdrq;
122 /* kernel virtual address where hdrqtail is updated */
123 void *rcvhdrtail_kvaddr;
124 /*
125 * temp buffer for expected send setup, allocated at open, instead
126 * of each setup call
127 */
128 void *tid_pg_list;
129 /*
130 * Shared page for kernel to signal user processes that send buffers
131 * need disarming. The process should call QIB_CMD_DISARM_BUFS
132 * or QIB_CMD_ACK_EVENT with IPATH_EVENT_DISARM_BUFS set.
133 */
134 unsigned long *user_event_mask;
135 /* when waiting for rcv or pioavail */
136 wait_queue_head_t wait;
137 /*
138 * rcvegr bufs base, physical, must fit
139 * in 44 bits so 32 bit programs mmap64 44 bit works)
140 */
141 dma_addr_t rcvegr_phys;
142 /* mmap of hdrq, must fit in 44 bits */
143 dma_addr_t rcvhdrq_phys;
144 dma_addr_t rcvhdrqtailaddr_phys;
145
146 /*
147 * number of opens (including slave sub-contexts) on this instance
148 * (ignoring forks, dup, etc. for now)
149 */
150 int cnt;
151 /*
152 * how much space to leave at start of eager TID entries for
153 * protocol use, on each TID
154 */
155 /* instead of calculating it */
156 unsigned ctxt;
157 /* non-zero if ctxt is being shared. */
158 u16 subctxt_cnt;
159 /* non-zero if ctxt is being shared. */
160 u16 subctxt_id;
161 /* number of eager TID entries. */
162 u16 rcvegrcnt;
163 /* index of first eager TID entry. */
164 u16 rcvegr_tid_base;
165 /* number of pio bufs for this ctxt (all procs, if shared) */
166 u32 piocnt;
167 /* first pio buffer for this ctxt */
168 u32 pio_base;
169 /* chip offset of PIO buffers for this ctxt */
170 u32 piobufs;
171 /* how many alloc_pages() chunks in rcvegrbuf_pages */
172 u32 rcvegrbuf_chunks;
173 /* how many egrbufs per chunk */
174 u16 rcvegrbufs_perchunk;
175 /* ilog2 of above */
176 u16 rcvegrbufs_perchunk_shift;
177 /* order for rcvegrbuf_pages */
178 size_t rcvegrbuf_size;
179 /* rcvhdrq size (for freeing) */
180 size_t rcvhdrq_size;
181 /* per-context flags for fileops/intr communication */
182 unsigned long flag;
183 /* next expected TID to check when looking for free */
184 u32 tidcursor;
185 /* WAIT_RCV that timed out, no interrupt */
186 u32 rcvwait_to;
187 /* WAIT_PIO that timed out, no interrupt */
188 u32 piowait_to;
189 /* WAIT_RCV already happened, no wait */
190 u32 rcvnowait;
191 /* WAIT_PIO already happened, no wait */
192 u32 pionowait;
193 /* total number of polled urgent packets */
194 u32 urgent;
195 /* saved total number of polled urgent packets for poll edge trigger */
196 u32 urgent_poll;
197 /* pid of process using this ctxt */
198 pid_t pid;
199 pid_t subpid[QLOGIC_IB_MAX_SUBCTXT];
200 /* same size as task_struct .comm[], command that opened context */
201 char comm[16];
202 /* pkeys set by this use of this ctxt */
203 u16 pkeys[4];
204 /* so file ops can get at unit */
205 struct qib_devdata *dd;
206 /* so funcs that need physical port can get it easily */
207 struct qib_pportdata *ppd;
208 /* A page of memory for rcvhdrhead, rcvegrhead, rcvegrtail * N */
209 void *subctxt_uregbase;
210 /* An array of pages for the eager receive buffers * N */
211 void *subctxt_rcvegrbuf;
212 /* An array of pages for the eager header queue entries * N */
213 void *subctxt_rcvhdr_base;
214 /* The version of the library which opened this ctxt */
215 u32 userversion;
216 /* Bitmask of active slaves */
217 u32 active_slaves;
218 /* Type of packets or conditions we want to poll for */
219 u16 poll_type;
220 /* receive packet sequence counter */
221 u8 seq_cnt;
222 u8 redirect_seq_cnt;
223 /* ctxt rcvhdrq head offset */
224 u32 head;
225 u32 pkt_count;
226 /* lookaside fields */
227 struct qib_qp *lookaside_qp;
228 u32 lookaside_qpn;
229 /* QPs waiting for context processing */
230 struct list_head qp_wait_list;
231 };
232
233 struct qib_sge_state;
234
235 struct qib_sdma_txreq {
236 int flags;
237 int sg_count;
238 dma_addr_t addr;
239 void (*callback)(struct qib_sdma_txreq *, int);
240 u16 start_idx; /* sdma private */
241 u16 next_descq_idx; /* sdma private */
242 struct list_head list; /* sdma private */
243 };
244
245 struct qib_sdma_desc {
246 __le64 qw[2];
247 };
248
249 struct qib_verbs_txreq {
250 struct qib_sdma_txreq txreq;
251 struct qib_qp *qp;
252 struct qib_swqe *wqe;
253 u32 dwords;
254 u16 hdr_dwords;
255 u16 hdr_inx;
256 struct qib_pio_header *align_buf;
257 struct qib_mregion *mr;
258 struct qib_sge_state *ss;
259 };
260
261 #define QIB_SDMA_TXREQ_F_USELARGEBUF 0x1
262 #define QIB_SDMA_TXREQ_F_HEADTOHOST 0x2
263 #define QIB_SDMA_TXREQ_F_INTREQ 0x4
264 #define QIB_SDMA_TXREQ_F_FREEBUF 0x8
265 #define QIB_SDMA_TXREQ_F_FREEDESC 0x10
266
267 #define QIB_SDMA_TXREQ_S_OK 0
268 #define QIB_SDMA_TXREQ_S_SENDERROR 1
269 #define QIB_SDMA_TXREQ_S_ABORTED 2
270 #define QIB_SDMA_TXREQ_S_SHUTDOWN 3
271
272 /*
273 * Get/Set IB link-level config parameters for f_get/set_ib_cfg()
274 * Mostly for MADs that set or query link parameters, also ipath
275 * config interfaces
276 */
277 #define QIB_IB_CFG_LIDLMC 0 /* LID (LS16b) and Mask (MS16b) */
278 #define QIB_IB_CFG_LWID_ENB 2 /* allowed Link-width */
279 #define QIB_IB_CFG_LWID 3 /* currently active Link-width */
280 #define QIB_IB_CFG_SPD_ENB 4 /* allowed Link speeds */
281 #define QIB_IB_CFG_SPD 5 /* current Link spd */
282 #define QIB_IB_CFG_RXPOL_ENB 6 /* Auto-RX-polarity enable */
283 #define QIB_IB_CFG_LREV_ENB 7 /* Auto-Lane-reversal enable */
284 #define QIB_IB_CFG_LINKLATENCY 8 /* Link Latency (IB1.2 only) */
285 #define QIB_IB_CFG_HRTBT 9 /* IB heartbeat off/enable/auto; DDR/QDR only */
286 #define QIB_IB_CFG_OP_VLS 10 /* operational VLs */
287 #define QIB_IB_CFG_VL_HIGH_CAP 11 /* num of VL high priority weights */
288 #define QIB_IB_CFG_VL_LOW_CAP 12 /* num of VL low priority weights */
289 #define QIB_IB_CFG_OVERRUN_THRESH 13 /* IB overrun threshold */
290 #define QIB_IB_CFG_PHYERR_THRESH 14 /* IB PHY error threshold */
291 #define QIB_IB_CFG_LINKDEFAULT 15 /* IB link default (sleep/poll) */
292 #define QIB_IB_CFG_PKEYS 16 /* update partition keys */
293 #define QIB_IB_CFG_MTU 17 /* update MTU in IBC */
294 #define QIB_IB_CFG_LSTATE 18 /* update linkcmd and linkinitcmd in IBC */
295 #define QIB_IB_CFG_VL_HIGH_LIMIT 19
296 #define QIB_IB_CFG_PMA_TICKS 20 /* PMA sample tick resolution */
297 #define QIB_IB_CFG_PORT 21 /* switch port we are connected to */
298
299 /*
300 * for CFG_LSTATE: LINKCMD in upper 16 bits, LINKINITCMD in lower 16
301 * IB_LINKINITCMD_POLL and SLEEP are also used as set/get values for
302 * QIB_IB_CFG_LINKDEFAULT cmd
303 */
304 #define IB_LINKCMD_DOWN (0 << 16)
305 #define IB_LINKCMD_ARMED (1 << 16)
306 #define IB_LINKCMD_ACTIVE (2 << 16)
307 #define IB_LINKINITCMD_NOP 0
308 #define IB_LINKINITCMD_POLL 1
309 #define IB_LINKINITCMD_SLEEP 2
310 #define IB_LINKINITCMD_DISABLE 3
311
312 /*
313 * valid states passed to qib_set_linkstate() user call
314 */
315 #define QIB_IB_LINKDOWN 0
316 #define QIB_IB_LINKARM 1
317 #define QIB_IB_LINKACTIVE 2
318 #define QIB_IB_LINKDOWN_ONLY 3
319 #define QIB_IB_LINKDOWN_SLEEP 4
320 #define QIB_IB_LINKDOWN_DISABLE 5
321
322 /*
323 * These 7 values (SDR, DDR, and QDR may be ORed for auto-speed
324 * negotiation) are used for the 3rd argument to path_f_set_ib_cfg
325 * with cmd QIB_IB_CFG_SPD_ENB, by direct calls or via sysfs. They
326 * are also the the possible values for qib_link_speed_enabled and active
327 * The values were chosen to match values used within the IB spec.
328 */
329 #define QIB_IB_SDR 1
330 #define QIB_IB_DDR 2
331 #define QIB_IB_QDR 4
332
333 #define QIB_DEFAULT_MTU 4096
334
335 /* max number of IB ports supported per HCA */
336 #define QIB_MAX_IB_PORTS 2
337
338 /*
339 * Possible IB config parameters for f_get/set_ib_table()
340 */
341 #define QIB_IB_TBL_VL_HIGH_ARB 1 /* Get/set VL high priority weights */
342 #define QIB_IB_TBL_VL_LOW_ARB 2 /* Get/set VL low priority weights */
343
344 /*
345 * Possible "operations" for f_rcvctrl(ppd, op, ctxt)
346 * these are bits so they can be combined, e.g.
347 * QIB_RCVCTRL_INTRAVAIL_ENB | QIB_RCVCTRL_CTXT_ENB
348 */
349 #define QIB_RCVCTRL_TAILUPD_ENB 0x01
350 #define QIB_RCVCTRL_TAILUPD_DIS 0x02
351 #define QIB_RCVCTRL_CTXT_ENB 0x04
352 #define QIB_RCVCTRL_CTXT_DIS 0x08
353 #define QIB_RCVCTRL_INTRAVAIL_ENB 0x10
354 #define QIB_RCVCTRL_INTRAVAIL_DIS 0x20
355 #define QIB_RCVCTRL_PKEY_ENB 0x40 /* Note, default is enabled */
356 #define QIB_RCVCTRL_PKEY_DIS 0x80
357 #define QIB_RCVCTRL_BP_ENB 0x0100
358 #define QIB_RCVCTRL_BP_DIS 0x0200
359 #define QIB_RCVCTRL_TIDFLOW_ENB 0x0400
360 #define QIB_RCVCTRL_TIDFLOW_DIS 0x0800
361
362 /*
363 * Possible "operations" for f_sendctrl(ppd, op, var)
364 * these are bits so they can be combined, e.g.
365 * QIB_SENDCTRL_BUFAVAIL_ENB | QIB_SENDCTRL_ENB
366 * Some operations (e.g. DISARM, ABORT) are known to
367 * be "one-shot", so do not modify shadow.
368 */
369 #define QIB_SENDCTRL_DISARM (0x1000)
370 #define QIB_SENDCTRL_DISARM_BUF(bufn) ((bufn) | QIB_SENDCTRL_DISARM)
371 /* available (0x2000) */
372 #define QIB_SENDCTRL_AVAIL_DIS (0x4000)
373 #define QIB_SENDCTRL_AVAIL_ENB (0x8000)
374 #define QIB_SENDCTRL_AVAIL_BLIP (0x10000)
375 #define QIB_SENDCTRL_SEND_DIS (0x20000)
376 #define QIB_SENDCTRL_SEND_ENB (0x40000)
377 #define QIB_SENDCTRL_FLUSH (0x80000)
378 #define QIB_SENDCTRL_CLEAR (0x100000)
379 #define QIB_SENDCTRL_DISARM_ALL (0x200000)
380
381 /*
382 * These are the generic indices for requesting per-port
383 * counter values via the f_portcntr function. They
384 * are always returned as 64 bit values, although most
385 * are 32 bit counters.
386 */
387 /* send-related counters */
388 #define QIBPORTCNTR_PKTSEND 0U
389 #define QIBPORTCNTR_WORDSEND 1U
390 #define QIBPORTCNTR_PSXMITDATA 2U
391 #define QIBPORTCNTR_PSXMITPKTS 3U
392 #define QIBPORTCNTR_PSXMITWAIT 4U
393 #define QIBPORTCNTR_SENDSTALL 5U
394 /* receive-related counters */
395 #define QIBPORTCNTR_PKTRCV 6U
396 #define QIBPORTCNTR_PSRCVDATA 7U
397 #define QIBPORTCNTR_PSRCVPKTS 8U
398 #define QIBPORTCNTR_RCVEBP 9U
399 #define QIBPORTCNTR_RCVOVFL 10U
400 #define QIBPORTCNTR_WORDRCV 11U
401 /* IB link related error counters */
402 #define QIBPORTCNTR_RXLOCALPHYERR 12U
403 #define QIBPORTCNTR_RXVLERR 13U
404 #define QIBPORTCNTR_ERRICRC 14U
405 #define QIBPORTCNTR_ERRVCRC 15U
406 #define QIBPORTCNTR_ERRLPCRC 16U
407 #define QIBPORTCNTR_BADFORMAT 17U
408 #define QIBPORTCNTR_ERR_RLEN 18U
409 #define QIBPORTCNTR_IBSYMBOLERR 19U
410 #define QIBPORTCNTR_INVALIDRLEN 20U
411 #define QIBPORTCNTR_UNSUPVL 21U
412 #define QIBPORTCNTR_EXCESSBUFOVFL 22U
413 #define QIBPORTCNTR_ERRLINK 23U
414 #define QIBPORTCNTR_IBLINKDOWN 24U
415 #define QIBPORTCNTR_IBLINKERRRECOV 25U
416 #define QIBPORTCNTR_LLI 26U
417 /* other error counters */
418 #define QIBPORTCNTR_RXDROPPKT 27U
419 #define QIBPORTCNTR_VL15PKTDROP 28U
420 #define QIBPORTCNTR_ERRPKEY 29U
421 #define QIBPORTCNTR_KHDROVFL 30U
422 /* sampling counters (these are actually control registers) */
423 #define QIBPORTCNTR_PSINTERVAL 31U
424 #define QIBPORTCNTR_PSSTART 32U
425 #define QIBPORTCNTR_PSSTAT 33U
426
427 /* how often we check for packet activity for "power on hours (in seconds) */
428 #define ACTIVITY_TIMER 5
429
430 #define MAX_NAME_SIZE 64
431 struct qib_msix_entry {
432 struct msix_entry msix;
433 void *arg;
434 char name[MAX_NAME_SIZE];
435 cpumask_var_t mask;
436 };
437
438 /* Below is an opaque struct. Each chip (device) can maintain
439 * private data needed for its operation, but not germane to the
440 * rest of the driver. For convenience, we define another that
441 * is chip-specific, per-port
442 */
443 struct qib_chip_specific;
444 struct qib_chipport_specific;
445
446 enum qib_sdma_states {
447 qib_sdma_state_s00_hw_down,
448 qib_sdma_state_s10_hw_start_up_wait,
449 qib_sdma_state_s20_idle,
450 qib_sdma_state_s30_sw_clean_up_wait,
451 qib_sdma_state_s40_hw_clean_up_wait,
452 qib_sdma_state_s50_hw_halt_wait,
453 qib_sdma_state_s99_running,
454 };
455
456 enum qib_sdma_events {
457 qib_sdma_event_e00_go_hw_down,
458 qib_sdma_event_e10_go_hw_start,
459 qib_sdma_event_e20_hw_started,
460 qib_sdma_event_e30_go_running,
461 qib_sdma_event_e40_sw_cleaned,
462 qib_sdma_event_e50_hw_cleaned,
463 qib_sdma_event_e60_hw_halted,
464 qib_sdma_event_e70_go_idle,
465 qib_sdma_event_e7220_err_halted,
466 qib_sdma_event_e7322_err_halted,
467 qib_sdma_event_e90_timer_tick,
468 };
469
470 extern char *qib_sdma_state_names[];
471 extern char *qib_sdma_event_names[];
472
473 struct sdma_set_state_action {
474 unsigned op_enable:1;
475 unsigned op_intenable:1;
476 unsigned op_halt:1;
477 unsigned op_drain:1;
478 unsigned go_s99_running_tofalse:1;
479 unsigned go_s99_running_totrue:1;
480 };
481
482 struct qib_sdma_state {
483 struct kref kref;
484 struct completion comp;
485 enum qib_sdma_states current_state;
486 struct sdma_set_state_action *set_state_action;
487 unsigned current_op;
488 unsigned go_s99_running;
489 unsigned first_sendbuf;
490 unsigned last_sendbuf; /* really last +1 */
491 /* debugging/devel */
492 enum qib_sdma_states previous_state;
493 unsigned previous_op;
494 enum qib_sdma_events last_event;
495 };
496
497 struct xmit_wait {
498 struct timer_list timer;
499 u64 counter;
500 u8 flags;
501 struct cache {
502 u64 psxmitdata;
503 u64 psrcvdata;
504 u64 psxmitpkts;
505 u64 psrcvpkts;
506 u64 psxmitwait;
507 } counter_cache;
508 };
509
510 /*
511 * The structure below encapsulates data relevant to a physical IB Port.
512 * Current chips support only one such port, but the separation
513 * clarifies things a bit. Note that to conform to IB conventions,
514 * port-numbers are one-based. The first or only port is port1.
515 */
516 struct qib_pportdata {
517 struct qib_ibport ibport_data;
518
519 struct qib_devdata *dd;
520 struct qib_chippport_specific *cpspec; /* chip-specific per-port */
521 struct kobject pport_kobj;
522 struct kobject sl2vl_kobj;
523 struct kobject diagc_kobj;
524
525 /* GUID for this interface, in network order */
526 __be64 guid;
527
528 /* QIB_POLL, etc. link-state specific flags, per port */
529 u32 lflags;
530 /* qib_lflags driver is waiting for */
531 u32 state_wanted;
532 spinlock_t lflags_lock;
533 /* number of (port-specific) interrupts for this port -- saturates... */
534 u32 int_counter;
535
536 /* ref count for each pkey */
537 atomic_t pkeyrefs[4];
538
539 /*
540 * this address is mapped readonly into user processes so they can
541 * get status cheaply, whenever they want. One qword of status per port
542 */
543 u64 *statusp;
544
545 /* SendDMA related entries */
546 spinlock_t sdma_lock;
547 struct qib_sdma_state sdma_state;
548 unsigned long sdma_buf_jiffies;
549 struct qib_sdma_desc *sdma_descq;
550 u64 sdma_descq_added;
551 u64 sdma_descq_removed;
552 u16 sdma_descq_cnt;
553 u16 sdma_descq_tail;
554 u16 sdma_descq_head;
555 u16 sdma_next_intr;
556 u16 sdma_reset_wait;
557 u8 sdma_generation;
558 struct tasklet_struct sdma_sw_clean_up_task;
559 struct list_head sdma_activelist;
560
561 dma_addr_t sdma_descq_phys;
562 volatile __le64 *sdma_head_dma; /* DMA'ed by chip */
563 dma_addr_t sdma_head_phys;
564
565 wait_queue_head_t state_wait; /* for state_wanted */
566
567 /* HoL blocking for SMP replies */
568 unsigned hol_state;
569 struct timer_list hol_timer;
570
571 /*
572 * Shadow copies of registers; size indicates read access size.
573 * Most of them are readonly, but some are write-only register,
574 * where we manipulate the bits in the shadow copy, and then write
575 * the shadow copy to qlogic_ib.
576 *
577 * We deliberately make most of these 32 bits, since they have
578 * restricted range. For any that we read, we won't to generate 32
579 * bit accesses, since Opteron will generate 2 separate 32 bit HT
580 * transactions for a 64 bit read, and we want to avoid unnecessary
581 * bus transactions.
582 */
583
584 /* This is the 64 bit group */
585 /* last ibcstatus. opaque outside chip-specific code */
586 u64 lastibcstat;
587
588 /* these are the "32 bit" regs */
589
590 /*
591 * the following two are 32-bit bitmasks, but {test,clear,set}_bit
592 * all expect bit fields to be "unsigned long"
593 */
594 unsigned long p_rcvctrl; /* shadow per-port rcvctrl */
595 unsigned long p_sendctrl; /* shadow per-port sendctrl */
596
597 u32 ibmtu; /* The MTU programmed for this unit */
598 /*
599 * Current max size IB packet (in bytes) including IB headers, that
600 * we can send. Changes when ibmtu changes.
601 */
602 u32 ibmaxlen;
603 /*
604 * ibmaxlen at init time, limited by chip and by receive buffer
605 * size. Not changed after init.
606 */
607 u32 init_ibmaxlen;
608 /* LID programmed for this instance */
609 u16 lid;
610 /* list of pkeys programmed; 0 if not set */
611 u16 pkeys[4];
612 /* LID mask control */
613 u8 lmc;
614 u8 link_width_supported;
615 u8 link_speed_supported;
616 u8 link_width_enabled;
617 u8 link_speed_enabled;
618 u8 link_width_active;
619 u8 link_speed_active;
620 u8 vls_supported;
621 u8 vls_operational;
622 /* Rx Polarity inversion (compensate for ~tx on partner) */
623 u8 rx_pol_inv;
624
625 u8 hw_pidx; /* physical port index */
626 u8 port; /* IB port number and index into dd->pports - 1 */
627
628 u8 delay_mult;
629
630 /* used to override LED behavior */
631 u8 led_override; /* Substituted for normal value, if non-zero */
632 u16 led_override_timeoff; /* delta to next timer event */
633 u8 led_override_vals[2]; /* Alternates per blink-frame */
634 u8 led_override_phase; /* Just counts, LSB picks from vals[] */
635 atomic_t led_override_timer_active;
636 /* Used to flash LEDs in override mode */
637 struct timer_list led_override_timer;
638 struct xmit_wait cong_stats;
639 struct timer_list symerr_clear_timer;
640 };
641
642 /* Observers. Not to be taken lightly, possibly not to ship. */
643 /*
644 * If a diag read or write is to (bottom <= offset <= top),
645 * the "hoook" is called, allowing, e.g. shadows to be
646 * updated in sync with the driver. struct diag_observer
647 * is the "visible" part.
648 */
649 struct diag_observer;
650
651 typedef int (*diag_hook) (struct qib_devdata *dd,
652 const struct diag_observer *op,
653 u32 offs, u64 *data, u64 mask, int only_32);
654
655 struct diag_observer {
656 diag_hook hook;
657 u32 bottom;
658 u32 top;
659 };
660
661 extern int qib_register_observer(struct qib_devdata *dd,
662 const struct diag_observer *op);
663
664 /* Only declared here, not defined. Private to diags */
665 struct diag_observer_list_elt;
666
667 /* device data struct now contains only "general per-device" info.
668 * fields related to a physical IB port are in a qib_pportdata struct,
669 * described above) while fields only used by a particular chip-type are in
670 * a qib_chipdata struct, whose contents are opaque to this file.
671 */
672 struct qib_devdata {
673 struct qib_ibdev verbs_dev; /* must be first */
674 struct list_head list;
675 /* pointers to related structs for this device */
676 /* pci access data structure */
677 struct pci_dev *pcidev;
678 struct cdev *user_cdev;
679 struct cdev *diag_cdev;
680 struct device *user_device;
681 struct device *diag_device;
682
683 /* mem-mapped pointer to base of chip regs */
684 u64 __iomem *kregbase;
685 /* end of mem-mapped chip space excluding sendbuf and user regs */
686 u64 __iomem *kregend;
687 /* physical address of chip for io_remap, etc. */
688 resource_size_t physaddr;
689 /* qib_cfgctxts pointers */
690 struct qib_ctxtdata **rcd; /* Receive Context Data */
691
692 /* qib_pportdata, points to array of (physical) port-specific
693 * data structs, indexed by pidx (0..n-1)
694 */
695 struct qib_pportdata *pport;
696 struct qib_chip_specific *cspec; /* chip-specific */
697
698 /* kvirt address of 1st 2k pio buffer */
699 void __iomem *pio2kbase;
700 /* kvirt address of 1st 4k pio buffer */
701 void __iomem *pio4kbase;
702 /* mem-mapped pointer to base of PIO buffers (if using WC PAT) */
703 void __iomem *piobase;
704 /* mem-mapped pointer to base of user chip regs (if using WC PAT) */
705 u64 __iomem *userbase;
706 void __iomem *piovl15base; /* base of VL15 buffers, if not WC */
707 /*
708 * points to area where PIOavail registers will be DMA'ed.
709 * Has to be on a page of it's own, because the page will be
710 * mapped into user program space. This copy is *ONLY* ever
711 * written by DMA, not by the driver! Need a copy per device
712 * when we get to multiple devices
713 */
714 volatile __le64 *pioavailregs_dma; /* DMA'ed by chip */
715 /* physical address where updates occur */
716 dma_addr_t pioavailregs_phys;
717
718 /* device-specific implementations of functions needed by
719 * common code. Contrary to previous consensus, we can't
720 * really just point to a device-specific table, because we
721 * may need to "bend", e.g. *_f_put_tid
722 */
723 /* fallback to alternate interrupt type if possible */
724 int (*f_intr_fallback)(struct qib_devdata *);
725 /* hard reset chip */
726 int (*f_reset)(struct qib_devdata *);
727 void (*f_quiet_serdes)(struct qib_pportdata *);
728 int (*f_bringup_serdes)(struct qib_pportdata *);
729 int (*f_early_init)(struct qib_devdata *);
730 void (*f_clear_tids)(struct qib_devdata *, struct qib_ctxtdata *);
731 void (*f_put_tid)(struct qib_devdata *, u64 __iomem*,
732 u32, unsigned long);
733 void (*f_cleanup)(struct qib_devdata *);
734 void (*f_setextled)(struct qib_pportdata *, u32);
735 /* fill out chip-specific fields */
736 int (*f_get_base_info)(struct qib_ctxtdata *, struct qib_base_info *);
737 /* free irq */
738 void (*f_free_irq)(struct qib_devdata *);
739 struct qib_message_header *(*f_get_msgheader)
740 (struct qib_devdata *, __le32 *);
741 void (*f_config_ctxts)(struct qib_devdata *);
742 int (*f_get_ib_cfg)(struct qib_pportdata *, int);
743 int (*f_set_ib_cfg)(struct qib_pportdata *, int, u32);
744 int (*f_set_ib_loopback)(struct qib_pportdata *, const char *);
745 int (*f_get_ib_table)(struct qib_pportdata *, int, void *);
746 int (*f_set_ib_table)(struct qib_pportdata *, int, void *);
747 u32 (*f_iblink_state)(u64);
748 u8 (*f_ibphys_portstate)(u64);
749 void (*f_xgxs_reset)(struct qib_pportdata *);
750 /* per chip actions needed for IB Link up/down changes */
751 int (*f_ib_updown)(struct qib_pportdata *, int, u64);
752 u32 __iomem *(*f_getsendbuf)(struct qib_pportdata *, u64, u32 *);
753 /* Read/modify/write of GPIO pins (potentially chip-specific */
754 int (*f_gpio_mod)(struct qib_devdata *dd, u32 out, u32 dir,
755 u32 mask);
756 /* Enable writes to config EEPROM (if supported) */
757 int (*f_eeprom_wen)(struct qib_devdata *dd, int wen);
758 /*
759 * modify rcvctrl shadow[s] and write to appropriate chip-regs.
760 * see above QIB_RCVCTRL_xxx_ENB/DIS for operations.
761 * (ctxt == -1) means "all contexts", only meaningful for
762 * clearing. Could remove if chip_spec shutdown properly done.
763 */
764 void (*f_rcvctrl)(struct qib_pportdata *, unsigned int op,
765 int ctxt);
766 /* Read/modify/write sendctrl appropriately for op and port. */
767 void (*f_sendctrl)(struct qib_pportdata *, u32 op);
768 void (*f_set_intr_state)(struct qib_devdata *, u32);
769 void (*f_set_armlaunch)(struct qib_devdata *, u32);
770 void (*f_wantpiobuf_intr)(struct qib_devdata *, u32);
771 int (*f_late_initreg)(struct qib_devdata *);
772 int (*f_init_sdma_regs)(struct qib_pportdata *);
773 u16 (*f_sdma_gethead)(struct qib_pportdata *);
774 int (*f_sdma_busy)(struct qib_pportdata *);
775 void (*f_sdma_update_tail)(struct qib_pportdata *, u16);
776 void (*f_sdma_set_desc_cnt)(struct qib_pportdata *, unsigned);
777 void (*f_sdma_sendctrl)(struct qib_pportdata *, unsigned);
778 void (*f_sdma_hw_clean_up)(struct qib_pportdata *);
779 void (*f_sdma_hw_start_up)(struct qib_pportdata *);
780 void (*f_sdma_init_early)(struct qib_pportdata *);
781 void (*f_set_cntr_sample)(struct qib_pportdata *, u32, u32);
782 void (*f_update_usrhead)(struct qib_ctxtdata *, u64, u32, u32, u32);
783 u32 (*f_hdrqempty)(struct qib_ctxtdata *);
784 u64 (*f_portcntr)(struct qib_pportdata *, u32);
785 u32 (*f_read_cntrs)(struct qib_devdata *, loff_t, char **,
786 u64 **);
787 u32 (*f_read_portcntrs)(struct qib_devdata *, loff_t, u32,
788 char **, u64 **);
789 u32 (*f_setpbc_control)(struct qib_pportdata *, u32, u8, u8);
790 void (*f_initvl15_bufs)(struct qib_devdata *);
791 void (*f_init_ctxt)(struct qib_ctxtdata *);
792 void (*f_txchk_change)(struct qib_devdata *, u32, u32, u32,
793 struct qib_ctxtdata *);
794 void (*f_writescratch)(struct qib_devdata *, u32);
795 int (*f_tempsense_rd)(struct qib_devdata *, int regnum);
796
797 char *boardname; /* human readable board info */
798
799 /* template for writing TIDs */
800 u64 tidtemplate;
801 /* value to write to free TIDs */
802 u64 tidinvalid;
803
804 /* number of registers used for pioavail */
805 u32 pioavregs;
806 /* device (not port) flags, basically device capabilities */
807 u32 flags;
808 /* last buffer for user use */
809 u32 lastctxt_piobuf;
810
811 /* saturating counter of (non-port-specific) device interrupts */
812 u32 int_counter;
813
814 /* pio bufs allocated per ctxt */
815 u32 pbufsctxt;
816 /* if remainder on bufs/ctxt, ctxts < extrabuf get 1 extra */
817 u32 ctxts_extrabuf;
818 /*
819 * number of ctxts configured as max; zero is set to number chip
820 * supports, less gives more pio bufs/ctxt, etc.
821 */
822 u32 cfgctxts;
823 /*
824 * number of ctxts available for PSM open
825 */
826 u32 freectxts;
827
828 /*
829 * hint that we should update pioavailshadow before
830 * looking for a PIO buffer
831 */
832 u32 upd_pio_shadow;
833
834 /* internal debugging stats */
835 u32 maxpkts_call;
836 u32 avgpkts_call;
837 u64 nopiobufs;
838
839 /* PCI Vendor ID (here for NodeInfo) */
840 u16 vendorid;
841 /* PCI Device ID (here for NodeInfo) */
842 u16 deviceid;
843 /* for write combining settings */
844 unsigned long wc_cookie;
845 unsigned long wc_base;
846 unsigned long wc_len;
847
848 /* shadow copy of struct page *'s for exp tid pages */
849 struct page **pageshadow;
850 /* shadow copy of dma handles for exp tid pages */
851 dma_addr_t *physshadow;
852 u64 __iomem *egrtidbase;
853 spinlock_t sendctrl_lock; /* protect changes to sendctrl shadow */
854 /* around rcd and (user ctxts) ctxt_cnt use (intr vs free) */
855 spinlock_t uctxt_lock; /* rcd and user context changes */
856 /*
857 * per unit status, see also portdata statusp
858 * mapped readonly into user processes so they can get unit and
859 * IB link status cheaply
860 */
861 u64 *devstatusp;
862 char *freezemsg; /* freeze msg if hw error put chip in freeze */
863 u32 freezelen; /* max length of freezemsg */
864 /* timer used to prevent stats overflow, error throttling, etc. */
865 struct timer_list stats_timer;
866
867 /* timer to verify interrupts work, and fallback if possible */
868 struct timer_list intrchk_timer;
869 unsigned long ureg_align; /* user register alignment */
870
871 /*
872 * Protects pioavailshadow, pioavailkernel, pio_need_disarm, and
873 * pio_writing.
874 */
875 spinlock_t pioavail_lock;
876
877 /*
878 * Shadow copies of registers; size indicates read access size.
879 * Most of them are readonly, but some are write-only register,
880 * where we manipulate the bits in the shadow copy, and then write
881 * the shadow copy to qlogic_ib.
882 *
883 * We deliberately make most of these 32 bits, since they have
884 * restricted range. For any that we read, we won't to generate 32
885 * bit accesses, since Opteron will generate 2 separate 32 bit HT
886 * transactions for a 64 bit read, and we want to avoid unnecessary
887 * bus transactions.
888 */
889
890 /* This is the 64 bit group */
891
892 unsigned long pioavailshadow[6];
893 /* bitmap of send buffers available for the kernel to use with PIO. */
894 unsigned long pioavailkernel[6];
895 /* bitmap of send buffers which need to be disarmed. */
896 unsigned long pio_need_disarm[3];
897 /* bitmap of send buffers which are being written to. */
898 unsigned long pio_writing[3];
899 /* kr_revision shadow */
900 u64 revision;
901 /* Base GUID for device (from eeprom, network order) */
902 __be64 base_guid;
903
904 /*
905 * kr_sendpiobufbase value (chip offset of pio buffers), and the
906 * base of the 2KB buffer s(user processes only use 2K)
907 */
908 u64 piobufbase;
909 u32 pio2k_bufbase;
910
911 /* these are the "32 bit" regs */
912
913 /* number of GUIDs in the flash for this interface */
914 u32 nguid;
915 /*
916 * the following two are 32-bit bitmasks, but {test,clear,set}_bit
917 * all expect bit fields to be "unsigned long"
918 */
919 unsigned long rcvctrl; /* shadow per device rcvctrl */
920 unsigned long sendctrl; /* shadow per device sendctrl */
921
922 /* value we put in kr_rcvhdrcnt */
923 u32 rcvhdrcnt;
924 /* value we put in kr_rcvhdrsize */
925 u32 rcvhdrsize;
926 /* value we put in kr_rcvhdrentsize */
927 u32 rcvhdrentsize;
928 /* kr_ctxtcnt value */
929 u32 ctxtcnt;
930 /* kr_pagealign value */
931 u32 palign;
932 /* number of "2KB" PIO buffers */
933 u32 piobcnt2k;
934 /* size in bytes of "2KB" PIO buffers */
935 u32 piosize2k;
936 /* max usable size in dwords of a "2KB" PIO buffer before going "4KB" */
937 u32 piosize2kmax_dwords;
938 /* number of "4KB" PIO buffers */
939 u32 piobcnt4k;
940 /* size in bytes of "4KB" PIO buffers */
941 u32 piosize4k;
942 /* kr_rcvegrbase value */
943 u32 rcvegrbase;
944 /* kr_rcvtidbase value */
945 u32 rcvtidbase;
946 /* kr_rcvtidcnt value */
947 u32 rcvtidcnt;
948 /* kr_userregbase */
949 u32 uregbase;
950 /* shadow the control register contents */
951 u32 control;
952
953 /* chip address space used by 4k pio buffers */
954 u32 align4k;
955 /* size of each rcvegrbuffer */
956 u16 rcvegrbufsize;
957 /* log2 of above */
958 u16 rcvegrbufsize_shift;
959 /* localbus width (1, 2,4,8,16,32) from config space */
960 u32 lbus_width;
961 /* localbus speed in MHz */
962 u32 lbus_speed;
963 int unit; /* unit # of this chip */
964
965 /* start of CHIP_SPEC move to chipspec, but need code changes */
966 /* low and high portions of MSI capability/vector */
967 u32 msi_lo;
968 /* saved after PCIe init for restore after reset */
969 u32 msi_hi;
970 /* MSI data (vector) saved for restore */
971 u16 msi_data;
972 /* so we can rewrite it after a chip reset */
973 u32 pcibar0;
974 /* so we can rewrite it after a chip reset */
975 u32 pcibar1;
976 u64 rhdrhead_intr_off;
977
978 /*
979 * ASCII serial number, from flash, large enough for original
980 * all digit strings, and longer QLogic serial number format
981 */
982 u8 serial[16];
983 /* human readable board version */
984 u8 boardversion[96];
985 u8 lbus_info[32]; /* human readable localbus info */
986 /* chip major rev, from qib_revision */
987 u8 majrev;
988 /* chip minor rev, from qib_revision */
989 u8 minrev;
990
991 /* Misc small ints */
992 /* Number of physical ports available */
993 u8 num_pports;
994 /* Lowest context number which can be used by user processes */
995 u8 first_user_ctxt;
996 u8 n_krcv_queues;
997 u8 qpn_mask;
998 u8 skip_kctxt_mask;
999
1000 u16 rhf_offset; /* offset of RHF within receive header entry */
1001
1002 /*
1003 * GPIO pins for twsi-connected devices, and device code for eeprom
1004 */
1005 u8 gpio_sda_num;
1006 u8 gpio_scl_num;
1007 u8 twsi_eeprom_dev;
1008 u8 board_atten;
1009
1010 /* Support (including locks) for EEPROM logging of errors and time */
1011 /* control access to actual counters, timer */
1012 spinlock_t eep_st_lock;
1013 /* control high-level access to EEPROM */
1014 struct mutex eep_lock;
1015 uint64_t traffic_wds;
1016 /* active time is kept in seconds, but logged in hours */
1017 atomic_t active_time;
1018 /* Below are nominal shadow of EEPROM, new since last EEPROM update */
1019 uint8_t eep_st_errs[QIB_EEP_LOG_CNT];
1020 uint8_t eep_st_new_errs[QIB_EEP_LOG_CNT];
1021 uint16_t eep_hrs;
1022 /*
1023 * masks for which bits of errs, hwerrs that cause
1024 * each of the counters to increment.
1025 */
1026 struct qib_eep_log_mask eep_st_masks[QIB_EEP_LOG_CNT];
1027 struct qib_diag_client *diag_client;
1028 spinlock_t qib_diag_trans_lock; /* protect diag observer ops */
1029 struct diag_observer_list_elt *diag_observer_list;
1030
1031 u8 psxmitwait_supported;
1032 /* cycle length of PS* counters in HW (in picoseconds) */
1033 u16 psxmitwait_check_rate;
1034 /* high volume overflow errors defered to tasklet */
1035 struct tasklet_struct error_tasklet;
1036 };
1037
1038 /* hol_state values */
1039 #define QIB_HOL_UP 0
1040 #define QIB_HOL_INIT 1
1041
1042 #define QIB_SDMA_SENDCTRL_OP_ENABLE (1U << 0)
1043 #define QIB_SDMA_SENDCTRL_OP_INTENABLE (1U << 1)
1044 #define QIB_SDMA_SENDCTRL_OP_HALT (1U << 2)
1045 #define QIB_SDMA_SENDCTRL_OP_CLEANUP (1U << 3)
1046 #define QIB_SDMA_SENDCTRL_OP_DRAIN (1U << 4)
1047
1048 /* operation types for f_txchk_change() */
1049 #define TXCHK_CHG_TYPE_DIS1 3
1050 #define TXCHK_CHG_TYPE_ENAB1 2
1051 #define TXCHK_CHG_TYPE_KERN 1
1052 #define TXCHK_CHG_TYPE_USER 0
1053
1054 #define QIB_CHASE_TIME msecs_to_jiffies(145)
1055 #define QIB_CHASE_DIS_TIME msecs_to_jiffies(160)
1056
1057 /* Private data for file operations */
1058 struct qib_filedata {
1059 struct qib_ctxtdata *rcd;
1060 unsigned subctxt;
1061 unsigned tidcursor;
1062 struct qib_user_sdma_queue *pq;
1063 int rec_cpu_num; /* for cpu affinity; -1 if none */
1064 };
1065
1066 extern struct list_head qib_dev_list;
1067 extern spinlock_t qib_devs_lock;
1068 extern struct qib_devdata *qib_lookup(int unit);
1069 extern u32 qib_cpulist_count;
1070 extern unsigned long *qib_cpulist;
1071
1072 extern unsigned qib_wc_pat;
1073 int qib_init(struct qib_devdata *, int);
1074 int init_chip_wc_pat(struct qib_devdata *dd, u32);
1075 int qib_enable_wc(struct qib_devdata *dd);
1076 void qib_disable_wc(struct qib_devdata *dd);
1077 int qib_count_units(int *npresentp, int *nupp);
1078 int qib_count_active_units(void);
1079
1080 int qib_cdev_init(int minor, const char *name,
1081 const struct file_operations *fops,
1082 struct cdev **cdevp, struct device **devp);
1083 void qib_cdev_cleanup(struct cdev **cdevp, struct device **devp);
1084 int qib_dev_init(void);
1085 void qib_dev_cleanup(void);
1086
1087 int qib_diag_add(struct qib_devdata *);
1088 void qib_diag_remove(struct qib_devdata *);
1089 void qib_handle_e_ibstatuschanged(struct qib_pportdata *, u64);
1090 void qib_sdma_update_tail(struct qib_pportdata *, u16); /* hold sdma_lock */
1091
1092 int qib_decode_err(struct qib_devdata *dd, char *buf, size_t blen, u64 err);
1093 void qib_bad_intrstatus(struct qib_devdata *);
1094 void qib_handle_urcv(struct qib_devdata *, u64);
1095
1096 /* clean up any per-chip chip-specific stuff */
1097 void qib_chip_cleanup(struct qib_devdata *);
1098 /* clean up any chip type-specific stuff */
1099 void qib_chip_done(void);
1100
1101 /* check to see if we have to force ordering for write combining */
1102 int qib_unordered_wc(void);
1103 void qib_pio_copy(void __iomem *to, const void *from, size_t count);
1104
1105 void qib_disarm_piobufs(struct qib_devdata *, unsigned, unsigned);
1106 int qib_disarm_piobufs_ifneeded(struct qib_ctxtdata *);
1107 void qib_disarm_piobufs_set(struct qib_devdata *, unsigned long *, unsigned);
1108 void qib_cancel_sends(struct qib_pportdata *);
1109
1110 int qib_create_rcvhdrq(struct qib_devdata *, struct qib_ctxtdata *);
1111 int qib_setup_eagerbufs(struct qib_ctxtdata *);
1112 void qib_set_ctxtcnt(struct qib_devdata *);
1113 int qib_create_ctxts(struct qib_devdata *dd);
1114 struct qib_ctxtdata *qib_create_ctxtdata(struct qib_pportdata *, u32);
1115 void qib_init_pportdata(struct qib_pportdata *, struct qib_devdata *, u8, u8);
1116 void qib_free_ctxtdata(struct qib_devdata *, struct qib_ctxtdata *);
1117
1118 u32 qib_kreceive(struct qib_ctxtdata *, u32 *, u32 *);
1119 int qib_reset_device(int);
1120 int qib_wait_linkstate(struct qib_pportdata *, u32, int);
1121 int qib_set_linkstate(struct qib_pportdata *, u8);
1122 int qib_set_mtu(struct qib_pportdata *, u16);
1123 int qib_set_lid(struct qib_pportdata *, u32, u8);
1124 void qib_hol_down(struct qib_pportdata *);
1125 void qib_hol_init(struct qib_pportdata *);
1126 void qib_hol_up(struct qib_pportdata *);
1127 void qib_hol_event(unsigned long);
1128 void qib_disable_after_error(struct qib_devdata *);
1129 int qib_set_uevent_bits(struct qib_pportdata *, const int);
1130
1131 /* for use in system calls, where we want to know device type, etc. */
1132 #define ctxt_fp(fp) \
1133 (((struct qib_filedata *)(fp)->private_data)->rcd)
1134 #define subctxt_fp(fp) \
1135 (((struct qib_filedata *)(fp)->private_data)->subctxt)
1136 #define tidcursor_fp(fp) \
1137 (((struct qib_filedata *)(fp)->private_data)->tidcursor)
1138 #define user_sdma_queue_fp(fp) \
1139 (((struct qib_filedata *)(fp)->private_data)->pq)
1140
dd_from_ppd(struct qib_pportdata * ppd)1141 static inline struct qib_devdata *dd_from_ppd(struct qib_pportdata *ppd)
1142 {
1143 return ppd->dd;
1144 }
1145
dd_from_dev(struct qib_ibdev * dev)1146 static inline struct qib_devdata *dd_from_dev(struct qib_ibdev *dev)
1147 {
1148 return container_of(dev, struct qib_devdata, verbs_dev);
1149 }
1150
dd_from_ibdev(struct ib_device * ibdev)1151 static inline struct qib_devdata *dd_from_ibdev(struct ib_device *ibdev)
1152 {
1153 return dd_from_dev(to_idev(ibdev));
1154 }
1155
ppd_from_ibp(struct qib_ibport * ibp)1156 static inline struct qib_pportdata *ppd_from_ibp(struct qib_ibport *ibp)
1157 {
1158 return container_of(ibp, struct qib_pportdata, ibport_data);
1159 }
1160
to_iport(struct ib_device * ibdev,u8 port)1161 static inline struct qib_ibport *to_iport(struct ib_device *ibdev, u8 port)
1162 {
1163 struct qib_devdata *dd = dd_from_ibdev(ibdev);
1164 unsigned pidx = port - 1; /* IB number port from 1, hdw from 0 */
1165
1166 WARN_ON(pidx >= dd->num_pports);
1167 return &dd->pport[pidx].ibport_data;
1168 }
1169
1170 /*
1171 * values for dd->flags (_device_ related flags) and
1172 */
1173 #define QIB_HAS_LINK_LATENCY 0x1 /* supports link latency (IB 1.2) */
1174 #define QIB_INITTED 0x2 /* chip and driver up and initted */
1175 #define QIB_DOING_RESET 0x4 /* in the middle of doing chip reset */
1176 #define QIB_PRESENT 0x8 /* chip accesses can be done */
1177 #define QIB_PIO_FLUSH_WC 0x10 /* Needs Write combining flush for PIO */
1178 #define QIB_HAS_THRESH_UPDATE 0x40
1179 #define QIB_HAS_SDMA_TIMEOUT 0x80
1180 #define QIB_USE_SPCL_TRIG 0x100 /* SpecialTrigger launch enabled */
1181 #define QIB_NODMA_RTAIL 0x200 /* rcvhdrtail register DMA enabled */
1182 #define QIB_HAS_INTX 0x800 /* Supports INTx interrupts */
1183 #define QIB_HAS_SEND_DMA 0x1000 /* Supports Send DMA */
1184 #define QIB_HAS_VLSUPP 0x2000 /* Supports multiple VLs; PBC different */
1185 #define QIB_HAS_HDRSUPP 0x4000 /* Supports header suppression */
1186 #define QIB_BADINTR 0x8000 /* severe interrupt problems */
1187 #define QIB_DCA_ENABLED 0x10000 /* Direct Cache Access enabled */
1188 #define QIB_HAS_QSFP 0x20000 /* device (card instance) has QSFP */
1189
1190 /*
1191 * values for ppd->lflags (_ib_port_ related flags)
1192 */
1193 #define QIBL_LINKV 0x1 /* IB link state valid */
1194 #define QIBL_LINKDOWN 0x8 /* IB link is down */
1195 #define QIBL_LINKINIT 0x10 /* IB link level is up */
1196 #define QIBL_LINKARMED 0x20 /* IB link is ARMED */
1197 #define QIBL_LINKACTIVE 0x40 /* IB link is ACTIVE */
1198 /* leave a gap for more IB-link state */
1199 #define QIBL_IB_AUTONEG_INPROG 0x1000 /* non-IBTA DDR/QDR neg active */
1200 #define QIBL_IB_AUTONEG_FAILED 0x2000 /* non-IBTA DDR/QDR neg failed */
1201 #define QIBL_IB_LINK_DISABLED 0x4000 /* Linkdown-disable forced,
1202 * Do not try to bring up */
1203 #define QIBL_IB_FORCE_NOTIFY 0x8000 /* force notify on next ib change */
1204
1205 /* IB dword length mask in PBC (lower 11 bits); same for all chips */
1206 #define QIB_PBC_LENGTH_MASK ((1 << 11) - 1)
1207
1208
1209 /* ctxt_flag bit offsets */
1210 /* waiting for a packet to arrive */
1211 #define QIB_CTXT_WAITING_RCV 2
1212 /* master has not finished initializing */
1213 #define QIB_CTXT_MASTER_UNINIT 4
1214 /* waiting for an urgent packet to arrive */
1215 #define QIB_CTXT_WAITING_URG 5
1216
1217 /* free up any allocated data at closes */
1218 void qib_free_data(struct qib_ctxtdata *dd);
1219 void qib_chg_pioavailkernel(struct qib_devdata *, unsigned, unsigned,
1220 u32, struct qib_ctxtdata *);
1221 struct qib_devdata *qib_init_iba7322_funcs(struct pci_dev *,
1222 const struct pci_device_id *);
1223 struct qib_devdata *qib_init_iba7220_funcs(struct pci_dev *,
1224 const struct pci_device_id *);
1225 struct qib_devdata *qib_init_iba6120_funcs(struct pci_dev *,
1226 const struct pci_device_id *);
1227 void qib_free_devdata(struct qib_devdata *);
1228 struct qib_devdata *qib_alloc_devdata(struct pci_dev *pdev, size_t extra);
1229
1230 #define QIB_TWSI_NO_DEV 0xFF
1231 /* Below qib_twsi_ functions must be called with eep_lock held */
1232 int qib_twsi_reset(struct qib_devdata *dd);
1233 int qib_twsi_blk_rd(struct qib_devdata *dd, int dev, int addr, void *buffer,
1234 int len);
1235 int qib_twsi_blk_wr(struct qib_devdata *dd, int dev, int addr,
1236 const void *buffer, int len);
1237 void qib_get_eeprom_info(struct qib_devdata *);
1238 int qib_update_eeprom_log(struct qib_devdata *dd);
1239 void qib_inc_eeprom_err(struct qib_devdata *dd, u32 eidx, u32 incr);
1240 void qib_dump_lookup_output_queue(struct qib_devdata *);
1241 void qib_force_pio_avail_update(struct qib_devdata *);
1242 void qib_clear_symerror_on_linkup(unsigned long opaque);
1243
1244 /*
1245 * Set LED override, only the two LSBs have "public" meaning, but
1246 * any non-zero value substitutes them for the Link and LinkTrain
1247 * LED states.
1248 */
1249 #define QIB_LED_PHYS 1 /* Physical (linktraining) GREEN LED */
1250 #define QIB_LED_LOG 2 /* Logical (link) YELLOW LED */
1251 void qib_set_led_override(struct qib_pportdata *ppd, unsigned int val);
1252
1253 /* send dma routines */
1254 int qib_setup_sdma(struct qib_pportdata *);
1255 void qib_teardown_sdma(struct qib_pportdata *);
1256 void __qib_sdma_intr(struct qib_pportdata *);
1257 void qib_sdma_intr(struct qib_pportdata *);
1258 int qib_sdma_verbs_send(struct qib_pportdata *, struct qib_sge_state *,
1259 u32, struct qib_verbs_txreq *);
1260 /* ppd->sdma_lock should be locked before calling this. */
1261 int qib_sdma_make_progress(struct qib_pportdata *dd);
1262
1263 /* must be called under qib_sdma_lock */
qib_sdma_descq_freecnt(const struct qib_pportdata * ppd)1264 static inline u16 qib_sdma_descq_freecnt(const struct qib_pportdata *ppd)
1265 {
1266 return ppd->sdma_descq_cnt -
1267 (ppd->sdma_descq_added - ppd->sdma_descq_removed) - 1;
1268 }
1269
__qib_sdma_running(struct qib_pportdata * ppd)1270 static inline int __qib_sdma_running(struct qib_pportdata *ppd)
1271 {
1272 return ppd->sdma_state.current_state == qib_sdma_state_s99_running;
1273 }
1274 int qib_sdma_running(struct qib_pportdata *);
1275
1276 void __qib_sdma_process_event(struct qib_pportdata *, enum qib_sdma_events);
1277 void qib_sdma_process_event(struct qib_pportdata *, enum qib_sdma_events);
1278
1279 /*
1280 * number of words used for protocol header if not set by qib_userinit();
1281 */
1282 #define QIB_DFLT_RCVHDRSIZE 9
1283
1284 /*
1285 * We need to be able to handle an IB header of at least 24 dwords.
1286 * We need the rcvhdrq large enough to handle largest IB header, but
1287 * still have room for a 2KB MTU standard IB packet.
1288 * Additionally, some processor/memory controller combinations
1289 * benefit quite strongly from having the DMA'ed data be cacheline
1290 * aligned and a cacheline multiple, so we set the size to 32 dwords
1291 * (2 64-byte primary cachelines for pretty much all processors of
1292 * interest). The alignment hurts nothing, other than using somewhat
1293 * more memory.
1294 */
1295 #define QIB_RCVHDR_ENTSIZE 32
1296
1297 int qib_get_user_pages(unsigned long, size_t, struct page **);
1298 void qib_release_user_pages(struct page **, size_t);
1299 int qib_eeprom_read(struct qib_devdata *, u8, void *, int);
1300 int qib_eeprom_write(struct qib_devdata *, u8, const void *, int);
1301 u32 __iomem *qib_getsendbuf_range(struct qib_devdata *, u32 *, u32, u32);
1302 void qib_sendbuf_done(struct qib_devdata *, unsigned);
1303
qib_clear_rcvhdrtail(const struct qib_ctxtdata * rcd)1304 static inline void qib_clear_rcvhdrtail(const struct qib_ctxtdata *rcd)
1305 {
1306 *((u64 *) rcd->rcvhdrtail_kvaddr) = 0ULL;
1307 }
1308
qib_get_rcvhdrtail(const struct qib_ctxtdata * rcd)1309 static inline u32 qib_get_rcvhdrtail(const struct qib_ctxtdata *rcd)
1310 {
1311 /*
1312 * volatile because it's a DMA target from the chip, routine is
1313 * inlined, and don't want register caching or reordering.
1314 */
1315 return (u32) le64_to_cpu(
1316 *((volatile __le64 *)rcd->rcvhdrtail_kvaddr)); /* DMA'ed */
1317 }
1318
qib_get_hdrqtail(const struct qib_ctxtdata * rcd)1319 static inline u32 qib_get_hdrqtail(const struct qib_ctxtdata *rcd)
1320 {
1321 const struct qib_devdata *dd = rcd->dd;
1322 u32 hdrqtail;
1323
1324 if (dd->flags & QIB_NODMA_RTAIL) {
1325 __le32 *rhf_addr;
1326 u32 seq;
1327
1328 rhf_addr = (__le32 *) rcd->rcvhdrq +
1329 rcd->head + dd->rhf_offset;
1330 seq = qib_hdrget_seq(rhf_addr);
1331 hdrqtail = rcd->head;
1332 if (seq == rcd->seq_cnt)
1333 hdrqtail++;
1334 } else
1335 hdrqtail = qib_get_rcvhdrtail(rcd);
1336
1337 return hdrqtail;
1338 }
1339
1340 /*
1341 * sysfs interface.
1342 */
1343
1344 extern const char ib_qib_version[];
1345
1346 int qib_device_create(struct qib_devdata *);
1347 void qib_device_remove(struct qib_devdata *);
1348
1349 int qib_create_port_files(struct ib_device *ibdev, u8 port_num,
1350 struct kobject *kobj);
1351 int qib_verbs_register_sysfs(struct qib_devdata *);
1352 void qib_verbs_unregister_sysfs(struct qib_devdata *);
1353 /* Hook for sysfs read of QSFP */
1354 extern int qib_qsfp_dump(struct qib_pportdata *ppd, char *buf, int len);
1355
1356 int __init qib_init_qibfs(void);
1357 int __exit qib_exit_qibfs(void);
1358
1359 int qibfs_add(struct qib_devdata *);
1360 int qibfs_remove(struct qib_devdata *);
1361
1362 int qib_pcie_init(struct pci_dev *, const struct pci_device_id *);
1363 int qib_pcie_ddinit(struct qib_devdata *, struct pci_dev *,
1364 const struct pci_device_id *);
1365 void qib_pcie_ddcleanup(struct qib_devdata *);
1366 int qib_pcie_params(struct qib_devdata *, u32, u32 *, struct qib_msix_entry *);
1367 int qib_reinit_intr(struct qib_devdata *);
1368 void qib_enable_intx(struct pci_dev *);
1369 void qib_nomsi(struct qib_devdata *);
1370 void qib_nomsix(struct qib_devdata *);
1371 void qib_pcie_getcmd(struct qib_devdata *, u16 *, u8 *, u8 *);
1372 void qib_pcie_reenable(struct qib_devdata *, u16, u8, u8);
1373
1374 /*
1375 * dma_addr wrappers - all 0's invalid for hw
1376 */
1377 dma_addr_t qib_map_page(struct pci_dev *, struct page *, unsigned long,
1378 size_t, int);
1379 const char *qib_get_unit_name(int unit);
1380
1381 /*
1382 * Flush write combining store buffers (if present) and perform a write
1383 * barrier.
1384 */
1385 #if defined(CONFIG_X86_64)
1386 #define qib_flush_wc() asm volatile("sfence" : : : "memory")
1387 #else
1388 #define qib_flush_wc() wmb() /* no reorder around wc flush */
1389 #endif
1390
1391 /* global module parameter variables */
1392 extern unsigned qib_ibmtu;
1393 extern ushort qib_cfgctxts;
1394 extern ushort qib_num_cfg_vls;
1395 extern ushort qib_mini_init; /* If set, do few (ideally 0) writes to chip */
1396 extern unsigned qib_n_krcv_queues;
1397 extern unsigned qib_sdma_fetch_arb;
1398 extern unsigned qib_compat_ddr_negotiate;
1399 extern int qib_special_trigger;
1400
1401 extern struct mutex qib_mutex;
1402
1403 /* Number of seconds before our card status check... */
1404 #define STATUS_TIMEOUT 60
1405
1406 #define QIB_DRV_NAME "ib_qib"
1407 #define QIB_USER_MINOR_BASE 0
1408 #define QIB_TRACE_MINOR 127
1409 #define QIB_DIAGPKT_MINOR 128
1410 #define QIB_DIAG_MINOR_BASE 129
1411 #define QIB_NMINORS 255
1412
1413 #define PCI_VENDOR_ID_PATHSCALE 0x1fc1
1414 #define PCI_VENDOR_ID_QLOGIC 0x1077
1415 #define PCI_DEVICE_ID_QLOGIC_IB_6120 0x10
1416 #define PCI_DEVICE_ID_QLOGIC_IB_7220 0x7220
1417 #define PCI_DEVICE_ID_QLOGIC_IB_7322 0x7322
1418
1419 /*
1420 * qib_early_err is used (only!) to print early errors before devdata is
1421 * allocated, or when dd->pcidev may not be valid, and at the tail end of
1422 * cleanup when devdata may have been freed, etc. qib_dev_porterr is
1423 * the same as qib_dev_err, but is used when the message really needs
1424 * the IB port# to be definitive as to what's happening..
1425 * All of these go to the trace log, and the trace log entry is done
1426 * first to avoid possible serial port delays from printk.
1427 */
1428 #define qib_early_err(dev, fmt, ...) \
1429 do { \
1430 dev_err(dev, fmt, ##__VA_ARGS__); \
1431 } while (0)
1432
1433 #define qib_dev_err(dd, fmt, ...) \
1434 do { \
1435 dev_err(&(dd)->pcidev->dev, "%s: " fmt, \
1436 qib_get_unit_name((dd)->unit), ##__VA_ARGS__); \
1437 } while (0)
1438
1439 #define qib_dev_porterr(dd, port, fmt, ...) \
1440 do { \
1441 dev_err(&(dd)->pcidev->dev, "%s: IB%u:%u " fmt, \
1442 qib_get_unit_name((dd)->unit), (dd)->unit, (port), \
1443 ##__VA_ARGS__); \
1444 } while (0)
1445
1446 #define qib_devinfo(pcidev, fmt, ...) \
1447 do { \
1448 dev_info(&(pcidev)->dev, fmt, ##__VA_ARGS__); \
1449 } while (0)
1450
1451 /*
1452 * this is used for formatting hw error messages...
1453 */
1454 struct qib_hwerror_msgs {
1455 u64 mask;
1456 const char *msg;
1457 size_t sz;
1458 };
1459
1460 #define QLOGIC_IB_HWE_MSG(a, b) { .mask = a, .msg = b }
1461
1462 /* in qib_intr.c... */
1463 void qib_format_hwerrors(u64 hwerrs,
1464 const struct qib_hwerror_msgs *hwerrmsgs,
1465 size_t nhwerrmsgs, char *msg, size_t lmsg);
1466 #endif /* _QIB_KERNEL_H */
1467