1 /*
2 * arch/arm/mach-tegra/fuse.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@android.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20 #include <linux/kernel.h>
21 #include <linux/io.h>
22 #include <linux/export.h>
23
24 #include <mach/iomap.h>
25
26 #include "fuse.h"
27 #include "apbio.h"
28
29 #define FUSE_UID_LOW 0x108
30 #define FUSE_UID_HIGH 0x10c
31 #define FUSE_SKU_INFO 0x110
32 #define FUSE_SPARE_BIT 0x200
33
34 int tegra_sku_id;
35 int tegra_cpu_process_id;
36 int tegra_core_process_id;
37 int tegra_chip_id;
38 enum tegra_revision tegra_revision;
39
40 /* The BCT to use at boot is specified by board straps that can be read
41 * through a APB misc register and decoded. 2 bits, i.e. 4 possible BCTs.
42 */
43 int tegra_bct_strapping;
44
45 #define STRAP_OPT 0x008
46 #define GMI_AD0 (1 << 4)
47 #define GMI_AD1 (1 << 5)
48 #define RAM_ID_MASK (GMI_AD0 | GMI_AD1)
49 #define RAM_CODE_SHIFT 4
50
51 static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
52 [TEGRA_REVISION_UNKNOWN] = "unknown",
53 [TEGRA_REVISION_A01] = "A01",
54 [TEGRA_REVISION_A02] = "A02",
55 [TEGRA_REVISION_A03] = "A03",
56 [TEGRA_REVISION_A03p] = "A03 prime",
57 [TEGRA_REVISION_A04] = "A04",
58 };
59
tegra_fuse_readl(unsigned long offset)60 static inline u32 tegra_fuse_readl(unsigned long offset)
61 {
62 return tegra_apb_readl(TEGRA_FUSE_BASE + offset);
63 }
64
get_spare_fuse(int bit)65 static inline bool get_spare_fuse(int bit)
66 {
67 return tegra_fuse_readl(FUSE_SPARE_BIT + bit * 4);
68 }
69
tegra_get_revision(u32 id)70 static enum tegra_revision tegra_get_revision(u32 id)
71 {
72 u32 minor_rev = (id >> 16) & 0xf;
73
74 switch (minor_rev) {
75 case 1:
76 return TEGRA_REVISION_A01;
77 case 2:
78 return TEGRA_REVISION_A02;
79 case 3:
80 if (tegra_chip_id == TEGRA20 &&
81 (get_spare_fuse(18) || get_spare_fuse(19)))
82 return TEGRA_REVISION_A03p;
83 else
84 return TEGRA_REVISION_A03;
85 case 4:
86 return TEGRA_REVISION_A04;
87 default:
88 return TEGRA_REVISION_UNKNOWN;
89 }
90 }
91
tegra_init_fuse(void)92 void tegra_init_fuse(void)
93 {
94 u32 id;
95
96 u32 reg = readl(IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48));
97 reg |= 1 << 28;
98 writel(reg, IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48));
99
100 reg = tegra_fuse_readl(FUSE_SKU_INFO);
101 tegra_sku_id = reg & 0xFF;
102
103 reg = tegra_fuse_readl(FUSE_SPARE_BIT);
104 tegra_cpu_process_id = (reg >> 6) & 3;
105
106 reg = tegra_fuse_readl(FUSE_SPARE_BIT);
107 tegra_core_process_id = (reg >> 12) & 3;
108
109 reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT);
110 tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;
111
112 id = readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804);
113 tegra_chip_id = (id >> 8) & 0xff;
114
115 tegra_revision = tegra_get_revision(id);
116
117 pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
118 tegra_revision_name[tegra_revision],
119 tegra_sku_id, tegra_cpu_process_id,
120 tegra_core_process_id);
121 }
122
tegra_chip_uid(void)123 unsigned long long tegra_chip_uid(void)
124 {
125 unsigned long long lo, hi;
126
127 lo = tegra_fuse_readl(FUSE_UID_LOW);
128 hi = tegra_fuse_readl(FUSE_UID_HIGH);
129 return (hi << 32ull) | lo;
130 }
131 EXPORT_SYMBOL(tegra_chip_uid);
132