1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. 4 * 5 * This software is licensed under the terms of the GNU General Public 6 * License version 2, as published by the Free Software Foundation, and 7 * may be copied, distributed, and modified under those terms. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 */ 15 16 #include <linux/module.h> 17 #include <linux/platform_device.h> 18 #include <soc/tegra/fuse.h> 19 20 #include <dt-bindings/thermal/tegra124-soctherm.h> 21 22 #include "soctherm.h" 23 24 #define TEGRA210_THERMTRIP_ANY_EN_MASK (0x1 << 31) 25 #define TEGRA210_THERMTRIP_MEM_EN_MASK (0x1 << 30) 26 #define TEGRA210_THERMTRIP_GPU_EN_MASK (0x1 << 29) 27 #define TEGRA210_THERMTRIP_CPU_EN_MASK (0x1 << 28) 28 #define TEGRA210_THERMTRIP_TSENSE_EN_MASK (0x1 << 27) 29 #define TEGRA210_THERMTRIP_GPUMEM_THRESH_MASK (0x1ff << 18) 30 #define TEGRA210_THERMTRIP_CPU_THRESH_MASK (0x1ff << 9) 31 #define TEGRA210_THERMTRIP_TSENSE_THRESH_MASK 0x1ff 32 33 #define TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK (0x1ff << 18) 34 #define TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK (0x1ff << 9) 35 36 #define TEGRA210_THRESH_GRAIN 500 37 #define TEGRA210_BPTT 9 38 39 static const struct tegra_tsensor_configuration tegra210_tsensor_config = { 40 .tall = 16300, 41 .tiddq_en = 1, 42 .ten_count = 1, 43 .tsample = 120, 44 .tsample_ate = 480, 45 }; 46 47 static const struct tegra_tsensor_group tegra210_tsensor_group_cpu = { 48 .id = TEGRA124_SOCTHERM_SENSOR_CPU, 49 .name = "cpu", 50 .sensor_temp_offset = SENSOR_TEMP1, 51 .sensor_temp_mask = SENSOR_TEMP1_CPU_TEMP_MASK, 52 .pdiv = 8, 53 .pdiv_ate = 8, 54 .pdiv_mask = SENSOR_PDIV_CPU_MASK, 55 .pllx_hotspot_diff = 10, 56 .pllx_hotspot_mask = SENSOR_HOTSPOT_CPU_MASK, 57 .thermtrip_any_en_mask = TEGRA210_THERMTRIP_ANY_EN_MASK, 58 .thermtrip_enable_mask = TEGRA210_THERMTRIP_CPU_EN_MASK, 59 .thermtrip_threshold_mask = TEGRA210_THERMTRIP_CPU_THRESH_MASK, 60 .thermctl_isr_mask = THERM_IRQ_CPU_MASK, 61 .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_CPU, 62 .thermctl_lvl0_up_thresh_mask = TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK, 63 .thermctl_lvl0_dn_thresh_mask = TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK, 64 }; 65 66 static const struct tegra_tsensor_group tegra210_tsensor_group_gpu = { 67 .id = TEGRA124_SOCTHERM_SENSOR_GPU, 68 .name = "gpu", 69 .sensor_temp_offset = SENSOR_TEMP1, 70 .sensor_temp_mask = SENSOR_TEMP1_GPU_TEMP_MASK, 71 .pdiv = 8, 72 .pdiv_ate = 8, 73 .pdiv_mask = SENSOR_PDIV_GPU_MASK, 74 .pllx_hotspot_diff = 5, 75 .pllx_hotspot_mask = SENSOR_HOTSPOT_GPU_MASK, 76 .thermtrip_any_en_mask = TEGRA210_THERMTRIP_ANY_EN_MASK, 77 .thermtrip_enable_mask = TEGRA210_THERMTRIP_GPU_EN_MASK, 78 .thermtrip_threshold_mask = TEGRA210_THERMTRIP_GPUMEM_THRESH_MASK, 79 .thermctl_isr_mask = THERM_IRQ_GPU_MASK, 80 .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_GPU, 81 .thermctl_lvl0_up_thresh_mask = TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK, 82 .thermctl_lvl0_dn_thresh_mask = TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK, 83 }; 84 85 static const struct tegra_tsensor_group tegra210_tsensor_group_pll = { 86 .id = TEGRA124_SOCTHERM_SENSOR_PLLX, 87 .name = "pll", 88 .sensor_temp_offset = SENSOR_TEMP2, 89 .sensor_temp_mask = SENSOR_TEMP2_PLLX_TEMP_MASK, 90 .pdiv = 8, 91 .pdiv_ate = 8, 92 .pdiv_mask = SENSOR_PDIV_PLLX_MASK, 93 .thermtrip_any_en_mask = TEGRA210_THERMTRIP_ANY_EN_MASK, 94 .thermtrip_enable_mask = TEGRA210_THERMTRIP_TSENSE_EN_MASK, 95 .thermtrip_threshold_mask = TEGRA210_THERMTRIP_TSENSE_THRESH_MASK, 96 .thermctl_isr_mask = THERM_IRQ_TSENSE_MASK, 97 .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_TSENSE, 98 .thermctl_lvl0_up_thresh_mask = TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK, 99 .thermctl_lvl0_dn_thresh_mask = TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK, 100 }; 101 102 static const struct tegra_tsensor_group tegra210_tsensor_group_mem = { 103 .id = TEGRA124_SOCTHERM_SENSOR_MEM, 104 .name = "mem", 105 .sensor_temp_offset = SENSOR_TEMP2, 106 .sensor_temp_mask = SENSOR_TEMP2_MEM_TEMP_MASK, 107 .pdiv = 8, 108 .pdiv_ate = 8, 109 .pdiv_mask = SENSOR_PDIV_MEM_MASK, 110 .pllx_hotspot_diff = 0, 111 .pllx_hotspot_mask = SENSOR_HOTSPOT_MEM_MASK, 112 .thermtrip_any_en_mask = TEGRA210_THERMTRIP_ANY_EN_MASK, 113 .thermtrip_enable_mask = TEGRA210_THERMTRIP_MEM_EN_MASK, 114 .thermtrip_threshold_mask = TEGRA210_THERMTRIP_GPUMEM_THRESH_MASK, 115 .thermctl_isr_mask = THERM_IRQ_MEM_MASK, 116 .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_MEM, 117 .thermctl_lvl0_up_thresh_mask = TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK, 118 .thermctl_lvl0_dn_thresh_mask = TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK, 119 }; 120 121 static const struct tegra_tsensor_group *tegra210_tsensor_groups[] = { 122 &tegra210_tsensor_group_cpu, 123 &tegra210_tsensor_group_gpu, 124 &tegra210_tsensor_group_pll, 125 &tegra210_tsensor_group_mem, 126 }; 127 128 static const struct tegra_tsensor tegra210_tsensors[] = { 129 { 130 .name = "cpu0", 131 .base = 0xc0, 132 .config = &tegra210_tsensor_config, 133 .calib_fuse_offset = 0x098, 134 .fuse_corr_alpha = 1085000, 135 .fuse_corr_beta = 3244200, 136 .group = &tegra210_tsensor_group_cpu, 137 }, { 138 .name = "cpu1", 139 .base = 0xe0, 140 .config = &tegra210_tsensor_config, 141 .calib_fuse_offset = 0x084, 142 .fuse_corr_alpha = 1126200, 143 .fuse_corr_beta = -67500, 144 .group = &tegra210_tsensor_group_cpu, 145 }, { 146 .name = "cpu2", 147 .base = 0x100, 148 .config = &tegra210_tsensor_config, 149 .calib_fuse_offset = 0x088, 150 .fuse_corr_alpha = 1098400, 151 .fuse_corr_beta = 2251100, 152 .group = &tegra210_tsensor_group_cpu, 153 }, { 154 .name = "cpu3", 155 .base = 0x120, 156 .config = &tegra210_tsensor_config, 157 .calib_fuse_offset = 0x12c, 158 .fuse_corr_alpha = 1108000, 159 .fuse_corr_beta = 602700, 160 .group = &tegra210_tsensor_group_cpu, 161 }, { 162 .name = "mem0", 163 .base = 0x140, 164 .config = &tegra210_tsensor_config, 165 .calib_fuse_offset = 0x158, 166 .fuse_corr_alpha = 1069200, 167 .fuse_corr_beta = 3549900, 168 .group = &tegra210_tsensor_group_mem, 169 }, { 170 .name = "mem1", 171 .base = 0x160, 172 .config = &tegra210_tsensor_config, 173 .calib_fuse_offset = 0x15c, 174 .fuse_corr_alpha = 1173700, 175 .fuse_corr_beta = -6263600, 176 .group = &tegra210_tsensor_group_mem, 177 }, { 178 .name = "gpu", 179 .base = 0x180, 180 .config = &tegra210_tsensor_config, 181 .calib_fuse_offset = 0x154, 182 .fuse_corr_alpha = 1074300, 183 .fuse_corr_beta = 2734900, 184 .group = &tegra210_tsensor_group_gpu, 185 }, { 186 .name = "pllx", 187 .base = 0x1a0, 188 .config = &tegra210_tsensor_config, 189 .calib_fuse_offset = 0x160, 190 .fuse_corr_alpha = 1039700, 191 .fuse_corr_beta = 6829100, 192 .group = &tegra210_tsensor_group_pll, 193 }, 194 }; 195 196 /* 197 * Mask/shift bits in FUSE_TSENSOR_COMMON and 198 * FUSE_TSENSOR_COMMON, which are described in 199 * tegra_soctherm_fuse.c 200 */ 201 static const struct tegra_soctherm_fuse tegra210_soctherm_fuse = { 202 .fuse_base_cp_mask = 0x3ff << 11, 203 .fuse_base_cp_shift = 11, 204 .fuse_base_ft_mask = 0x7ff << 21, 205 .fuse_base_ft_shift = 21, 206 .fuse_shift_ft_mask = 0x1f << 6, 207 .fuse_shift_ft_shift = 6, 208 .fuse_spare_realignment = 0, 209 }; 210 211 static struct tsensor_group_thermtrips tegra210_tsensor_thermtrips[] = { 212 {.id = TEGRA124_SOCTHERM_SENSOR_NUM}, 213 {.id = TEGRA124_SOCTHERM_SENSOR_NUM}, 214 {.id = TEGRA124_SOCTHERM_SENSOR_NUM}, 215 {.id = TEGRA124_SOCTHERM_SENSOR_NUM}, 216 }; 217 218 const struct tegra_soctherm_soc tegra210_soctherm = { 219 .tsensors = tegra210_tsensors, 220 .num_tsensors = ARRAY_SIZE(tegra210_tsensors), 221 .ttgs = tegra210_tsensor_groups, 222 .num_ttgs = ARRAY_SIZE(tegra210_tsensor_groups), 223 .tfuse = &tegra210_soctherm_fuse, 224 .thresh_grain = TEGRA210_THRESH_GRAIN, 225 .bptt = TEGRA210_BPTT, 226 .use_ccroc = false, 227 .thermtrips = tegra210_tsensor_thermtrips, 228 }; 229