1 /*
2 * URB OHCI HCD (Host Controller Driver) for USB.
3 *
4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
5 * (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net>
6 *
7 * [ Initialisation is based on Linus' ]
8 * [ uhci code and gregs ohci fragments ]
9 * [ (C) Copyright 1999 Linus Torvalds ]
10 * [ (C) Copyright 1999 Gregory P. Smith]
11 *
12 *
13 * History:
14 *
15 * 2002/10/22 OHCI_USB_OPER for ALi lockup in IBM i1200 (ALEX <thchou@ali>)
16 * 2002/03/08 interrupt unlink fix (Matt Hughes), better cleanup on
17 * load failure (Matthew Frederickson)
18 * 2002/01/20 async unlink fixes: return -EINPROGRESS (per spec) and
19 * make interrupt unlink-in-completion work (db)
20 * 2001/09/19 USB_ZERO_PACKET support (Jean Tourrilhes)
21 * 2001/07/17 power management and pmac cleanup (Benjamin Herrenschmidt)
22 * 2001/03/24 td/ed hashing to remove bus_to_virt (Steve Longerbeam);
23 pci_map_single (db)
24 * 2001/03/21 td and dev/ed allocation uses new pci_pool API (db)
25 * 2001/03/07 hcca allocation uses pci_alloc_consistent (Steve Longerbeam)
26 *
27 * 2000/09/26 fixed races in removing the private portion of the urb
28 * 2000/09/07 disable bulk and control lists when unlinking the last
29 * endpoint descriptor in order to avoid unrecoverable errors on
30 * the Lucent chips. (rwc@sgi)
31 * 2000/08/29 use bandwidth claiming hooks (thanks Randy!), fix some
32 * urb unlink probs, indentation fixes
33 * 2000/08/11 various oops fixes mostly affecting iso and cleanup from
34 * device unplugs.
35 * 2000/06/28 use PCI hotplug framework, for better power management
36 * and for Cardbus support (David Brownell)
37 * 2000/earlier: fixes for NEC/Lucent chips; suspend/resume handling
38 * when the controller loses power; handle UE; cleanup; ...
39 *
40 * v5.2 1999/12/07 URB 3rd preview,
41 * v5.1 1999/11/30 URB 2nd preview, cpia, (usb-scsi)
42 * v5.0 1999/11/22 URB Technical preview, Paul Mackerras powerbook susp/resume
43 * i386: HUB, Keyboard, Mouse, Printer
44 *
45 * v4.3 1999/10/27 multiple HCs, bulk_request
46 * v4.2 1999/09/05 ISO API alpha, new dev alloc, neg Error-codes
47 * v4.1 1999/08/27 Randy Dunlap's - ISO API first impl.
48 * v4.0 1999/08/18
49 * v3.0 1999/06/25
50 * v2.1 1999/05/09 code clean up
51 * v2.0 1999/05/04
52 * v1.0 1999/04/27 initial release
53 */
54
55 #include <linux/config.h>
56 #include <linux/module.h>
57 #include <linux/pci.h>
58 #include <linux/kernel.h>
59 #include <linux/delay.h>
60 #include <linux/ioport.h>
61 #include <linux/sched.h>
62 #include <linux/slab.h>
63 #include <linux/smp_lock.h>
64 #include <linux/errno.h>
65 #include <linux/init.h>
66 #include <linux/timer.h>
67 #include <linux/list.h>
68 #include <linux/interrupt.h> /* for in_interrupt() */
69 #undef DEBUG
70 #include <linux/usb.h>
71
72 #include <asm/io.h>
73 #include <asm/irq.h>
74 #include <asm/system.h>
75 #include <asm/unaligned.h>
76
77 #define OHCI_USE_NPS // force NoPowerSwitching mode
78 // #define OHCI_VERBOSE_DEBUG /* not always helpful */
79
80 #include "usb-ohci.h"
81
82 #include "../hcd.h"
83
84 #ifdef CONFIG_PMAC_PBOOK
85 #include <asm/machdep.h>
86 #include <asm/pmac_feature.h>
87 #include <asm/pci-bridge.h>
88 #ifndef CONFIG_PM
89 #define CONFIG_PM
90 #endif
91 #endif
92
93
94 /*
95 * Version Information
96 */
97 #define DRIVER_VERSION "v5.3"
98 #define DRIVER_AUTHOR "Roman Weissgaerber <weissg@vienna.at>, David Brownell"
99 #define DRIVER_DESC "USB OHCI Host Controller Driver"
100
101 /* For initializing controller (mask in an HCFS mode too) */
102 #define OHCI_CONTROL_INIT \
103 (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
104
105 #define OHCI_UNLINK_TIMEOUT (HZ / 10)
106
107 /*-------------------------------------------------------------------------*/
108
109 /* AMD-756 (D2 rev) reports corrupt register contents in some cases.
110 * The erratum (#4) description is incorrect. AMD's workaround waits
111 * till some bits (mostly reserved) are clear; ok for all revs.
112 */
113 #define read_roothub(hc, register, mask) ({ \
114 u32 temp = readl (&hc->regs->roothub.register); \
115 if (hc->flags & OHCI_QUIRK_AMD756) \
116 while (temp & mask) \
117 temp = readl (&hc->regs->roothub.register); \
118 temp; })
119
roothub_a(struct ohci * hc)120 static u32 roothub_a (struct ohci *hc)
121 { return read_roothub (hc, a, 0xfc0fe000); }
roothub_b(struct ohci * hc)122 static inline u32 roothub_b (struct ohci *hc)
123 { return readl (&hc->regs->roothub.b); }
roothub_status(struct ohci * hc)124 static inline u32 roothub_status (struct ohci *hc)
125 { return readl (&hc->regs->roothub.status); }
roothub_portstatus(struct ohci * hc,int i)126 static u32 roothub_portstatus (struct ohci *hc, int i)
127 { return read_roothub (hc, portstatus [i], 0xffe0fce0); }
128
129
130 /*-------------------------------------------------------------------------*
131 * URB support functions
132 *-------------------------------------------------------------------------*/
133
ohci_complete_add(struct ohci * ohci,struct urb * urb)134 static void ohci_complete_add(struct ohci *ohci, struct urb *urb)
135 {
136
137 if (urb->hcpriv != NULL) {
138 printk("completing with non-null priv!\n");
139 return;
140 }
141
142 if (ohci->complete_tail == NULL) {
143 ohci->complete_head = urb;
144 ohci->complete_tail = urb;
145 } else {
146 ohci->complete_tail->hcpriv = urb;
147 ohci->complete_tail = urb;
148 }
149 }
150
ohci_complete_get(struct ohci * ohci)151 static inline struct urb *ohci_complete_get(struct ohci *ohci)
152 {
153 struct urb *urb;
154
155 if ((urb = ohci->complete_head) == NULL)
156 return NULL;
157 if (urb == ohci->complete_tail) {
158 ohci->complete_tail = NULL;
159 ohci->complete_head = NULL;
160 } else {
161 ohci->complete_head = urb->hcpriv;
162 }
163 urb->hcpriv = NULL;
164 return urb;
165 }
166
ohci_complete(struct ohci * ohci)167 static inline void ohci_complete(struct ohci *ohci)
168 {
169 struct urb *urb;
170
171 spin_lock(&ohci->ohci_lock);
172 while ((urb = ohci_complete_get(ohci)) != NULL) {
173 spin_unlock(&ohci->ohci_lock);
174 if (urb->dev) {
175 usb_dec_dev_use (urb->dev);
176 urb->dev = NULL;
177 }
178 if (urb->complete)
179 (*urb->complete)(urb);
180 spin_lock(&ohci->ohci_lock);
181 }
182 spin_unlock(&ohci->ohci_lock);
183 }
184
185 /* free HCD-private data associated with this URB */
186
urb_free_priv(struct ohci * hc,urb_priv_t * urb_priv)187 static void urb_free_priv (struct ohci *hc, urb_priv_t * urb_priv)
188 {
189 int i;
190 int last = urb_priv->length - 1;
191 int len;
192 int dir;
193 struct td *td;
194
195 if (last >= 0) {
196
197 /* ISOC, BULK, INTR data buffer starts at td 0
198 * CTRL setup starts at td 0 */
199 td = urb_priv->td [0];
200
201 len = td->urb->transfer_buffer_length,
202 dir = usb_pipeout (td->urb->pipe)
203 ? PCI_DMA_TODEVICE
204 : PCI_DMA_FROMDEVICE;
205
206 /* unmap CTRL URB setup */
207 if (usb_pipecontrol (td->urb->pipe)) {
208 pci_unmap_single (hc->ohci_dev,
209 td->data_dma, 8, PCI_DMA_TODEVICE);
210
211 /* CTRL data buffer starts at td 1 if len > 0 */
212 if (len && last > 0)
213 td = urb_priv->td [1];
214 }
215
216 /* unmap data buffer */
217 if (len && td->data_dma)
218 pci_unmap_single (hc->ohci_dev, td->data_dma, len, dir);
219
220 for (i = 0; i <= last; i++) {
221 td = urb_priv->td [i];
222 if (td)
223 td_free (hc, td);
224 }
225 }
226
227 kfree (urb_priv);
228 }
229
urb_rm_priv_locked(struct urb * urb)230 static void urb_rm_priv_locked (struct urb * urb)
231 {
232 urb_priv_t * urb_priv = urb->hcpriv;
233
234 if (urb_priv) {
235 urb->hcpriv = NULL;
236
237 #ifdef DO_TIMEOUTS
238 if (urb->timeout) {
239 list_del (&urb->urb_list);
240 urb->timeout -= jiffies;
241 }
242 #endif
243
244 /* Release int/iso bandwidth */
245 if (urb->bandwidth) {
246 switch (usb_pipetype(urb->pipe)) {
247 case PIPE_INTERRUPT:
248 usb_release_bandwidth (urb->dev, urb, 0);
249 break;
250 case PIPE_ISOCHRONOUS:
251 usb_release_bandwidth (urb->dev, urb, 1);
252 break;
253 default:
254 break;
255 }
256 }
257
258 urb_free_priv ((struct ohci *)urb->dev->bus->hcpriv, urb_priv);
259 } else {
260 if (urb->dev != NULL) {
261 err ("Non-null dev at rm_priv time");
262 // urb->dev = NULL;
263 }
264 }
265 }
266
267 /*-------------------------------------------------------------------------*/
268
269 #ifdef DEBUG
270 static int sohci_get_current_frame_number (struct usb_device * dev);
271
272 /* debug| print the main components of an URB
273 * small: 0) header + data packets 1) just header */
274
urb_print(struct urb * urb,char * str,int small)275 static void urb_print (struct urb * urb, char * str, int small)
276 {
277 unsigned int pipe= urb->pipe;
278
279 if (!urb->dev || !urb->dev->bus) {
280 dbg("%s URB: no dev", str);
281 return;
282 }
283
284 #ifndef OHCI_VERBOSE_DEBUG
285 if (urb->status != 0)
286 #endif
287 dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,flags:%4x,len:%d/%d,stat:%d(%x)",
288 str,
289 sohci_get_current_frame_number (urb->dev),
290 usb_pipedevice (pipe),
291 usb_pipeendpoint (pipe),
292 usb_pipeout (pipe)? 'O': 'I',
293 usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
294 (usb_pipecontrol (pipe)? "CTRL": "BULK"),
295 urb->transfer_flags,
296 urb->actual_length,
297 urb->transfer_buffer_length,
298 urb->status, urb->status);
299 #ifdef OHCI_VERBOSE_DEBUG
300 if (!small) {
301 int i, len;
302
303 if (usb_pipecontrol (pipe)) {
304 printk (KERN_DEBUG __FILE__ ": cmd(8):");
305 for (i = 0; i < 8 ; i++)
306 printk (" %02x", ((__u8 *) urb->setup_packet) [i]);
307 printk ("\n");
308 }
309 if (urb->transfer_buffer_length > 0 && urb->transfer_buffer) {
310 printk (KERN_DEBUG __FILE__ ": data(%d/%d):",
311 urb->actual_length,
312 urb->transfer_buffer_length);
313 len = usb_pipeout (pipe)?
314 urb->transfer_buffer_length: urb->actual_length;
315 for (i = 0; i < 16 && i < len; i++)
316 printk (" %02x", ((__u8 *) urb->transfer_buffer) [i]);
317 printk ("%s stat:%d\n", i < len? "...": "", urb->status);
318 }
319 }
320 #endif
321 }
322
323 /* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
ep_print_int_eds(ohci_t * ohci,char * str)324 void ep_print_int_eds (ohci_t * ohci, char * str) {
325 int i, j;
326 __u32 * ed_p;
327 for (i= 0; i < 32; i++) {
328 j = 5;
329 ed_p = &(ohci->hcca->int_table [i]);
330 if (*ed_p == 0)
331 continue;
332 printk (KERN_DEBUG __FILE__ ": %s branch int %2d(%2x):", str, i, i);
333 while (*ed_p != 0 && j--) {
334 ed_t *ed = dma_to_ed (ohci, le32_to_cpup(ed_p));
335 printk (" ed: %4x;", ed->hwINFO);
336 ed_p = &ed->hwNextED;
337 }
338 printk ("\n");
339 }
340 }
341
342
ohci_dump_intr_mask(char * label,__u32 mask)343 static void ohci_dump_intr_mask (char *label, __u32 mask)
344 {
345 dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
346 label,
347 mask,
348 (mask & OHCI_INTR_MIE) ? " MIE" : "",
349 (mask & OHCI_INTR_OC) ? " OC" : "",
350 (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
351 (mask & OHCI_INTR_FNO) ? " FNO" : "",
352 (mask & OHCI_INTR_UE) ? " UE" : "",
353 (mask & OHCI_INTR_RD) ? " RD" : "",
354 (mask & OHCI_INTR_SF) ? " SF" : "",
355 (mask & OHCI_INTR_WDH) ? " WDH" : "",
356 (mask & OHCI_INTR_SO) ? " SO" : ""
357 );
358 }
359
maybe_print_eds(char * label,__u32 value)360 static void maybe_print_eds (char *label, __u32 value)
361 {
362 if (value)
363 dbg ("%s %08x", label, value);
364 }
365
hcfs2string(int state)366 static char *hcfs2string (int state)
367 {
368 switch (state) {
369 case OHCI_USB_RESET: return "reset";
370 case OHCI_USB_RESUME: return "resume";
371 case OHCI_USB_OPER: return "operational";
372 case OHCI_USB_SUSPEND: return "suspend";
373 }
374 return "?";
375 }
376
377 // dump control and status registers
ohci_dump_status(ohci_t * controller)378 static void ohci_dump_status (ohci_t *controller)
379 {
380 struct ohci_regs *regs = controller->regs;
381 __u32 temp;
382
383 temp = readl (®s->revision) & 0xff;
384 if (temp != 0x10)
385 dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));
386
387 temp = readl (®s->control);
388 dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
389 (temp & OHCI_CTRL_RWE) ? " RWE" : "",
390 (temp & OHCI_CTRL_RWC) ? " RWC" : "",
391 (temp & OHCI_CTRL_IR) ? " IR" : "",
392 hcfs2string (temp & OHCI_CTRL_HCFS),
393 (temp & OHCI_CTRL_BLE) ? " BLE" : "",
394 (temp & OHCI_CTRL_CLE) ? " CLE" : "",
395 (temp & OHCI_CTRL_IE) ? " IE" : "",
396 (temp & OHCI_CTRL_PLE) ? " PLE" : "",
397 temp & OHCI_CTRL_CBSR
398 );
399
400 temp = readl (®s->cmdstatus);
401 dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
402 (temp & OHCI_SOC) >> 16,
403 (temp & OHCI_OCR) ? " OCR" : "",
404 (temp & OHCI_BLF) ? " BLF" : "",
405 (temp & OHCI_CLF) ? " CLF" : "",
406 (temp & OHCI_HCR) ? " HCR" : ""
407 );
408
409 ohci_dump_intr_mask ("intrstatus", readl (®s->intrstatus));
410 ohci_dump_intr_mask ("intrenable", readl (®s->intrenable));
411 // intrdisable always same as intrenable
412 // ohci_dump_intr_mask ("intrdisable", readl (®s->intrdisable));
413
414 maybe_print_eds ("ed_periodcurrent", readl (®s->ed_periodcurrent));
415
416 maybe_print_eds ("ed_controlhead", readl (®s->ed_controlhead));
417 maybe_print_eds ("ed_controlcurrent", readl (®s->ed_controlcurrent));
418
419 maybe_print_eds ("ed_bulkhead", readl (®s->ed_bulkhead));
420 maybe_print_eds ("ed_bulkcurrent", readl (®s->ed_bulkcurrent));
421
422 maybe_print_eds ("donehead", readl (®s->donehead));
423 }
424
ohci_dump_roothub(ohci_t * controller,int verbose)425 static void ohci_dump_roothub (ohci_t *controller, int verbose)
426 {
427 __u32 temp, ndp, i;
428
429 temp = roothub_a (controller);
430 if (temp == ~(u32)0)
431 return;
432 ndp = (temp & RH_A_NDP);
433
434 if (verbose) {
435 dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
436 ((temp & RH_A_POTPGT) >> 24) & 0xff,
437 (temp & RH_A_NOCP) ? " NOCP" : "",
438 (temp & RH_A_OCPM) ? " OCPM" : "",
439 (temp & RH_A_DT) ? " DT" : "",
440 (temp & RH_A_NPS) ? " NPS" : "",
441 (temp & RH_A_PSM) ? " PSM" : "",
442 ndp
443 );
444 temp = roothub_b (controller);
445 dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
446 temp,
447 (temp & RH_B_PPCM) >> 16,
448 (temp & RH_B_DR)
449 );
450 temp = roothub_status (controller);
451 dbg ("roothub.status: %08x%s%s%s%s%s%s",
452 temp,
453 (temp & RH_HS_CRWE) ? " CRWE" : "",
454 (temp & RH_HS_OCIC) ? " OCIC" : "",
455 (temp & RH_HS_LPSC) ? " LPSC" : "",
456 (temp & RH_HS_DRWE) ? " DRWE" : "",
457 (temp & RH_HS_OCI) ? " OCI" : "",
458 (temp & RH_HS_LPS) ? " LPS" : ""
459 );
460 }
461
462 for (i = 0; i < ndp; i++) {
463 temp = roothub_portstatus (controller, i);
464 dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
465 i,
466 temp,
467 (temp & RH_PS_PRSC) ? " PRSC" : "",
468 (temp & RH_PS_OCIC) ? " OCIC" : "",
469 (temp & RH_PS_PSSC) ? " PSSC" : "",
470 (temp & RH_PS_PESC) ? " PESC" : "",
471 (temp & RH_PS_CSC) ? " CSC" : "",
472
473 (temp & RH_PS_LSDA) ? " LSDA" : "",
474 (temp & RH_PS_PPS) ? " PPS" : "",
475 (temp & RH_PS_PRS) ? " PRS" : "",
476 (temp & RH_PS_POCI) ? " POCI" : "",
477 (temp & RH_PS_PSS) ? " PSS" : "",
478
479 (temp & RH_PS_PES) ? " PES" : "",
480 (temp & RH_PS_CCS) ? " CCS" : ""
481 );
482 }
483 }
484
ohci_dump(ohci_t * controller,int verbose)485 static void ohci_dump (ohci_t *controller, int verbose)
486 {
487 dbg ("OHCI controller usb-%s state", controller->ohci_dev->slot_name);
488
489 // dumps some of the state we know about
490 ohci_dump_status (controller);
491 if (verbose)
492 ep_print_int_eds (controller, "hcca");
493 dbg ("hcca frame #%04x", controller->hcca->frame_no);
494 ohci_dump_roothub (controller, 1);
495 }
496
497
498 #endif
499
500 /*-------------------------------------------------------------------------*
501 * Interface functions (URB)
502 *-------------------------------------------------------------------------*/
503
504 /* return a request to the completion handler */
505
sohci_return_urb(struct ohci * hc,struct urb * urb)506 static int sohci_return_urb (struct ohci *hc, struct urb * urb)
507 {
508 urb_priv_t * urb_priv = urb->hcpriv;
509 struct urb * urbt;
510 int i;
511
512 if (!urb_priv)
513 return -1; /* urb already unlinked */
514
515 /* just to be sure */
516 if (!urb->complete) {
517 urb_rm_priv_locked (urb);
518 ohci_complete_add(hc, urb); /* Just usb_dec_dev_use */
519 return -1;
520 }
521
522 #ifdef DEBUG
523 urb_print (urb, "RET", usb_pipeout (urb->pipe));
524 #endif
525
526 switch (usb_pipetype (urb->pipe)) {
527 case PIPE_INTERRUPT:
528 pci_unmap_single (hc->ohci_dev,
529 urb_priv->td [0]->data_dma,
530 urb->transfer_buffer_length,
531 usb_pipeout (urb->pipe)
532 ? PCI_DMA_TODEVICE
533 : PCI_DMA_FROMDEVICE);
534 if (urb->interval) {
535 urb->complete (urb);
536
537 /* implicitly requeued */
538 urb->actual_length = 0;
539 urb->status = -EINPROGRESS;
540 td_submit_urb (urb);
541 } else {
542 urb_rm_priv_locked (urb);
543 ohci_complete_add(hc, urb);
544 }
545 break;
546
547 case PIPE_ISOCHRONOUS:
548 for (urbt = urb->next; urbt && (urbt != urb); urbt = urbt->next);
549 if (urbt) { /* send the reply and requeue URB */
550 pci_unmap_single (hc->ohci_dev,
551 urb_priv->td [0]->data_dma,
552 urb->transfer_buffer_length,
553 usb_pipeout (urb->pipe)
554 ? PCI_DMA_TODEVICE
555 : PCI_DMA_FROMDEVICE);
556 urb->complete (urb);
557 urb->actual_length = 0;
558 urb->status = USB_ST_URB_PENDING;
559 urb->start_frame = urb_priv->ed->last_iso + 1;
560 if (urb_priv->state != URB_DEL) {
561 for (i = 0; i < urb->number_of_packets; i++) {
562 urb->iso_frame_desc[i].actual_length = 0;
563 urb->iso_frame_desc[i].status = -EXDEV;
564 }
565 td_submit_urb (urb);
566 }
567
568 } else { /* unlink URB, call complete */
569 urb_rm_priv_locked (urb);
570 ohci_complete_add(hc, urb);
571 }
572 break;
573
574 case PIPE_BULK:
575 case PIPE_CONTROL: /* unlink URB, call complete */
576 urb_rm_priv_locked (urb);
577 ohci_complete_add(hc, urb);
578 break;
579 }
580 return 0;
581 }
582
583 /*-------------------------------------------------------------------------*/
584
585 /* get a transfer request */
586
sohci_submit_urb(struct urb * urb)587 static int sohci_submit_urb (struct urb * urb)
588 {
589 ohci_t * ohci;
590 ed_t * ed;
591 urb_priv_t * urb_priv;
592 unsigned int pipe = urb->pipe;
593 int maxps = usb_maxpacket (urb->dev, pipe, usb_pipeout (pipe));
594 int i, size = 0;
595 unsigned long flags;
596 int bustime = 0;
597 int mem_flags = GFP_ATOMIC;
598
599 if (!urb->dev || !urb->dev->bus)
600 return -ENODEV;
601
602 if (urb->hcpriv) /* urb already in use */
603 return -EINVAL;
604
605 // if(usb_endpoint_halted (urb->dev, usb_pipeendpoint (pipe), usb_pipeout (pipe)))
606 // return -EPIPE;
607
608 usb_inc_dev_use (urb->dev);
609 ohci = (ohci_t *) urb->dev->bus->hcpriv;
610
611 #ifdef DEBUG
612 urb_print (urb, "SUB", usb_pipein (pipe));
613 #endif
614
615 /* handle a request to the virtual root hub */
616 if (usb_pipedevice (pipe) == ohci->rh.devnum)
617 return rh_submit_urb (urb);
618
619 spin_lock_irqsave(&ohci->ohci_lock, flags);
620
621 /* when controller's hung, permit only roothub cleanup attempts
622 * such as powering down ports */
623 if (ohci->disabled) {
624 spin_unlock_irqrestore(&ohci->ohci_lock, flags);
625 usb_dec_dev_use (urb->dev);
626 return -ESHUTDOWN;
627 }
628
629 /* every endpoint has a ed, locate and fill it */
630 if (!(ed = ep_add_ed (urb->dev, pipe, urb->interval, 1, mem_flags))) {
631 spin_unlock_irqrestore(&ohci->ohci_lock, flags);
632 usb_dec_dev_use (urb->dev);
633 return -ENOMEM;
634 }
635
636 /* for the private part of the URB we need the number of TDs (size) */
637 switch (usb_pipetype (pipe)) {
638 case PIPE_BULK: /* one TD for every 4096 Byte */
639 size = (urb->transfer_buffer_length - 1) / 4096 + 1;
640
641 /* If the transfer size is multiple of the pipe mtu,
642 * we may need an extra TD to create a empty frame
643 * Jean II */
644 if ((urb->transfer_flags & USB_ZERO_PACKET) &&
645 usb_pipeout (pipe) &&
646 (urb->transfer_buffer_length != 0) &&
647 ((urb->transfer_buffer_length % maxps) == 0))
648 size++;
649 break;
650 case PIPE_ISOCHRONOUS: /* number of packets from URB */
651 size = urb->number_of_packets;
652 if (size <= 0) {
653 spin_unlock_irqrestore(&ohci->ohci_lock, flags);
654 usb_dec_dev_use (urb->dev);
655 return -EINVAL;
656 }
657 for (i = 0; i < urb->number_of_packets; i++) {
658 urb->iso_frame_desc[i].actual_length = 0;
659 urb->iso_frame_desc[i].status = -EXDEV;
660 }
661 break;
662 case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
663 size = (urb->transfer_buffer_length == 0)? 2:
664 (urb->transfer_buffer_length - 1) / 4096 + 3;
665 break;
666 case PIPE_INTERRUPT: /* one TD */
667 size = 1;
668 break;
669 }
670
671 /* allocate the private part of the URB */
672 urb_priv = kmalloc (sizeof (urb_priv_t) + size * sizeof (td_t *),
673 GFP_ATOMIC);
674 if (!urb_priv) {
675 spin_unlock_irqrestore(&ohci->ohci_lock, flags);
676 usb_dec_dev_use (urb->dev);
677 return -ENOMEM;
678 }
679 memset (urb_priv, 0, sizeof (urb_priv_t) + size * sizeof (td_t *));
680
681 /* fill the private part of the URB */
682 urb_priv->length = size;
683 urb_priv->ed = ed;
684
685 /* allocate the TDs (updating hash chains) */
686 for (i = 0; i < size; i++) {
687 urb_priv->td[i] = td_alloc (ohci, SLAB_ATOMIC);
688 if (!urb_priv->td[i]) {
689 urb_priv->length = i;
690 urb_free_priv (ohci, urb_priv);
691 spin_unlock_irqrestore(&ohci->ohci_lock, flags);
692 usb_dec_dev_use (urb->dev);
693 return -ENOMEM;
694 }
695 }
696
697 if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
698 urb_free_priv (ohci, urb_priv);
699 spin_unlock_irqrestore(&ohci->ohci_lock, flags);
700 usb_dec_dev_use (urb->dev);
701 return -EINVAL;
702 }
703
704 /* allocate and claim bandwidth if needed; ISO
705 * needs start frame index if it was't provided.
706 */
707 switch (usb_pipetype (pipe)) {
708 case PIPE_ISOCHRONOUS:
709 if (urb->transfer_flags & USB_ISO_ASAP) {
710 urb->start_frame = ((ed->state == ED_OPER)
711 ? (ed->last_iso + 1)
712 : (le16_to_cpu (ohci->hcca->frame_no) + 10)) & 0xffff;
713 }
714 /* FALLTHROUGH */
715 case PIPE_INTERRUPT:
716 if (urb->bandwidth == 0) {
717 bustime = usb_check_bandwidth (urb->dev, urb);
718 }
719 if (bustime < 0) {
720 urb_free_priv (ohci, urb_priv);
721 spin_unlock_irqrestore(&ohci->ohci_lock, flags);
722 usb_dec_dev_use (urb->dev);
723 return bustime;
724 }
725 usb_claim_bandwidth (urb->dev, urb, bustime, usb_pipeisoc (urb->pipe));
726 #ifdef DO_TIMEOUTS
727 urb->timeout = 0;
728 #endif
729 }
730
731 urb->actual_length = 0;
732 urb->hcpriv = urb_priv;
733 urb->status = USB_ST_URB_PENDING;
734
735 /* link the ed into a chain if is not already */
736 if (ed->state != ED_OPER)
737 ep_link (ohci, ed);
738
739 /* fill the TDs and link it to the ed */
740 td_submit_urb (urb);
741
742 #ifdef DO_TIMEOUTS
743 /* maybe add to ordered list of timeouts */
744 if (urb->timeout) {
745 struct list_head *entry;
746
747 urb->timeout += jiffies;
748
749 list_for_each (entry, &ohci->timeout_list) {
750 struct urb *next_urb;
751
752 next_urb = list_entry (entry, struct urb, urb_list);
753 if (time_after_eq (urb->timeout, next_urb->timeout))
754 break;
755 }
756 list_add (&urb->urb_list, entry);
757
758 /* drive timeouts by SF (messy, but works) */
759 writel (OHCI_INTR_SF, &ohci->regs->intrenable);
760 (void)readl (&ohci->regs->intrdisable); /* PCI posting flush */
761 }
762 #endif
763
764 spin_unlock_irqrestore(&ohci->ohci_lock, flags);
765
766 return 0;
767 }
768
769 /*-------------------------------------------------------------------------*/
770
771 /* deactivate all TDs and remove the private part of the URB */
772 /* interrupt callers must use async unlink mode */
773
sohci_unlink_urb(struct urb * urb)774 static int sohci_unlink_urb (struct urb * urb)
775 {
776 unsigned long flags;
777 ohci_t * ohci;
778
779 if (!urb) /* just to be sure */
780 return -EINVAL;
781
782 if (!urb->dev || !urb->dev->bus)
783 return -ENODEV;
784
785 ohci = (ohci_t *) urb->dev->bus->hcpriv;
786
787 #ifdef DEBUG
788 urb_print (urb, "UNLINK", 1);
789 #endif
790
791 /* handle a request to the virtual root hub */
792 if (usb_pipedevice (urb->pipe) == ohci->rh.devnum)
793 return rh_unlink_urb (urb);
794
795 spin_lock_irqsave(&ohci->ohci_lock, flags);
796 if (urb->hcpriv && (urb->status == USB_ST_URB_PENDING)) {
797 if (!ohci->disabled) {
798 urb_priv_t * urb_priv;
799
800 /* interrupt code may not sleep; it must use
801 * async status return to unlink pending urbs.
802 */
803 if (!(urb->transfer_flags & USB_ASYNC_UNLINK)
804 && in_interrupt ()) {
805 spin_unlock_irqrestore(&ohci->ohci_lock, flags);
806 err ("bug in call from %p; use async!",
807 __builtin_return_address(0));
808 return -EWOULDBLOCK;
809 }
810
811 /* flag the urb and its TDs for deletion in some
812 * upcoming SF interrupt delete list processing
813 */
814 urb_priv = urb->hcpriv;
815
816 if (!urb_priv || (urb_priv->state == URB_DEL)) {
817 spin_unlock_irqrestore(&ohci->ohci_lock, flags);
818 return 0;
819 }
820
821 urb_priv->state = URB_DEL;
822 ep_rm_ed (urb->dev, urb_priv->ed);
823 urb_priv->ed->state |= ED_URB_DEL;
824
825 if (!(urb->transfer_flags & USB_ASYNC_UNLINK)) {
826 DECLARE_WAIT_QUEUE_HEAD (unlink_wakeup);
827 DECLARE_WAITQUEUE (wait, current);
828 int timeout = OHCI_UNLINK_TIMEOUT;
829
830 add_wait_queue (&unlink_wakeup, &wait);
831 urb_priv->wait = &unlink_wakeup;
832 spin_unlock_irqrestore(&ohci->ohci_lock, flags);
833
834 /* wait until all TDs are deleted */
835 set_current_state(TASK_UNINTERRUPTIBLE);
836 while (timeout && (urb->status == USB_ST_URB_PENDING)) {
837 timeout = schedule_timeout (timeout);
838 set_current_state(TASK_UNINTERRUPTIBLE);
839 }
840 set_current_state(TASK_RUNNING);
841
842 /*
843 * A waitqueue head is self-locked, but we try
844 * to interlock with the dl_del_urb().
845 */
846 spin_lock_irqsave(&ohci->ohci_lock, flags);
847 remove_wait_queue(&unlink_wakeup, &wait);
848 spin_unlock_irqrestore(&ohci->ohci_lock, flags);
849 if (urb->status == USB_ST_URB_PENDING) {
850 err ("unlink URB timeout");
851 return -ETIMEDOUT;
852 }
853
854 usb_dec_dev_use (urb->dev);
855 urb->dev = NULL;
856 if (urb->complete)
857 urb->complete (urb);
858 } else {
859 /* usb_dec_dev_use done in dl_del_list() */
860 urb->status = -EINPROGRESS;
861 spin_unlock_irqrestore(&ohci->ohci_lock, flags);
862 return -EINPROGRESS;
863 }
864 } else {
865 urb_rm_priv_locked (urb);
866 spin_unlock_irqrestore(&ohci->ohci_lock, flags);
867 usb_dec_dev_use (urb->dev);
868 urb->dev = NULL;
869 if (urb->transfer_flags & USB_ASYNC_UNLINK) {
870 urb->status = -ECONNRESET;
871 if (urb->complete)
872 urb->complete (urb);
873 } else
874 urb->status = -ENOENT;
875 }
876 } else {
877 spin_unlock_irqrestore(&ohci->ohci_lock, flags);
878 }
879 return 0;
880 }
881
882 /*-------------------------------------------------------------------------*/
883
884 /* allocate private data space for a usb device */
885
sohci_alloc_dev(struct usb_device * usb_dev)886 static int sohci_alloc_dev (struct usb_device *usb_dev)
887 {
888 struct ohci_device * dev;
889
890 dev = dev_alloc ((struct ohci *) usb_dev->bus->hcpriv, ALLOC_FLAGS);
891 if (!dev)
892 return -ENOMEM;
893
894 usb_dev->hcpriv = dev;
895 return 0;
896 }
897
898 /*-------------------------------------------------------------------------*/
899
900 /* may be called from interrupt context */
901 /* frees private data space of usb device */
902
sohci_free_dev(struct usb_device * usb_dev)903 static int sohci_free_dev (struct usb_device * usb_dev)
904 {
905 unsigned long flags;
906 int i, cnt = 0;
907 ed_t * ed;
908 struct ohci_device * dev = usb_to_ohci (usb_dev);
909 ohci_t * ohci = usb_dev->bus->hcpriv;
910
911 if (!dev)
912 return 0;
913
914 if (usb_dev->devnum >= 0) {
915
916 /* driver disconnects should have unlinked all urbs
917 * (freeing all the TDs, unlinking EDs) but we need
918 * to defend against bugs that prevent that.
919 */
920 spin_lock_irqsave(&ohci->ohci_lock, flags);
921 for(i = 0; i < NUM_EDS; i++) {
922 ed = &(dev->ed[i]);
923 if (ed->state != ED_NEW) {
924 if (ed->state == ED_OPER) {
925 /* driver on that interface didn't unlink an urb */
926 dbg ("driver usb-%s dev %d ed 0x%x unfreed URB",
927 ohci->ohci_dev->slot_name, usb_dev->devnum, i);
928 ep_unlink (ohci, ed);
929 }
930 ep_rm_ed (usb_dev, ed);
931 ed->state = ED_DEL;
932 cnt++;
933 }
934 }
935 spin_unlock_irqrestore(&ohci->ohci_lock, flags);
936
937 /* if the controller is running, tds for those unlinked
938 * urbs get freed by dl_del_list at the next SF interrupt
939 */
940 if (cnt > 0) {
941
942 if (ohci->disabled) {
943 /* FIXME: Something like this should kick in,
944 * though it's currently an exotic case ...
945 * the controller won't ever be touching
946 * these lists again!!
947 dl_del_list (ohci,
948 le16_to_cpu (ohci->hcca->frame_no) & 1);
949 */
950 warn ("TD leak, %d", cnt);
951
952 } else if (!in_interrupt ()) {
953 DECLARE_WAITQUEUE (wait, current);
954 int timeout = OHCI_UNLINK_TIMEOUT;
955
956 /* SF interrupt handler calls dl_del_list */
957 add_wait_queue (&dev->wait, &wait);
958 set_current_state(TASK_UNINTERRUPTIBLE);
959 while (timeout && dev->ed_cnt)
960 timeout = schedule_timeout (timeout);
961 set_current_state(TASK_RUNNING);
962 remove_wait_queue (&dev->wait, &wait);
963 if (dev->ed_cnt) {
964 err ("free device %d timeout", usb_dev->devnum);
965 return -ETIMEDOUT;
966 }
967 } else {
968 /* likely some interface's driver has a refcount bug */
969 err ("bus %s devnum %d deletion in interrupt",
970 ohci->ohci_dev->slot_name, usb_dev->devnum);
971 BUG ();
972 }
973 }
974 }
975
976 /* free device, and associated EDs */
977 dev_free (ohci, dev);
978
979 return 0;
980 }
981
982 /*-------------------------------------------------------------------------*/
983
984 /* tell us the current USB frame number */
985
sohci_get_current_frame_number(struct usb_device * usb_dev)986 static int sohci_get_current_frame_number (struct usb_device *usb_dev)
987 {
988 ohci_t * ohci = usb_dev->bus->hcpriv;
989
990 return le16_to_cpu (ohci->hcca->frame_no);
991 }
992
993 /*-------------------------------------------------------------------------*/
994
995 struct usb_operations sohci_device_operations = {
996 sohci_alloc_dev,
997 sohci_free_dev,
998 sohci_get_current_frame_number,
999 sohci_submit_urb,
1000 sohci_unlink_urb
1001 };
1002
1003 /*-------------------------------------------------------------------------*
1004 * ED handling functions
1005 *-------------------------------------------------------------------------*/
1006
1007 /* search for the right branch to insert an interrupt ed into the int tree
1008 * do some load ballancing;
1009 * returns the branch and
1010 * sets the interval to interval = 2^integer (ld (interval)) */
1011
ep_int_ballance(ohci_t * ohci,int interval,int load)1012 static int ep_int_ballance (ohci_t * ohci, int interval, int load)
1013 {
1014 int i, branch = 0;
1015
1016 /* search for the least loaded interrupt endpoint branch of all 32 branches */
1017 for (i = 0; i < 32; i++)
1018 if (ohci->ohci_int_load [branch] > ohci->ohci_int_load [i]) branch = i;
1019
1020 branch = branch % interval;
1021 for (i = branch; i < 32; i += interval) ohci->ohci_int_load [i] += load;
1022
1023 return branch;
1024 }
1025
1026 /*-------------------------------------------------------------------------*/
1027
1028 /* 2^int( ld (inter)) */
1029
ep_2_n_interval(int inter)1030 static int ep_2_n_interval (int inter)
1031 {
1032 int i;
1033 for (i = 0; ((inter >> i) > 1 ) && (i < 5); i++);
1034 return 1 << i;
1035 }
1036
1037 /*-------------------------------------------------------------------------*/
1038
1039 /* the int tree is a binary tree
1040 * in order to process it sequentially the indexes of the branches have to be mapped
1041 * the mapping reverses the bits of a word of num_bits length */
1042
ep_rev(int num_bits,int word)1043 static int ep_rev (int num_bits, int word)
1044 {
1045 int i, wout = 0;
1046
1047 for (i = 0; i < num_bits; i++) wout |= (((word >> i) & 1) << (num_bits - i - 1));
1048 return wout;
1049 }
1050
1051 /*-------------------------------------------------------------------------*/
1052
1053 /* link an ed into one of the HC chains */
1054
ep_link(ohci_t * ohci,ed_t * edi)1055 static int ep_link (ohci_t * ohci, ed_t * edi)
1056 {
1057 int int_branch;
1058 int i;
1059 int inter;
1060 int interval;
1061 int load;
1062 __u32 * ed_p;
1063 volatile ed_t * ed = edi;
1064
1065 ed->state = ED_OPER;
1066
1067 switch (ed->type) {
1068 case PIPE_CONTROL:
1069 ed->hwNextED = 0;
1070 if (ohci->ed_controltail == NULL) {
1071 writel (ed->dma, &ohci->regs->ed_controlhead);
1072 } else {
1073 ohci->ed_controltail->hwNextED = cpu_to_le32 (ed->dma);
1074 }
1075 ed->ed_prev = ohci->ed_controltail;
1076 if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
1077 !ohci->ed_rm_list[1] && !ohci->sleeping) {
1078 ohci->hc_control |= OHCI_CTRL_CLE;
1079 writel (ohci->hc_control, &ohci->regs->control);
1080 }
1081 ohci->ed_controltail = edi;
1082 break;
1083
1084 case PIPE_BULK:
1085 ed->hwNextED = 0;
1086 if (ohci->ed_bulktail == NULL) {
1087 writel (ed->dma, &ohci->regs->ed_bulkhead);
1088 } else {
1089 ohci->ed_bulktail->hwNextED = cpu_to_le32 (ed->dma);
1090 }
1091 ed->ed_prev = ohci->ed_bulktail;
1092 if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
1093 !ohci->ed_rm_list[1] && !ohci->sleeping) {
1094 ohci->hc_control |= OHCI_CTRL_BLE;
1095 writel (ohci->hc_control, &ohci->regs->control);
1096 }
1097 ohci->ed_bulktail = edi;
1098 break;
1099
1100 case PIPE_INTERRUPT:
1101 load = ed->int_load;
1102 interval = ep_2_n_interval (ed->int_period);
1103 ed->int_interval = interval;
1104 int_branch = ep_int_ballance (ohci, interval, load);
1105 ed->int_branch = int_branch;
1106
1107 for (i = 0; i < ep_rev (6, interval); i += inter) {
1108 inter = 1;
1109 for (ed_p = &(ohci->hcca->int_table[ep_rev (5, i) + int_branch]);
1110 (*ed_p != 0) && ((dma_to_ed (ohci, le32_to_cpup (ed_p)))->int_interval >= interval);
1111 ed_p = &((dma_to_ed (ohci, le32_to_cpup (ed_p)))->hwNextED))
1112 inter = ep_rev (6, (dma_to_ed (ohci, le32_to_cpup (ed_p)))->int_interval);
1113 ed->hwNextED = *ed_p;
1114 *ed_p = cpu_to_le32 (ed->dma);
1115 }
1116 #ifdef DEBUG
1117 ep_print_int_eds (ohci, "LINK_INT");
1118 #endif
1119 break;
1120
1121 case PIPE_ISOCHRONOUS:
1122 ed->hwNextED = 0;
1123 ed->int_interval = 1;
1124 if (ohci->ed_isotail != NULL) {
1125 ohci->ed_isotail->hwNextED = cpu_to_le32 (ed->dma);
1126 ed->ed_prev = ohci->ed_isotail;
1127 } else {
1128 for ( i = 0; i < 32; i += inter) {
1129 inter = 1;
1130 for (ed_p = &(ohci->hcca->int_table[ep_rev (5, i)]);
1131 *ed_p != 0;
1132 ed_p = &((dma_to_ed (ohci, le32_to_cpup (ed_p)))->hwNextED))
1133 inter = ep_rev (6, (dma_to_ed (ohci, le32_to_cpup (ed_p)))->int_interval);
1134 *ed_p = cpu_to_le32 (ed->dma);
1135 }
1136 ed->ed_prev = NULL;
1137 }
1138 ohci->ed_isotail = edi;
1139 #ifdef DEBUG
1140 ep_print_int_eds (ohci, "LINK_ISO");
1141 #endif
1142 break;
1143 }
1144 return 0;
1145 }
1146
1147 /*-------------------------------------------------------------------------*/
1148
1149 /* scan the periodic table to find and unlink this ED */
periodic_unlink(struct ohci * ohci,struct ed * ed,unsigned index,unsigned period)1150 static void periodic_unlink (
1151 struct ohci *ohci,
1152 struct ed *ed,
1153 unsigned index,
1154 unsigned period
1155 ) {
1156 for (; index < NUM_INTS; index += period) {
1157 __u32 *ed_p = &ohci->hcca->int_table [index];
1158
1159 /* ED might have been unlinked through another path */
1160 while (*ed_p != 0) {
1161 if ((dma_to_ed (ohci, le32_to_cpup (ed_p))) == ed) {
1162 *ed_p = ed->hwNextED;
1163 break;
1164 }
1165 ed_p = & ((dma_to_ed (ohci,
1166 le32_to_cpup (ed_p)))->hwNextED);
1167 }
1168 }
1169 }
1170
1171 /* unlink an ed from one of the HC chains.
1172 * just the link to the ed is unlinked.
1173 * the link from the ed still points to another operational ed or 0
1174 * so the HC can eventually finish the processing of the unlinked ed */
1175
ep_unlink(ohci_t * ohci,ed_t * ed)1176 static int ep_unlink (ohci_t * ohci, ed_t * ed)
1177 {
1178 int i;
1179
1180 ed->hwINFO |= cpu_to_le32 (OHCI_ED_SKIP);
1181
1182 switch (ed->type) {
1183 case PIPE_CONTROL:
1184 if (ed->ed_prev == NULL) {
1185 if (!ed->hwNextED) {
1186 ohci->hc_control &= ~OHCI_CTRL_CLE;
1187 writel (ohci->hc_control, &ohci->regs->control);
1188 }
1189 writel (le32_to_cpup (&ed->hwNextED), &ohci->regs->ed_controlhead);
1190 } else {
1191 ed->ed_prev->hwNextED = ed->hwNextED;
1192 }
1193 if (ohci->ed_controltail == ed) {
1194 ohci->ed_controltail = ed->ed_prev;
1195 } else {
1196 (dma_to_ed (ohci, le32_to_cpup (&ed->hwNextED)))->ed_prev = ed->ed_prev;
1197 }
1198 break;
1199
1200 case PIPE_BULK:
1201 if (ed->ed_prev == NULL) {
1202 if (!ed->hwNextED) {
1203 ohci->hc_control &= ~OHCI_CTRL_BLE;
1204 writel (ohci->hc_control, &ohci->regs->control);
1205 }
1206 writel (le32_to_cpup (&ed->hwNextED), &ohci->regs->ed_bulkhead);
1207 } else {
1208 ed->ed_prev->hwNextED = ed->hwNextED;
1209 }
1210 if (ohci->ed_bulktail == ed) {
1211 ohci->ed_bulktail = ed->ed_prev;
1212 } else {
1213 (dma_to_ed (ohci, le32_to_cpup (&ed->hwNextED)))->ed_prev = ed->ed_prev;
1214 }
1215 break;
1216
1217 case PIPE_INTERRUPT:
1218 periodic_unlink (ohci, ed, 0, 1);
1219 for (i = ed->int_branch; i < 32; i += ed->int_interval)
1220 ohci->ohci_int_load[i] -= ed->int_load;
1221 #ifdef DEBUG
1222 ep_print_int_eds (ohci, "UNLINK_INT");
1223 #endif
1224 break;
1225
1226 case PIPE_ISOCHRONOUS:
1227 if (ohci->ed_isotail == ed)
1228 ohci->ed_isotail = ed->ed_prev;
1229 if (ed->hwNextED != 0)
1230 (dma_to_ed (ohci, le32_to_cpup (&ed->hwNextED)))
1231 ->ed_prev = ed->ed_prev;
1232
1233 if (ed->ed_prev != NULL)
1234 ed->ed_prev->hwNextED = ed->hwNextED;
1235 else
1236 periodic_unlink (ohci, ed, 0, 1);
1237 #ifdef DEBUG
1238 ep_print_int_eds (ohci, "UNLINK_ISO");
1239 #endif
1240 break;
1241 }
1242 ed->state = ED_UNLINK;
1243 return 0;
1244 }
1245
1246
1247 /*-------------------------------------------------------------------------*/
1248
1249 /* add/reinit an endpoint; this should be done once at the usb_set_configuration command,
1250 * but the USB stack is a little bit stateless so we do it at every transaction
1251 * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK
1252 * in all other cases the state is left unchanged
1253 * the ed info fields are setted anyway even though most of them should not change */
1254
ep_add_ed(struct usb_device * usb_dev,unsigned int pipe,int interval,int load,int mem_flags)1255 static ed_t * ep_add_ed (
1256 struct usb_device * usb_dev,
1257 unsigned int pipe,
1258 int interval,
1259 int load,
1260 int mem_flags
1261 )
1262 {
1263 ohci_t * ohci = usb_dev->bus->hcpriv;
1264 td_t * td;
1265 ed_t * ed_ret;
1266 volatile ed_t * ed;
1267
1268 ed = ed_ret = &(usb_to_ohci (usb_dev)->ed[(usb_pipeendpoint (pipe) << 1) |
1269 (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))]);
1270
1271 if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
1272 /* pending delete request */
1273 return NULL;
1274 }
1275
1276 if (ed->state == ED_NEW) {
1277 ed->hwINFO = cpu_to_le32 (OHCI_ED_SKIP); /* skip ed */
1278 /* dummy td; end of td list for ed */
1279 td = td_alloc (ohci, SLAB_ATOMIC);
1280 /* hash the ed for later reverse mapping */
1281 if (!td || !hash_add_ed (ohci, (ed_t *)ed)) {
1282 /* out of memory */
1283 if (td)
1284 td_free(ohci, td);
1285 return NULL;
1286 }
1287 ed->hwTailP = cpu_to_le32 (td->td_dma);
1288 ed->hwHeadP = ed->hwTailP;
1289 ed->state = ED_UNLINK;
1290 ed->type = usb_pipetype (pipe);
1291 usb_to_ohci (usb_dev)->ed_cnt++;
1292 }
1293
1294 ohci->dev[usb_pipedevice (pipe)] = usb_dev;
1295
1296 ed->hwINFO = cpu_to_le32 (usb_pipedevice (pipe)
1297 | usb_pipeendpoint (pipe) << 7
1298 | (usb_pipeisoc (pipe)? 0x8000: 0)
1299 | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
1300 | usb_pipeslow (pipe) << 13
1301 | usb_maxpacket (usb_dev, pipe, usb_pipeout (pipe)) << 16);
1302
1303 if (ed->type == PIPE_INTERRUPT && ed->state == ED_UNLINK) {
1304 ed->int_period = interval;
1305 ed->int_load = load;
1306 }
1307
1308 return ed_ret;
1309 }
1310
1311 /*-------------------------------------------------------------------------*/
1312
1313 /* request the removal of an endpoint
1314 * put the ep on the rm_list and request a stop of the bulk or ctrl list
1315 * real removal is done at the next start frame (SF) hardware interrupt */
1316
ep_rm_ed(struct usb_device * usb_dev,ed_t * ed)1317 static void ep_rm_ed (struct usb_device * usb_dev, ed_t * ed)
1318 {
1319 unsigned int frame;
1320 ohci_t * ohci = usb_dev->bus->hcpriv;
1321
1322 if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL))
1323 return;
1324
1325 ed->hwINFO |= cpu_to_le32 (OHCI_ED_SKIP);
1326
1327 if (!ohci->disabled) {
1328 switch (ed->type) {
1329 case PIPE_CONTROL: /* stop control list */
1330 ohci->hc_control &= ~OHCI_CTRL_CLE;
1331 writel (ohci->hc_control, &ohci->regs->control);
1332 break;
1333 case PIPE_BULK: /* stop bulk list */
1334 ohci->hc_control &= ~OHCI_CTRL_BLE;
1335 writel (ohci->hc_control, &ohci->regs->control);
1336 break;
1337 }
1338 }
1339
1340 frame = le16_to_cpu (ohci->hcca->frame_no) & 0x1;
1341 ed->ed_rm_list = ohci->ed_rm_list[frame];
1342 ohci->ed_rm_list[frame] = ed;
1343
1344 if (!ohci->disabled && !ohci->sleeping) {
1345 /* enable SOF interrupt */
1346 writel (OHCI_INTR_SF, &ohci->regs->intrstatus);
1347 writel (OHCI_INTR_SF, &ohci->regs->intrenable);
1348 (void)readl (&ohci->regs->intrdisable); /* PCI posting flush */
1349 }
1350 }
1351
1352 /*-------------------------------------------------------------------------*
1353 * TD handling functions
1354 *-------------------------------------------------------------------------*/
1355
1356 /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
1357
1358 static void
td_fill(ohci_t * ohci,unsigned int info,dma_addr_t data,int len,struct urb * urb,int index)1359 td_fill (ohci_t * ohci, unsigned int info,
1360 dma_addr_t data, int len,
1361 struct urb * urb, int index)
1362 {
1363 volatile td_t * td, * td_pt;
1364 urb_priv_t * urb_priv = urb->hcpriv;
1365
1366 if (index >= urb_priv->length) {
1367 err("internal OHCI error: TD index > length");
1368 return;
1369 }
1370
1371 /* use this td as the next dummy */
1372 td_pt = urb_priv->td [index];
1373 td_pt->hwNextTD = 0;
1374
1375 /* fill the old dummy TD */
1376 td = urb_priv->td [index] = dma_to_td (ohci,
1377 le32_to_cpup (&urb_priv->ed->hwTailP) & ~0xf);
1378
1379 td->ed = urb_priv->ed;
1380 td->next_dl_td = NULL;
1381 td->index = index;
1382 td->urb = urb;
1383 td->data_dma = data;
1384 if (!len)
1385 data = 0;
1386
1387 td->hwINFO = cpu_to_le32 (info);
1388 if ((td->ed->type) == PIPE_ISOCHRONOUS) {
1389 td->hwCBP = cpu_to_le32 (data & 0xFFFFF000);
1390 td->ed->last_iso = info & 0xffff;
1391 } else {
1392 td->hwCBP = cpu_to_le32 (data);
1393 }
1394 if (data)
1395 td->hwBE = cpu_to_le32 (data + len - 1);
1396 else
1397 td->hwBE = 0;
1398 td->hwNextTD = cpu_to_le32 (td_pt->td_dma);
1399 td->hwPSW [0] = cpu_to_le16 ((data & 0x0FFF) | 0xE000);
1400
1401 /* append to queue */
1402 wmb();
1403 td->ed->hwTailP = td->hwNextTD;
1404 }
1405
1406 /*-------------------------------------------------------------------------*/
1407
1408 /* prepare all TDs of a transfer */
1409
td_submit_urb(struct urb * urb)1410 static void td_submit_urb (struct urb * urb)
1411 {
1412 urb_priv_t * urb_priv = urb->hcpriv;
1413 ohci_t * ohci = (ohci_t *) urb->dev->bus->hcpriv;
1414 dma_addr_t data;
1415 int data_len = urb->transfer_buffer_length;
1416 int maxps = usb_maxpacket (urb->dev, urb->pipe, usb_pipeout (urb->pipe));
1417 int cnt = 0;
1418 __u32 info = 0;
1419 unsigned int toggle = 0;
1420
1421 /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
1422 if(usb_gettoggle(urb->dev, usb_pipeendpoint(urb->pipe), usb_pipeout(urb->pipe))) {
1423 toggle = TD_T_TOGGLE;
1424 } else {
1425 toggle = TD_T_DATA0;
1426 usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), usb_pipeout(urb->pipe), 1);
1427 }
1428
1429 urb_priv->td_cnt = 0;
1430
1431 if (data_len) {
1432 data = pci_map_single (ohci->ohci_dev,
1433 urb->transfer_buffer, data_len,
1434 usb_pipeout (urb->pipe)
1435 ? PCI_DMA_TODEVICE
1436 : PCI_DMA_FROMDEVICE
1437 );
1438 } else
1439 data = 0;
1440
1441 switch (usb_pipetype (urb->pipe)) {
1442 case PIPE_BULK:
1443 info = usb_pipeout (urb->pipe)?
1444 TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
1445 while(data_len > 4096) {
1446 td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, urb, cnt);
1447 data += 4096; data_len -= 4096; cnt++;
1448 }
1449 info = usb_pipeout (urb->pipe)?
1450 TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
1451 td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, urb, cnt);
1452 cnt++;
1453
1454 /* If the transfer size is multiple of the pipe mtu,
1455 * we may need an extra TD to create a empty frame
1456 * Note : another way to check this condition is
1457 * to test if(urb_priv->length > cnt) - Jean II */
1458 if ((urb->transfer_flags & USB_ZERO_PACKET) &&
1459 usb_pipeout (urb->pipe) &&
1460 (urb->transfer_buffer_length != 0) &&
1461 ((urb->transfer_buffer_length % maxps) == 0)) {
1462 td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), 0, 0, urb, cnt);
1463 cnt++;
1464 }
1465
1466 if (!ohci->sleeping) {
1467 wmb();
1468 writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
1469 (void)readl (&ohci->regs->intrdisable); /* PCI posting flush */
1470 }
1471 break;
1472
1473 case PIPE_INTERRUPT:
1474 info = usb_pipeout (urb->pipe)?
1475 TD_CC | TD_DP_OUT | toggle: TD_CC | TD_R | TD_DP_IN | toggle;
1476 td_fill (ohci, info, data, data_len, urb, cnt++);
1477 break;
1478
1479 case PIPE_CONTROL:
1480 info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
1481 td_fill (ohci, info,
1482 pci_map_single (ohci->ohci_dev,
1483 urb->setup_packet, 8,
1484 PCI_DMA_TODEVICE),
1485 8, urb, cnt++);
1486 if (data_len > 0) {
1487 info = usb_pipeout (urb->pipe)?
1488 TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
1489 /* NOTE: mishandles transfers >8K, some >4K */
1490 td_fill (ohci, info, data, data_len, urb, cnt++);
1491 }
1492 info = usb_pipeout (urb->pipe)?
1493 TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1;
1494 td_fill (ohci, info, data, 0, urb, cnt++);
1495 if (!ohci->sleeping) {
1496 wmb();
1497 writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
1498 (void)readl (&ohci->regs->intrdisable); /* PCI posting flush */
1499 }
1500 break;
1501
1502 case PIPE_ISOCHRONOUS:
1503 for (cnt = 0; cnt < urb->number_of_packets; cnt++) {
1504 td_fill (ohci, TD_CC|TD_ISO | ((urb->start_frame + cnt) & 0xffff),
1505 data + urb->iso_frame_desc[cnt].offset,
1506 urb->iso_frame_desc[cnt].length, urb, cnt);
1507 }
1508 break;
1509 }
1510 if (urb_priv->length != cnt)
1511 dbg("TD LENGTH %d != CNT %d", urb_priv->length, cnt);
1512 }
1513
1514 /*-------------------------------------------------------------------------*
1515 * Done List handling functions
1516 *-------------------------------------------------------------------------*/
1517
1518
1519 /* calculate the transfer length and update the urb */
1520
dl_transfer_length(td_t * td)1521 static void dl_transfer_length(td_t * td)
1522 {
1523 __u32 tdINFO, tdBE, tdCBP;
1524 __u16 tdPSW;
1525 struct urb * urb = td->urb;
1526 urb_priv_t * urb_priv = urb->hcpriv;
1527 int dlen = 0;
1528 int cc = 0;
1529
1530 tdINFO = le32_to_cpup (&td->hwINFO);
1531 tdBE = le32_to_cpup (&td->hwBE);
1532 tdCBP = le32_to_cpup (&td->hwCBP);
1533
1534
1535 if (tdINFO & TD_ISO) {
1536 tdPSW = le16_to_cpu (td->hwPSW[0]);
1537 cc = (tdPSW >> 12) & 0xF;
1538 if (cc < 0xE) {
1539 if (usb_pipeout(urb->pipe)) {
1540 dlen = urb->iso_frame_desc[td->index].length;
1541 } else {
1542 dlen = tdPSW & 0x3ff;
1543 }
1544 urb->actual_length += dlen;
1545 urb->iso_frame_desc[td->index].actual_length = dlen;
1546 if (!(urb->transfer_flags & USB_DISABLE_SPD) && (cc == TD_DATAUNDERRUN))
1547 cc = TD_CC_NOERROR;
1548
1549 urb->iso_frame_desc[td->index].status = cc_to_error[cc];
1550 }
1551 } else { /* BULK, INT, CONTROL DATA */
1552 if (!(usb_pipetype (urb->pipe) == PIPE_CONTROL &&
1553 ((td->index == 0) || (td->index == urb_priv->length - 1)))) {
1554 if (tdBE != 0) {
1555 if (td->hwCBP == 0)
1556 urb->actual_length += tdBE - td->data_dma + 1;
1557 else
1558 urb->actual_length += tdCBP - td->data_dma;
1559 }
1560 }
1561 }
1562 }
1563
1564 /* handle an urb that is being unlinked */
1565
dl_del_urb(ohci_t * ohci,struct urb * urb)1566 static void dl_del_urb (ohci_t *ohci, struct urb * urb)
1567 {
1568 wait_queue_head_t * wait_head = ((urb_priv_t *)(urb->hcpriv))->wait;
1569
1570 urb_rm_priv_locked (urb);
1571
1572 if (urb->transfer_flags & USB_ASYNC_UNLINK) {
1573 urb->status = -ECONNRESET;
1574 ohci_complete_add(ohci, urb);
1575 } else {
1576 urb->status = -ENOENT;
1577
1578 /* unblock sohci_unlink_urb */
1579 if (wait_head)
1580 wake_up (wait_head);
1581 }
1582 }
1583
1584 /*-------------------------------------------------------------------------*/
1585
1586 /* replies to the request have to be on a FIFO basis so
1587 * we reverse the reversed done-list */
1588
dl_reverse_done_list(ohci_t * ohci)1589 static td_t * dl_reverse_done_list (ohci_t * ohci)
1590 {
1591 __u32 td_list_hc;
1592 td_t * td_rev = NULL;
1593 td_t * td_list = NULL;
1594 urb_priv_t * urb_priv = NULL;
1595
1596 td_list_hc = le32_to_cpup (&ohci->hcca->done_head) & 0xfffffff0;
1597 ohci->hcca->done_head = 0;
1598
1599 while (td_list_hc) {
1600 td_list = dma_to_td (ohci, td_list_hc);
1601
1602 if (TD_CC_GET (le32_to_cpup (&td_list->hwINFO))) {
1603 urb_priv = (urb_priv_t *) td_list->urb->hcpriv;
1604 dbg(" USB-error/status: %x : %p",
1605 TD_CC_GET (le32_to_cpup (&td_list->hwINFO)), td_list);
1606 if (td_list->ed->hwHeadP & cpu_to_le32 (0x1)) {
1607 if (urb_priv && ((td_list->index + 1) < urb_priv->length)) {
1608 td_list->ed->hwHeadP =
1609 (urb_priv->td[urb_priv->length - 1]->hwNextTD & cpu_to_le32 (0xfffffff0)) |
1610 (td_list->ed->hwHeadP & cpu_to_le32 (0x2));
1611 urb_priv->td_cnt += urb_priv->length - td_list->index - 1;
1612 } else
1613 td_list->ed->hwHeadP &= cpu_to_le32 (0xfffffff2);
1614 }
1615 }
1616
1617 td_list->next_dl_td = td_rev;
1618 td_rev = td_list;
1619 td_list_hc = le32_to_cpup (&td_list->hwNextTD) & 0xfffffff0;
1620 }
1621 return td_list;
1622 }
1623
1624 /*-------------------------------------------------------------------------*/
1625
1626 /* there are some pending requests to remove
1627 * - some of the eds (if ed->state & ED_DEL (set by sohci_free_dev)
1628 * - some URBs/TDs if urb_priv->state == URB_DEL */
1629
dl_del_list(ohci_t * ohci,unsigned int frame)1630 static void dl_del_list (ohci_t * ohci, unsigned int frame)
1631 {
1632 ed_t * ed;
1633 __u32 edINFO;
1634 __u32 tdINFO;
1635 td_t * td = NULL, * td_next = NULL, * tdHeadP = NULL, * tdTailP;
1636 __u32 * td_p;
1637 int ctrl = 0, bulk = 0;
1638
1639 for (ed = ohci->ed_rm_list[frame]; ed != NULL; ed = ed->ed_rm_list) {
1640
1641 tdTailP = dma_to_td (ohci, le32_to_cpup (&ed->hwTailP) & 0xfffffff0);
1642 tdHeadP = dma_to_td (ohci, le32_to_cpup (&ed->hwHeadP) & 0xfffffff0);
1643 edINFO = le32_to_cpup (&ed->hwINFO);
1644 td_p = &ed->hwHeadP;
1645
1646 for (td = tdHeadP; td != tdTailP; td = td_next) {
1647 struct urb * urb = td->urb;
1648 urb_priv_t * urb_priv = td->urb->hcpriv;
1649
1650 td_next = dma_to_td (ohci, le32_to_cpup (&td->hwNextTD) & 0xfffffff0);
1651 if ((urb_priv->state == URB_DEL) || (ed->state & ED_DEL)) {
1652 tdINFO = le32_to_cpup (&td->hwINFO);
1653 if (TD_CC_GET (tdINFO) < 0xE)
1654 dl_transfer_length (td);
1655 *td_p = td->hwNextTD | (*td_p & cpu_to_le32 (0x3));
1656
1657 /* URB is done; clean up */
1658 if (++(urb_priv->td_cnt) == urb_priv->length)
1659 dl_del_urb (ohci, urb);
1660 } else {
1661 td_p = &td->hwNextTD;
1662 }
1663 }
1664
1665 if (ed->state & ED_DEL) { /* set by sohci_free_dev */
1666 struct ohci_device * dev = usb_to_ohci (ohci->dev[edINFO & 0x7F]);
1667 td_free (ohci, tdTailP); /* free dummy td */
1668 ed->hwINFO = cpu_to_le32 (OHCI_ED_SKIP);
1669 ed->state = ED_NEW;
1670 hash_free_ed(ohci, ed);
1671 /* if all eds are removed wake up sohci_free_dev */
1672 if (!--dev->ed_cnt)
1673 wake_up(&dev->wait);
1674 } else {
1675 ed->state &= ~ED_URB_DEL;
1676 tdHeadP = dma_to_td (ohci, le32_to_cpup (&ed->hwHeadP) & 0xfffffff0);
1677
1678 if (tdHeadP == tdTailP) {
1679 if (ed->state == ED_OPER)
1680 ep_unlink(ohci, ed);
1681 } else
1682 ed->hwINFO &= ~cpu_to_le32 (OHCI_ED_SKIP);
1683 }
1684
1685 switch (ed->type) {
1686 case PIPE_CONTROL:
1687 ctrl = 1;
1688 break;
1689 case PIPE_BULK:
1690 bulk = 1;
1691 break;
1692 }
1693 }
1694
1695 /* maybe reenable control and bulk lists */
1696 if (!ohci->disabled) {
1697 if (ctrl) /* reset control list */
1698 writel (0, &ohci->regs->ed_controlcurrent);
1699 if (bulk) /* reset bulk list */
1700 writel (0, &ohci->regs->ed_bulkcurrent);
1701 if (!ohci->ed_rm_list[!frame] && !ohci->sleeping) {
1702 if (ohci->ed_controltail)
1703 ohci->hc_control |= OHCI_CTRL_CLE;
1704 if (ohci->ed_bulktail)
1705 ohci->hc_control |= OHCI_CTRL_BLE;
1706 writel (ohci->hc_control, &ohci->regs->control);
1707 }
1708 }
1709
1710 ohci->ed_rm_list[frame] = NULL;
1711 }
1712
1713
1714
1715 /*-------------------------------------------------------------------------*/
1716
1717 /* td done list */
1718
dl_done_list(ohci_t * ohci,td_t * td_list)1719 static void dl_done_list (ohci_t * ohci, td_t * td_list)
1720 {
1721 td_t * td_list_next = NULL;
1722 ed_t * ed;
1723 int cc = 0;
1724 struct urb * urb;
1725 urb_priv_t * urb_priv;
1726 __u32 tdINFO, edHeadP, edTailP;
1727
1728 while (td_list) {
1729 td_list_next = td_list->next_dl_td;
1730
1731 urb = td_list->urb;
1732 urb_priv = urb->hcpriv;
1733 tdINFO = le32_to_cpup (&td_list->hwINFO);
1734
1735 ed = td_list->ed;
1736
1737 dl_transfer_length(td_list);
1738
1739 /* error code of transfer */
1740 cc = TD_CC_GET (tdINFO);
1741 if (cc == TD_CC_STALL)
1742 usb_endpoint_halt(urb->dev,
1743 usb_pipeendpoint(urb->pipe),
1744 usb_pipeout(urb->pipe));
1745
1746 if (!(urb->transfer_flags & USB_DISABLE_SPD)
1747 && (cc == TD_DATAUNDERRUN))
1748 cc = TD_CC_NOERROR;
1749
1750 if (++(urb_priv->td_cnt) == urb_priv->length) {
1751 if ((ed->state & (ED_OPER | ED_UNLINK))
1752 && (urb_priv->state != URB_DEL)) {
1753 urb->status = cc_to_error[cc];
1754 sohci_return_urb (ohci, urb);
1755 } else {
1756 dl_del_urb (ohci, urb);
1757 }
1758 }
1759
1760 if (ed->state != ED_NEW) {
1761 edHeadP = le32_to_cpup (&ed->hwHeadP) & 0xfffffff0;
1762 edTailP = le32_to_cpup (&ed->hwTailP);
1763
1764 /* unlink eds if they are not busy */
1765 if ((edHeadP == edTailP) && (ed->state == ED_OPER))
1766 ep_unlink (ohci, ed);
1767 }
1768
1769 td_list = td_list_next;
1770 }
1771 }
1772
1773
1774
1775
1776 /*-------------------------------------------------------------------------*
1777 * Virtual Root Hub
1778 *-------------------------------------------------------------------------*/
1779
1780 /* Device descriptor */
1781 static __u8 root_hub_dev_des[] =
1782 {
1783 0x12, /* __u8 bLength; */
1784 0x01, /* __u8 bDescriptorType; Device */
1785 0x10, /* __u16 bcdUSB; v1.1 */
1786 0x01,
1787 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
1788 0x00, /* __u8 bDeviceSubClass; */
1789 0x00, /* __u8 bDeviceProtocol; */
1790 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
1791 0x00, /* __u16 idVendor; */
1792 0x00,
1793 0x00, /* __u16 idProduct; */
1794 0x00,
1795 0x00, /* __u16 bcdDevice; */
1796 0x00,
1797 0x00, /* __u8 iManufacturer; */
1798 0x02, /* __u8 iProduct; */
1799 0x01, /* __u8 iSerialNumber; */
1800 0x01 /* __u8 bNumConfigurations; */
1801 };
1802
1803
1804 /* Configuration descriptor */
1805 static __u8 root_hub_config_des[] =
1806 {
1807 0x09, /* __u8 bLength; */
1808 0x02, /* __u8 bDescriptorType; Configuration */
1809 0x19, /* __u16 wTotalLength; */
1810 0x00,
1811 0x01, /* __u8 bNumInterfaces; */
1812 0x01, /* __u8 bConfigurationValue; */
1813 0x00, /* __u8 iConfiguration; */
1814 0x40, /* __u8 bmAttributes;
1815 Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
1816 0x00, /* __u8 MaxPower; */
1817
1818 /* interface */
1819 0x09, /* __u8 if_bLength; */
1820 0x04, /* __u8 if_bDescriptorType; Interface */
1821 0x00, /* __u8 if_bInterfaceNumber; */
1822 0x00, /* __u8 if_bAlternateSetting; */
1823 0x01, /* __u8 if_bNumEndpoints; */
1824 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
1825 0x00, /* __u8 if_bInterfaceSubClass; */
1826 0x00, /* __u8 if_bInterfaceProtocol; */
1827 0x00, /* __u8 if_iInterface; */
1828
1829 /* endpoint */
1830 0x07, /* __u8 ep_bLength; */
1831 0x05, /* __u8 ep_bDescriptorType; Endpoint */
1832 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
1833 0x03, /* __u8 ep_bmAttributes; Interrupt */
1834 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
1835 0x00,
1836 0xff /* __u8 ep_bInterval; 255 ms */
1837 };
1838
1839 /* Hub class-specific descriptor is constructed dynamically */
1840
1841
1842 /*-------------------------------------------------------------------------*/
1843
1844 /* prepare Interrupt pipe data; HUB INTERRUPT ENDPOINT */
1845
rh_send_irq(ohci_t * ohci,void * rh_data,int rh_len)1846 static int rh_send_irq (ohci_t * ohci, void * rh_data, int rh_len)
1847 {
1848 int num_ports;
1849 int i;
1850 int ret;
1851 int len;
1852
1853 __u8 data[8];
1854
1855 num_ports = roothub_a (ohci) & RH_A_NDP;
1856 if (num_ports > MAX_ROOT_PORTS) {
1857 err ("bogus NDP=%d for OHCI usb-%s", num_ports,
1858 ohci->ohci_dev->slot_name);
1859 err ("rereads as NDP=%d",
1860 readl (&ohci->regs->roothub.a) & RH_A_NDP);
1861 /* retry later; "should not happen" */
1862 return 0;
1863 }
1864 *(__u8 *) data = (roothub_status (ohci) & (RH_HS_LPSC | RH_HS_OCIC))
1865 ? 1: 0;
1866 ret = *(__u8 *) data;
1867
1868 for ( i = 0; i < num_ports; i++) {
1869 *(__u8 *) (data + (i + 1) / 8) |=
1870 ((roothub_portstatus (ohci, i) &
1871 (RH_PS_CSC | RH_PS_PESC | RH_PS_PSSC | RH_PS_OCIC | RH_PS_PRSC))
1872 ? 1: 0) << ((i + 1) % 8);
1873 ret += *(__u8 *) (data + (i + 1) / 8);
1874 }
1875 len = i/8 + 1;
1876
1877 if (ret > 0) {
1878 memcpy(rh_data, data,
1879 min_t(unsigned int, len,
1880 min_t(unsigned int, rh_len, sizeof(data))));
1881 return len;
1882 }
1883 return 0;
1884 }
1885
1886 /*-------------------------------------------------------------------------*/
1887
1888 /* Virtual Root Hub INTs are polled by this timer every "interval" ms */
1889
rh_int_timer_do(unsigned long ptr)1890 static void rh_int_timer_do (unsigned long ptr)
1891 {
1892 int len;
1893
1894 struct urb * urb = (struct urb *) ptr;
1895 ohci_t * ohci = urb->dev->bus->hcpriv;
1896
1897 if (ohci->disabled)
1898 return;
1899
1900 /* ignore timers firing during PM suspend, etc */
1901 if ((ohci->hc_control & OHCI_CTRL_HCFS) != OHCI_USB_OPER)
1902 goto out;
1903
1904 if(ohci->rh.send) {
1905 len = rh_send_irq (ohci, urb->transfer_buffer, urb->transfer_buffer_length);
1906 if (len > 0) {
1907 urb->actual_length = len;
1908 #ifdef DEBUG
1909 urb_print (urb, "RET-t(rh)", usb_pipeout (urb->pipe));
1910 #endif
1911 if (urb->complete)
1912 urb->complete (urb);
1913 }
1914 }
1915 out:
1916 rh_init_int_timer (urb);
1917 }
1918
1919 /*-------------------------------------------------------------------------*/
1920
1921 /* Root Hub INTs are polled by this timer */
1922
rh_init_int_timer(struct urb * urb)1923 static int rh_init_int_timer (struct urb * urb)
1924 {
1925 ohci_t * ohci = urb->dev->bus->hcpriv;
1926
1927 ohci->rh.interval = urb->interval;
1928 init_timer (&ohci->rh.rh_int_timer);
1929 ohci->rh.rh_int_timer.function = rh_int_timer_do;
1930 ohci->rh.rh_int_timer.data = (unsigned long) urb;
1931 ohci->rh.rh_int_timer.expires =
1932 jiffies + (HZ * (urb->interval < 30? 30: urb->interval)) / 1000;
1933 add_timer (&ohci->rh.rh_int_timer);
1934
1935 return 0;
1936 }
1937
1938 /*-------------------------------------------------------------------------*/
1939
1940 #define OK(x) len = (x); break
1941 #define WR_RH_STAT(x) writel((x), &ohci->regs->roothub.status)
1942 #define WR_RH_PORTSTAT(x) writel((x), &ohci->regs->roothub.portstatus[wIndex-1])
1943 #define RD_RH_STAT roothub_status(ohci)
1944 #define RD_RH_PORTSTAT roothub_portstatus(ohci,wIndex-1)
1945
1946 /* request to virtual root hub */
1947
rh_submit_urb(struct urb * urb)1948 static int rh_submit_urb (struct urb * urb)
1949 {
1950 struct usb_device * usb_dev = urb->dev;
1951 ohci_t * ohci = usb_dev->bus->hcpriv;
1952 unsigned int pipe = urb->pipe;
1953 struct usb_ctrlrequest * cmd = (struct usb_ctrlrequest *) urb->setup_packet;
1954 void * data = urb->transfer_buffer;
1955 int leni = urb->transfer_buffer_length;
1956 int len = 0;
1957 int status = TD_CC_NOERROR;
1958 unsigned long flags;
1959
1960 __u32 datab[4];
1961 __u8 * data_buf = (__u8 *) datab;
1962
1963 __u16 bmRType_bReq;
1964 __u16 wValue;
1965 __u16 wIndex;
1966 __u16 wLength;
1967
1968 spin_lock_irqsave(&ohci->ohci_lock, flags);
1969
1970 if (usb_pipeint(pipe)) {
1971 ohci->rh.urb = urb;
1972 ohci->rh.send = 1;
1973 ohci->rh.interval = urb->interval;
1974 rh_init_int_timer(urb);
1975 urb->status = cc_to_error [TD_CC_NOERROR];
1976
1977 spin_unlock_irqrestore(&ohci->ohci_lock, flags);
1978 return 0;
1979 }
1980
1981 bmRType_bReq = cmd->bRequestType | (cmd->bRequest << 8);
1982 wValue = le16_to_cpu (cmd->wValue);
1983 wIndex = le16_to_cpu (cmd->wIndex);
1984 wLength = le16_to_cpu (cmd->wLength);
1985
1986 switch (bmRType_bReq) {
1987 /* Request Destination:
1988 without flags: Device,
1989 RH_INTERFACE: interface,
1990 RH_ENDPOINT: endpoint,
1991 RH_CLASS means HUB here,
1992 RH_OTHER | RH_CLASS almost ever means HUB_PORT here
1993 */
1994
1995 case RH_GET_STATUS:
1996 *(__u16 *) data_buf = cpu_to_le16 (1); OK (2);
1997 case RH_GET_STATUS | RH_INTERFACE:
1998 *(__u16 *) data_buf = cpu_to_le16 (0); OK (2);
1999 case RH_GET_STATUS | RH_ENDPOINT:
2000 *(__u16 *) data_buf = cpu_to_le16 (0); OK (2);
2001 case RH_GET_STATUS | RH_CLASS:
2002 *(__u32 *) data_buf = cpu_to_le32 (
2003 RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
2004 OK (4);
2005 case RH_GET_STATUS | RH_OTHER | RH_CLASS:
2006 *(__u32 *) data_buf = cpu_to_le32 (RD_RH_PORTSTAT); OK (4);
2007
2008 case RH_CLEAR_FEATURE | RH_ENDPOINT:
2009 switch (wValue) {
2010 case (RH_ENDPOINT_STALL): OK (0);
2011 }
2012 break;
2013
2014 case RH_CLEAR_FEATURE | RH_CLASS:
2015 switch (wValue) {
2016 case RH_C_HUB_LOCAL_POWER:
2017 OK(0);
2018 case (RH_C_HUB_OVER_CURRENT):
2019 WR_RH_STAT(RH_HS_OCIC); OK (0);
2020 }
2021 break;
2022
2023 case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
2024 switch (wValue) {
2025 case (RH_PORT_ENABLE):
2026 WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);
2027 case (RH_PORT_SUSPEND):
2028 WR_RH_PORTSTAT (RH_PS_POCI); OK (0);
2029 case (RH_PORT_POWER):
2030 WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);
2031 case (RH_C_PORT_CONNECTION):
2032 WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);
2033 case (RH_C_PORT_ENABLE):
2034 WR_RH_PORTSTAT (RH_PS_PESC); OK (0);
2035 case (RH_C_PORT_SUSPEND):
2036 WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);
2037 case (RH_C_PORT_OVER_CURRENT):
2038 WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);
2039 case (RH_C_PORT_RESET):
2040 WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);
2041 }
2042 break;
2043
2044 case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
2045 switch (wValue) {
2046 case (RH_PORT_SUSPEND):
2047 WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);
2048 case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
2049 if (RD_RH_PORTSTAT & RH_PS_CCS)
2050 WR_RH_PORTSTAT (RH_PS_PRS);
2051 OK (0);
2052 case (RH_PORT_POWER):
2053 WR_RH_PORTSTAT (RH_PS_PPS ); OK (0);
2054 case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
2055 if (RD_RH_PORTSTAT & RH_PS_CCS)
2056 WR_RH_PORTSTAT (RH_PS_PES );
2057 OK (0);
2058 }
2059 break;
2060
2061 case RH_SET_ADDRESS: ohci->rh.devnum = wValue; OK(0);
2062
2063 case RH_GET_DESCRIPTOR:
2064 switch ((wValue & 0xff00) >> 8) {
2065 case (0x01): /* device descriptor */
2066 len = min_t(unsigned int,
2067 leni,
2068 min_t(unsigned int,
2069 sizeof (root_hub_dev_des),
2070 wLength));
2071 data_buf = root_hub_dev_des; OK(len);
2072 case (0x02): /* configuration descriptor */
2073 len = min_t(unsigned int,
2074 leni,
2075 min_t(unsigned int,
2076 sizeof (root_hub_config_des),
2077 wLength));
2078 data_buf = root_hub_config_des; OK(len);
2079 case (0x03): /* string descriptors */
2080 len = usb_root_hub_string (wValue & 0xff,
2081 (int)(long) ohci->regs, "OHCI",
2082 data, wLength);
2083 if (len > 0) {
2084 data_buf = data;
2085 OK(min_t(int, leni, len));
2086 }
2087 // else fallthrough
2088 default:
2089 status = TD_CC_STALL;
2090 }
2091 break;
2092
2093 case RH_GET_DESCRIPTOR | RH_CLASS:
2094 {
2095 __u32 temp = roothub_a (ohci);
2096
2097 data_buf [0] = 9; // min length;
2098 data_buf [1] = 0x29;
2099 data_buf [2] = temp & RH_A_NDP;
2100 data_buf [3] = 0;
2101 if (temp & RH_A_PSM) /* per-port power switching? */
2102 data_buf [3] |= 0x1;
2103 if (temp & RH_A_NOCP) /* no overcurrent reporting? */
2104 data_buf [3] |= 0x10;
2105 else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */
2106 data_buf [3] |= 0x8;
2107
2108 datab [1] = 0;
2109 data_buf [5] = (temp & RH_A_POTPGT) >> 24;
2110 temp = roothub_b (ohci);
2111 data_buf [7] = temp & RH_B_DR;
2112 if (data_buf [2] < 7) {
2113 data_buf [8] = 0xff;
2114 } else {
2115 data_buf [0] += 2;
2116 data_buf [8] = (temp & RH_B_DR) >> 8;
2117 data_buf [10] = data_buf [9] = 0xff;
2118 }
2119
2120 len = min_t(unsigned int, leni,
2121 min_t(unsigned int, data_buf [0], wLength));
2122 OK (len);
2123 }
2124
2125 case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1);
2126
2127 case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0);
2128
2129 default:
2130 dbg ("unsupported root hub command");
2131 status = TD_CC_STALL;
2132 }
2133
2134 #ifdef DEBUG
2135 // ohci_dump_roothub (ohci, 0);
2136 #endif
2137
2138 len = min_t(int, len, leni);
2139 if (data != data_buf)
2140 memcpy (data, data_buf, len);
2141 urb->actual_length = len;
2142 urb->status = cc_to_error [status];
2143
2144 #ifdef DEBUG
2145 urb_print (urb, "RET(rh)", usb_pipeout (urb->pipe));
2146 #endif
2147
2148 urb->hcpriv = NULL;
2149 spin_unlock_irqrestore(&ohci->ohci_lock, flags);
2150 usb_dec_dev_use (usb_dev);
2151 urb->dev = NULL;
2152 if (urb->complete)
2153 urb->complete (urb);
2154 return 0;
2155 }
2156
2157 /*-------------------------------------------------------------------------*/
2158
rh_unlink_urb(struct urb * urb)2159 static int rh_unlink_urb (struct urb * urb)
2160 {
2161 ohci_t * ohci = urb->dev->bus->hcpriv;
2162 unsigned long flags;
2163
2164 spin_lock_irqsave(&ohci->ohci_lock, flags);
2165 if (ohci->rh.urb == urb) {
2166 ohci->rh.send = 0;
2167 del_timer (&ohci->rh.rh_int_timer);
2168 ohci->rh.urb = NULL;
2169
2170 urb->hcpriv = NULL;
2171 spin_unlock_irqrestore(&ohci->ohci_lock, flags);
2172 usb_dec_dev_use(urb->dev);
2173 urb->dev = NULL;
2174 if (urb->transfer_flags & USB_ASYNC_UNLINK) {
2175 urb->status = -ECONNRESET;
2176 if (urb->complete)
2177 urb->complete (urb);
2178 } else
2179 urb->status = -ENOENT;
2180 } else {
2181 spin_unlock_irqrestore(&ohci->ohci_lock, flags);
2182 }
2183 return 0;
2184 }
2185
2186 /*-------------------------------------------------------------------------*
2187 * HC functions
2188 *-------------------------------------------------------------------------*/
2189
2190 /* reset the HC and BUS */
2191
hc_reset(ohci_t * ohci)2192 static int hc_reset (ohci_t * ohci)
2193 {
2194 int timeout = 30;
2195 int smm_timeout = 50; /* 0,5 sec */
2196
2197 #ifndef __hppa__
2198 /* PA-RISC doesn't have SMM, but PDC might leave IR set */
2199 if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
2200 writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
2201 dbg("USB HC TakeOver from SMM");
2202 while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
2203 wait_ms (10);
2204 if (--smm_timeout == 0) {
2205 err("USB HC TakeOver failed!");
2206 return -1;
2207 }
2208 }
2209 }
2210 #endif
2211
2212 /* Disable HC interrupts */
2213 writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
2214
2215 dbg("USB HC reset_hc usb-%s: ctrl = 0x%x ;",
2216 ohci->ohci_dev->slot_name,
2217 readl (&ohci->regs->control));
2218
2219 /* Reset USB (needed by some controllers) */
2220 writel (0, &ohci->regs->control);
2221
2222 /* Force a state change from USBRESET to USBOPERATIONAL for ALi */
2223 (void) readl (&ohci->regs->control); /* PCI posting */
2224 writel (ohci->hc_control = OHCI_USB_OPER, &ohci->regs->control);
2225
2226 /* HC Reset requires max 10 ms delay */
2227 writel (OHCI_HCR, &ohci->regs->cmdstatus);
2228 while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
2229 if (--timeout == 0) {
2230 err("USB HC reset timed out!");
2231 return -1;
2232 }
2233 udelay (1);
2234 }
2235 return 0;
2236 }
2237
2238 /*-------------------------------------------------------------------------*/
2239
2240 /* Start an OHCI controller, set the BUS operational
2241 * enable interrupts
2242 * connect the virtual root hub */
2243
hc_start(ohci_t * ohci)2244 static int hc_start (ohci_t * ohci)
2245 {
2246 __u32 mask;
2247 unsigned int fminterval;
2248 struct usb_device * usb_dev;
2249 struct ohci_device * dev;
2250
2251 ohci->disabled = 1;
2252
2253 /* Tell the controller where the control and bulk lists are
2254 * The lists are empty now. */
2255
2256 writel (0, &ohci->regs->ed_controlhead);
2257 writel (0, &ohci->regs->ed_bulkhead);
2258
2259 writel (ohci->hcca_dma, &ohci->regs->hcca); /* a reset clears this */
2260
2261 fminterval = 0x2edf;
2262 writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
2263 fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
2264 writel (fminterval, &ohci->regs->fminterval);
2265 writel (0x628, &ohci->regs->lsthresh);
2266
2267 /* start controller operations */
2268 ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
2269 ohci->disabled = 0;
2270 writel (ohci->hc_control, &ohci->regs->control);
2271
2272 /* Choose the interrupts we care about now, others later on demand */
2273 mask = OHCI_INTR_MIE | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
2274 writel (mask, &ohci->regs->intrenable);
2275 writel (mask, &ohci->regs->intrstatus);
2276
2277 #ifdef OHCI_USE_NPS
2278 if(ohci->flags & OHCI_QUIRK_SUCKYIO)
2279 {
2280 /* NSC 87560 at least requires different setup .. */
2281 writel ((roothub_a (ohci) | RH_A_NOCP) &
2282 ~(RH_A_OCPM | RH_A_POTPGT | RH_A_PSM | RH_A_NPS),
2283 &ohci->regs->roothub.a);
2284 }
2285 else
2286 {
2287 /* required for AMD-756 and some Mac platforms */
2288 writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM,
2289 &ohci->regs->roothub.a);
2290 }
2291 writel (RH_HS_LPSC, &ohci->regs->roothub.status);
2292 #endif /* OHCI_USE_NPS */
2293
2294 (void)readl (&ohci->regs->intrdisable); /* PCI posting flush */
2295
2296 // POTPGT delay is bits 24-31, in 2 ms units.
2297 mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
2298
2299 /* connect the virtual root hub */
2300 ohci->rh.devnum = 0;
2301 usb_dev = usb_alloc_dev (NULL, ohci->bus);
2302 if (!usb_dev) {
2303 ohci->disabled = 1;
2304 return -ENOMEM;
2305 }
2306
2307 dev = usb_to_ohci (usb_dev);
2308 ohci->bus->root_hub = usb_dev;
2309 usb_connect (usb_dev);
2310 if (usb_new_device (usb_dev) != 0) {
2311 usb_free_dev (usb_dev);
2312 ohci->disabled = 1;
2313 return -ENODEV;
2314 }
2315
2316 return 0;
2317 }
2318
2319 /*-------------------------------------------------------------------------*/
2320
2321 /* called only from interrupt handler */
2322
check_timeouts(struct ohci * ohci)2323 static void check_timeouts (struct ohci *ohci)
2324 {
2325 spin_lock (&ohci->ohci_lock);
2326 while (!list_empty (&ohci->timeout_list)) {
2327 struct urb *urb;
2328
2329 urb = list_entry (ohci->timeout_list.next, struct urb, urb_list);
2330 if (time_after (jiffies, urb->timeout))
2331 break;
2332
2333 list_del_init (&urb->urb_list);
2334 if (urb->status != -EINPROGRESS)
2335 continue;
2336
2337 urb->transfer_flags |= USB_TIMEOUT_KILLED | USB_ASYNC_UNLINK;
2338 spin_unlock (&ohci->ohci_lock);
2339
2340 // outside the interrupt handler (in a timer...)
2341 // this reference would race interrupts
2342 sohci_unlink_urb (urb);
2343
2344 spin_lock (&ohci->ohci_lock);
2345 }
2346 spin_unlock (&ohci->ohci_lock);
2347 }
2348
2349
2350 /*-------------------------------------------------------------------------*/
2351
2352 /* an interrupt happens */
2353
hc_interrupt(int irq,void * __ohci,struct pt_regs * r)2354 static void hc_interrupt (int irq, void * __ohci, struct pt_regs * r)
2355 {
2356 ohci_t * ohci = __ohci;
2357 struct ohci_regs * regs = ohci->regs;
2358 int ints;
2359
2360 spin_lock (&ohci->ohci_lock);
2361
2362 /* avoid (slow) readl if only WDH happened */
2363 if ((ohci->hcca->done_head != 0)
2364 && !(le32_to_cpup (&ohci->hcca->done_head) & 0x01)) {
2365 ints = OHCI_INTR_WDH;
2366
2367 /* cardbus/... hardware gone before remove() */
2368 } else if ((ints = readl (®s->intrstatus)) == ~(u32)0) {
2369 ohci->disabled++;
2370 spin_unlock (&ohci->ohci_lock);
2371 err ("%s device removed!", ohci->ohci_dev->slot_name);
2372 return;
2373
2374 /* interrupt for some other device? */
2375 } else if ((ints &= readl (®s->intrenable)) == 0) {
2376 spin_unlock (&ohci->ohci_lock);
2377 return;
2378 }
2379
2380 // dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no));
2381
2382 if (ints & OHCI_INTR_UE) {
2383 ohci->disabled++;
2384 err ("OHCI Unrecoverable Error, controller usb-%s disabled",
2385 ohci->ohci_dev->slot_name);
2386 // e.g. due to PCI Master/Target Abort
2387
2388 #ifdef DEBUG
2389 ohci_dump (ohci, 1);
2390 #else
2391 // FIXME: be optimistic, hope that bug won't repeat often.
2392 // Make some non-interrupt context restart the controller.
2393 // Count and limit the retries though; either hardware or
2394 // software errors can go forever...
2395 #endif
2396 hc_reset (ohci);
2397 }
2398
2399 if (ints & OHCI_INTR_WDH) {
2400 writel (OHCI_INTR_WDH, ®s->intrdisable);
2401 (void)readl (®s->intrdisable); /* PCI posting flush */
2402 dl_done_list (ohci, dl_reverse_done_list (ohci));
2403 writel (OHCI_INTR_WDH, ®s->intrenable);
2404 (void)readl (®s->intrdisable); /* PCI posting flush */
2405 }
2406
2407 if (ints & OHCI_INTR_SO) {
2408 dbg("USB Schedule overrun");
2409 writel (OHCI_INTR_SO, ®s->intrenable);
2410 (void)readl (®s->intrdisable); /* PCI posting flush */
2411 }
2412
2413 // FIXME: this assumes SOF (1/ms) interrupts don't get lost...
2414 if (ints & OHCI_INTR_SF) {
2415 unsigned int frame = le16_to_cpu (ohci->hcca->frame_no) & 1;
2416 writel (OHCI_INTR_SF, ®s->intrdisable);
2417 (void)readl (®s->intrdisable); /* PCI posting flush */
2418 if (ohci->ed_rm_list[!frame] != NULL) {
2419 dl_del_list (ohci, !frame);
2420 }
2421 if (ohci->ed_rm_list[frame] != NULL) {
2422 writel (OHCI_INTR_SF, ®s->intrenable);
2423 (void)readl (®s->intrdisable); /* PCI posting flush */
2424 }
2425 }
2426
2427 /*
2428 * Finally, we are done with trashing about our hardware lists
2429 * and other CPUs are allowed in. The festive flipping of the lock
2430 * ensues as we struggle with the check_timeouts disaster.
2431 */
2432 spin_unlock (&ohci->ohci_lock);
2433
2434 if (!list_empty (&ohci->timeout_list)) {
2435 check_timeouts (ohci);
2436 // FIXME: enable SF as needed in a timer;
2437 // don't make lots of 1ms interrupts
2438 // On unloaded USB, think 4k ~= 4-5msec
2439 if (!list_empty (&ohci->timeout_list))
2440 writel (OHCI_INTR_SF, ®s->intrenable);
2441 }
2442
2443 writel (ints, ®s->intrstatus);
2444 writel (OHCI_INTR_MIE, ®s->intrenable);
2445 (void)readl (®s->intrdisable); /* PCI posting flush */
2446
2447 ohci_complete(ohci);
2448 }
2449
2450 /*-------------------------------------------------------------------------*/
2451
2452 /* allocate OHCI */
2453
hc_alloc_ohci(struct pci_dev * dev,void * mem_base)2454 static ohci_t * __devinit hc_alloc_ohci (struct pci_dev *dev, void * mem_base)
2455 {
2456 ohci_t * ohci;
2457
2458 ohci = (ohci_t *) kmalloc (sizeof *ohci, GFP_KERNEL);
2459 if (!ohci)
2460 return NULL;
2461
2462 memset (ohci, 0, sizeof (ohci_t));
2463
2464 ohci->hcca = pci_alloc_consistent (dev, sizeof *ohci->hcca,
2465 &ohci->hcca_dma);
2466 if (!ohci->hcca) {
2467 kfree (ohci);
2468 return NULL;
2469 }
2470 memset (ohci->hcca, 0, sizeof (struct ohci_hcca));
2471
2472 ohci->disabled = 1;
2473 ohci->sleeping = 0;
2474 ohci->irq = -1;
2475 ohci->regs = mem_base;
2476
2477 ohci->ohci_dev = dev;
2478 pci_set_drvdata(dev, ohci);
2479
2480 INIT_LIST_HEAD (&ohci->timeout_list);
2481 spin_lock_init(&ohci->ohci_lock);
2482
2483 ohci->bus = usb_alloc_bus (&sohci_device_operations);
2484 if (!ohci->bus) {
2485 pci_set_drvdata (dev, NULL);
2486 pci_free_consistent (ohci->ohci_dev, sizeof *ohci->hcca,
2487 ohci->hcca, ohci->hcca_dma);
2488 kfree (ohci);
2489 return NULL;
2490 }
2491 ohci->bus->bus_name = dev->slot_name;
2492 ohci->bus->hcpriv = (void *) ohci;
2493
2494 return ohci;
2495 }
2496
2497
2498 /*-------------------------------------------------------------------------*/
2499
2500 /* De-allocate all resources.. */
2501
hc_release_ohci(ohci_t * ohci)2502 static void hc_release_ohci (ohci_t * ohci)
2503 {
2504 dbg ("USB HC release ohci usb-%s", ohci->ohci_dev->slot_name);
2505
2506 /* disconnect all devices */
2507 if (ohci->bus->root_hub)
2508 usb_disconnect (&ohci->bus->root_hub);
2509
2510 if (!ohci->disabled)
2511 hc_reset (ohci);
2512
2513 if (ohci->irq >= 0) {
2514 free_irq (ohci->irq, ohci);
2515 ohci->irq = -1;
2516 }
2517 pci_set_drvdata(ohci->ohci_dev, NULL);
2518 if (ohci->bus) {
2519 if (ohci->bus->busnum != -1)
2520 usb_deregister_bus (ohci->bus);
2521
2522 usb_free_bus (ohci->bus);
2523 }
2524
2525 ohci_mem_cleanup (ohci);
2526
2527 /* unmap the IO address space */
2528 iounmap (ohci->regs);
2529
2530 pci_free_consistent (ohci->ohci_dev, sizeof *ohci->hcca,
2531 ohci->hcca, ohci->hcca_dma);
2532 kfree (ohci);
2533 }
2534
2535 /*-------------------------------------------------------------------------*/
2536
2537 /* Increment the module usage count, start the control thread and
2538 * return success. */
2539
2540 static struct pci_driver ohci_pci_driver;
2541
2542 static int __devinit
hc_found_ohci(struct pci_dev * dev,int irq,void * mem_base,const struct pci_device_id * id)2543 hc_found_ohci (struct pci_dev *dev, int irq,
2544 void *mem_base, const struct pci_device_id *id)
2545 {
2546 ohci_t * ohci;
2547 char buf[8], *bufp = buf;
2548 int ret;
2549
2550 #ifndef __sparc__
2551 sprintf(buf, "%d", irq);
2552 #else
2553 bufp = __irq_itoa(irq);
2554 #endif
2555 printk(KERN_INFO __FILE__ ": USB OHCI at membase 0x%lx, IRQ %s\n",
2556 (unsigned long) mem_base, bufp);
2557 printk(KERN_INFO __FILE__ ": usb-%s, %s\n", dev->slot_name, dev->name);
2558
2559 ohci = hc_alloc_ohci (dev, mem_base);
2560 if (!ohci) {
2561 return -ENOMEM;
2562 }
2563 if ((ret = ohci_mem_init (ohci)) < 0) {
2564 hc_release_ohci (ohci);
2565 return ret;
2566 }
2567 ohci->flags = id->driver_data;
2568
2569 /* Check for NSC87560. We have to look at the bridge (fn1) to identify
2570 the USB (fn2). This quirk might apply to more or even all NSC stuff
2571 I don't know.. */
2572
2573 if(dev->vendor == PCI_VENDOR_ID_NS)
2574 {
2575 struct pci_dev *fn1 = pci_find_slot(dev->bus->number, PCI_DEVFN(PCI_SLOT(dev->devfn), 1));
2576 if(fn1 && fn1->vendor == PCI_VENDOR_ID_NS && fn1->device == PCI_DEVICE_ID_NS_87560_LIO)
2577 ohci->flags |= OHCI_QUIRK_SUCKYIO;
2578
2579 }
2580
2581 if (ohci->flags & OHCI_QUIRK_SUCKYIO)
2582 printk (KERN_INFO __FILE__ ": Using NSC SuperIO setup\n");
2583 if (ohci->flags & OHCI_QUIRK_AMD756)
2584 printk (KERN_INFO __FILE__ ": AMD756 erratum 4 workaround\n");
2585
2586 if (hc_reset (ohci) < 0) {
2587 hc_release_ohci (ohci);
2588 return -ENODEV;
2589 }
2590
2591 /* FIXME this is a second HC reset; why?? */
2592 writel (ohci->hc_control = OHCI_USB_RESET, &ohci->regs->control);
2593 (void)readl (&ohci->regs->intrdisable); /* PCI posting flush */
2594 wait_ms (10);
2595
2596 usb_register_bus (ohci->bus);
2597
2598 if (request_irq (irq, hc_interrupt, SA_SHIRQ,
2599 ohci_pci_driver.name, ohci) != 0) {
2600 err ("request interrupt %s failed", bufp);
2601 hc_release_ohci (ohci);
2602 return -EBUSY;
2603 }
2604 ohci->irq = irq;
2605
2606 if (hc_start (ohci) < 0) {
2607 err ("can't start usb-%s", dev->slot_name);
2608 hc_release_ohci (ohci);
2609 return -EBUSY;
2610 }
2611
2612 #ifdef DEBUG
2613 ohci_dump (ohci, 1);
2614 #endif
2615 return 0;
2616 }
2617
2618 /*-------------------------------------------------------------------------*/
2619
2620 #ifdef CONFIG_PM
2621
2622 /* controller died; cleanup debris, then restart */
2623 /* must not be called from interrupt context */
2624
hc_restart(ohci_t * ohci)2625 static void hc_restart (ohci_t *ohci)
2626 {
2627 int temp;
2628 int i;
2629
2630 if (ohci->pci_latency)
2631 pci_write_config_byte (ohci->ohci_dev, PCI_LATENCY_TIMER, ohci->pci_latency);
2632
2633 ohci->disabled = 1;
2634 ohci->sleeping = 0;
2635 if (ohci->bus->root_hub)
2636 usb_disconnect (&ohci->bus->root_hub);
2637
2638 /* empty the interrupt branches */
2639 for (i = 0; i < NUM_INTS; i++) ohci->ohci_int_load[i] = 0;
2640 for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table[i] = 0;
2641
2642 /* no EDs to remove */
2643 ohci->ed_rm_list [0] = NULL;
2644 ohci->ed_rm_list [1] = NULL;
2645
2646 /* empty control and bulk lists */
2647 ohci->ed_isotail = NULL;
2648 ohci->ed_controltail = NULL;
2649 ohci->ed_bulktail = NULL;
2650
2651 if ((temp = hc_reset (ohci)) < 0 || (temp = hc_start (ohci)) < 0) {
2652 err ("can't restart usb-%s, %d", ohci->ohci_dev->slot_name, temp);
2653 } else
2654 dbg ("restart usb-%s completed", ohci->ohci_dev->slot_name);
2655 }
2656
2657 #endif /* CONFIG_PM */
2658
2659 /*-------------------------------------------------------------------------*/
2660
2661 /* configured so that an OHCI device is always provided */
2662 /* always called with process context; sleeping is OK */
2663
2664 static int __devinit
ohci_pci_probe(struct pci_dev * dev,const struct pci_device_id * id)2665 ohci_pci_probe (struct pci_dev *dev, const struct pci_device_id *id)
2666 {
2667 unsigned long mem_resource, mem_len;
2668 void *mem_base;
2669 int status;
2670
2671 if (pci_enable_device(dev) < 0)
2672 return -ENODEV;
2673
2674 if (!dev->irq) {
2675 err("found OHCI device with no IRQ assigned. check BIOS settings!");
2676 pci_disable_device (dev);
2677 return -ENODEV;
2678 }
2679
2680 /* we read its hardware registers as memory */
2681 mem_resource = pci_resource_start(dev, 0);
2682 mem_len = pci_resource_len(dev, 0);
2683 if (!request_mem_region (mem_resource, mem_len, ohci_pci_driver.name)) {
2684 dbg ("controller already in use");
2685 pci_disable_device (dev);
2686 return -EBUSY;
2687 }
2688
2689 mem_base = ioremap_nocache (mem_resource, mem_len);
2690 if (!mem_base) {
2691 err("Error mapping OHCI memory");
2692 release_mem_region (mem_resource, mem_len);
2693 pci_disable_device (dev);
2694 return -EFAULT;
2695 }
2696
2697 /* controller writes into our memory */
2698 pci_set_master (dev);
2699
2700 status = hc_found_ohci (dev, dev->irq, mem_base, id);
2701 if (status < 0) {
2702 iounmap (mem_base);
2703 release_mem_region (mem_resource, mem_len);
2704 pci_disable_device (dev);
2705 }
2706 return status;
2707 }
2708
2709 /*-------------------------------------------------------------------------*/
2710
2711 /* may be called from interrupt context [interface spec] */
2712 /* may be called without controller present */
2713 /* may be called with controller, bus, and devices active */
2714
2715 static void __devexit
ohci_pci_remove(struct pci_dev * dev)2716 ohci_pci_remove (struct pci_dev *dev)
2717 {
2718 ohci_t *ohci = pci_get_drvdata(dev);
2719
2720 dbg ("remove %s controller usb-%s%s%s",
2721 hcfs2string (ohci->hc_control & OHCI_CTRL_HCFS),
2722 dev->slot_name,
2723 ohci->disabled ? " (disabled)" : "",
2724 in_interrupt () ? " in interrupt" : ""
2725 );
2726 #ifdef DEBUG
2727 ohci_dump (ohci, 1);
2728 #endif
2729
2730 /* don't wake up sleeping controllers, or block in interrupt context */
2731 if ((ohci->hc_control & OHCI_CTRL_HCFS) != OHCI_USB_OPER || in_interrupt ()) {
2732 dbg ("controller being disabled");
2733 ohci->disabled = 1;
2734 }
2735
2736 /* on return, USB will always be reset (if present) */
2737 if (ohci->disabled)
2738 writel (ohci->hc_control = OHCI_USB_RESET,
2739 &ohci->regs->control);
2740
2741 hc_release_ohci (ohci);
2742
2743 release_mem_region (pci_resource_start (dev, 0), pci_resource_len (dev, 0));
2744 pci_disable_device (dev);
2745 }
2746
2747
2748 #ifdef CONFIG_PM
2749
2750 /*-------------------------------------------------------------------------*/
2751
2752 static int
ohci_pci_suspend(struct pci_dev * dev,u32 state)2753 ohci_pci_suspend (struct pci_dev *dev, u32 state)
2754 {
2755 ohci_t *ohci = pci_get_drvdata(dev);
2756 unsigned long flags;
2757 u16 cmd;
2758
2759 if ((ohci->hc_control & OHCI_CTRL_HCFS) != OHCI_USB_OPER) {
2760 dbg ("can't suspend usb-%s (state is %s)", dev->slot_name,
2761 hcfs2string (ohci->hc_control & OHCI_CTRL_HCFS));
2762 return -EIO;
2763 }
2764
2765 /* act as if usb suspend can always be used */
2766 info ("USB suspend: usb-%s", dev->slot_name);
2767 ohci->sleeping = 1;
2768
2769 /* First stop processing */
2770 spin_lock_irqsave (&ohci->ohci_lock, flags);
2771 ohci->hc_control &= ~(OHCI_CTRL_PLE|OHCI_CTRL_CLE|OHCI_CTRL_BLE|OHCI_CTRL_IE);
2772 writel (ohci->hc_control, &ohci->regs->control);
2773 writel (OHCI_INTR_SF, &ohci->regs->intrstatus);
2774 (void) readl (&ohci->regs->intrstatus);
2775 spin_unlock_irqrestore (&ohci->ohci_lock, flags);
2776
2777 /* Wait a frame or two */
2778 mdelay(1);
2779 if (!readl (&ohci->regs->intrstatus) & OHCI_INTR_SF)
2780 mdelay (1);
2781
2782 #ifdef CONFIG_PMAC_PBOOK
2783 if (_machine == _MACH_Pmac)
2784 disable_irq (ohci->irq);
2785 /* else, 2.4 assumes shared irqs -- don't disable */
2786 #endif
2787 /* Enable remote wakeup */
2788 writel (readl(&ohci->regs->intrenable) | OHCI_INTR_RD, &ohci->regs->intrenable);
2789
2790 /* Suspend chip and let things settle down a bit */
2791 ohci->hc_control = OHCI_USB_SUSPEND;
2792 writel (ohci->hc_control, &ohci->regs->control);
2793 (void) readl (&ohci->regs->control);
2794 mdelay (500); /* No schedule here ! */
2795 switch (readl (&ohci->regs->control) & OHCI_CTRL_HCFS) {
2796 case OHCI_USB_RESET:
2797 dbg("Bus in reset phase ???");
2798 break;
2799 case OHCI_USB_RESUME:
2800 dbg("Bus in resume phase ???");
2801 break;
2802 case OHCI_USB_OPER:
2803 dbg("Bus in operational phase ???");
2804 break;
2805 case OHCI_USB_SUSPEND:
2806 dbg("Bus suspended");
2807 break;
2808 }
2809 /* In some rare situations, Apple's OHCI have happily trashed
2810 * memory during sleep. We disable it's bus master bit during
2811 * suspend
2812 */
2813 pci_read_config_word (dev, PCI_COMMAND, &cmd);
2814 cmd &= ~PCI_COMMAND_MASTER;
2815 pci_write_config_word (dev, PCI_COMMAND, cmd);
2816 #ifdef CONFIG_PMAC_PBOOK
2817 {
2818 struct device_node *of_node;
2819
2820 /* Disable USB PAD & cell clock */
2821 of_node = pci_device_to_OF_node (ohci->ohci_dev);
2822 if (of_node)
2823 pmac_call_feature(PMAC_FTR_USB_ENABLE, of_node, 0, 0);
2824 }
2825 #endif
2826 return 0;
2827 }
2828
2829 /*-------------------------------------------------------------------------*/
2830
2831 static int
ohci_pci_resume(struct pci_dev * dev)2832 ohci_pci_resume (struct pci_dev *dev)
2833 {
2834 ohci_t *ohci = pci_get_drvdata(dev);
2835 int temp;
2836 unsigned long flags;
2837
2838 /* guard against multiple resumes */
2839 atomic_inc (&ohci->resume_count);
2840 if (atomic_read (&ohci->resume_count) != 1) {
2841 err ("concurrent PCI resumes for usb-%s", dev->slot_name);
2842 atomic_dec (&ohci->resume_count);
2843 return 0;
2844 }
2845
2846 #ifdef CONFIG_PMAC_PBOOK
2847 {
2848 struct device_node *of_node;
2849
2850 /* Re-enable USB PAD & cell clock */
2851 of_node = pci_device_to_OF_node (ohci->ohci_dev);
2852 if (of_node)
2853 pmac_call_feature(PMAC_FTR_USB_ENABLE, of_node, 0, 1);
2854 }
2855 #endif
2856
2857 /* did we suspend, or were we powered off? */
2858 ohci->hc_control = readl (&ohci->regs->control);
2859 temp = ohci->hc_control & OHCI_CTRL_HCFS;
2860
2861 #ifdef DEBUG
2862 /* the registers may look crazy here */
2863 ohci_dump_status (ohci);
2864 #endif
2865
2866 /* Re-enable bus mastering */
2867 pci_set_master(ohci->ohci_dev);
2868
2869 switch (temp) {
2870
2871 case OHCI_USB_RESET: // lost power
2872 info ("USB restart: usb-%s", dev->slot_name);
2873 hc_restart (ohci);
2874 break;
2875
2876 case OHCI_USB_SUSPEND: // host wakeup
2877 case OHCI_USB_RESUME: // remote wakeup
2878 info ("USB continue: usb-%s from %s wakeup", dev->slot_name,
2879 (temp == OHCI_USB_SUSPEND)
2880 ? "host" : "remote");
2881 ohci->hc_control = OHCI_USB_RESUME;
2882 writel (ohci->hc_control, &ohci->regs->control);
2883 (void) readl (&ohci->regs->control);
2884 mdelay (20); /* no schedule here ! */
2885 /* Some controllers (lucent) need a longer delay here */
2886 mdelay (15);
2887 temp = readl (&ohci->regs->control);
2888 temp = ohci->hc_control & OHCI_CTRL_HCFS;
2889 if (temp != OHCI_USB_RESUME) {
2890 err ("controller usb-%s won't resume", dev->slot_name);
2891 ohci->disabled = 1;
2892 return -EIO;
2893 }
2894
2895 /* Some chips likes being resumed first */
2896 writel (OHCI_USB_OPER, &ohci->regs->control);
2897 (void) readl (&ohci->regs->control);
2898 mdelay (3);
2899
2900 /* Then re-enable operations */
2901 spin_lock_irqsave (&ohci->ohci_lock, flags);
2902 ohci->disabled = 0;
2903 ohci->sleeping = 0;
2904 ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
2905 if (!ohci->ed_rm_list[0] && !ohci->ed_rm_list[1]) {
2906 if (ohci->ed_controltail)
2907 ohci->hc_control |= OHCI_CTRL_CLE;
2908 if (ohci->ed_bulktail)
2909 ohci->hc_control |= OHCI_CTRL_BLE;
2910 }
2911 writel (ohci->hc_control, &ohci->regs->control);
2912 writel (OHCI_INTR_SF, &ohci->regs->intrstatus);
2913 writel (OHCI_INTR_SF, &ohci->regs->intrenable);
2914 /* Check for a pending done list */
2915 writel (OHCI_INTR_WDH, &ohci->regs->intrdisable);
2916 (void) readl (&ohci->regs->intrdisable);
2917 #ifdef CONFIG_PMAC_PBOOK
2918 if (_machine == _MACH_Pmac)
2919 enable_irq (ohci->irq);
2920 #endif
2921 if (ohci->hcca->done_head)
2922 dl_done_list (ohci, dl_reverse_done_list (ohci));
2923 writel (OHCI_INTR_WDH, &ohci->regs->intrenable);
2924 writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
2925 writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
2926 spin_unlock_irqrestore (&ohci->ohci_lock, flags);
2927 break;
2928
2929 default:
2930 warn ("odd PCI resume for usb-%s", dev->slot_name);
2931 }
2932
2933 /* controller is operational, extra resumes are harmless */
2934 atomic_dec (&ohci->resume_count);
2935
2936 return 0;
2937 }
2938
2939 #endif /* CONFIG_PM */
2940
2941
2942 /*-------------------------------------------------------------------------*/
2943
2944 static const struct pci_device_id __devinitdata ohci_pci_ids [] = { {
2945
2946 /*
2947 * AMD-756 [Viper] USB has a serious erratum when used with
2948 * lowspeed devices like mice.
2949 */
2950 vendor: 0x1022,
2951 device: 0x740c,
2952 subvendor: PCI_ANY_ID,
2953 subdevice: PCI_ANY_ID,
2954
2955 driver_data: OHCI_QUIRK_AMD756,
2956
2957 } , {
2958
2959 /* handle any USB OHCI controller */
2960 class: ((PCI_CLASS_SERIAL_USB << 8) | 0x10),
2961 class_mask: ~0,
2962
2963 /* no matter who makes it */
2964 vendor: PCI_ANY_ID,
2965 device: PCI_ANY_ID,
2966 subvendor: PCI_ANY_ID,
2967 subdevice: PCI_ANY_ID,
2968
2969 }, { /* end: all zeroes */ }
2970 };
2971
2972 MODULE_DEVICE_TABLE (pci, ohci_pci_ids);
2973
2974 static struct pci_driver ohci_pci_driver = {
2975 name: "usb-ohci",
2976 id_table: &ohci_pci_ids [0],
2977
2978 probe: ohci_pci_probe,
2979 remove: __devexit_p(ohci_pci_remove),
2980
2981 #ifdef CONFIG_PM
2982 suspend: ohci_pci_suspend,
2983 resume: ohci_pci_resume,
2984 #endif /* PM */
2985 };
2986
2987
2988 /*-------------------------------------------------------------------------*/
2989
ohci_hcd_init(void)2990 static int __init ohci_hcd_init (void)
2991 {
2992 return pci_module_init (&ohci_pci_driver);
2993 }
2994
2995 /*-------------------------------------------------------------------------*/
2996
ohci_hcd_cleanup(void)2997 static void __exit ohci_hcd_cleanup (void)
2998 {
2999 pci_unregister_driver (&ohci_pci_driver);
3000 }
3001
3002 module_init (ohci_hcd_init);
3003 module_exit (ohci_hcd_cleanup);
3004
3005
3006 MODULE_AUTHOR( DRIVER_AUTHOR );
3007 MODULE_DESCRIPTION( DRIVER_DESC );
3008 MODULE_LICENSE("GPL");
3009