1/* $Id: swift.S,v 1.7 2000/07/16 21:48:52 anton Exp $
2 * swift.S: MicroSparc-II mmu/cache operations.
3 *
4 * Copyright (C) 1999 David S. Miller (davem@redhat.com)
5 */
6
7#include <linux/config.h>
8#include <asm/psr.h>
9#include <asm/asi.h>
10#include <asm/page.h>
11#include <asm/pgtsrmmu.h>
12#include <asm/asm_offsets.h>
13
14	.text
15	.align	4
16
17#if 1	/* XXX screw this, I can't get the VAC flushes working
18	 * XXX reliably... -DaveM
19	 */
20	.globl	swift_flush_cache_all, swift_flush_cache_mm
21	.globl	swift_flush_cache_range, swift_flush_cache_page
22	.globl	swift_flush_page_for_dma
23	.globl	swift_flush_page_to_ram
24
25swift_flush_cache_all:
26swift_flush_cache_mm:
27swift_flush_cache_range:
28swift_flush_cache_page:
29swift_flush_page_for_dma:
30swift_flush_page_to_ram:
31	sethi	%hi(0x2000), %o0
321:	subcc	%o0, 0x10, %o0
33	add	%o0, %o0, %o1
34	sta	%g0, [%o0] ASI_M_DATAC_TAG
35	bne	1b
36	 sta	%g0, [%o1] ASI_M_TXTC_TAG
37	retl
38	 nop
39#else
40
41	.globl	swift_flush_cache_all
42swift_flush_cache_all:
43	WINDOW_FLUSH(%g4, %g5)
44
45	/* Just clear out all the tags. */
46	sethi	%hi(16 * 1024), %o0
471:	subcc	%o0, 16, %o0
48	sta	%g0, [%o0] ASI_M_TXTC_TAG
49	bne	1b
50	 sta	%g0, [%o0] ASI_M_DATAC_TAG
51	retl
52	 nop
53
54	.globl	swift_flush_cache_mm
55swift_flush_cache_mm:
56	ld	[%o0 + AOFF_mm_context], %g2
57	cmp	%g2, -1
58	be	swift_flush_cache_mm_out
59	WINDOW_FLUSH(%g4, %g5)
60	rd	%psr, %g1
61	andn	%g1, PSR_ET, %g3
62	wr	%g3, 0x0, %psr
63	nop
64	nop
65	mov	SRMMU_CTX_REG, %g7
66	lda	[%g7] ASI_M_MMUREGS, %g5
67	sta	%g2, [%g7] ASI_M_MMUREGS
68
69#if 1
70	sethi	%hi(0x2000), %o0
711:	subcc	%o0, 0x10, %o0
72	sta	%g0, [%o0] ASI_M_FLUSH_CTX
73	bne	1b
74	 nop
75#else
76	clr	%o0
77	or	%g0, 2048, %g7
78	or	%g0, 2048, %o1
79	add	%o1, 2048, %o2
80	add	%o2, 2048, %o3
81	mov	16, %o4
82	add	%o4, 2048, %o5
83	add	%o5, 2048, %g2
84	add	%g2, 2048, %g3
851:	sta	%g0, [%o0      ] ASI_M_FLUSH_CTX
86	sta	%g0, [%o0 + %o1] ASI_M_FLUSH_CTX
87	sta	%g0, [%o0 + %o2] ASI_M_FLUSH_CTX
88	sta	%g0, [%o0 + %o3] ASI_M_FLUSH_CTX
89	sta	%g0, [%o0 + %o4] ASI_M_FLUSH_CTX
90	sta	%g0, [%o0 + %o5] ASI_M_FLUSH_CTX
91	sta	%g0, [%o0 + %g2] ASI_M_FLUSH_CTX
92	sta	%g0, [%o0 + %g3] ASI_M_FLUSH_CTX
93	subcc	%g7, 32, %g7
94	bne	1b
95	 add	%o0, 32, %o0
96#endif
97
98	mov	SRMMU_CTX_REG, %g7
99	sta	%g5, [%g7] ASI_M_MMUREGS
100	wr	%g1, 0x0, %psr
101	nop
102	nop
103swift_flush_cache_mm_out:
104	retl
105	 nop
106
107	.globl	swift_flush_cache_range
108swift_flush_cache_range:
109	sub	%o2, %o1, %o2
110	sethi	%hi(4096), %o3
111	cmp	%o2, %o3
112	bgu	swift_flush_cache_mm
113	 nop
114	b	70f
115	 nop
116
117	.globl	swift_flush_cache_page
118swift_flush_cache_page:
119	ld	[%o0 + 0x0], %o0		/* XXX vma->vm_mm, GROSS XXX */
12070:
121	ld	[%o0 + AOFF_mm_context], %g2
122	cmp	%g2, -1
123	be	swift_flush_cache_page_out
124	WINDOW_FLUSH(%g4, %g5)
125	rd	%psr, %g1
126	andn	%g1, PSR_ET, %g3
127	wr	%g3, 0x0, %psr
128	nop
129	nop
130	mov	SRMMU_CTX_REG, %g7
131	lda	[%g7] ASI_M_MMUREGS, %g5
132	sta	%g2, [%g7] ASI_M_MMUREGS
133
134	andn	%o1, (PAGE_SIZE - 1), %o1
135#if 1
136	sethi	%hi(0x1000), %o0
1371:	subcc	%o0, 0x10, %o0
138	sta	%g0, [%o1 + %o0] ASI_M_FLUSH_PAGE
139	bne	1b
140	 nop
141#else
142	or	%g0, 512, %g7
143	or	%g0, 512, %o0
144	add	%o0, 512, %o2
145	add	%o2, 512, %o3
146	add	%o3, 512, %o4
147	add	%o4, 512, %o5
148	add	%o5, 512, %g3
149	add	%g3, 512, %g4
1501:	sta	%g0, [%o1      ] ASI_M_FLUSH_PAGE
151	sta	%g0, [%o1 + %o0] ASI_M_FLUSH_PAGE
152	sta	%g0, [%o1 + %o2] ASI_M_FLUSH_PAGE
153	sta	%g0, [%o1 + %o3] ASI_M_FLUSH_PAGE
154	sta	%g0, [%o1 + %o4] ASI_M_FLUSH_PAGE
155	sta	%g0, [%o1 + %o5] ASI_M_FLUSH_PAGE
156	sta	%g0, [%o1 + %g3] ASI_M_FLUSH_PAGE
157	sta	%g0, [%o1 + %g4] ASI_M_FLUSH_PAGE
158	subcc	%g7, 16, %g7
159	bne	1b
160	 add	%o1, 16, %o1
161#endif
162
163	mov	SRMMU_CTX_REG, %g7
164	sta	%g5, [%g7] ASI_M_MMUREGS
165	wr	%g1, 0x0, %psr
166	nop
167	nop
168swift_flush_cache_page_out:
169	retl
170	 nop
171
172	/* Swift is write-thru, however it is not
173	 * I/O nor TLB-walk coherent.  Also it has
174	 * caches which are virtually indexed and tagged.
175	 */
176	.globl	swift_flush_page_for_dma
177	.globl	swift_flush_page_to_ram
178swift_flush_page_for_dma:
179swift_flush_page_to_ram:
180	andn	%o0, (PAGE_SIZE - 1), %o1
181#if 1
182	sethi	%hi(0x1000), %o0
1831:	subcc	%o0, 0x10, %o0
184	sta	%g0, [%o1 + %o0] ASI_M_FLUSH_PAGE
185	bne	1b
186	 nop
187#else
188	or	%g0, 512, %g7
189	or	%g0, 512, %o0
190	add	%o0, 512, %o2
191	add	%o2, 512, %o3
192	add	%o3, 512, %o4
193	add	%o4, 512, %o5
194	add	%o5, 512, %g3
195	add	%g3, 512, %g4
1961:	sta	%g0, [%o1      ] ASI_M_FLUSH_PAGE
197	sta	%g0, [%o1 + %o0] ASI_M_FLUSH_PAGE
198	sta	%g0, [%o1 + %o2] ASI_M_FLUSH_PAGE
199	sta	%g0, [%o1 + %o3] ASI_M_FLUSH_PAGE
200	sta	%g0, [%o1 + %o4] ASI_M_FLUSH_PAGE
201	sta	%g0, [%o1 + %o5] ASI_M_FLUSH_PAGE
202	sta	%g0, [%o1 + %g3] ASI_M_FLUSH_PAGE
203	sta	%g0, [%o1 + %g4] ASI_M_FLUSH_PAGE
204	subcc	%g7, 16, %g7
205	bne	1b
206	 add	%o1, 16, %o1
207#endif
208	retl
209	 nop
210#endif
211
212	.globl	swift_flush_sig_insns
213swift_flush_sig_insns:
214	flush	%o1
215	retl
216	 flush	%o1 + 4
217
218	.globl	swift_flush_tlb_mm
219	.globl	swift_flush_tlb_range
220	.globl	swift_flush_tlb_all
221swift_flush_tlb_mm:
222swift_flush_tlb_range:
223	ld	[%o0 + AOFF_mm_context], %g2
224	cmp	%g2, -1
225	be	swift_flush_tlb_all_out
226swift_flush_tlb_all:
227	mov	0x400, %o1
228	sta	%g0, [%o1] ASI_M_FLUSH_PROBE
229swift_flush_tlb_all_out:
230	retl
231	 nop
232
233	.globl	swift_flush_tlb_page
234swift_flush_tlb_page:
235	ld	[%o0 + 0x00], %o0	/* XXX vma->vm_mm GROSS XXX */
236	mov	SRMMU_CTX_REG, %g1
237	ld	[%o0 + AOFF_mm_context], %o3
238	andn	%o1, (PAGE_SIZE - 1), %o1
239	cmp	%o3, -1
240	be	swift_flush_tlb_page_out
241	 nop
242#if 1
243	mov	0x400, %o1
244	sta	%g0, [%o1] ASI_M_FLUSH_PROBE
245#else
246	lda	[%g1] ASI_M_MMUREGS, %g5
247	sta	%o3, [%g1] ASI_M_MMUREGS
248	sta	%g0, [%o1] ASI_M_FLUSH_PAGE	/* rem. virt. cache. prot. */
249	sta	%g0, [%o1] ASI_M_FLUSH_PROBE
250	sta	%g5, [%g1] ASI_M_MMUREGS
251#endif
252swift_flush_tlb_page_out:
253	retl
254	 nop
255