1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
67
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72 #include <ttm/ttm_execbuf_util.h>
73
74 #include "radeon_family.h"
75 #include "radeon_mode.h"
76 #include "radeon_reg.h"
77
78 /*
79 * Modules parameters.
80 */
81 extern int radeon_no_wb;
82 extern int radeon_modeset;
83 extern int radeon_dynclks;
84 extern int radeon_r4xx_atom;
85 extern int radeon_agpmode;
86 extern int radeon_vram_limit;
87 extern int radeon_gart_size;
88 extern int radeon_benchmarking;
89 extern int radeon_testing;
90 extern int radeon_connector_table;
91 extern int radeon_tv;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
95 extern int radeon_pcie_gen2;
96 extern int radeon_msi;
97
98 /*
99 * Copy from radeon_drv.h so we don't have to include both and have conflicting
100 * symbol;
101 */
102 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
103 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
104 /* RADEON_IB_POOL_SIZE must be a power of 2 */
105 #define RADEON_IB_POOL_SIZE 16
106 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
107 #define RADEONFB_CONN_LIMIT 4
108 #define RADEON_BIOS_NUM_SCRATCH 8
109
110 /* max number of rings */
111 #define RADEON_NUM_RINGS 3
112
113 /* internal ring indices */
114 /* r1xx+ has gfx CP ring */
115 #define RADEON_RING_TYPE_GFX_INDEX 0
116
117 /* cayman has 2 compute CP rings */
118 #define CAYMAN_RING_TYPE_CP1_INDEX 1
119 #define CAYMAN_RING_TYPE_CP2_INDEX 2
120
121 /* hardcode those limit for now */
122 #define RADEON_VA_RESERVED_SIZE (8 << 20)
123 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
124
125 /*
126 * Errata workarounds.
127 */
128 enum radeon_pll_errata {
129 CHIP_ERRATA_R300_CG = 0x00000001,
130 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
131 CHIP_ERRATA_PLL_DELAY = 0x00000004
132 };
133
134
135 struct radeon_device;
136
137
138 /*
139 * BIOS.
140 */
141 bool radeon_get_bios(struct radeon_device *rdev);
142
143
144 /*
145 * Mutex which allows recursive locking from the same process.
146 */
147 struct radeon_mutex {
148 struct mutex mutex;
149 struct task_struct *owner;
150 int level;
151 };
152
radeon_mutex_init(struct radeon_mutex * mutex)153 static inline void radeon_mutex_init(struct radeon_mutex *mutex)
154 {
155 mutex_init(&mutex->mutex);
156 mutex->owner = NULL;
157 mutex->level = 0;
158 }
159
radeon_mutex_lock(struct radeon_mutex * mutex)160 static inline void radeon_mutex_lock(struct radeon_mutex *mutex)
161 {
162 if (mutex_trylock(&mutex->mutex)) {
163 /* The mutex was unlocked before, so it's ours now */
164 mutex->owner = current;
165 } else if (mutex->owner != current) {
166 /* Another process locked the mutex, take it */
167 mutex_lock(&mutex->mutex);
168 mutex->owner = current;
169 }
170 /* Otherwise the mutex was already locked by this process */
171
172 mutex->level++;
173 }
174
radeon_mutex_unlock(struct radeon_mutex * mutex)175 static inline void radeon_mutex_unlock(struct radeon_mutex *mutex)
176 {
177 if (--mutex->level > 0)
178 return;
179
180 mutex->owner = NULL;
181 mutex_unlock(&mutex->mutex);
182 }
183
184
185 /*
186 * Dummy page
187 */
188 struct radeon_dummy_page {
189 struct page *page;
190 dma_addr_t addr;
191 };
192 int radeon_dummy_page_init(struct radeon_device *rdev);
193 void radeon_dummy_page_fini(struct radeon_device *rdev);
194
195
196 /*
197 * Clocks
198 */
199 struct radeon_clock {
200 struct radeon_pll p1pll;
201 struct radeon_pll p2pll;
202 struct radeon_pll dcpll;
203 struct radeon_pll spll;
204 struct radeon_pll mpll;
205 /* 10 Khz units */
206 uint32_t default_mclk;
207 uint32_t default_sclk;
208 uint32_t default_dispclk;
209 uint32_t dp_extclk;
210 uint32_t max_pixel_clock;
211 };
212
213 /*
214 * Power management
215 */
216 int radeon_pm_init(struct radeon_device *rdev);
217 void radeon_pm_fini(struct radeon_device *rdev);
218 void radeon_pm_compute_clocks(struct radeon_device *rdev);
219 void radeon_pm_suspend(struct radeon_device *rdev);
220 void radeon_pm_resume(struct radeon_device *rdev);
221 void radeon_combios_get_power_modes(struct radeon_device *rdev);
222 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
223 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
224 void rs690_pm_info(struct radeon_device *rdev);
225 extern int rv6xx_get_temp(struct radeon_device *rdev);
226 extern int rv770_get_temp(struct radeon_device *rdev);
227 extern int evergreen_get_temp(struct radeon_device *rdev);
228 extern int sumo_get_temp(struct radeon_device *rdev);
229 extern int si_get_temp(struct radeon_device *rdev);
230 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
231 unsigned *bankh, unsigned *mtaspect,
232 unsigned *tile_split);
233
234 /*
235 * Fences.
236 */
237 struct radeon_fence_driver {
238 uint32_t scratch_reg;
239 uint64_t gpu_addr;
240 volatile uint32_t *cpu_addr;
241 atomic_t seq;
242 uint32_t last_seq;
243 unsigned long last_jiffies;
244 unsigned long last_timeout;
245 wait_queue_head_t queue;
246 struct list_head created;
247 struct list_head emitted;
248 struct list_head signaled;
249 bool initialized;
250 };
251
252 struct radeon_fence {
253 struct radeon_device *rdev;
254 struct kref kref;
255 struct list_head list;
256 /* protected by radeon_fence.lock */
257 uint32_t seq;
258 bool emitted;
259 bool signaled;
260 /* RB, DMA, etc. */
261 int ring;
262 struct radeon_semaphore *semaphore;
263 };
264
265 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
266 int radeon_fence_driver_init(struct radeon_device *rdev);
267 void radeon_fence_driver_fini(struct radeon_device *rdev);
268 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
269 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
270 void radeon_fence_process(struct radeon_device *rdev, int ring);
271 bool radeon_fence_signaled(struct radeon_fence *fence);
272 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
273 int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
274 int radeon_fence_wait_last(struct radeon_device *rdev, int ring);
275 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
276 void radeon_fence_unref(struct radeon_fence **fence);
277 int radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
278
279 /*
280 * Tiling registers
281 */
282 struct radeon_surface_reg {
283 struct radeon_bo *bo;
284 };
285
286 #define RADEON_GEM_MAX_SURFACES 8
287
288 /*
289 * TTM.
290 */
291 struct radeon_mman {
292 struct ttm_bo_global_ref bo_global_ref;
293 struct drm_global_reference mem_global_ref;
294 struct ttm_bo_device bdev;
295 bool mem_global_referenced;
296 bool initialized;
297 };
298
299 /* bo virtual address in a specific vm */
300 struct radeon_bo_va {
301 /* bo list is protected by bo being reserved */
302 struct list_head bo_list;
303 /* vm list is protected by vm mutex */
304 struct list_head vm_list;
305 /* constant after initialization */
306 struct radeon_vm *vm;
307 struct radeon_bo *bo;
308 uint64_t soffset;
309 uint64_t eoffset;
310 uint32_t flags;
311 bool valid;
312 };
313
314 struct radeon_bo {
315 /* Protected by gem.mutex */
316 struct list_head list;
317 /* Protected by tbo.reserved */
318 u32 placements[3];
319 struct ttm_placement placement;
320 struct ttm_buffer_object tbo;
321 struct ttm_bo_kmap_obj kmap;
322 unsigned pin_count;
323 void *kptr;
324 u32 tiling_flags;
325 u32 pitch;
326 int surface_reg;
327 /* list of all virtual address to which this bo
328 * is associated to
329 */
330 struct list_head va;
331 /* Constant after initialization */
332 struct radeon_device *rdev;
333 struct drm_gem_object gem_base;
334 };
335 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
336
337 struct radeon_bo_list {
338 struct ttm_validate_buffer tv;
339 struct radeon_bo *bo;
340 uint64_t gpu_offset;
341 unsigned rdomain;
342 unsigned wdomain;
343 u32 tiling_flags;
344 };
345
346 /* sub-allocation manager, it has to be protected by another lock.
347 * By conception this is an helper for other part of the driver
348 * like the indirect buffer or semaphore, which both have their
349 * locking.
350 *
351 * Principe is simple, we keep a list of sub allocation in offset
352 * order (first entry has offset == 0, last entry has the highest
353 * offset).
354 *
355 * When allocating new object we first check if there is room at
356 * the end total_size - (last_object_offset + last_object_size) >=
357 * alloc_size. If so we allocate new object there.
358 *
359 * When there is not enough room at the end, we start waiting for
360 * each sub object until we reach object_offset+object_size >=
361 * alloc_size, this object then become the sub object we return.
362 *
363 * Alignment can't be bigger than page size.
364 *
365 * Hole are not considered for allocation to keep things simple.
366 * Assumption is that there won't be hole (all object on same
367 * alignment).
368 */
369 struct radeon_sa_manager {
370 struct radeon_bo *bo;
371 struct list_head sa_bo;
372 unsigned size;
373 uint64_t gpu_addr;
374 void *cpu_ptr;
375 uint32_t domain;
376 };
377
378 struct radeon_sa_bo;
379
380 /* sub-allocation buffer */
381 struct radeon_sa_bo {
382 struct list_head list;
383 struct radeon_sa_manager *manager;
384 unsigned offset;
385 unsigned size;
386 };
387
388 /*
389 * GEM objects.
390 */
391 struct radeon_gem {
392 struct mutex mutex;
393 struct list_head objects;
394 };
395
396 int radeon_gem_init(struct radeon_device *rdev);
397 void radeon_gem_fini(struct radeon_device *rdev);
398 int radeon_gem_object_create(struct radeon_device *rdev, int size,
399 int alignment, int initial_domain,
400 bool discardable, bool kernel,
401 struct drm_gem_object **obj);
402
403 int radeon_mode_dumb_create(struct drm_file *file_priv,
404 struct drm_device *dev,
405 struct drm_mode_create_dumb *args);
406 int radeon_mode_dumb_mmap(struct drm_file *filp,
407 struct drm_device *dev,
408 uint32_t handle, uint64_t *offset_p);
409 int radeon_mode_dumb_destroy(struct drm_file *file_priv,
410 struct drm_device *dev,
411 uint32_t handle);
412
413 /*
414 * Semaphores.
415 */
416 struct radeon_ring;
417
418 #define RADEON_SEMAPHORE_BO_SIZE 256
419
420 struct radeon_semaphore_driver {
421 rwlock_t lock;
422 struct list_head bo;
423 };
424
425 struct radeon_semaphore_bo;
426
427 /* everything here is constant */
428 struct radeon_semaphore {
429 struct list_head list;
430 uint64_t gpu_addr;
431 uint32_t *cpu_ptr;
432 struct radeon_semaphore_bo *bo;
433 };
434
435 struct radeon_semaphore_bo {
436 struct list_head list;
437 struct radeon_ib *ib;
438 struct list_head free;
439 struct radeon_semaphore semaphores[RADEON_SEMAPHORE_BO_SIZE/8];
440 unsigned nused;
441 };
442
443 void radeon_semaphore_driver_fini(struct radeon_device *rdev);
444 int radeon_semaphore_create(struct radeon_device *rdev,
445 struct radeon_semaphore **semaphore);
446 void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
447 struct radeon_semaphore *semaphore);
448 void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
449 struct radeon_semaphore *semaphore);
450 void radeon_semaphore_free(struct radeon_device *rdev,
451 struct radeon_semaphore *semaphore);
452
453 /*
454 * GART structures, functions & helpers
455 */
456 struct radeon_mc;
457
458 #define RADEON_GPU_PAGE_SIZE 4096
459 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
460 #define RADEON_GPU_PAGE_SHIFT 12
461 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
462
463 struct radeon_gart {
464 dma_addr_t table_addr;
465 struct radeon_bo *robj;
466 void *ptr;
467 unsigned num_gpu_pages;
468 unsigned num_cpu_pages;
469 unsigned table_size;
470 struct page **pages;
471 dma_addr_t *pages_addr;
472 bool ready;
473 };
474
475 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
476 void radeon_gart_table_ram_free(struct radeon_device *rdev);
477 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
478 void radeon_gart_table_vram_free(struct radeon_device *rdev);
479 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
480 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
481 int radeon_gart_init(struct radeon_device *rdev);
482 void radeon_gart_fini(struct radeon_device *rdev);
483 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
484 int pages);
485 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
486 int pages, struct page **pagelist,
487 dma_addr_t *dma_addr);
488 void radeon_gart_restore(struct radeon_device *rdev);
489
490
491 /*
492 * GPU MC structures, functions & helpers
493 */
494 struct radeon_mc {
495 resource_size_t aper_size;
496 resource_size_t aper_base;
497 resource_size_t agp_base;
498 /* for some chips with <= 32MB we need to lie
499 * about vram size near mc fb location */
500 u64 mc_vram_size;
501 u64 visible_vram_size;
502 u64 gtt_size;
503 u64 gtt_start;
504 u64 gtt_end;
505 u64 vram_start;
506 u64 vram_end;
507 unsigned vram_width;
508 u64 real_vram_size;
509 int vram_mtrr;
510 bool vram_is_ddr;
511 bool igp_sideport_enabled;
512 u64 gtt_base_align;
513 };
514
515 bool radeon_combios_sideport_present(struct radeon_device *rdev);
516 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
517
518 /*
519 * GPU scratch registers structures, functions & helpers
520 */
521 struct radeon_scratch {
522 unsigned num_reg;
523 uint32_t reg_base;
524 bool free[32];
525 uint32_t reg[32];
526 };
527
528 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
529 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
530
531
532 /*
533 * IRQS.
534 */
535
536 struct radeon_unpin_work {
537 struct work_struct work;
538 struct radeon_device *rdev;
539 int crtc_id;
540 struct radeon_fence *fence;
541 struct drm_pending_vblank_event *event;
542 struct radeon_bo *old_rbo;
543 u64 new_crtc_base;
544 };
545
546 struct r500_irq_stat_regs {
547 u32 disp_int;
548 };
549
550 struct r600_irq_stat_regs {
551 u32 disp_int;
552 u32 disp_int_cont;
553 u32 disp_int_cont2;
554 u32 d1grph_int;
555 u32 d2grph_int;
556 };
557
558 struct evergreen_irq_stat_regs {
559 u32 disp_int;
560 u32 disp_int_cont;
561 u32 disp_int_cont2;
562 u32 disp_int_cont3;
563 u32 disp_int_cont4;
564 u32 disp_int_cont5;
565 u32 d1grph_int;
566 u32 d2grph_int;
567 u32 d3grph_int;
568 u32 d4grph_int;
569 u32 d5grph_int;
570 u32 d6grph_int;
571 };
572
573 union radeon_irq_stat_regs {
574 struct r500_irq_stat_regs r500;
575 struct r600_irq_stat_regs r600;
576 struct evergreen_irq_stat_regs evergreen;
577 };
578
579 #define RADEON_MAX_HPD_PINS 6
580 #define RADEON_MAX_CRTCS 6
581 #define RADEON_MAX_HDMI_BLOCKS 2
582
583 struct radeon_irq {
584 bool installed;
585 bool sw_int[RADEON_NUM_RINGS];
586 bool crtc_vblank_int[RADEON_MAX_CRTCS];
587 bool pflip[RADEON_MAX_CRTCS];
588 wait_queue_head_t vblank_queue;
589 bool hpd[RADEON_MAX_HPD_PINS];
590 bool gui_idle;
591 bool gui_idle_acked;
592 wait_queue_head_t idle_queue;
593 bool hdmi[RADEON_MAX_HDMI_BLOCKS];
594 spinlock_t sw_lock;
595 int sw_refcount[RADEON_NUM_RINGS];
596 union radeon_irq_stat_regs stat_regs;
597 spinlock_t pflip_lock[RADEON_MAX_CRTCS];
598 int pflip_refcount[RADEON_MAX_CRTCS];
599 };
600
601 int radeon_irq_kms_init(struct radeon_device *rdev);
602 void radeon_irq_kms_fini(struct radeon_device *rdev);
603 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
604 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
605 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
606 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
607
608 /*
609 * CP & rings.
610 */
611
612 struct radeon_ib {
613 struct radeon_sa_bo sa_bo;
614 unsigned idx;
615 uint32_t length_dw;
616 uint64_t gpu_addr;
617 uint32_t *ptr;
618 struct radeon_fence *fence;
619 unsigned vm_id;
620 bool is_const_ib;
621 };
622
623 /*
624 * locking -
625 * mutex protects scheduled_ibs, ready, alloc_bm
626 */
627 struct radeon_ib_pool {
628 struct radeon_mutex mutex;
629 struct radeon_sa_manager sa_manager;
630 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
631 bool ready;
632 unsigned head_id;
633 };
634
635 struct radeon_ring {
636 struct radeon_bo *ring_obj;
637 volatile uint32_t *ring;
638 unsigned rptr;
639 unsigned rptr_offs;
640 unsigned rptr_reg;
641 unsigned wptr;
642 unsigned wptr_old;
643 unsigned wptr_reg;
644 unsigned ring_size;
645 unsigned ring_free_dw;
646 int count_dw;
647 uint64_t gpu_addr;
648 uint32_t align_mask;
649 uint32_t ptr_mask;
650 struct mutex mutex;
651 bool ready;
652 u32 ptr_reg_shift;
653 u32 ptr_reg_mask;
654 u32 nop;
655 };
656
657 /*
658 * VM
659 */
660 struct radeon_vm {
661 struct list_head list;
662 struct list_head va;
663 int id;
664 unsigned last_pfn;
665 u64 pt_gpu_addr;
666 u64 *pt;
667 struct radeon_sa_bo sa_bo;
668 struct mutex mutex;
669 /* last fence for cs using this vm */
670 struct radeon_fence *fence;
671 };
672
673 struct radeon_vm_funcs {
674 int (*init)(struct radeon_device *rdev);
675 void (*fini)(struct radeon_device *rdev);
676 /* cs mutex must be lock for schedule_ib */
677 int (*bind)(struct radeon_device *rdev, struct radeon_vm *vm, int id);
678 void (*unbind)(struct radeon_device *rdev, struct radeon_vm *vm);
679 void (*tlb_flush)(struct radeon_device *rdev, struct radeon_vm *vm);
680 uint32_t (*page_flags)(struct radeon_device *rdev,
681 struct radeon_vm *vm,
682 uint32_t flags);
683 void (*set_page)(struct radeon_device *rdev, struct radeon_vm *vm,
684 unsigned pfn, uint64_t addr, uint32_t flags);
685 };
686
687 struct radeon_vm_manager {
688 struct list_head lru_vm;
689 uint32_t use_bitmap;
690 struct radeon_sa_manager sa_manager;
691 uint32_t max_pfn;
692 /* fields constant after init */
693 const struct radeon_vm_funcs *funcs;
694 /* number of VMIDs */
695 unsigned nvm;
696 /* vram base address for page table entry */
697 u64 vram_base_offset;
698 /* is vm enabled? */
699 bool enabled;
700 };
701
702 /*
703 * file private structure
704 */
705 struct radeon_fpriv {
706 struct radeon_vm vm;
707 };
708
709 /*
710 * R6xx+ IH ring
711 */
712 struct r600_ih {
713 struct radeon_bo *ring_obj;
714 volatile uint32_t *ring;
715 unsigned rptr;
716 unsigned rptr_offs;
717 unsigned wptr;
718 unsigned wptr_old;
719 unsigned ring_size;
720 uint64_t gpu_addr;
721 uint32_t ptr_mask;
722 spinlock_t lock;
723 bool enabled;
724 };
725
726 struct r600_blit_cp_primitives {
727 void (*set_render_target)(struct radeon_device *rdev, int format,
728 int w, int h, u64 gpu_addr);
729 void (*cp_set_surface_sync)(struct radeon_device *rdev,
730 u32 sync_type, u32 size,
731 u64 mc_addr);
732 void (*set_shaders)(struct radeon_device *rdev);
733 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
734 void (*set_tex_resource)(struct radeon_device *rdev,
735 int format, int w, int h, int pitch,
736 u64 gpu_addr, u32 size);
737 void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
738 int x2, int y2);
739 void (*draw_auto)(struct radeon_device *rdev);
740 void (*set_default_state)(struct radeon_device *rdev);
741 };
742
743 struct r600_blit {
744 struct mutex mutex;
745 struct radeon_bo *shader_obj;
746 struct r600_blit_cp_primitives primitives;
747 int max_dim;
748 int ring_size_common;
749 int ring_size_per_loop;
750 u64 shader_gpu_addr;
751 u32 vs_offset, ps_offset;
752 u32 state_offset;
753 u32 state_len;
754 u32 vb_used, vb_total;
755 struct radeon_ib *vb_ib;
756 };
757
758 void r600_blit_suspend(struct radeon_device *rdev);
759
760 /*
761 * SI RLC stuff
762 */
763 struct si_rlc {
764 /* for power gating */
765 struct radeon_bo *save_restore_obj;
766 uint64_t save_restore_gpu_addr;
767 /* for clear state */
768 struct radeon_bo *clear_state_obj;
769 uint64_t clear_state_gpu_addr;
770 };
771
772 int radeon_ib_get(struct radeon_device *rdev, int ring,
773 struct radeon_ib **ib, unsigned size);
774 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
775 bool radeon_ib_try_free(struct radeon_device *rdev, struct radeon_ib *ib);
776 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
777 int radeon_ib_pool_init(struct radeon_device *rdev);
778 void radeon_ib_pool_fini(struct radeon_device *rdev);
779 int radeon_ib_pool_start(struct radeon_device *rdev);
780 int radeon_ib_pool_suspend(struct radeon_device *rdev);
781 /* Ring access between begin & end cannot sleep */
782 int radeon_ring_index(struct radeon_device *rdev, struct radeon_ring *cp);
783 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
784 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
785 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
786 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
787 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
788 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
789 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
790 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
791 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
792 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
793 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
794
795
796 /*
797 * CS.
798 */
799 struct radeon_cs_reloc {
800 struct drm_gem_object *gobj;
801 struct radeon_bo *robj;
802 struct radeon_bo_list lobj;
803 uint32_t handle;
804 uint32_t flags;
805 };
806
807 struct radeon_cs_chunk {
808 uint32_t chunk_id;
809 uint32_t length_dw;
810 int kpage_idx[2];
811 uint32_t *kpage[2];
812 uint32_t *kdata;
813 void __user *user_ptr;
814 int last_copied_page;
815 int last_page_index;
816 };
817
818 struct radeon_cs_parser {
819 struct device *dev;
820 struct radeon_device *rdev;
821 struct drm_file *filp;
822 /* chunks */
823 unsigned nchunks;
824 struct radeon_cs_chunk *chunks;
825 uint64_t *chunks_array;
826 /* IB */
827 unsigned idx;
828 /* relocations */
829 unsigned nrelocs;
830 struct radeon_cs_reloc *relocs;
831 struct radeon_cs_reloc **relocs_ptr;
832 struct list_head validated;
833 /* indices of various chunks */
834 int chunk_ib_idx;
835 int chunk_relocs_idx;
836 int chunk_flags_idx;
837 int chunk_const_ib_idx;
838 struct radeon_ib *ib;
839 struct radeon_ib *const_ib;
840 void *track;
841 unsigned family;
842 int parser_error;
843 u32 cs_flags;
844 u32 ring;
845 s32 priority;
846 };
847
848 extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
849 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
850 extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
851
852 struct radeon_cs_packet {
853 unsigned idx;
854 unsigned type;
855 unsigned reg;
856 unsigned opcode;
857 int count;
858 unsigned one_reg_wr;
859 };
860
861 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
862 struct radeon_cs_packet *pkt,
863 unsigned idx, unsigned reg);
864 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
865 struct radeon_cs_packet *pkt);
866
867
868 /*
869 * AGP
870 */
871 int radeon_agp_init(struct radeon_device *rdev);
872 void radeon_agp_resume(struct radeon_device *rdev);
873 void radeon_agp_suspend(struct radeon_device *rdev);
874 void radeon_agp_fini(struct radeon_device *rdev);
875
876
877 /*
878 * Writeback
879 */
880 struct radeon_wb {
881 struct radeon_bo *wb_obj;
882 volatile uint32_t *wb;
883 uint64_t gpu_addr;
884 bool enabled;
885 bool use_event;
886 };
887
888 #define RADEON_WB_SCRATCH_OFFSET 0
889 #define RADEON_WB_CP_RPTR_OFFSET 1024
890 #define RADEON_WB_CP1_RPTR_OFFSET 1280
891 #define RADEON_WB_CP2_RPTR_OFFSET 1536
892 #define R600_WB_IH_WPTR_OFFSET 2048
893 #define R600_WB_EVENT_OFFSET 3072
894
895 /**
896 * struct radeon_pm - power management datas
897 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
898 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
899 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
900 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
901 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
902 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
903 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
904 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
905 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
906 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
907 * @needed_bandwidth: current bandwidth needs
908 *
909 * It keeps track of various data needed to take powermanagement decision.
910 * Bandwidth need is used to determine minimun clock of the GPU and memory.
911 * Equation between gpu/memory clock and available bandwidth is hw dependent
912 * (type of memory, bus size, efficiency, ...)
913 */
914
915 enum radeon_pm_method {
916 PM_METHOD_PROFILE,
917 PM_METHOD_DYNPM,
918 };
919
920 enum radeon_dynpm_state {
921 DYNPM_STATE_DISABLED,
922 DYNPM_STATE_MINIMUM,
923 DYNPM_STATE_PAUSED,
924 DYNPM_STATE_ACTIVE,
925 DYNPM_STATE_SUSPENDED,
926 };
927 enum radeon_dynpm_action {
928 DYNPM_ACTION_NONE,
929 DYNPM_ACTION_MINIMUM,
930 DYNPM_ACTION_DOWNCLOCK,
931 DYNPM_ACTION_UPCLOCK,
932 DYNPM_ACTION_DEFAULT
933 };
934
935 enum radeon_voltage_type {
936 VOLTAGE_NONE = 0,
937 VOLTAGE_GPIO,
938 VOLTAGE_VDDC,
939 VOLTAGE_SW
940 };
941
942 enum radeon_pm_state_type {
943 POWER_STATE_TYPE_DEFAULT,
944 POWER_STATE_TYPE_POWERSAVE,
945 POWER_STATE_TYPE_BATTERY,
946 POWER_STATE_TYPE_BALANCED,
947 POWER_STATE_TYPE_PERFORMANCE,
948 };
949
950 enum radeon_pm_profile_type {
951 PM_PROFILE_DEFAULT,
952 PM_PROFILE_AUTO,
953 PM_PROFILE_LOW,
954 PM_PROFILE_MID,
955 PM_PROFILE_HIGH,
956 };
957
958 #define PM_PROFILE_DEFAULT_IDX 0
959 #define PM_PROFILE_LOW_SH_IDX 1
960 #define PM_PROFILE_MID_SH_IDX 2
961 #define PM_PROFILE_HIGH_SH_IDX 3
962 #define PM_PROFILE_LOW_MH_IDX 4
963 #define PM_PROFILE_MID_MH_IDX 5
964 #define PM_PROFILE_HIGH_MH_IDX 6
965 #define PM_PROFILE_MAX 7
966
967 struct radeon_pm_profile {
968 int dpms_off_ps_idx;
969 int dpms_on_ps_idx;
970 int dpms_off_cm_idx;
971 int dpms_on_cm_idx;
972 };
973
974 enum radeon_int_thermal_type {
975 THERMAL_TYPE_NONE,
976 THERMAL_TYPE_RV6XX,
977 THERMAL_TYPE_RV770,
978 THERMAL_TYPE_EVERGREEN,
979 THERMAL_TYPE_SUMO,
980 THERMAL_TYPE_NI,
981 THERMAL_TYPE_SI,
982 };
983
984 struct radeon_voltage {
985 enum radeon_voltage_type type;
986 /* gpio voltage */
987 struct radeon_gpio_rec gpio;
988 u32 delay; /* delay in usec from voltage drop to sclk change */
989 bool active_high; /* voltage drop is active when bit is high */
990 /* VDDC voltage */
991 u8 vddc_id; /* index into vddc voltage table */
992 u8 vddci_id; /* index into vddci voltage table */
993 bool vddci_enabled;
994 /* r6xx+ sw */
995 u16 voltage;
996 /* evergreen+ vddci */
997 u16 vddci;
998 };
999
1000 /* clock mode flags */
1001 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1002
1003 struct radeon_pm_clock_info {
1004 /* memory clock */
1005 u32 mclk;
1006 /* engine clock */
1007 u32 sclk;
1008 /* voltage info */
1009 struct radeon_voltage voltage;
1010 /* standardized clock flags */
1011 u32 flags;
1012 };
1013
1014 /* state flags */
1015 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1016
1017 struct radeon_power_state {
1018 enum radeon_pm_state_type type;
1019 struct radeon_pm_clock_info *clock_info;
1020 /* number of valid clock modes in this power state */
1021 int num_clock_modes;
1022 struct radeon_pm_clock_info *default_clock_mode;
1023 /* standardized state flags */
1024 u32 flags;
1025 u32 misc; /* vbios specific flags */
1026 u32 misc2; /* vbios specific flags */
1027 int pcie_lanes; /* pcie lanes */
1028 };
1029
1030 /*
1031 * Some modes are overclocked by very low value, accept them
1032 */
1033 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1034
1035 struct radeon_pm {
1036 struct mutex mutex;
1037 u32 active_crtcs;
1038 int active_crtc_count;
1039 int req_vblank;
1040 bool vblank_sync;
1041 bool gui_idle;
1042 fixed20_12 max_bandwidth;
1043 fixed20_12 igp_sideport_mclk;
1044 fixed20_12 igp_system_mclk;
1045 fixed20_12 igp_ht_link_clk;
1046 fixed20_12 igp_ht_link_width;
1047 fixed20_12 k8_bandwidth;
1048 fixed20_12 sideport_bandwidth;
1049 fixed20_12 ht_bandwidth;
1050 fixed20_12 core_bandwidth;
1051 fixed20_12 sclk;
1052 fixed20_12 mclk;
1053 fixed20_12 needed_bandwidth;
1054 struct radeon_power_state *power_state;
1055 /* number of valid power states */
1056 int num_power_states;
1057 int current_power_state_index;
1058 int current_clock_mode_index;
1059 int requested_power_state_index;
1060 int requested_clock_mode_index;
1061 int default_power_state_index;
1062 u32 current_sclk;
1063 u32 current_mclk;
1064 u16 current_vddc;
1065 u16 current_vddci;
1066 u32 default_sclk;
1067 u32 default_mclk;
1068 u16 default_vddc;
1069 u16 default_vddci;
1070 struct radeon_i2c_chan *i2c_bus;
1071 /* selected pm method */
1072 enum radeon_pm_method pm_method;
1073 /* dynpm power management */
1074 struct delayed_work dynpm_idle_work;
1075 enum radeon_dynpm_state dynpm_state;
1076 enum radeon_dynpm_action dynpm_planned_action;
1077 unsigned long dynpm_action_timeout;
1078 bool dynpm_can_upclock;
1079 bool dynpm_can_downclock;
1080 /* profile-based power management */
1081 enum radeon_pm_profile_type profile;
1082 int profile_index;
1083 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1084 /* internal thermal controller on rv6xx+ */
1085 enum radeon_int_thermal_type int_thermal_type;
1086 struct device *int_hwmon_dev;
1087 };
1088
1089 int radeon_pm_get_type_index(struct radeon_device *rdev,
1090 enum radeon_pm_state_type ps_type,
1091 int instance);
1092
1093 /*
1094 * Benchmarking
1095 */
1096 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1097
1098
1099 /*
1100 * Testing
1101 */
1102 void radeon_test_moves(struct radeon_device *rdev);
1103 void radeon_test_ring_sync(struct radeon_device *rdev,
1104 struct radeon_ring *cpA,
1105 struct radeon_ring *cpB);
1106 void radeon_test_syncing(struct radeon_device *rdev);
1107
1108
1109 /*
1110 * Debugfs
1111 */
1112 struct radeon_debugfs {
1113 struct drm_info_list *files;
1114 unsigned num_files;
1115 };
1116
1117 int radeon_debugfs_add_files(struct radeon_device *rdev,
1118 struct drm_info_list *files,
1119 unsigned nfiles);
1120 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1121
1122
1123 /*
1124 * ASIC specific functions.
1125 */
1126 struct radeon_asic {
1127 int (*init)(struct radeon_device *rdev);
1128 void (*fini)(struct radeon_device *rdev);
1129 int (*resume)(struct radeon_device *rdev);
1130 int (*suspend)(struct radeon_device *rdev);
1131 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1132 bool (*gpu_is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1133 int (*asic_reset)(struct radeon_device *rdev);
1134 /* ioctl hw specific callback. Some hw might want to perform special
1135 * operation on specific ioctl. For instance on wait idle some hw
1136 * might want to perform and HDP flush through MMIO as it seems that
1137 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1138 * through ring.
1139 */
1140 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1141 /* check if 3D engine is idle */
1142 bool (*gui_idle)(struct radeon_device *rdev);
1143 /* wait for mc_idle */
1144 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1145 /* gart */
1146 struct {
1147 void (*tlb_flush)(struct radeon_device *rdev);
1148 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1149 } gart;
1150 /* ring specific callbacks */
1151 struct {
1152 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1153 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1154 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1155 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1156 struct radeon_semaphore *semaphore, bool emit_wait);
1157 int (*cs_parse)(struct radeon_cs_parser *p);
1158 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1159 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1160 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1161 } ring[RADEON_NUM_RINGS];
1162 /* irqs */
1163 struct {
1164 int (*set)(struct radeon_device *rdev);
1165 int (*process)(struct radeon_device *rdev);
1166 } irq;
1167 /* displays */
1168 struct {
1169 /* display watermarks */
1170 void (*bandwidth_update)(struct radeon_device *rdev);
1171 /* get frame count */
1172 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1173 /* wait for vblank */
1174 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1175 } display;
1176 /* copy functions for bo handling */
1177 struct {
1178 int (*blit)(struct radeon_device *rdev,
1179 uint64_t src_offset,
1180 uint64_t dst_offset,
1181 unsigned num_gpu_pages,
1182 struct radeon_fence *fence);
1183 u32 blit_ring_index;
1184 int (*dma)(struct radeon_device *rdev,
1185 uint64_t src_offset,
1186 uint64_t dst_offset,
1187 unsigned num_gpu_pages,
1188 struct radeon_fence *fence);
1189 u32 dma_ring_index;
1190 /* method used for bo copy */
1191 int (*copy)(struct radeon_device *rdev,
1192 uint64_t src_offset,
1193 uint64_t dst_offset,
1194 unsigned num_gpu_pages,
1195 struct radeon_fence *fence);
1196 /* ring used for bo copies */
1197 u32 copy_ring_index;
1198 } copy;
1199 /* surfaces */
1200 struct {
1201 int (*set_reg)(struct radeon_device *rdev, int reg,
1202 uint32_t tiling_flags, uint32_t pitch,
1203 uint32_t offset, uint32_t obj_size);
1204 void (*clear_reg)(struct radeon_device *rdev, int reg);
1205 } surface;
1206 /* hotplug detect */
1207 struct {
1208 void (*init)(struct radeon_device *rdev);
1209 void (*fini)(struct radeon_device *rdev);
1210 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1211 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1212 } hpd;
1213 /* power management */
1214 struct {
1215 void (*misc)(struct radeon_device *rdev);
1216 void (*prepare)(struct radeon_device *rdev);
1217 void (*finish)(struct radeon_device *rdev);
1218 void (*init_profile)(struct radeon_device *rdev);
1219 void (*get_dynpm_state)(struct radeon_device *rdev);
1220 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1221 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1222 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1223 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1224 int (*get_pcie_lanes)(struct radeon_device *rdev);
1225 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1226 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1227 } pm;
1228 /* pageflipping */
1229 struct {
1230 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1231 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1232 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1233 } pflip;
1234 };
1235
1236 /*
1237 * Asic structures
1238 */
1239 struct r100_gpu_lockup {
1240 unsigned long last_jiffies;
1241 u32 last_cp_rptr;
1242 };
1243
1244 struct r100_asic {
1245 const unsigned *reg_safe_bm;
1246 unsigned reg_safe_bm_size;
1247 u32 hdp_cntl;
1248 struct r100_gpu_lockup lockup;
1249 };
1250
1251 struct r300_asic {
1252 const unsigned *reg_safe_bm;
1253 unsigned reg_safe_bm_size;
1254 u32 resync_scratch;
1255 u32 hdp_cntl;
1256 struct r100_gpu_lockup lockup;
1257 };
1258
1259 struct r600_asic {
1260 unsigned max_pipes;
1261 unsigned max_tile_pipes;
1262 unsigned max_simds;
1263 unsigned max_backends;
1264 unsigned max_gprs;
1265 unsigned max_threads;
1266 unsigned max_stack_entries;
1267 unsigned max_hw_contexts;
1268 unsigned max_gs_threads;
1269 unsigned sx_max_export_size;
1270 unsigned sx_max_export_pos_size;
1271 unsigned sx_max_export_smx_size;
1272 unsigned sq_num_cf_insts;
1273 unsigned tiling_nbanks;
1274 unsigned tiling_npipes;
1275 unsigned tiling_group_size;
1276 unsigned tile_config;
1277 unsigned backend_map;
1278 struct r100_gpu_lockup lockup;
1279 };
1280
1281 struct rv770_asic {
1282 unsigned max_pipes;
1283 unsigned max_tile_pipes;
1284 unsigned max_simds;
1285 unsigned max_backends;
1286 unsigned max_gprs;
1287 unsigned max_threads;
1288 unsigned max_stack_entries;
1289 unsigned max_hw_contexts;
1290 unsigned max_gs_threads;
1291 unsigned sx_max_export_size;
1292 unsigned sx_max_export_pos_size;
1293 unsigned sx_max_export_smx_size;
1294 unsigned sq_num_cf_insts;
1295 unsigned sx_num_of_sets;
1296 unsigned sc_prim_fifo_size;
1297 unsigned sc_hiz_tile_fifo_size;
1298 unsigned sc_earlyz_tile_fifo_fize;
1299 unsigned tiling_nbanks;
1300 unsigned tiling_npipes;
1301 unsigned tiling_group_size;
1302 unsigned tile_config;
1303 unsigned backend_map;
1304 struct r100_gpu_lockup lockup;
1305 };
1306
1307 struct evergreen_asic {
1308 unsigned num_ses;
1309 unsigned max_pipes;
1310 unsigned max_tile_pipes;
1311 unsigned max_simds;
1312 unsigned max_backends;
1313 unsigned max_gprs;
1314 unsigned max_threads;
1315 unsigned max_stack_entries;
1316 unsigned max_hw_contexts;
1317 unsigned max_gs_threads;
1318 unsigned sx_max_export_size;
1319 unsigned sx_max_export_pos_size;
1320 unsigned sx_max_export_smx_size;
1321 unsigned sq_num_cf_insts;
1322 unsigned sx_num_of_sets;
1323 unsigned sc_prim_fifo_size;
1324 unsigned sc_hiz_tile_fifo_size;
1325 unsigned sc_earlyz_tile_fifo_size;
1326 unsigned tiling_nbanks;
1327 unsigned tiling_npipes;
1328 unsigned tiling_group_size;
1329 unsigned tile_config;
1330 unsigned backend_map;
1331 struct r100_gpu_lockup lockup;
1332 };
1333
1334 struct cayman_asic {
1335 unsigned max_shader_engines;
1336 unsigned max_pipes_per_simd;
1337 unsigned max_tile_pipes;
1338 unsigned max_simds_per_se;
1339 unsigned max_backends_per_se;
1340 unsigned max_texture_channel_caches;
1341 unsigned max_gprs;
1342 unsigned max_threads;
1343 unsigned max_gs_threads;
1344 unsigned max_stack_entries;
1345 unsigned sx_num_of_sets;
1346 unsigned sx_max_export_size;
1347 unsigned sx_max_export_pos_size;
1348 unsigned sx_max_export_smx_size;
1349 unsigned max_hw_contexts;
1350 unsigned sq_num_cf_insts;
1351 unsigned sc_prim_fifo_size;
1352 unsigned sc_hiz_tile_fifo_size;
1353 unsigned sc_earlyz_tile_fifo_size;
1354
1355 unsigned num_shader_engines;
1356 unsigned num_shader_pipes_per_simd;
1357 unsigned num_tile_pipes;
1358 unsigned num_simds_per_se;
1359 unsigned num_backends_per_se;
1360 unsigned backend_disable_mask_per_asic;
1361 unsigned backend_map;
1362 unsigned num_texture_channel_caches;
1363 unsigned mem_max_burst_length_bytes;
1364 unsigned mem_row_size_in_kb;
1365 unsigned shader_engine_tile_size;
1366 unsigned num_gpus;
1367 unsigned multi_gpu_tile_size;
1368
1369 unsigned tile_config;
1370 struct r100_gpu_lockup lockup;
1371 };
1372
1373 struct si_asic {
1374 unsigned max_shader_engines;
1375 unsigned max_pipes_per_simd;
1376 unsigned max_tile_pipes;
1377 unsigned max_simds_per_se;
1378 unsigned max_backends_per_se;
1379 unsigned max_texture_channel_caches;
1380 unsigned max_gprs;
1381 unsigned max_gs_threads;
1382 unsigned max_hw_contexts;
1383 unsigned sc_prim_fifo_size_frontend;
1384 unsigned sc_prim_fifo_size_backend;
1385 unsigned sc_hiz_tile_fifo_size;
1386 unsigned sc_earlyz_tile_fifo_size;
1387
1388 unsigned num_shader_engines;
1389 unsigned num_tile_pipes;
1390 unsigned num_backends_per_se;
1391 unsigned backend_disable_mask_per_asic;
1392 unsigned backend_map;
1393 unsigned num_texture_channel_caches;
1394 unsigned mem_max_burst_length_bytes;
1395 unsigned mem_row_size_in_kb;
1396 unsigned shader_engine_tile_size;
1397 unsigned num_gpus;
1398 unsigned multi_gpu_tile_size;
1399
1400 unsigned tile_config;
1401 struct r100_gpu_lockup lockup;
1402 };
1403
1404 union radeon_asic_config {
1405 struct r300_asic r300;
1406 struct r100_asic r100;
1407 struct r600_asic r600;
1408 struct rv770_asic rv770;
1409 struct evergreen_asic evergreen;
1410 struct cayman_asic cayman;
1411 struct si_asic si;
1412 };
1413
1414 /*
1415 * asic initizalization from radeon_asic.c
1416 */
1417 void radeon_agp_disable(struct radeon_device *rdev);
1418 int radeon_asic_init(struct radeon_device *rdev);
1419
1420
1421 /*
1422 * IOCTL.
1423 */
1424 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1425 struct drm_file *filp);
1426 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1427 struct drm_file *filp);
1428 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1429 struct drm_file *file_priv);
1430 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1431 struct drm_file *file_priv);
1432 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1433 struct drm_file *file_priv);
1434 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1435 struct drm_file *file_priv);
1436 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1437 struct drm_file *filp);
1438 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1439 struct drm_file *filp);
1440 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1441 struct drm_file *filp);
1442 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1443 struct drm_file *filp);
1444 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
1445 struct drm_file *filp);
1446 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1447 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1448 struct drm_file *filp);
1449 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1450 struct drm_file *filp);
1451
1452 /* VRAM scratch page for HDP bug, default vram page */
1453 struct r600_vram_scratch {
1454 struct radeon_bo *robj;
1455 volatile uint32_t *ptr;
1456 u64 gpu_addr;
1457 };
1458
1459
1460 /*
1461 * Core structure, functions and helpers.
1462 */
1463 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1464 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1465
1466 struct radeon_device {
1467 struct device *dev;
1468 struct drm_device *ddev;
1469 struct pci_dev *pdev;
1470 /* ASIC */
1471 union radeon_asic_config config;
1472 enum radeon_family family;
1473 unsigned long flags;
1474 int usec_timeout;
1475 enum radeon_pll_errata pll_errata;
1476 int num_gb_pipes;
1477 int num_z_pipes;
1478 int disp_priority;
1479 /* BIOS */
1480 uint8_t *bios;
1481 bool is_atom_bios;
1482 uint16_t bios_header_start;
1483 struct radeon_bo *stollen_vga_memory;
1484 /* Register mmio */
1485 resource_size_t rmmio_base;
1486 resource_size_t rmmio_size;
1487 void __iomem *rmmio;
1488 radeon_rreg_t mc_rreg;
1489 radeon_wreg_t mc_wreg;
1490 radeon_rreg_t pll_rreg;
1491 radeon_wreg_t pll_wreg;
1492 uint32_t pcie_reg_mask;
1493 radeon_rreg_t pciep_rreg;
1494 radeon_wreg_t pciep_wreg;
1495 /* io port */
1496 void __iomem *rio_mem;
1497 resource_size_t rio_mem_size;
1498 struct radeon_clock clock;
1499 struct radeon_mc mc;
1500 struct radeon_gart gart;
1501 struct radeon_mode_info mode_info;
1502 struct radeon_scratch scratch;
1503 struct radeon_mman mman;
1504 rwlock_t fence_lock;
1505 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
1506 struct radeon_semaphore_driver semaphore_drv;
1507 struct radeon_ring ring[RADEON_NUM_RINGS];
1508 struct radeon_ib_pool ib_pool;
1509 struct radeon_irq irq;
1510 struct radeon_asic *asic;
1511 struct radeon_gem gem;
1512 struct radeon_pm pm;
1513 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1514 struct radeon_mutex cs_mutex;
1515 struct radeon_wb wb;
1516 struct radeon_dummy_page dummy_page;
1517 bool gpu_lockup;
1518 bool shutdown;
1519 bool suspend;
1520 bool need_dma32;
1521 bool accel_working;
1522 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1523 const struct firmware *me_fw; /* all family ME firmware */
1524 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
1525 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
1526 const struct firmware *mc_fw; /* NI MC firmware */
1527 const struct firmware *ce_fw; /* SI CE firmware */
1528 struct r600_blit r600_blit;
1529 struct r600_vram_scratch vram_scratch;
1530 int msi_enabled; /* msi enabled */
1531 struct r600_ih ih; /* r6/700 interrupt ring */
1532 struct si_rlc rlc;
1533 struct work_struct hotplug_work;
1534 int num_crtc; /* number of crtcs */
1535 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1536 struct mutex vram_mutex;
1537
1538 /* audio stuff */
1539 bool audio_enabled;
1540 struct timer_list audio_timer;
1541 int audio_channels;
1542 int audio_rate;
1543 int audio_bits_per_sample;
1544 uint8_t audio_status_bits;
1545 uint8_t audio_category_code;
1546
1547 struct notifier_block acpi_nb;
1548 /* only one userspace can use Hyperz features or CMASK at a time */
1549 struct drm_file *hyperz_filp;
1550 struct drm_file *cmask_filp;
1551 /* i2c buses */
1552 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
1553 /* debugfs */
1554 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
1555 unsigned debugfs_count;
1556 /* virtual memory */
1557 struct radeon_vm_manager vm_manager;
1558 };
1559
1560 int radeon_device_init(struct radeon_device *rdev,
1561 struct drm_device *ddev,
1562 struct pci_dev *pdev,
1563 uint32_t flags);
1564 void radeon_device_fini(struct radeon_device *rdev);
1565 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1566
1567 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
1568 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
1569 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
1570 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1571
1572 /*
1573 * Cast helper
1574 */
1575 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1576
1577 /*
1578 * Registers read & write functions.
1579 */
1580 #define RREG8(reg) readb((rdev->rmmio) + (reg))
1581 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
1582 #define RREG16(reg) readw((rdev->rmmio) + (reg))
1583 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
1584 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
1585 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1586 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1587 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1588 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1589 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1590 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1591 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1592 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1593 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1594 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1595 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1596 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1597 #define WREG32_P(reg, val, mask) \
1598 do { \
1599 uint32_t tmp_ = RREG32(reg); \
1600 tmp_ &= (mask); \
1601 tmp_ |= ((val) & ~(mask)); \
1602 WREG32(reg, tmp_); \
1603 } while (0)
1604 #define WREG32_PLL_P(reg, val, mask) \
1605 do { \
1606 uint32_t tmp_ = RREG32_PLL(reg); \
1607 tmp_ &= (mask); \
1608 tmp_ |= ((val) & ~(mask)); \
1609 WREG32_PLL(reg, tmp_); \
1610 } while (0)
1611 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1612 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1613 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1614
1615 /*
1616 * Indirect registers accessor
1617 */
rv370_pcie_rreg(struct radeon_device * rdev,uint32_t reg)1618 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1619 {
1620 uint32_t r;
1621
1622 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1623 r = RREG32(RADEON_PCIE_DATA);
1624 return r;
1625 }
1626
rv370_pcie_wreg(struct radeon_device * rdev,uint32_t reg,uint32_t v)1627 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1628 {
1629 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1630 WREG32(RADEON_PCIE_DATA, (v));
1631 }
1632
1633 void r100_pll_errata_after_index(struct radeon_device *rdev);
1634
1635
1636 /*
1637 * ASICs helpers.
1638 */
1639 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1640 (rdev->pdev->device == 0x5969))
1641 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1642 (rdev->family == CHIP_RV200) || \
1643 (rdev->family == CHIP_RS100) || \
1644 (rdev->family == CHIP_RS200) || \
1645 (rdev->family == CHIP_RV250) || \
1646 (rdev->family == CHIP_RV280) || \
1647 (rdev->family == CHIP_RS300))
1648 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1649 (rdev->family == CHIP_RV350) || \
1650 (rdev->family == CHIP_R350) || \
1651 (rdev->family == CHIP_RV380) || \
1652 (rdev->family == CHIP_R420) || \
1653 (rdev->family == CHIP_R423) || \
1654 (rdev->family == CHIP_RV410) || \
1655 (rdev->family == CHIP_RS400) || \
1656 (rdev->family == CHIP_RS480))
1657 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1658 (rdev->ddev->pdev->device == 0x9443) || \
1659 (rdev->ddev->pdev->device == 0x944B) || \
1660 (rdev->ddev->pdev->device == 0x9506) || \
1661 (rdev->ddev->pdev->device == 0x9509) || \
1662 (rdev->ddev->pdev->device == 0x950F) || \
1663 (rdev->ddev->pdev->device == 0x689C) || \
1664 (rdev->ddev->pdev->device == 0x689D))
1665 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1666 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
1667 (rdev->family == CHIP_RS690) || \
1668 (rdev->family == CHIP_RS740) || \
1669 (rdev->family >= CHIP_R600))
1670 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1671 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1672 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1673 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1674 (rdev->flags & RADEON_IS_IGP))
1675 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
1676 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
1677 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
1678 (rdev->flags & RADEON_IS_IGP))
1679
1680 /*
1681 * BIOS helpers.
1682 */
1683 #define RBIOS8(i) (rdev->bios[i])
1684 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1685 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1686
1687 int radeon_combios_init(struct radeon_device *rdev);
1688 void radeon_combios_fini(struct radeon_device *rdev);
1689 int radeon_atombios_init(struct radeon_device *rdev);
1690 void radeon_atombios_fini(struct radeon_device *rdev);
1691
1692
1693 /*
1694 * RING helpers.
1695 */
1696 #if DRM_DEBUG_CODE == 0
radeon_ring_write(struct radeon_ring * ring,uint32_t v)1697 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
1698 {
1699 ring->ring[ring->wptr++] = v;
1700 ring->wptr &= ring->ptr_mask;
1701 ring->count_dw--;
1702 ring->ring_free_dw--;
1703 }
1704 #else
1705 /* With debugging this is just too big to inline */
1706 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
1707 #endif
1708
1709 /*
1710 * ASICs macro.
1711 */
1712 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1713 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1714 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1715 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1716 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p))
1717 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1718 #define radeon_gpu_is_lockup(rdev, cp) (rdev)->asic->gpu_is_lockup((rdev), (cp))
1719 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1720 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
1721 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
1722 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp))
1723 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp))
1724 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp))
1725 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
1726 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib))
1727 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
1728 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
1729 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
1730 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
1731 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
1732 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
1733 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
1734 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
1735 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
1736 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
1737 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
1738 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
1739 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
1740 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
1741 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
1742 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
1743 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
1744 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
1745 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
1746 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
1747 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
1748 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
1749 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
1750 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
1751 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
1752 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1753 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
1754 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
1755 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
1756 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
1757 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
1758 #define radeon_pre_page_flip(rdev, crtc) rdev->asic->pflip.pre_page_flip((rdev), (crtc))
1759 #define radeon_page_flip(rdev, crtc, base) rdev->asic->pflip.page_flip((rdev), (crtc), (base))
1760 #define radeon_post_page_flip(rdev, crtc) rdev->asic->pflip.post_page_flip((rdev), (crtc))
1761 #define radeon_wait_for_vblank(rdev, crtc) rdev->asic->display.wait_for_vblank((rdev), (crtc))
1762 #define radeon_mc_wait_for_idle(rdev) rdev->asic->mc_wait_for_idle((rdev))
1763
1764 /* Common functions */
1765 /* AGP */
1766 extern int radeon_gpu_reset(struct radeon_device *rdev);
1767 extern void radeon_agp_disable(struct radeon_device *rdev);
1768 extern int radeon_modeset_init(struct radeon_device *rdev);
1769 extern void radeon_modeset_fini(struct radeon_device *rdev);
1770 extern bool radeon_card_posted(struct radeon_device *rdev);
1771 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1772 extern void radeon_update_display_priority(struct radeon_device *rdev);
1773 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1774 extern void radeon_scratch_init(struct radeon_device *rdev);
1775 extern void radeon_wb_fini(struct radeon_device *rdev);
1776 extern int radeon_wb_init(struct radeon_device *rdev);
1777 extern void radeon_wb_disable(struct radeon_device *rdev);
1778 extern void radeon_surface_init(struct radeon_device *rdev);
1779 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1780 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1781 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1782 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1783 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1784 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1785 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1786 extern int radeon_resume_kms(struct drm_device *dev);
1787 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1788 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
1789
1790 /*
1791 * vm
1792 */
1793 int radeon_vm_manager_init(struct radeon_device *rdev);
1794 void radeon_vm_manager_fini(struct radeon_device *rdev);
1795 int radeon_vm_manager_start(struct radeon_device *rdev);
1796 int radeon_vm_manager_suspend(struct radeon_device *rdev);
1797 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
1798 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
1799 int radeon_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm);
1800 void radeon_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm);
1801 int radeon_vm_bo_update_pte(struct radeon_device *rdev,
1802 struct radeon_vm *vm,
1803 struct radeon_bo *bo,
1804 struct ttm_mem_reg *mem);
1805 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
1806 struct radeon_bo *bo);
1807 int radeon_vm_bo_add(struct radeon_device *rdev,
1808 struct radeon_vm *vm,
1809 struct radeon_bo *bo,
1810 uint64_t offset,
1811 uint32_t flags);
1812 int radeon_vm_bo_rmv(struct radeon_device *rdev,
1813 struct radeon_vm *vm,
1814 struct radeon_bo *bo);
1815
1816
1817 /*
1818 * R600 vram scratch functions
1819 */
1820 int r600_vram_scratch_init(struct radeon_device *rdev);
1821 void r600_vram_scratch_fini(struct radeon_device *rdev);
1822
1823 /*
1824 * r600 cs checking helper
1825 */
1826 unsigned r600_mip_minify(unsigned size, unsigned level);
1827 bool r600_fmt_is_valid_color(u32 format);
1828 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
1829 int r600_fmt_get_blocksize(u32 format);
1830 int r600_fmt_get_nblocksx(u32 format, u32 w);
1831 int r600_fmt_get_nblocksy(u32 format, u32 h);
1832
1833 /*
1834 * r600 functions used by radeon_encoder.c
1835 */
1836 extern void r600_hdmi_enable(struct drm_encoder *encoder);
1837 extern void r600_hdmi_disable(struct drm_encoder *encoder);
1838 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1839
1840 extern int ni_init_microcode(struct radeon_device *rdev);
1841 extern int ni_mc_load_microcode(struct radeon_device *rdev);
1842
1843 /* radeon_acpi.c */
1844 #if defined(CONFIG_ACPI)
1845 extern int radeon_acpi_init(struct radeon_device *rdev);
1846 #else
radeon_acpi_init(struct radeon_device * rdev)1847 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1848 #endif
1849
1850 #include "radeon_object.h"
1851
1852 #endif
1853