1 /* $Id: pbm.h,v 1.27 2001/08/12 13:18:23 davem Exp $ 2 * pbm.h: UltraSparc PCI controller software state. 3 * 4 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com) 5 */ 6 7 #ifndef __SPARC64_PBM_H 8 #define __SPARC64_PBM_H 9 10 #include <linux/types.h> 11 #include <linux/pci.h> 12 #include <linux/ioport.h> 13 #include <linux/spinlock.h> 14 15 #include <asm/io.h> 16 #include <asm/page.h> 17 #include <asm/oplib.h> 18 19 /* The abstraction used here is that there are PCI controllers, 20 * each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules 21 * underneath. Each PCI bus module uses an IOMMU (shared by both 22 * PBMs of a controller, or per-PBM), and if a streaming buffer 23 * is present, each PCI bus module has it's own. (ie. the IOMMU 24 * might be shared between PBMs, the STC is never shared) 25 * Furthermore, each PCI bus module controls it's own autonomous 26 * PCI bus. 27 */ 28 29 #define PBM_LOGCLUSTERS 3 30 #define PBM_NCLUSTERS (1 << PBM_LOGCLUSTERS) 31 32 struct pci_controller_info; 33 34 /* This contains the software state necessary to drive a PCI 35 * controller's IOMMU. 36 */ 37 struct pci_iommu { 38 /* This protects the controller's IOMMU and all 39 * streaming buffers underneath. 40 */ 41 spinlock_t lock; 42 43 /* Context allocator. */ 44 unsigned int iommu_cur_ctx; 45 46 /* IOMMU page table, a linear array of ioptes. */ 47 iopte_t *page_table; /* The page table itself. */ 48 int page_table_sz_bits; /* log2 of ow many pages does it map? */ 49 50 /* Base PCI memory space address where IOMMU mappings 51 * begin. 52 */ 53 u32 page_table_map_base; 54 55 /* IOMMU Controller Registers */ 56 unsigned long iommu_control; /* IOMMU control register */ 57 unsigned long iommu_tsbbase; /* IOMMU page table base register */ 58 unsigned long iommu_flush; /* IOMMU page flush register */ 59 unsigned long iommu_ctxflush; /* IOMMU context flush register */ 60 61 /* This is a register in the PCI controller, which if 62 * read will have no side-effects but will guarentee 63 * completion of all previous writes into IOMMU/STC. 64 */ 65 unsigned long write_complete_reg; 66 67 /* The lowest used consistent mapping entry. Since 68 * we allocate consistent maps out of cluster 0 this 69 * is relative to the beginning of closter 0. 70 */ 71 u32 lowest_consistent_map; 72 73 /* In order to deal with some buggy third-party PCI bridges that 74 * do wrong prefetching, we never mark valid mappings as invalid. 75 * Instead we point them at this dummy page. 76 */ 77 unsigned long dummy_page; 78 unsigned long dummy_page_pa; 79 80 /* If PBM_NCLUSTERS is ever decreased to 4 or lower, 81 * or if largest supported page_table_sz * 8K goes above 82 * 2GB, you must increase the size of the type of 83 * these counters. You have been duly warned. -DaveM 84 */ 85 struct { 86 u16 next; 87 u16 flush; 88 } alloc_info[PBM_NCLUSTERS]; 89 90 /* Here a PCI controller driver describes the areas of 91 * PCI memory space where DMA to/from physical memory 92 * are addressed. Drivers interrogate the PCI layer 93 * if their device has addressing limitations. They 94 * do so via pci_dma_supported, and pass in a mask of 95 * DMA address bits their device can actually drive. 96 * 97 * The test for being usable is: 98 * (device_mask & dma_addr_mask) == dma_addr_mask 99 */ 100 u32 dma_addr_mask; 101 }; 102 103 extern void pci_iommu_table_init(struct pci_iommu *, int); 104 105 /* This describes a PCI bus module's streaming buffer. */ 106 struct pci_strbuf { 107 int strbuf_enabled; /* Present and using it? */ 108 109 /* Streaming Buffer Control Registers */ 110 unsigned long strbuf_control; /* STC control register */ 111 unsigned long strbuf_pflush; /* STC page flush register */ 112 unsigned long strbuf_fsync; /* STC flush synchronization reg */ 113 unsigned long strbuf_ctxflush; /* STC context flush register */ 114 unsigned long strbuf_ctxmatch_base; /* STC context flush match reg */ 115 unsigned long strbuf_flushflag_pa; /* Physical address of flush flag */ 116 volatile unsigned long *strbuf_flushflag; /* The flush flag itself */ 117 118 /* And this is the actual flush flag area. 119 * We allocate extra because the chips require 120 * a 64-byte aligned area. 121 */ 122 volatile unsigned long __flushflag_buf[(64 + (64 - 1)) / sizeof(long)]; 123 }; 124 125 #define PCI_STC_FLUSHFLAG_INIT(STC) \ 126 (*((STC)->strbuf_flushflag) = 0UL) 127 #define PCI_STC_FLUSHFLAG_SET(STC) \ 128 (*((STC)->strbuf_flushflag) != 0UL) 129 130 /* There can be quite a few ranges and interrupt maps on a PCI 131 * segment. Thus... 132 */ 133 #define PROM_PCIRNG_MAX 64 134 #define PROM_PCIIMAP_MAX 64 135 136 struct pci_pbm_info { 137 /* PCI controller we sit under. */ 138 struct pci_controller_info *parent; 139 140 /* Physical address base of controller registers. */ 141 unsigned long controller_regs; 142 143 /* Physical address base of PBM registers. */ 144 unsigned long pbm_regs; 145 146 /* Opaque 32-bit system bus Port ID. */ 147 u32 portid; 148 149 /* Chipset version information. */ 150 int chip_type; 151 #define PBM_CHIP_TYPE_SABRE 1 152 #define PBM_CHIP_TYPE_PSYCHO 2 153 #define PBM_CHIP_TYPE_SCHIZO 3 154 #define PBM_CHIP_TYPE_SCHIZO_PLUS 4 155 #define PBM_CHIP_TYPE_TOMATILLO 5 156 int chip_version; 157 int chip_revision; 158 159 /* Name used for top-level resources. */ 160 char name[64]; 161 162 /* OBP specific information. */ 163 int prom_node; 164 char prom_name[64]; 165 struct linux_prom_pci_ranges pbm_ranges[PROM_PCIRNG_MAX]; 166 int num_pbm_ranges; 167 struct linux_prom_pci_intmap pbm_intmap[PROM_PCIIMAP_MAX]; 168 int num_pbm_intmap; 169 struct linux_prom_pci_intmask pbm_intmask; 170 u64 ino_bitmap; 171 172 /* PBM I/O and Memory space resources. */ 173 struct resource io_space; 174 struct resource mem_space; 175 176 /* Base of PCI Config space, can be per-PBM or shared. */ 177 unsigned long config_space; 178 179 /* State of 66MHz capabilities on this PBM. */ 180 int is_66mhz_capable; 181 int all_devs_66mhz; 182 183 /* This PBM's streaming buffer. */ 184 struct pci_strbuf stc; 185 186 /* IOMMU state, potentially shared by both PBM segments. */ 187 struct pci_iommu *iommu; 188 189 /* PCI slot mapping. */ 190 unsigned int pci_first_slot; 191 192 /* Now things for the actual PCI bus probes. */ 193 unsigned int pci_first_busno; 194 unsigned int pci_last_busno; 195 struct pci_bus *pci_bus; 196 }; 197 198 struct pci_controller_info { 199 /* List of all PCI controllers. */ 200 struct pci_controller_info *next; 201 202 /* Each controller gets a unique index, used mostly for 203 * error logging purposes. 204 */ 205 int index; 206 207 /* Do the PBMs both exist in the same PCI domain? */ 208 int pbms_same_domain; 209 210 /* The PCI bus modules controlled by us. */ 211 struct pci_pbm_info pbm_A; 212 struct pci_pbm_info pbm_B; 213 214 /* Operations which are controller specific. */ 215 void (*scan_bus)(struct pci_controller_info *); 216 unsigned int (*irq_build)(struct pci_pbm_info *, struct pci_dev *, unsigned int); 217 void (*base_address_update)(struct pci_dev *, int); 218 void (*resource_adjust)(struct pci_dev *, struct resource *, struct resource *); 219 220 /* Now things for the actual PCI bus probes. */ 221 struct pci_ops *pci_ops; 222 unsigned int pci_first_busno; 223 unsigned int pci_last_busno; 224 225 void *starfire_cookie; 226 }; 227 228 /* PCI devices which are not bridges have this placed in their pci_dev 229 * sysdata member. This makes OBP aware PCI device drivers easier to 230 * code. 231 */ 232 struct pcidev_cookie { 233 struct pci_pbm_info *pbm; 234 char prom_name[64]; 235 int prom_node; 236 struct linux_prom_pci_registers prom_regs[PROMREG_MAX]; 237 int num_prom_regs; 238 struct linux_prom_pci_registers prom_assignments[PROMREG_MAX]; 239 int num_prom_assignments; 240 }; 241 242 /* Currently these are the same across all PCI controllers 243 * we support. Someday they may not be... 244 */ 245 #define PCI_IRQ_IGN 0x000007c0 /* Interrupt Group Number */ 246 #define PCI_IRQ_INO 0x0000003f /* Interrupt Number */ 247 248 #endif /* !(__SPARC64_PBM_H) */ 249